Dft Report

DFT REPORT FOR SEQUENCE DETECTOR

For typical.lib:set_attribute hdl_search_path "/homedir/13mvd0046/test1/asiclab" "/homedir/13mvd0046/test1/asiclab" set_attribute lib_search_path "/root/Cadence_tools/rclabs/library" "/root/Cadence_tools/rclabs/library" set_attribute library [list typical.lib] set_attribute information_level 6 set myFiles [list fsm.v] set basename fsm set myClk CK set myPeriod_ps 10000 set myInDelay_ps 250 set myOutDelay_ps 250 set runname RTL set DESIGN "fsm" set runname RTL read_hdl ${myFiles} elaborate ${basename} set clock [define_clock -period ${myPeriod_ps} -name ${myClk} [clock_ports]] external_delay -input $myInDelay_ps -clock ${myClk} [find / -port ports_in/*] external_delay -output $myOutDelay_ps -clock ${myClk} [find / -port ports_out/*] set_attribute dft_scan_style muxed_scan / define_dft shift_enable -name SE -active high -create_port SE define_dft test_mode -design ${DESIGN} -name TM -active high TM -create report dft_setup synthesize -to_generic check_dft_rules report dft_registers set_attribute dft_scan_output_preference auto /designs/$DESIGN /designs/$DESIGN set_attr dft_scan_map_mode tdrc_pass /designs/$DESIGN /designs/$DESIGN check_dft_rules >dft_rules.report2 synthesize -incremental -effort high define_dft scan_chain -name chain1 -create_ports -sdi tdi -sdo tdo set_attr dft_identify_internal_test_clocks dft_identify_internal_test_clocks true set_attr dft_min_number_of_scan_chains 1 /designs/$DESIGN /designs/$DESIGN set_attr dft_mix_clock_edges_in_scan_chain dft_mix_clock_edges_in_scan_chainss true /designs/$DESIGN /designs/$DESIGN report dft_setup connect_scan_chains -auto_create_chains -preview

Report for total registers scannable: Identified 64 valid usable scan cells Detected 0 DFT rule violation(s) Summary of check_dft_rules **************************  Number of usable scan cells: 64 Clock Rule Violations: --------------------Internally driven clock net: 0 Tied constant clock net: 0 Undriven clock net: 0 Conflicting async & clock net: 0 Misc. clock net: 0 Async. set/reset Rule Violations: -------------------------------Internally driven async net: 0 Tied active async net: 0 Undriven async net: 0 Misc. async net: 0 Total number of DFT violations: 0 Total number of Test Clock Domains: 1 DFT Test Clock Domain: clk Test Clock 'clk' (Positive edge) has 2 registers  Number of user specified non-Scan registers: 0  Number of registers that fail DFT rules: 0  Number of registers that pass DFT rules: 2 Percentage of total registers that are scannable: 100%

Report for single scan cell(mux): Reporting 1 scan chain (muxed_scan) Chain 1: chain1 scan_in: tdi scan_out: tdo shift_enable: SE (active high) clock_domain: clk (edge: rise) length: 2  bit 1 ps_reg[0]  bit 2 ps_reg[1] -----------------------assign pin=TM assign pin=SE assign pin=clk assign pin=tdi assign pin=tdo

test_function= +TI; test_function= +SE; test_function= -ES; test_function= SI0; test_function= SO0;

# test_mode # shift_enable

Report Area: ============================================================ Generated by: Encounter(R) RTL Compiler RC12.10 - v12.10-p006_1 Generated on: Mar 18 2014 01:23:05 pm Module: fsm Technology library: typical 1.13 Operating conditions: typical (balanced_tree) Wireload mode: segmented Area mode: timing library ============================================================

Gate Instances Area Library ----------------------------------------AND3X2 1 16.632 typical AOI21X1 1 13.306 typical  NAND2BX1 2 26.611 typical  NAND3BX1 1 16.632 typical OAI2BB1X1 1 16.632 typical SDFFHQX1 2 133.056 typical ----------------------------------------total 8 222.869

Type Instances Area Area % -----------------------------------sequential 2 133.056 59.7 logic 6 89.813 40.3 -----------------------------------total 8 222.869 100.0

Complete analysis of DFT analysis: Design Name =========== fsm Scan Style ========== muxed_scan Design has a valid DFT rule check status Global Constraints ================== Minimum number of scan chains: 1 Maximum length of scan chains: no_value Lock-up element type: preferred_level_sensitive Mix clock edges in scan chain: true Prefix for unnamed scan objects: DFT_

Test signal objects =================== shift_enable: object name: SE  pin name: SE hookup_pin: SE hookup_polarity: non_inverted active: high ideal: true user defined: true test_mode: object name: TM  pin name: TM hookup_pin: TM hookup_polarity: non_inverted active: high ideal: true user defined: true

Test clock objects ================== test_clock: object name: clk test_clock_domain: clk user defined: false source: clk root source: clk root source polarity: non_inverting hookup_pin: clk  period: 50000.0

DFT controllable objects ======================== DFT don't scan objects ====================== DFT abstract don't scan objects =============================== DFT scan segment constraints ============================

DFT scan chain constraints ========================== User Chain: object name: chain1 scan-in: tdi scan-in hookup_pin: tdi scan-out: tdo scan-out hookup_pin: tdo shared out: false shift_enable object name: max length: no_value complete: false

DFT actual scan chains ====================== Actual Chain: object name: chain1 scan-in: tdi scan-in hookup_pin: tdi scan-out: tdo scan-out hookup_pin: tdo shared out: false shift_enable: SE length: 2 segment objects: none analyzed: false test_clock domain: clk test_clock edge: rise

Report for power: ============================================================ Generated by: Encounter(R) RTL Compiler RC12.10 - v12.10-p006_1 Generated on: Mar 18 2014 01:23:05 pm Module: fsm Technology library: typical 1.13 Operating conditions: typical (balanced_tree) Wireload mode: segmented Area mode: timing library ============================================================ Leakage Dynamic Instance Cells Power(nW) Power(nW) --------------------------------------------fsm 8 1.283 40165.434

Total Power(nW) 40166.716

Report for timing: ============================================================ Generated by: Encounter(R) RTL Compiler RC12.10 - v12.10-p006_1 Generated on: Mar 18 2014 01:23:05 pm Module: fsm Technology library: typical 1.13 Operating conditions: typical (balanced_tree) Wireload mode: segmented Area mode: timing library ============================================================ Pin

Type

Fanout Load Slew Delay Arrival (fF) (ps) (ps) ( ps) ----------------------------------------------------------------------------------------------------(clock CK) launch 0R  ps_reg[0]/CK 400 0R  ps_reg[0]/Q SDFFHQX1 5 32.1 322 +358 358 R g311/AN +0 358 g311/Y NAND3BX1 1 8.2 150 +132 489 R g309/A0 +0 489 g309/Y AOI21X1 1 5.4 91 +55 544 F  ps_reg[1]/D SDFFHQX1 +0 544  ps_reg[1]/CK setup 400 +449 993 R - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - (clock CK) capture 10000 R --------------------------------------------------------------------------------------------------Timing slack : 9007ps Start-point : ps_reg[0]/CK End-point : ps_reg[1]/D

SDC file: # #################################################################### # Created by Encounter(R) RTL Compiler RC12.10 - v12.10-p006_1 on Tue Mar 18 13:23:05 +0530 2014 # #################################################################### set sdc_version 1.7 set_units -capacitance 1000.0fF set_units -time 1000.0ps # Set the current design current_design fsm create_clock -name "CK" -add -period 10.0 -waveform {0.0 5.0} [get_ports clk] set_clock_transition 0.4 [get_clocks CK] set_clock_gating_check -setup 0.0

For slow.lib:set_attribute hdl_search_path "/homedir/13mvd0046/test1/asiclab" set_attribute lib_search_path "/root/Cadence_tools/rclabs/library" set_attribute library [list slow.lib] set_attribute information_level 6 set myFiles [list fsm.v] set basename fsm set myClk CK set myPeriod_ps 10000 set myInDelay_ps 250 set myOutDelay_ps 250 set runname RTL set DESIGN "fsm" set runname RTL read_hdl ${myFiles} elaborate ${basename} set clock [define_clock -period ${myPeriod_ps} -name ${myClk} [clock_ports]] external_delay -input $myInDelay_ps -clock ${myClk} [find / -port ports_in/*] external_delay -output $myOutDelay_ps -clock ${myClk} [find / -port ports_out/*] set_attribute dft_scan_style muxed_scan / define_dft shift_enable -name SE -active high -create_port SE define_dft test_mode -design ${DESIGN} -name TM -active high TM -create report dft_setup synthesize -to_generic check_dft_rules report dft_registers set_attribute dft_scan_output_preference auto /designs/$DESIGN set_attr dft_scan_map_mode tdrc_pass /designs/$DESIGN check_dft_rules >dft_rules.report2 synthesize -incremental -effort high define_dft scan_chain -name chain1 -create_ports -sdi tdi -sdo tdo set_attr dft_identify_internal_test_clocks true set_attr dft_min_number_of_scan_chains 1 /designs/$DESIGN set_attr dft_mix_clock_edges_in_scan_chains true /designs/$DESIGN report dft_setup connect_scan_chains -auto_create_chains -preview

Report for total registers scannable: Identified 60 valid usable scan cells Detected 0 DFT rule violation(s) Summary of check_dft_rules **************************  Number of usable scan cells: 60 Clock Rule Violations: --------------------Internally driven clock net: 0 Tied constant clock net: 0 Undriven clock net: 0 Conflicting async & clock net: 0 Misc. clock net: 0 Async. set/reset Rule Violations: -------------------------------Internally driven async net: 0 Tied active async net: 0 Undriven async net: 0 Misc. async net: 0 Total number of DFT violations: 0 Total number of Test Clock Domains: 1 DFT Test Clock Domain: clk Test Clock 'clk' (Positive edge) has 2 registers  Number of user specified non-Scan registers: 0  Number of registers that fail DFT rules: 0  Number of registers that pass DFT rules: 2 Percentage of total registers that are scannable: 100%

Report Area: ============================================================ Generated by: Encounter(R) RTL Compiler RC12.10 - v12.10-p006_1 Generated on: Mar 24 2014 07:47:48 pm Module: fsm Technology library: slow 1.1 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================

Gate Instances Area Library -------------------------------------------------AO21XL 1 8.487 slow AOI32X1 1 11.882 slow INVX1 2 6.790 slow  NAND2X1 1 5.092 slow  NOR2X1 1 5.092 slow  NOR2XL 1 5.092 slow SDFFQX1 2 64.501 slow --------------------------------------------total 9 106.936

Type Instances Area Area % ----------------------------------------------sequential 2 64.501 60.3 inverter 2 6.790 6.3 logic 5 35.645 33.3 ----------------------------------------------total 9 106.936 100.0

Report for power: ============================================================ Generated by: Encounter(R) RTL Compiler RC12.10 - v12.10-p006_1 Generated on: Mar 24 2014 07:47:48 pm Module: fsm Technology library: slow 1.1 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Leakage Dynamic Total Instance Cells Power(nW) Power(nW) Power(nW) ------------------------------------------------------------------------fsm 9 201.280 5737.441 5938.722

Report for timing: ============================================================ Generated by: Encounter(R) RTL Compiler RC12.10 - v12.10-p006_1 Generated on: Mar 24 2014 07:47:48 pm Module: fsm Technology library: slow 1.1 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Pin

Type

Fanout

Load Slew Delay Arrival (fF) (ps) (ps) (ps) -------------------------------------------------------------------------------------------(clock CK) launch 0R  ps_reg[0]/CK 400 0R  ps_reg[0]/Q SDFFQX1 4 9.5 144 +361 361 R g305/A +0 361 g305/Y NAND2X1 2 3.1 62 +51 412 F g303/A0 +0 412 g303/Y AO21XL 1 1.0 64 +164 576 F  ps_reg[0]/D SDFFQX1 +0 576  ps_reg[0]/CK setup 400 +441 1017 R - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - -- - - - - - - - - - - - - - - (clock CK) capture 10000 R -------------------------------------------------------------------------------------------------Timing slack : 8983ps Start-point : ps_reg[0]/CK End-point : ps_reg[0]/D

Simulation graph for fsm :(include slow.v)

It shows some delay in output waveform: