dft ppt

I N V E N T I V E

DFT Compr om pre ess ssio ion n flo f low w in in RTL Compi om piler ler Sandeep Bhatia Cadence Design Systems Session 3.7

What is Test Test Compr om pre ess ssio ion? n?

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Test Test Comp Compre ress ssio ion n is the the tec techn hniq ique ue of redu reduci cing ng the the test test data volume and test application time (TAT) while retaining test coverage. Every tte est co compr mpression ion so solut lution requ equires ires – Compression logic via hardware on on the designs inputs and outputs • de-c de-com ompr pre ess ssor or on the the sc scan input nput sid side • resp respon onse se comp compac acto torr on on the the sc scan an outp output ut side side – ATPG capabilities to work with with compression logic

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© 2007 Cadence Cadence Design System Systems, s, Inc. All rights rights reserved reserved worldwide. worldwide.

What is Test Test Compr om pre ess ssio ion? n?

•

•

Test Test Comp Compre ress ssio ion n is the the tec techn hniq ique ue of redu reduci cing ng the the test test data volume and test application time (TAT) while retaining test coverage. Every tte est co compr mpression ion so solut lution requ equires ires – Compression logic via hardware on on the designs inputs and outputs • de-c de-com ompr pre ess ssor or on the the sc scan input nput sid side • resp respon onse se comp compac acto torr on on the the sc scan an outp output ut side side – ATPG capabilities to work with with compression logic

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Why do we nee need Test Test Compr om pre ess ssio ion: n: • Incr Increa ease se in the the num numbe berr of of tes testt pat patte tern rnss – Transition fault testing requires 3-5x more patterns than stuck-at fault testing

• Newe Newerr chip chips s wit with h more more pins pins and funct function ionali ality ty but older older ATE equipment. – Less pins – Not enough buffer memory

• Lowow-cost AT ATE - redu educed pi pin co count unt te tester ters • Keep down test cost

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Test Data Volume v/s Technology Node

e m u l o v a t a d t s e t e v i t a l e R

140 120 100

Other

80

Bridgi ng test

60

At-Speed tests Stuck-at tests

40 20 0 180 nm 150 nm 130 nm

90 nm

65 nm

Technol ogy Node

Reference – www.elecdesign.com 4

© 2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Comparison of Full vs Compressed Scan s r o t c e V n a c S

T e s t e r m e m o r y

Respo nse Data

Free space

Stimulu s Data

MBIST + Boundary + Mixed-Signal + Functional Tests

n

n

100011010111010001010101011

001011010111011111101110110

110011010111010001101110001

Respon se Data Stimulus Data

MBIST + Boundary + Mixed-Signal + Functional Tests

n

n

100011010111010001

r o s s e r p m o C e D

100110101110101010 001011010111011111 001010010011010111 110011010111010001 101110010111011101

1011100101110111011110001110

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T e s t e r m e m o r y

r o s s e r p m o C

RC 7.1 Compression Structures Supported for both ATPG and Diagnostics Compressed Input Stream

Input Side: Fan-out only or



Chip



Space Expander (Spreader Network)

…

…



XOR Spreader

… Output Side: Space compactor





Masking

Masking

Space Compactor (XOR Trees) Compressed Output Stream 6


Masking

Optional X-state masking 

Test Compression Structures •

De-compressor: – Insert a simple scan fan-out (broadcast) or combinatorial linear (XOR) spreader to decompress the test stimulus from a small number of scan in pins to a large number internal scan channels.

•

Compactor: – Insert a combinatorial linear (XOR) space compactor on the internal scan channel outputs allowing the test responses to be compressed down to a fewer number of scan out pins. – Optionally can insert masking logic to block X’s from entering the compressor using a wide1 style masking.

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X- Masking • Output Compression ratios and ATPG results are degraded by the capture of unknown (‘X’) states • Sources of X-states – – – –

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Un-modeled ATPG logic: RAMs, mixed signal logic, black boxes etc. Non-scan flops that get corrupted during scan operation Flops on paths slower than tester launch-capture cycle Unintended consequences of last minute design changes


Example of Test Time Reduction • Original design: – 200K flops with10 scan chains • 20K flops per chain

– 10K test patterns with 100 ns shift clock – Test application time = 20 sec. • 20K bits X 100 ns x 10K patterns

• Design with 10X Test Compression: – Configure 200K flops into 100 compression mode scan chains – Max. scan chain length = 2K bits – Test application time = 2 sec. • 2K x 100 ns x 10K patterns

10X reduction

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Example Test Data Volume Reduction 1 bit for input data (0,1)

2 bits for output data (0,1,X,Z)

• Original design – Input Stim Data = 2 Gbits • 10K patterns X 10 scan in pins X 20K bits scan depth X 1 bit

– Output response Data = 4 Gbits • 10K patterns X 10 scan in pins X 20K bits scan depth X 2 bit

– Total = 6 Gbits of storage on tester

• Design with 10X Test Compression – Input Stim Data = 200 Mbits • 10K patterns x 10 scan in pins x 2K bits scan depth X 1 bit

– Output response Data = 400 Mbits • 10K X 10 X 2K bits scan depth X 2 bits

– Total = 600 Mega-Bits of storage on tester 10X reduction 10


How Much Test Compression Do I Need? • Original Design: 6Gb of test data and 20 sec. ATE time for scan test • 10 X compression: 90% reduction (600 Mb, 2 sec) • 20 X compression: 95% reduction (300 Mb,1 sec) • 50 X compression: 98% reduction (120 Mb, 0.4 sec) • 100X compression: 99% reduction (60 Mb, 0.2 sec) • Real Benefits start diminishing somewhere between 50-100X while P&R and ATPG complexity kick in. • Non-Scan vectors (MBIST, Functional, I/O, etc.) dominate test time and memory at higher compression

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Flow

• • • •

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Emphasis on Ease of use Similar to Full-Scan design flow Integrated into RTL Compiler Synthesis Links into ET ATPG through setup files


Flow

1. Build Full Scan Chains – – – – – – –

Complex full chains constraints (head, tail, body …) Segments (fixed, floating, preserved, abstract) Mixed clock domains, lockup latches Low power Physical aware scan chain design Incremental scan chain synthesis (selective building of chains) Detailed chain reports

2. Compress Full Scan Chains

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Test Compression Gate level Flow Read Libraries and Netlist Define full-scan chain DFT setup

define_dft shift_enable define_dft test_clock set_attr dft_dont_scan … set_attr dft_controllable define_dft test_mode

Define the compression control pins

etc…

define_dft xxx_segment

Set Other Parameters Run the DFT rule checks, Fix any DFT Violations

fix_dft_violations

Build Full Scan Chains

connect_scan_chains

Compress Full Scan Chains Write ET ATPG Files Save Netlist

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define_dft scan_chain


check_dft_rules

compress_scan_chains

write_et –library …-compression Full-scan Pin Assign File

Compression Pin Assign Files

Compression Verification and ATPG … write_et command • Use the write_et command to generate the necessary script files to: – Verify test structures and create ATPG test vectors – run NCVerilog to simulate the test vectors for fullscan and compression test modes.

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Compression Results (smaller is better) 1800 1600 1400

s e l c 1200 y c t 1000 s e T e 800 v i t a 600 l e R

Full-scan XOR Spreader Compression broadcast

400 200 0 1x

5x

10x

20x

40x

Compression ratio

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60x

80x

Compression Results (smaller is better) 400 350 s e l c y c t s e T e v i t a l e R

300 Full-scan

250

XOR Spreader

200

Compression broadcast

150 100 50 0 1x

5x

10x

20x

40x

Compression ratio

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60x

80x

Target v/s Actual Compression Advantage of Effective Masking (higher is better) 120

100 o i t a r

n o i s s e r p m o C

80 Target With Masking

60

Without Masking 40

20

0 1

18

2

3

4


5

6

7

Masking v/s No masking (higher is better) Compression Results 70 60 o i t 50 a r n o 40 i s s e 30 r p m o 20 C

with m asking without masking

10 0 1

2

3

4

Experiment

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5

6

7

Conclusion

DFT Compression • Can be very effective in reducing Test Cost – Test Application Time – Test Data Volume

• Ease of use – similar to Full-Scan DFT/ATPG flow • X-Masking is very critical to get efficient compression

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Co-Authors acknowledgement

• • • • •

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Vivek Chickermane Brian Foutz Pradeep Nagaraj Vinayak Kadam …


compress_scan_chains command: rc> compress_scan_chains -ratio [-chains +] [-decompressor < broadcast | xor >] [-master_control ] [-auto_create | [-comp_enable ] [-spread_enable ]] [-mask [-auto_create | [-mask_load ] [-mask_enable ] [-mask_clock ] [-mask_sdi ] [-mask_sdo -shared_output]] [-preview] [-inside ] []

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Test Data Volume

Reference – www.elecdesign.com 24


write_et command

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Target v/s Actual Compression Ratio Compression Results 25 20

o i t a r n 15 o i s s e r 10 p m o C

Target with masking without masking

5 0

1

2

Experiment

26


3

Benefits of XOR-based Compression: – Inserted and validated as part of the synthesis flow – Non-proprietary, combinational (simple), and efficient technology – (Optional) Insertion of X-state masking logic: • ATPG generates mask data and special scan sequences to load masks prior to scan unload, as required • ATPG selects and applies mask on a scan cycle basis during scan

– ATPG support for all fault models including, IDDQ, stuck-at, transition, pattern faults – Enables on-line (one pass) diagnostics methodology • The data collected during the test can be used for diagnostics without having to rerun the test to collect full scan data. – diagnose the failure information of the compressed test set allows important statistical data to be gathered during production in support of yield analysis. – This helps to ramp the yield as quickly as possible and increase profits. 27


Target v/s Actual Compression Ratio

70 60 o 50 i t a r n 40 o i s s e r 30 p m o C 20

Target With Masking Without Masking

10 0 1

2

3 Experiment

28


4

5

Masking v/s No masking

Compression Results 70 60 o i t 50 a r n o 40 i s s e 30 r p m o 20 C

with m asking without masking

10 0 1

2

3

4

Experiment

29


5

6

7

Dealing with ‘X’-States • Output Compression ratios and ATPG results are degraded by the capture of unknown (‘X’) states • Sources of X-states – – – –

Un-modeled ATPG logic: RAMs, mixed signal logic, black boxes etc. Non-scan flops that get corrupted during scan operation Flops on paths slower than tester launch-capture cycle Unintended consequences of last minute design changes

• Mask X-source with a test point => flow bottleneck!

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X- Masking

Mask logic prevents X’s from scan channels to enter the Response Compactor

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dft ppt

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