IJSRD - International Journal for Scientific Research Research & Development| Vol. 4, Issue Issue 02, 2016 | ISSN (online): 2321-0613
Design of 16 × 16 Vedic Multiplier Niraj Patel1 Alpesh Patel 2 1 Student 2Assistant Professor 1,2 Vishwakarma Govt. Engineering College, Chandkheda Abstract — Design of Multiplier unit using Vedic Mathematics. Urdhva-Tiryagbhyam (vertically & crosswise) algorithm is the one of the multiplication technique. To reduce the partial product and to improve speed we have used this algorithm. Also different types of adders to reduce the partial product addition. Here design of 16X16 Vedic Multiplier using different adders and comparison of their delays. These delays compared to search for the best architecture. Design of the same implemented on XILINX ISE-14.5 simulator, Spartan-3 family and design coding in Verilog- HDL. Key words: Vedic Mathematics, Vedic Multiplier, Array Multiplier, Urdhva - Triyagbhyam Sutra
I. I NTRODUCTION NTRODUCTION In Digital signal processing, we perform operations like Finite Impulse Response (FIR) and Infinite Impulse Response (IIR), the frequency domain filtering. Also frequency transformations like DFT, FFT, and DCT. For these operations, the multiplication is an essential hardware component. The multiplier is the slowest and most time consuming element in the system [12, 13]. So, the performance of the multiplier is a key element for the performance of the entire DSP system. Thus, the optimization speed of the multiplier is a major challenge for the system designers. In order to improve the speed and performance of the multiplier unit, there are two major points. The first is the partial products reduction network that is used in the multiplication block and the second is addition. The main role of the given architecture to design the multiplier unit and compare the performance results with the conventional multiplier units like Array Multiplier in terms of digital parameter such as area, speed and number of resources. These challenges can be successfully overcome by the use of Vedic multiplier which uses the ancient knowledge of Vedic mathematics.
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Gunitasamuchyah - The product of the sum is equal to the sum of the product 7) Nikhilam Navatashcaramam Dashatah - All from 9 and the last from 10 8) Paraavartya Yojayet - Transpose and adjust. 9) Puranapuranabyham By the completion or non completion 10) Sankalana-vyavakalanabhyam - By addition and by subtraction 11) Shesanyankena Charamena - The remainders by the last digit 12) Shunyam Saamyasamuccaye - When the sum is the same that sum is zero 13) Sopaantyadvayamantyam - The ultimate and twice the penultimate 14) Urdhva-tiryakbyham - Vertically and crosswise 15) Vyashtisamanstih - Part and Whole 16) Yaavadunam - Whatever the extent of its deficiency III. VEDIC MULTIPLIER In order to improve the speed and performance of the multiplier unit, there are two major points. The first is the partial products reduction network that is used in the multiplication block. For this we use Vedic multiplier technique. One method of multiplication is Urdhva Tiryakbhyam (Vertical and Crosswise). The multiplier is based on an algorithm Urdhva Tiryakbhyam of ancient Indian Vedic mathematics. Urdhva Tiryakbhyam sutra is general multiplication formula applicable to all case of multiplication. It is based on a novel concept through which generation of all partial products can be done them; concurrent addition of these partial products can be done. Thus parallelism in generation of partial product is obtained by using Urdhva Tiryakbhyam sutra [10].
II. VEDIC MATHEMATICS Vedic Mathematics or ‘Sixteen Simple Mathematical Formulae from the Vedas’ was written by His Holine ss Jagadguru Sankaracarya Sri Bharati Krsna Tirthaji Maharaja. It deals with various Vedic Mathematical formulae and their applications for carrying out tedious and cumbersome arithmetical operations [10]. Vedic Sutras: 1) (Anurupye) Shunyamanyat - If one is in ratio, the other is zero 2) Chalana-Kalanabyham - Differences and Similarities. 3) Ekadhikina Purvena - By one more than the previous one. 4) Ekanyunena Purvena - By one less than the previous one 5) Gunakasamuchyah - The factors of the sum is equal to the sum of the factors
Fig. 1: Example of Urdhva-triyagbhyam method The above Fig.1 shows the ancient method vertical and cross wise multiplication [10]. In this example we have the carry but as in digital multiplication there will be no carry for intermediate steps.
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Design of 16 × 16 Vedic Multiplier (IJSRD/Vol. 4/Issue 02/2016/42 02/2016/423) 3)
IV. DIGITAL IMPLEMENTATION OF VEDIC MULTIPLIER In implementation of 16×16 Vedic multiplier we use Divide and conquer technique. Thus, we have 2×2 as a basic building block for implementation. A. Implementation of 2×2 Vedic Multiplier
D. Implementation of 16×16 Vedic Multiplier
Here we used basic structure of N×N to implement any Nbit multiplier. So, we can compare the delay report of each multiplier. For speed and performance improvement we used different adders. By putting N=4, 8, 16 we implemented respective Vedic multipliers [9].
With the realization of Urdhva-triyagbhyam sutra and Fig.1. We implemented 2×2 Vedic multiplier as our basic building block [2].
Fig. 2: Logic gate Implementation of 2×2 Vedic Multiplier (0) = (0) ∙ (0) (1.1) (1) = (1) ∙ (0) ( (0) ∙ (1) (1.2) (1.2) (2) = [(1) ∙ (0) ∙ (0) ∙ (1)] [( [ (1) ∙ (1)] (1.3) (3) = [ (1) ∙ (0) ∙ (0) ∙ (1)] ∙ [( [(1) ∙ (1)] (1.4) B. Implementation of 4×4 Vedic Multiplier
Fig. 4: Implementation of N×N Vedic Multiplier V. VEDIC MULTIPLIER WITH DIFFERENT ADDERS
Fig. 3: Implementation of 4×4 Vedic Multiplier with the help of 2×2 Vedic Multiplier block As we use the divide and conquer technique we can build the 4×4 Vedic Multiplier using initial 2×2 Vedic multiplier block. Fig.3 shows that with some adjustment we implemented the 4×4 Vedic Multiplier [5]. C. Implementation of 8×8 Vedic Multiplier
Fig. 4: Implementation of 8×8 Vedic Multiplier [9]
To achieve high speed we must have less delay. Thus, we used different adders rather than normal ripple carry adders. In ripple carry adder, as N-bit increases the last MSB bit have to wait for very large time for the carry manipulation. Adders Used in Vedic Multiplier: 1) Ripple Carry Adder 2) Carry Skip Adder 3) Carry Look Ahead Adder VI. R ESULTS ESULTS The Verilog code of 16 x 16 bit Vedic multiplier is synthesized using Xilinx ISE Design Suite 14.5 and is implemented on FPGA XCS500(Device), FG320(Package), -5(speed) of Spartan 3 family. Here comparison delay report summary of different adders with Array and Vedic Multipliers are shown, which are generated using Xilinx software. Here all delays are in nano-seconds with respect to maximum combinational delay. Input Ripple adder VEDIC ARRAY 2x2 6.861 6.861 4x4 12.874 14.564 8x8 21.484 29.153 16x16 41.533 61.969 Table 1: Comparison Delay Report of Vedic multiplier with Ripple Carry Adder
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Design of 16 × 16 Vedic Multiplier (IJSRD/Vol. 4/Issue 02/2016/42 02/2016/423) 3)
Input
Carry Skip Adder VEDIC ARRAY 2x2 6.861 6.861 4x4 13.228 13.622 8x8 21.776 30.254 16x16 40.531 60.159 Table 2: Comparison Delay Report of Vedic multiplier with Carry Skip Adder Input Carry Look Ahead VEDIC ARRAY 2x2 6.861 6.861 4x4 12.653 12.657 8x8 20.739 29.482 16x16 39.391 59.657 Table 3: Comparison Delay Delay Report of Vedic multiplier with with Carry Look Ahead Adder
Fig. 5: Simulation waveform of 16×16 Vedic Multiplier VII. CONCLUSION From the results, it can say that Vedic Multiplier is efficient than Array Multiplier. From the comparison delay report with different adder, it can be seen that the carry look ahead adder in Vedic multiplier is the best architecture. The number of bit increases from 8 x 8 bit to 16 x 16 bit, the timing delay greatly reduces for Vedic multiplier as compared to array multiplier with carry look ahead adder. The time delay in Vedic multiplier with carry look ahead adder for 16 x 16 bit number is 39.391 ns while the time delay for Array multiplier is 59.567 ns respectively. Thus Vedic multiplier shows the improved speed among the conventional multiplier.
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