Expt. No. 4
CASCADE AMPLIFIER Objective: The aim of the experiment is to study the operation of cascade amplifier and obtain the frequency response and bandwidth Components and equipments required:
1. 2. 3. 4. 5. 6. 7. 8. 9.
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Circuit diagram:
Fig. 1
Theory:
A single stage of amplification is not enough for a particular application. The overall gain can be increased increased by using more than one stage, so when two amplifiers amplifiers are connected in such a way that the output signal of the first serves as the input signal to the second, the amplifiers are said to be connected in cascade. The most common cascade arrangement is the common-emitter RC coupled cascade amplifier. Common-emitter amplifier exhibit high voltage, high current, and high power gains, so they are very familiar than other configurations. Multistage amplifiers can be used either to increase the overall small signal voltage gain, or to provide an overall voltage gain greater than 1, with a very low output resistance. Figure 1 shows an RC-coupled cascaded amplifier. Capacitors C1 and C2 couple the signal into Q1 and Q2, respectively. C3 is used for coupling the signal from Q2 to its load. If the operation of coupled amplifiers is considered, a complicating factor appears. The addition of a second stage may alter the characteristics of the first stage and thus affect the level of signal fed to the second stage. To compute the overall gain of the amplifier, it is easier to calculate unloaded voltage gain for each stage, then including the loading effect by computing voltage dividers for the output resistance and input resistance of the following stage. This idea is illustrated in figure 2. Each Each trans transis isto torr is draw drawn n as an ampli amplifi fier er consi consist stin ing g of an input input resi resist stanc ancee R in , an output output resistance, R out out along with its unloaded gain, AV(NL).
Fig. 2
Then, the overall loaded gain
, of this amplifier can be found by: AV
Av=Av1Av2Rin2Ro1+Rin2RLRL+Ro2 For the RC Coupled (CE - CE) multistage amplifier with CE:
Rin1=R1|R2|βre1 Rin2=R3|R4|βre2 Ro1=RC1||Rin2 and Ro2=RC2||RL Note that if a load resistor was added across the output, an additional voltage divider consisting of the output resistance of the second stage and the added load resistor is used to compute the new gain. If Rin2≫Ro1 and RL≫Ro2
Av=Av1Av2 DC Analysis: For 1st stage amplifier: IB1=Vth1-VBE1Rth1+1+βRE1 Where, Vth1= VR2=VB1=VCCR2R1+R2 and Rth1=RB1=R1||R2
VCE1=VCC-IC1(RC1+RE1) IE1=VB1-VBE1RE1 Stability factor S=1+RB1RE1 For 2nd stage amplifier the analysis is same.
AC Analysis: For 1st stage amplifier: Voltage gain, Av1=-gmRo1
Input resistance, Rin1=RB1||rπ Output resistance, Ro1=RC1||Rin2 For 2 stage amplifier: Voltage gain, Av2=-gmRo2 nd
Input resistance, Rin2=RB2||rπ
Output resistance, Ro2=RC2||RL Design:
Given that
VCC=15V, IC1=1mA, IC2=3mA, RL=100kΩ, Av1=20dB, Av2=25dB, lower 3dB frequency fL=100Hz, Stability factor S=10 For 2nd stage amplifier:
gm=? RC2=? (Use a 100k pot in series with R C2 C2 to get required gain with less distortion at output) RE2=? R3=? R4=? From the above design find Ro2=?, Rin2=?
For 1st stage amplifier:
gm=? RC1=? (Use a 100k pot in series with R C1 C1 to get required gain with less distortion at output) RE1=? R1=? R2=? From the above design find Rin1=? and Ro1=?
For capacitors:
ωL=1C1rπ1, ωL=1C1rπ1, ωL=1CE2'rπ2
ωL=1C2(Ro1+Rin2), ωL=1C2(Ro1+Rin2),
ωL=1C3(Ro+RL)
,
ωL=1CE1'rπ1, ωL=1CE1'rπ1,
Where CE=(β+1)CE'
Pre-lab Assignments:
1. Find the Q-point of each stage of the circuit shown in fig.1, where R 1 = R 3 = 20kΩ, R 2 = R 4 = 10kΩ, R E1 E1=R E2 E2= 1kΩ, R C1 C1=4kΩ, R C2 C2=1kΩ VCC = 15V, VCE1= VCE2=0.2V, VBE1= VBE2=0.6V 2. Re-design the components of the circuit shown in fig. 1 for f L=1kHz 3. Define Define Power gain, Voltage Voltage gain gain and Current Current gain. gain. How it represent represent in dB? 4. What What is trans transit itio ion n freq frequen uency cy of tran transi sist stor or?? Give Give the the typi typica call valu valuee for for the the give given n transistor. Simula late te the the circ circui uitt given given in exper experim imen entt usin using g SPIC SPICE. E. Comp Compar aree desi design gned ed and and 5. Simu simulated dc biasing conditions, show input and its corresponding output wave forms, plot frequency response and compare it with designed values.
Model Waveforms: Input Wave form:
Output Waveforms (1st stage and 2nd stage):
Tabular Column:
For Single Stage Amplifier:
vin=1mVpp Input Signal Frequency, f (Hz)
Output Voltage, v o (vpp)
Voltage Gain, Av
Av in dB
Output Voltage, v o (vpp)
Voltage Gain, Av
Av in dB
For Two Stage Amplifier:
vin=5μVpp Input Signal Frequency, f (Hz)
Simulated Results:
First Stage Mid band gain = 21.9dB Lower cutoff frequency f L = 192Hz Upper cutoff frequency f H = 4.3MHz Bandwidth = 4.3MHz Multi Mu lti stage sta ge Mid band gain = 46.3dB Lower cutoff frequency f L = 257Hz Upper cutoff frequency f H = 4.15MHz Bandwidth = 4.15MHz
Viva Questions:
1. What are the the requirement requirementss of biasing biasing and coupling coupling circuits circuits in BJT BJT amplifie amplifiers? rs? 2. What is the use of C E in RC coupled amplifier and give its influence in frequency response? 3. Give the advantages and disadvantages of cascade amplifier. 4. What What is is half half-po -power wer freque frequency ncy?? 5. In amplifier amplifiers, s, why mid mid frequency frequency gain gain is independent independent to frequency? frequency? 6. What What is bode bode-p -plo lot? t? 7. What is is the method method to increas increasee the output output voltage voltage swing swing of an an amplifier? amplifier? 8. How load resistances influence the gain of BJT amplifiers? 9. What What is SPI SPICE CE??
