8 Cmos Capacitance

CMOS Capacitance Estimation

VLSI Design

Dr. Bassel Soudan Soudan – University of Sharjah Sharjah

1

MOS Transistor Capacitance

• •

Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important – Creates channel charge necessary for operation

•

Source and drain have capacitance to body – Across reverse-biased diodes – Called diffusion capacitance because it is associated with source/drain diffusion

VLSI Design


2

MOS Transistor Capacitance Gate

Gate Source

Source

Drain CGS

Drain CGS

CGD

CGB

CGB CSB

CGD

CSB

CDB

CDB

VDD

VLSI Design

3


Gate Capacitance C GB

• • •

=

WL

ε

OX

t OX

= C OX WL

Define Cpermicron = CoxL – Typical Typically ly about about 2 fF/ µm Therefore, CGB = Cpermicron X W Realistically, there are additional capacitances. However, the above relationship is a polysilicon good approximation gate W of the gate t capacitance. SiO L ox

n+

n+

gate oxide (good insulator, εox = 3.9ε0) 2

p-type body

VLSI Design


4

Diffusion Capacitance

• • •

CSB, CDB Undesirable, called parasitic capacitance parasitic capacitance Capacitance depends on area and perimeter – Comparable to CG for contacted diffusion – ½ CG for uncontacted – Varies with process

VLSI Design


5

MOSFET Resistance

•

The resistance of a MOSFET transistor must be determined from the Shockley I-V relationships. – However, Ids(Vds, Vgs). – Therefore, Therefore, R – the resistance resistance to current current moving moving from the drain to the source is:

⎛ ∂ I ds ⎞ ⎟⎟ ⎝ ∂V ds ⎠

−1

R = ⎜⎜

•

However, – Shockley models for MOSFET transistor are not accurate enough for modern transistors – Too complicated for hand analysis

VLSI Design


6

Effective Resistance

•

Simplification: treat transistor as resistor – Replace with effective resistance R • Ids = Vds /R

– R averaged across switching range of digital gate • Simulate Simulate the transistor transistor driving driving a known capacitance capacitance and and measure the time constant. • Too inaccura inaccurate te to predict predict current current at any any given given time time – But good enough to predict RC delay

VLSI Design

7


RC Delay Model

•

Use equivalent circuits for MOS transistors – Ideal switch + capacitances and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C • The PMOS PMOS resi resistan stance ce should should actua actually lly be (k’ (k’n /k’p)R

• •

Capacitance proportional to width Resistance inversely proportional to width d

g

d k s

kC

R/k

kC 2R/k

g

g kC

kC s

VLSI Design

s

s k d

kC g

kC d


8

RC Values

•

Capacitance – C = Cg = Cs = Cd = 2 fF/ µm of gate width – Values similar across many processes

•

Resistance – R ≈ 6 KΩ*µm in 0.6um process – Improves with shorter channel lengths

•

Unit transistors – May refer to minimum contacted device (4/2 λ) – Or maybe 1 µm wide device – Doesn’t matter as long as you are consistent

VLSI Design

9


Input Capacitance of the CMOS Inverter

•

The input capacitance of the CMOS inverter can be written as: – Cin = CGN + CGP = (WN + WP) Cpermicron – Cpermicron = COX X L: • COX – the oxide capacitan capacitance ce which depends depends on the the type of oxide used and is inversely dependent on the thickness of the oxide layer. – COX is typically in the range of ~700a ~700a F/ F/ µm2 » a stands a stands for atto atto – – 10-18.

• L – the the len lengt gth h of of the the chan channe nel. l.

VLSI Design


10

Example

•

Calculate the input capacitance for a CMOS inverter with the following characteristics: – COX = 690 aF/ µm2 – WN / LN = 4µm / 2µm – WP / LP = 8µm / 2µm

Using the expressions from above: Cin = (WN + WP) Cpermicron Cpermicron = L COX Cpermicron = 2µm X 690 aF/ µm2 = 1.38 fF/ µm Cin = (4µm + 8µm) X 1.38 fF/ µm Cin = 16.56 fF VLSI Design


11

Inverter Delay Estimate

•

A

Estimate the delay of a fanout-of-1 inverter

2 Y

2

1

1

VLSI Design


12


•

Estimate the delay of a fanout-of-1 inverter 2C R

A

2 Y

2

1

1

2C

2C Y

R

C

C

C

VLSI Design

13



•


A

2 Y

2

1

1

2C

2C

2C

2C

Y R

C

R

C

C

C

C

VLSI Design


14


•


A

2 Y

2

1

1

2C

2C

2C

2C

Y R

C

R

C

C

C

C

d = 6RC VLSI Design


15

Delay Components

•

Delay has two parts – due to capacitances of the – Parasitic delay – due driving gate itself. • 3 RC in the the inver inverter ter exampl example e above. above. • Inde Indepe pend ndent ent of load load..

– due to capacitances of the load – Effort delay – due gates. • The othe otherr 3 RC in the the invert inverter er examp example le above. above. • Dep Depends ends on on the number number and and type type of driven driven gates gates..

VLSI Design


16

Example: 3-input NAND

•

Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

VLSI Design


17


•

Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

VLSI Design


18

Ex.: Capacitances of a 3-input NAND

•

Determine the parasitic capacitances of a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

2

2

2 3 3 3

VLSI Design


19

3-input NAND Caps

•

Annotate the 3-input NAND gate with gate and diffusion capacitance.

2

2

2

3 3 3

VLSI Design


20

3-input NAND Caps

•

Annotate the 3-input NAND gate with gate and diffusion capacitance. 2C 2

2C 2C

2C 2

2C

2

2C

3C 3C 3C

VLSI Design

2C

2C 2C

3 3 3

3C 3C 3C 3C


21

Combining Capacitances

• •

Capacitors on source diffusions of transistors connected to V DD or GND will be shorted out. The DC voltage on the second terminal of a capacitor is irrelevant to delay calculation. – Therefore, all capacitors will be estimated as terminating to GND.

•

Combine parallel and series capacitances in the normal manner.

VLSI Design


22

3-input NAND Caps

•

Annotate the 3-input NAND gate with gate and diffusion capacitance.

2

2

2

9C

3

5C

3C

3

5C

3C

3

5C VLSI Design


23

Elmore Delay

• •

ON transistors look like resistors Pullllup Pu up or pu pulllldo down wn ne netw twor ork k model modeled ed as as RC ladder • Elmore delay of RC ladder t pd ≈ R −i t−o sourcC e i

∑

nodes

=

i

R1 C1 + ( R1 + R2 ) C2 R1

VLSI Design

+ ... + ( R +

R2

R2

R3

RN

C1

C2

1

C3

+ ... +

R N ) CN

CN


24


•

Estimate worst-case rising and falling delay of 2input NAND driving h identical gates. h identical

2

2

A

2

B

2x

Y h copies

VLSI Design


25


•

Estimate rising and falling propagation delays of a 2-input NAND driving h h identical identical gates.

2

2

A

2

B

2x

VLSI Design

6C

Y 4hC

h copies

2C


26


•

Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. h identical

2

2

A

2

B

2x

R

Y (6+4h)C

6C

Y 4hC

h copies

2C

t pdr = ( 6 + 4h ) RC

VLSI Design


27


•

Estimate rising and falling propagation delays of a 2-input NAND driving h h identical identical gates.

2

2

A

2

B

2x

VLSI Design

6C

Y 4hC

h copies

2C


28


•

Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. h identical

2

2

A

2

B

2x

x R/2

R/2 2C

6C

Y 4hC

h copies

2C

Y (6+4h)C

t pdf

= ( 2C ) ( )R+ ⎡⎣( 6 + 4h ) C ⎤⎦ ( +R )R = ( 7 + 4h ) RC 2

VLSI Design

2


2

29

Diffusion Capacitance

• • •

we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact – Reduces output capacitance by 2C – Merged uncontacted diffusion might help too 2C Shared Contacted Diffusion

Isolated Contacted Diffusion

Merged Uncontacted Diffusion

2

2

2 3 3

3C 3C 3C

VLSI Design

2C

3

7C 3C 3C


30

Layout Comparison

•

Which layout is better? VDD

A

VDD

B

A

B

Y

GND

Y

GND

VLSI Design

31


Determining the Total Delay for a Circuit

•

In order to determine the total delay for a circuit, circuit , one has to determine the delay of each stage and then calculate the total delay for all stages combined. – Two delays: rising and falling.

•

Example, using Elmore Delay Model, determine the total delay of the following circuit: IN OUT OUT

12 C

VLSI Design


32

Determine Transistor Sizes IN

P: 2 N: 1

P: 2 N: 2

P: 2 N: 1

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

VLSI Design

33


Assume Logic Transition PUN IN

P: 2 N: 1

PDN

1

P: 2 N: 2

PUN P: 2 N: 1

PDN

0

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

VLSI Design


34

Determine Individual Stage Delays PUN P: 2 N: 1

IN

PDN

PUN

P: 2 N: 2

1

P: 2 N: 1

0

PDN

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

R

4(4C)

3C

d = 19RC

VLSI Design

35


Determine Individual Stage Delays PUN IN

P: 2 N: 1

PDN

PUN

P: 2 N: 2

1

P: 2 N: 1

0

PDN

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

R

6C

3C

d = 9RC

VLSI Design


36


P: 2 N: 1

PDN

1

PUN

P: 2 N: 2

P: 2 N: 1

PDN

0

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

R

5C + 5C + 3C = 13C

3C

d = 16RC

VLSI Design

37



P: 2 N: 1

PDN

1

P: 2 N: 2

PUN P: 2 N: 1

PDN

0

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

R/2

R/2

4C

6C

12C

d = (R/2)4C + (R/2 + R/2) (6C + 12C) = 20RC

VLSI Design


38

Total Rising Output Delay PUN IN

P: 2 N: 1

PDN

1

PUN

P: 2 N: 2

P: 2 N: 1

PDN

0

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

Tpdr =

19RC

+

9RC

VLSI Design

+

16RC

+

20RC =

64RC

39


Other Logic Transition PDN IN

P: 2 N: 1

PUN

1

P: 2 N: 2

PDN P: 2 N: 1

PUN

0

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

VLSI Design


40

Determine Individual Stage Delays PDN P: 2 N: 1

IN

1

PUN

PDN

P: 2 N: 2

P: 2 N: 1

0

PUN

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

R

4(4C)

3C

d = 19RC

VLSI Design

41


Determine Individual Stage Delays PDN IN

P: 2 N: 1

1

PUN

PDN

P: 2 N: 2

P: 2 N: 1

0

PUN

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

R/2

R/2

2C

6C

3C

d = (R/2)2C + (R/2 + R/2) (6C + 3C) = 10RC

VLSI Design


42


P: 2 N: 1

PUN

1

PDN

P: 2 N: 2

P: 2 N: 1

PUN

0

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

R

5C + 5C + 3C = 13C

3C

d = 16RC

VLSI Design

43



P: 2 N: 1

PUN

1

P: 2 N: 2

PDN P: 2 N: 1

PUN

0

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

R

6C

12C

d = 18RC

VLSI Design


44

Total Falling Output Delay PDN IN

P: 2 N: 1

PUN

1

PDN

P: 2 N: 2

P: 2 N: 1

PUN

0

P: 4 N: 1

OUT OUT

12 C

P: 2 N: 3 P: 2 N: 1

Tpdf =

19RC

VLSI Design

+

10RC

+

16RC

+

18RC =

63RC


45

8 Cmos Capacitance

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