GEH-6353B
Instructions
MARK V LM 2''&6410+% 74$+0'10641. Panel Manual
MARK V LM Speedtronic Turbine Control Panel Manual GEH-6353B Issue Date: January, 1996 Revision A: Never Issued Revision B: February 1998
This document contains proprietary information of General Electric Company, U.S.A. and is furnished to its customer solely to assist that customer in the installation, testing, and/or maintenance of the equipment described herein. This document shall not be reproduced in whole or in part, nor shall its contents be disclosed to any third party without the prior written approval of GE Industrial Control Systems, Salem, Virginia, U.S.A. 24153. The information contained herein does not purport to cover all details or variations in equipment nor to provide for every possible contingency to be met during installation, operation and maintenance. Should further information be desired or should particular problems arise that are not covered sufficiently for the purchaser’s purposes, the matter should be referred to GE Industrial Control Systems, Salem, Virginia, U.S.A. 24153.
Copyright© 1998 by General Electric Company, U.S.A. All rights reserved. Printed in the United States of America. February 25, 1998
ARCNET is a registered trademark of Datapoint Corporation. Ethernet is a trademark of Xerox Corporation. HP is a trademark of Hewlett Packard Company. MODBUS is a trademark of Gould Inc. Proximitor is a registered trademark of Bentley Nevada Corporation. Speedtronic is a trademark of General Electric Company, USA. QNX is a registered trademark of Quantum Software Systems Ltd.
Safety Symbol Legend
WARNING Commands attention to an operating procedure, practice, condition or statement, which, if not strictly observed, could result in personal injury or death.
CAUTION Commands attention to an operating procedure, practice, condition or statement, which, if not strictly observed, could result in damage to or destruction of equipment.
Note Commands attention to an essential operating or maintenance procedure, condition, or statement that must be highlighted.
WARNING This equipment contains a potential hazard of electric shock or burn. Only personnel who are adequately trained and thoroughly familiar with the equipment and the instructions should install, operate, or maintain this equipment. Isolation of test equipment from the equipment under test presents potential electrical hazards. If the test equipment cannot be grounded to the equipment under test, the test equipment’s case must be shielded to prevent contact by personnel. To minimize hazard of electrical shock or burn, approved grounding practices and procedures must be strictly followed. To prevent personal injury or equipment damage caused by equipment malfunction, only adequately trained persons should modify any programmable machine.
Safety Symbol Legend (cont.)
Notes:
Mark V LM Turbine Control Manual
GEH-6353B
7DEOHRI&RQWHQWV CHAPTER 1 OVERVIEW 1-1. DEFINITION AND SCOPE ................................................................................................................................................1-1 1-2. EQUIPMENT OVERVIEW ................................................................................................................................................1-1 1-2.1. Mark V LM Control Panel ............................................................................................................................................1-1 1-2.2. Operator Interface .........................................................................................................................................................1-3 1-2.3. Communications ...........................................................................................................................................................1-3 1-2.3.1 STAGE LINK. ........................................................................................................................................................1-3 1-2.3.2. COREBUS. .............................................................................................................................................................1-4 1-2.3.3. IONET. ...................................................................................................................................................................1-4 1-2.3.4. THE ARCNET INTERFACE BOARD. .................................................................................................................1-5 1-3. RELATED DOCUMENTATION .......................................................................................................................................1-5 CHAPTER 2 2-1. 2-2. 2-3. 2-4. 2-5.
RECEIVING, HANDLING, AND STORAGE
INTRODUCTION ...............................................................................................................................................................2-1 RECEIVING AND HANDLING ........................................................................................................................................2-1 STORAGE ...........................................................................................................................................................................2-1 UNPACKING......................................................................................................................................................................2-2 TIME LIMITATIONS .........................................................................................................................................................2-3
CHAPTER 3
INSTALLATION AND INITIAL POWERUP
3-1. INTRODUCTION ...............................................................................................................................................................3-1 3-2. OPERATING ENVIRONMENT.........................................................................................................................................3-1 3-3. CABLING, WIRING, AND POWER SOURCES...............................................................................................................3-2 3-3.1. Spacing .........................................................................................................................................................................3-2 3-3.2. Power Sources ..............................................................................................................................................................3-2 3-3.3. Equipment Grounding...................................................................................................................................................3-4 3-4. POWER-OFF CHECKS ......................................................................................................................................................3-4 3-4.1. Control Panel Inspection...............................................................................................................................................3-4 3-4.2. Board Inspections .........................................................................................................................................................3-5 3-4.3. Wiring and Circuit Checks............................................................................................................................................3-5 3-5. CONTROL PANEL INITIAL ENERGIZATION ...............................................................................................................3-6 3-6. OPERATOR INTERFACE INSTALLATION AND STARTUP .......................................................................................3-7 3-6.1 Equipment Overview .....................................................................................................................................................3-7 3-6.2 Installation and Initial Startup........................................................................................................................................3-8 3-7 CONTROL PROCESSOR STARTUP .................................................................................................................................3-8 3-7.1 Setting the Stage Link ....................................................................................................................................................3-9 CHAPTER 4
FUNCTIONAL DESCRIPTION
4-1. INTRODUCTION ...............................................................................................................................................................4-1 4-2. HARDWARE STRUCTURE ..............................................................................................................................................4-1 4-3. APPLICATION SOFTWARE STRUCTURE.....................................................................................................................4-3 4-3.1. Big Block System .........................................................................................................................................................4-3 4-4. CONTROLLER OPERATION............................................................................................................................................4-4 4-5. CORE CONNECTION DRAWINGS..................................................................................................................................4-4
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7DEOHRI&RQWHQWV FRQW CHAPTER 5
PRINTED WIRING BOARD DESCRIPTIONS AND INTERCONNECTIONS
5-1. INTRODUCTION .............................................................................................................................................................. 5-1 5-2. BOARD IDENTIFICATION.............................................................................................................................................. 5-1 5-3. INITIAL CONFIGURATION ............................................................................................................................................ 5-1 5-3.1. Initial Hardware Jumper Settings ................................................................................................................................. 5-2 5-3.2. Adjusting Replacement Boards .................................................................................................................................... 5-2 5-3.3. I/O Board Software Configuration ............................................................................................................................... 5-2 5-4. PRINTED WIRING BOARDS........................................................................................................................................... 5-3 5-4.1. DS200AAHA – ARCNET Connection Board ............................................................................................................. 5-3 5-4.1.1. AAHA CONNECTORS........................................................................................................................................ 5-3 5-4.1.2. AAHA CONFIGURATION. ................................................................................................................................ 5-3 5-4.2. DS200PANA – ARCNET No-LAN Driver Board ...................................................................................................... 5-3 5-4.2.1. PANA CONNECTORS. ....................................................................................................................................... 5-4 5-4.2.2. PANA CONFIGURATION. ................................................................................................................................. 5-4 5-4.3. DS200STCA – Turbine Communication Board .......................................................................................................... 5-4 5-4.3.1. STCA CONNECTORS. ........................................................................................................................................ 5-5 5-4.3.2. STCA CONFIGURATION................................................................................................................................... 5-5 5-4.3.3. STCA PULSE RATE INPUT CIRCUIT. ............................................................................................................. 5-5 5-4.3.4. STCA SYNCH CHECK CIRCUIT....................................................................................................................... 5-5 5-4.4. DS200TCCA – COMMON ANALOG I/O BOARD................................................................................................... 5-5 5-4.4.1. TCCA CONNECTORS. ....................................................................................................................................... 5-6 5-4.4.2. TCCA CONFIGURATION. ................................................................................................................................. 5-6 5-4.4.3. TCCA 4–20 MA INPUT CIRCUIT. ..................................................................................................................... 5-6 5-4.4.4. TCCA 4–20 MA OUTPUT CIRCUIT. ................................................................................................................. 5-6 5-4.4.5. TCCA RTD CIRCUIT. ......................................................................................................................................... 5-6 5-4.4.6. TCCA THERMOCOUPLE CIRCUIT. ................................................................................................................. 5-6 5-4.4.7. TCCA SHAFT MONITORING. ........................................................................................................................... 5-6 5-4.5. DS200TCCB – Common Extended Analog I/O Board ................................................................................................ 5-7 5-4.5.1. TCCB CONNECTORS......................................................................................................................................... 5-7 5-4.5.2. TCCB CONFIGURATION. ................................................................................................................................. 5-7 5-4.5.3. TCCB 4–20 MA INPUT CIRCUIT. ..................................................................................................................... 5-7 5-4.5.4. TCCB RTD CIRCUIT. ......................................................................................................................................... 5-7 5-4.5.4. TCCB GENERATOR AND BUS VOLTAGE, LINE CURRENT CIRCUITS. .................................................. 5-7 5-4.6. DS200TCDA – Digital I/O Board ............................................................................................................................... 5-8 5-4.6.1. TCDA CONNECTORS. ....................................................................................................................................... 5-8 5-4.6.2. TCDA CONFIGURATION. ................................................................................................................................. 5-8 5-4.6.3. TCDA CONTACT INPUT CIRCUITS. ............................................................................................................... 5-8 5-4.6.4. TCDA CONTACT OUTPUT (RELAY/SOLENOID) CIRCUITS. ..................................................................... 5-8 5-4.7. DS200TCEA – Emergency Overspeed Board ............................................................................................................. 5-9 5-4.7.1. TCEA CONNECTORS......................................................................................................................................... 5-9 5-4.7.2. TCEA CONFIGURATION. ................................................................................................................................. 5-9 5-4.7.3. TCEA FLAME DETECTION CIRCUIT. .......................................................................................................... 5-10 5-4.7.4. TCEA TURBINE OVERSPEED CIRCUIT. ...................................................................................................... 5-10 5-4.7.5. TCEA AUTOMATIC SYNCHRONIZING CIRCUIT. ...................................................................................... 5-10 5-4.8. DS200TCEB – Protective Termination Expander Board .......................................................................................... 5-10 5-4.8.1. TCEB CONNECTORS. ...................................................................................................................................... 5-11 5-4.8.2. TCEB CONFIGURATION................................................................................................................................. 5-11 5-4.8.3. TCEB PT AND CT CIRCUIT. ........................................................................................................................... 5-11 5-4.8.4. TCEB FLAME DETECTION CIRCUIT. ........................................................................................................... 5-11 5-4.8.5. TCEB EMERGENCY OVERSPEED CIRCUIT. ............................................................................................... 5-11
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7DEOHRI&RQWHQWV FRQW 5-4.9 DS200TCPD – Power Distribution Module ................................................................................................................5-11 5-4.9.1. TCPD CONNECTORS........................................................................................................................................5-12 5-4.9.2. TCPD CONFIGURATION. ................................................................................................................................5-12 5-4.9.3. TCPD SWITCHES. .............................................................................................................................................5-13 5-4.9.4. TCPD POWER. ...................................................................................................................................................5-13 5-4.10. DS200TCPS – Power Supply Board.........................................................................................................................5-13 5-4.10.1. TCPS CONNECTORS. .....................................................................................................................................5-13 5-4.10.2. TCPS CONFIGURATION. ...............................................................................................................................5-13 5-4.11. DS200TCQA – Analog I/O Board ............................................................................................................................5-14 5-4.11.1. TCQA CONNECTORS. ....................................................................................................................................5-14 5-4.11.2. TCQA CONFIGURATION. ..............................................................................................................................5-14 5-4.11.3. TCQA PULSE RATE INPUT CIRCUIT. .........................................................................................................5-14 5-4.11.4. TCQA 4–20 MA INPUT CIRCUITS. ...............................................................................................................5-14 5-4.11.5. TCQA 4–20 MA OUTPUT CIRCUIT. .............................................................................................................5-14 5-4.11.6. TCQA THERMOCOUPLE CIRCUIT. .............................................................................................................5-15 5-4.11.7. TCQA LVDT/R CIRCUIT. ...............................................................................................................................5-15 5-4.11.8. TCQA SEISMIC VIBRATION CIRCUIT. .......................................................................................................5-15 5-4.11.9. TCQA GENERATOR AND LINE CIRCUIT. ..................................................................................................5-15 5-4.12. DS200TCQC – ANALOG I/O EXPANDER BOARD..............................................................................................5-15 5-4.12.1. TCQC CONNECTORS. ....................................................................................................................................5-16 5-4.12.2. TCQC CONFIGURATION. ..............................................................................................................................5-16 5-4.12.3. TCQC SERVO VALVE REGULATOR OUTPUT CIRCUIT. .........................................................................5-16 5-4.12.4. TCQC PULSE RATE INPUT CIRCUIT. ..........................................................................................................5-17 5-4.12.5. TCQC GENERATOR AND LINE FEEDBACK. .............................................................................................5-17 5-4.12.6. TCQC IONET CIRCUIT. ..................................................................................................................................5-17 5-4.12.7. TCQC LVDT/LVDR EXCITATION CIRCUIT. ..............................................................................................5-17 5-4.12.8. TCQC 4–20 MA INPUT CIRCUITS. ...............................................................................................................5-17 5-4.13. DS200TCQE – LM 6000 I/O Processor ...................................................................................................................5-17 5-4.13.1. TCQE CONNECTORS. ....................................................................................................................................5-17 5-4.13.2. TCQE CONFIGURATION. ..............................................................................................................................5-18 5-4.13.3. TCQE LVDT/LVDR CIRCUIT.........................................................................................................................5-18 5-4.13.4. TCQE 4–20 MA OUTPUT CIRCUIT. ..............................................................................................................5-18 5-4.13.5. TCQE LM VIBRATION INPUTS. ...................................................................................................................5-18 5-4.13.6. TCQE PROXIMETER VIBRATION INPUTS. ................................................................................................5-18 5-4.13.7. TCQE RTD CIRCUIT. ......................................................................................................................................5-18 5-4.13.8. TCQE PULSE RATE CIRCUIT. ......................................................................................................................5-18 5-4.13.9. TCQE LP SHAFT SHEAR CIRCUIT. ..............................................................................................................5-18 5-4.13.10. TCQE LOAD COUPLING SHEAR CIRCUIT. ..............................................................................................5-18 5-4.14. DS200TCRA – Relay Output Board.........................................................................................................................5-19 5-4.14.1. TCRA CONNECTORS. ....................................................................................................................................5-19 5-4.14.2. TCRA CONFIGURATION. ..............................................................................................................................5-20 5-4.14.3. TCRA CONTACT OUTPUT CIRCUIT. ..........................................................................................................5-20 5-4.15. DS200TCSA – Fuel Skid Interface Board ................................................................................................................5-20 5-4.15.1. TCSA CONNECTORS......................................................................................................................................5-20 5-4.15.2. TCSA CONFIGURATION................................................................................................................................5-20 5-4.15.3. TCSA PRESSURE TRANSDUCER INTERFACE. .........................................................................................5-20 5-4.16. DS200TCTG – Turbine Trip Board .........................................................................................................................5-21 5-4.16.1. TCTG CONNECTORS. ....................................................................................................................................5-21 5-4.16.2. TCTG CONFIGURATION. ..............................................................................................................................5-21 5-4.16.3. TCTG ETR RELAY CIRCUIT. ........................................................................................................................5-21 5-4.16.4. TCTG PTR RELAY CIRCUIT. ........................................................................................................................5-22
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7DEOHRI&RQWHQWV FRQW 5-4.16.5. TCTG GENERATOR BREAKER CLOSE CIRCUIT. .................................................................................... 5-22 5-4.16.6. TCTG MANUAL AND EXTERNAL TRIP CIRCUIT. ................................................................................... 5-22 5-4.17. DS200UCIA – UC2000 Mother Board .................................................................................................................... 5-22 5-4.17.1. UCIA CONNECTORS. .................................................................................................................................... 5-23 5-4.17.2. UCIA CONFIGURATION. .............................................................................................................................. 5-23 5-4.17.3. UCIA PRESSURE TRANSDUCER INTERFACE CIRCUIT. ........................................................................ 5-23 5-4.17.4. UCIA PANA BOARD AND UCPB BOARD COMMUNICATION CIRCUIT. ............................................. 5-23 5-4.17.5. UCIA GENIUS I/O CIRCUIT. ......................................................................................................................... 5-23 5-4.18. DS200UCPB – CPU Board ..................................................................................................................................... 5-24 5-4.18.1. UCPB CONTROL ENGINE. ........................................................................................................................... 5-24 5-4.18.1.1. UCPB Connectors. ..................................................................................................................................... 5-24 5-4.18.1.2. UCPB Configuration. ................................................................................................................................. 5-24 5-4.18.2. UCPB I/O ENGINE. ......................................................................................................................................... 5-24 5-4.18.2.1. UCPB Connectors. ..................................................................................................................................... 5-25 5-4.18.2.2. UCPB Configuration. ................................................................................................................................. 5-25 5-5. PRINTED WIRING TERMINAL BOARDS ................................................................................................................... 5-25 5-5.1. DS200CTBA -Termination Module .......................................................................................................................... 5-25 5-5.1.1. CTBA CONNECTIONS. .................................................................................................................................... 5-26 5-5.1.2. CTBA HARDWARE CONFIGURATION. ....................................................................................................... 5-26 5-5.2. DS200DTBA – Contact Input Termination Module .................................................................................................. 5-26 5-5.2.1. DTBA CONNECTIONS..................................................................................................................................... 5-26 5-5.2.2. DTBA HARDWARE CONFIGURATION. ....................................................................................................... 5-26 5-5.3. DS200DTBB – Contact Input Expansion Termination Module ................................................................................ 5-27 5-5.3.1. DTBB CONNECTORS. ..................................................................................................................................... 5-27 5-5.3.2. DTBB HARDWARE CONFIGURATION. ....................................................................................................... 5-27 5-5.4. DS200DTBC – Contact Output Termination Module ............................................................................................... 5-27 5-5.4.1. DTBC CONNECTORS. ..................................................................................................................................... 5-27 5-5.4.2. DTBC HARDWARE CONFIGURATION. ....................................................................................................... 5-27 5-5.5. DS200DTBD – Contact Output Expansion Termination Module.............................................................................. 5-28 5-5.5.1. DTBD CONNECTORS. ..................................................................................................................................... 5-28 5-5.5.2. DTBD HARDWARE CONFIGURATION. ....................................................................................................... 5-28 5-5.6. DS200PTBA – Protection Termination Module ........................................................................................................ 5-28 5-5.6.1. PTBA CONNECTORS. ...................................................................................................................................... 5-29 5-5.6.2. PTBA HARDWARE CONFIGURATION. ........................................................................................................ 5-29 5-5.7. DS200QTBA – Termination Module......................................................................................................................... 5-29 5-5.7.1. QTBA CONNECTIONS..................................................................................................................................... 5-29 5-5.7.2. QTBA HARDWARE CONFIGURATION. ....................................................................................................... 5-30 5-5.8. DS200TBCA – Termination Module RTD Inputs ..................................................................................................... 5-30 5-5.8.1. TBCA CONNECTIONS..................................................................................................................................... 5-30 5-5.8.2. TBCA HARDWARE CONFIGURATION. ....................................................................................................... 5-30 5-5.9. DS200TBCB – Termination Module RTD and 4–20 mA Input ................................................................................ 5-30 5-5.9.1. TBCB CONNECTIONS. .................................................................................................................................... 5-30 5-5.9.2. TBCB HARDWARE CONFIGURATION......................................................................................................... 5-30 5-5.10. DS200TBQA – Thermocouple Termination Module .............................................................................................. 5-31 5-5.10.1. TBQA CONNECTIONS................................................................................................................................... 5-31 5-5.10.2. TBQA HARDWARE CONFIGURATION. ..................................................................................................... 5-31 5-5.11. DS200TBQB – Input Termination Module ............................................................................................................. 5-31 5-5.11.1. TBQB CONNECTIONS. .................................................................................................................................. 5-31 5-5.11.2. TBQB HARDWARE CONFIGURATION. ..................................................................................................... 5-32 5-5.12. DS200TBQC – Analog Input, Milliamp Input/Output Termination Module ........................................................... 5-32 5-5.12.1. TBQC CONNECTIONS. .................................................................................................................................. 5-32
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7DEOHRI&RQWHQWV FRQW 5-5.12.2. TBQC HARDWARE CONFIGURATION. ......................................................................................................5-32 5-5.13. DS200TBQE – LM6000 Analog Termination Module ............................................................................................5-33 5-5.12.1. TBQE CONNECTIONS. ...................................................................................................................................5-33 5-5.13.2. TBQE HARDWARE CONFIGURATION. ......................................................................................................5-33 5-6. TERMINAL BOARDS......................................................................................................................................................5-33 5-6.1. TB1 .................................................................................................................... .........................................................5-33 5-6.2. TB2 .................................................................................................................... .........................................................5-33 5-6.3. TB3 .................................................................................................................... .........................................................5-34 5-6.4. 1TB .................................................................................................................... .........................................................5-34 CHAPTER 6
GENERAL INPUT AND OUTPUT CAPACITIES AND SPECIFICATIONS
6-1. CONTACT INPUTS ...........................................................................................................................................................6-1 6-2. CONTACT and SOLENOID OUTPUTS ............................................................................................................................6-1 6-3. THERMOCOUPLE INPUTS ..............................................................................................................................................6-2 6-4. RESISTANCE TEMPERATURE DEVICE (RTD) INPUTS .............................................................................................6-3 6-5. SEISMIC (VELOCITY) VIBRATION MEASUREMENT DEVICE INPUTS ..................................................................6-4 6-6. PROXIMITY TRANSDUCER INPUTS .............................................................................................................................6-4 6-7. FLAME DETECTOR INPUTS ...........................................................................................................................................6-4 6-8. PULSE RATE INPUTS .......................................................................................................................................................6-5 6-9. LVDT/LVDR POSITION FEEDBACK INPUTS ...............................................................................................................6-5 6-10. SERVO VALVE OUTPUTS .............................................................................................................................................6-6 6-11. ANALOG VOLTAGE AND CURRENT INPUTS AND OUTPUTS ..............................................................................6-6 CHAPTER 7
APPLICATION SPECIFIC FUNCTIONS
7-1. PULSE RATE INPUTS .......................................................................................................................................................7-1 7-2. THE MASTER TRIP CIRCUIT AND THE PROTECTION CORE ..................................................................................7-1 7-2.1. The Trip Board: TCTG .................................................................................................................................................7-4 7-3. SETTING THE PRIMARY AND EMERGENCY OVERSPEED TRIP SETPOINTS ......................................................7-5 7-3.1. Primary Overspeed Protection ......................................................................................................................................7-5 7-3.2. Emergency Overspeed Protection .................................................................................................................................7-6 7-4. SERVO VALVE DRIVE SYSTEM ....................................................................................................................................7-6 7-4.1. The Servo Valve ...........................................................................................................................................................7-6 7-4.2. Regulator Feedback Devices.........................................................................................................................................7-7 7-4.2.1. LVDT OR LVDR POSITION FEEDBACK. ........................................................................................................7-7 7-4.2.2. PRESSURE FEEDBACK......................................................................................................................................7-7 7-5. FLAME DETECTION ........................................................................................................................................................7-7 7-6. VIBRATION MEASUREMENT AND PROTECTION .....................................................................................................7-8 7-6.1. Seismic (Velocity) Sensors ...........................................................................................................................................7-8 7-6.1.1. CONFIGURING SEISMIC VIBRATION PICKUPS IN THE MARK V LM. .....................................................7-9 7-6.2. Accelerometer Inputs ....................................................................................................................................................7-9 7-6.3. Proximity Transducer Inputs.........................................................................................................................................7-9 7-7. SHAFT VOLTAGE AND CURRENT MONITOR INPUTS ...........................................................................................7-11 CHAPTER 8
TROUBLESHOOTING
8-1. INTRODUCTION ...............................................................................................................................................................8-1 8-2. GENERAL TROUBLESHOOTING ...................................................................................................................................8-2 8-3. I/O CORE TROUBLESHOOTING .....................................................................................................................................8-3 8-3.1. TIMN (Terminal Interface Monitor) .............................................................................................................................8-4
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7DEOHRI&RQWHQWV FRQW 8-3.1.1. CHECKING THE PROM REVISION LEVEL(S) OF THE BOARD(S) WITH THE LOWEST I/O STATUS. 8-5 8-3.2 Checking I/O Board Ionet Termination Resistor and Address Hardware Jumpers ....................................................... 8-7 8-4. TROUBLESHOOTING WITH THE OPERATOR INTERFACE ..................................................................................... 8-7 8-4.1 Diagnostic Alarm Display............................................................................................................................................. 8-8 CHAPTER 9
PARTS REPLACEMENT
9-1. INTRODUCTION .............................................................................................................................................................. 9-1 9-2. REPLACING BOARDS ..................................................................................................................................................... 9-1 9-3. REPLACING EPROMS ..................................................................................................................................................... 9-2 9-4. PREVENTATIVE MAINTENANCE ................................................................................................................................ 9-3 9-5. RENEWAL PARTS............................................................................................................................................................ 9-4 9-5.1 Part Numbers ................................................................................................................................................................ 9-5 CHAPTER 10
STAGE LINK CONFIGURATIONS
10-1. OVERVIEW ................................................................................................................................................................... 10-1 10-2. INTRODUCTION .......................................................................................................................................................... 10-1 10-2.1. Terms of Reference .................................................................................................................................................. 10-1 10-3. STAGE LINK CHARACTERISTICS ............................................................................................................................ 10-1 10-3.1. The Mark V LM Panel ............................................................................................................................................ 10-2 10-3.2. The Operator Interface ............................................................................................................................................. 10-2 10-4. CABLE RECOMMENDATIONS .................................................................................................................................. 10-3 10-5. STAGE LINK RULES.................................................................................................................................................... 10-4 10-6. SEGMENT RULES ........................................................................................................................................................ 10-4 10-7. TOTAL EFFECTIVE DISTANCE RULES ................................................................................................................... 10-6 10-8. EXAMPLES ................................................................................................................................................................... 10-6 10-8.1. Example 1: A Simple Plant Application .................................................................................................................. 10-6 10-8.3. Example 2: Complex Plant Application ................................................................................................................... 10-7 10-9. FIBER OPTICS .............................................................................................................................................................. 10-8 10-9.1. Advantages............................................................................................................................................................... 10-8 10-9.2. Disadvantages .......................................................................................................................................................... 10-9 10-9.3. Review of Components ............................................................................................................................................ 10-9 10-9.3.1. BASICS. ........................................................................................................................................................... 10-9 10-9.3.2. CABLE. .......................................................................................................................................................... 10-10 10-9.3.3. HUBS.............................................................................................................................................................. 10-10 10-9.3.4. CONNECTORS. ............................................................................................................................................. 10-10 10-9.4. System Considerations ........................................................................................................................................... 10-11 10-9.5. Installation ............................................................................................................................................................. 10-11 10-9.6. Specifications ......................................................................................................................................................... 10-11 10-9.6.1. FOUR FIBER CABLE WITHOUT ARMOR................................................................................................. 10-12 10-9.6.2. FOUR FIBER CABLE WITH ARMOR. ........................................................................................................ 10-13 10-9.6.3. FIBER OPTIC HUB. ...................................................................................................................................... 10-14 10-9.6.4. FIBER OPTIC CONNECTORS. .................................................................................................................... 10-14 10-10. TYPICAL STAGE LINK ADDRESSES.................................................................................................................... 10-14 APPENDIX A
HARDWARE JUMPERS
A-1. INTRODUCTION............................................................................................................................................................A-1 A-1.1. Table Formatting.........................................................................................................................................................A-1 A-1.2. Hardware Jumper Configurations................................................................................................................................A-2
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7DEOHRI&RQWHQWV FRQW APPENDIX B
HARDWARE DOCUMENTS
APPENDIX C
POWER DISTRIBUTION CORE DIAGRAMS
C-1. INTRODUCTION AND APPLICATION NOTES ........................................................................................................... C-1 C-2. SPECIAL USE CONTACT OUTPUTS AND RELATED COMPONENTS .................................................................... C-6 APPENDIX D
SIGNAL FLOW DIAGRAMS
D-1. DEFINITIONS OF ABBREVIATIONS............................................................................................................................D-2 D-2. SIGNAL FLOW DIAGRAMS...........................................................................................................................................D-3 APPENDIX E
FUSE RATINGS
E-1. POWER DISTRIBUTION - TCPD ................................................................................................................................... E-1 E-2. POWER SUPPLY - TCPS ................................................................................................................................................. E-2 E-3. POWER SUPPLY - TCEA ................................................................................................................................................ E-2
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/LVWRI)LJXUHV Figure 1-1. Mark V LM Panel Layout............................................................................................................................................ 1-2 Figure 1-2. Three Port Active Repeater ......................................................................................................................................... 1-4 Figure 5-1. Sample board part number, DS series........................................................................................................................ 5-35 Figure 5-2. AAHA board layout................................................................................................................................................... 5-36 Figure 5-3. PANA board layout ................................................................................................................................................... 5-37 Figure 5-4. STCA board layout .................................................................................................................................................... 5-38 Figure 5-5. TCCA board layout. .................................................................................................................................................. 5-39 Figure 5-6. TCCB board layout.................................................................................................................................................... 5-40 Figure 5-7. TCDA board layout. .................................................................................................................................................. 5-41 Figure 5-8. TCEA board layout.................................................................................................................................................... 5-42 Figure 5-9. TCEB board layout.................................................................................................................................................... 5-43 Figure 5-10. TCPD board layout.................................................................................................................................................. 5-44 Figure 5-11. TCPS board layout. ................................................................................................................................................. 5-45 Figure 5-12. TCQA board layout. ................................................................................................................................................ 5-46 Figure 5-13. TCQC board layout. ............................................................................................................................................... 5-47 Figure 5-14. TCQE board layout.................................................................................................................................................. 5-48 Figure 5-15. TCRA board layout. ................................................................................................................................................ 5-49 Figure 5-16. TCSA board layout. ................................................................................................................................................. 5-50 Figure 5-17. TCTG board layout.................................................................................................................................................. 5-51 Figure 5-18. UCIA board layout. ................................................................................................................................................. 5-52 Figure 5-19. UCPB board layout.................................................................................................................................................. 5-53 Figure 5-20. CTBA terminal board layout. .................................................................................................................................. 5-54 Figure 5-21. DTBA terminal board layout. .................................................................................................................................. 5-54 Figure 5-22. DTBB terminal board layout. .................................................................................................................................. 5-54 Figure 5-23. DTBC terminal board layout. .................................................................................................................................. 5-55 Figure 5-24. DTBD terminal board layout. .................................................................................................................................. 5-55 Figure 5-25. PTBA terminal board layout.................................................................................................................................... 5-55 Figure 5-26. QTBA terminal board layout. .................................................................................................................................. 5-56 Figure 5-27. TBCA terminal board layout. .................................................................................................................................. 5-56 Figure 5-28. TBCB terminal board layout. .................................................................................................................................. 5-56 Figure 5-29. TBQA terminal board. ............................................................................................................................................. 5-57 Figure 5-30. TBQB terminal board layout. .................................................................................................................................. 5-57 Figure 5-31. TBQC terminal board layout. .................................................................................................................................. 5-57 Figure 5-32. TBQE terminal board layout. .................................................................................................................................. 5-58 Figure 7-1. Simplified Block Diagram - TCEA Boards ................................................................................................................. 7-3 Figure 8-1. Pinout connections for DB-9 TIMN Interface Cable ................................................................................................... 8-4 Figure A-1. Table Formatting.........................................................................................................................................................A-1 Figure A-2. Feedback Resistors ...................................................................................................................................................A-11 Figure A-3. Feedback Jumpers.....................................................................................................................................................A-11 Figure B-1. Hardware document example – Panel Layout.............................................................................................................B-2 Figure B-2. Hardware document example –
core. ................................................................................................................B-3 Figure B-3. Hardware document example – core. ................................................................................................................B-4 Figure B-4. Hardware document example – core. ................................................................................................................B-5 Figure B-5. Hardware document example – core. ..................................................................................................................B-6 Figure B-6. Hardware document example – core.................................................................................................................B-7 Figure B-7. Hardware document example – core. ................................................................................................................B-8 Figure B-8. Hardware document example – core. ...............................................................................................................B-9 Figure B-9. Hardware document example – core.............................................................................................................B-10 Figure B-10. Hardware document example – core...........................................................................................................B-11 Figure C-1. Core Incoming AC & DC Circuits....................................................................................................................C-2 Figure C-2. Core DC Power Distribution ............................................................................................................................C-3 Figure C-3. Core AC Power Distribution ............................................................................................................................C-4
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/LVWRI)LJXUHV FRQW Figure C-4. Contact Output 16 Circuit ........................................................................................................................................... C-6 Figure C-5. Contact Ouput 17 Circuit ............................................................................................................................................ C-7 Figure C-6. Contact Output 18 Circuit ........................................................................................................................................... C-8 Figure D-1. Milliamp Input Connection Examples and Notes .......................................................................................................D-8 Figure D-2. core – Stage Link connections AAHA/UCPB ....................................................................................................D-9 Figure D-3. core – COREBUS connections AAHA/PANA.................................................................................................D-10 Figure D-4. core – RTD inputs TBQE/TCQE ...................................................................................................................D-11 Figure D-5. core – Pulse Rate inputs on TBQE .................................................................................................................D-13 Figure D-6. core – LVDT/R excitation and feedback signal on QTBA/TBQE .................................................................D-14 Figure D-7. core – 4–20/200 mA outputs on TBQE .......................................................................................................D-15 Figure D-8. core – Vibration Inputs on TBQE...................................................................................................................D-17 Figure D-9. core – Proximity Transducer inputs on TBQE ...............................................................................................D-18 Figure D-10. core – Proximity Transducer inputs on TBQE .............................................................................................D-19 Figure D-11. core – Proximity Transducer inputs on TBQE .............................................................................................D-20 Figure D-12. , and cores – 4–20 mA inputs on TBQC................................................................................D-21 Figure D-13. , and cores – LVDT/R excitation and feedback on QTBA/TBQC ............................................D-22 Figure D-14. , and cores – LVDT/R excitation and feedback on QTBA/TBQC ............................................D-23 Figure D-15. , and cores – Servo outputs on QTBA/TCQC ...........................................................................D-24 Figure D-16. , and cores – Servo outputs on QTBA/TCQC ...........................................................................D-24 Figure D-17. , and cores – Thermocouple inputs on TBQA ...........................................................................D-25 Figure D-18. , and cores – MegaWatt Transducer inputs on QTBA ...............................................................D-26 Figure D-19. , and cores - Pulse Rate inputs on QTBA ..................................................................................D-28 Figure D-20. , and cores – Pulse Rate inputs on QTBA .................................................................................D-29 Figure D-21. , and cores – 4–20 mA outputs on TBQC ..............................................................................D-30 Figure D-22. , and cores – TIMN monitor and IONET connections on QTBA ..............................................D-31 Figure D-23. , and cores – Power Supply monitoring .....................................................................................D-32 Figure D-24. and cores – Vibration inputs on TBQB ..............................................................................................D-33 Figure D-25. and cores – Analog Current and Voltage inputs on TBQB.................................................................D-34 Figure D-26. and cores – Compressor Stall Detector/milliamp input on TBQB ......................................................D-35 Figure D-27. core – 4–20 mA inputs on CTBA .............................................................................................................D-36 Figure D-28. core – 4–20 mA inputs on TBCB .............................................................................................................D-37 Figure D-29. core – 0–1 and 4–20 mA inputs on TBCB ...................................................................................................D-38 Figure D-30. core – Thermocouple inputs on TBQA/TCCA .............................................................................................D-39 Figure D-31. core – Thermocouple inputs on TBQA/TCCA .............................................................................................D-40 Figure D-32. core – Thermocouple inputs on TBQA/TCCA .............................................................................................D-41 Figure D-33. core – RTD inputs on TBCA/TCCA ............................................................................................................D-43 Figure D-34. core – RTD inputs on TBCA/TCCA ...........................................................................................................D-44 Figure D-35. core – RTD inputs on TBCB/TCCB.............................................................................................................D-45 Figure D-36. core – 4–20 mA outputs on CTBA .............................................................................................................D-46 Figure D-37. core – Shaft Voltage monitoring on CTBA ..................................................................................................D-47 Figure D-38. core – TIMN monitor and IONET connection on CTBA .............................................................................D-48 Figure D-39. core – COREBUS connection on CTBA ......................................................................................................D-49 Figure D-40. and cores – Ignition Transformer on DTBD ..................................................................................D-50 Figure D-41. and cores – Digital inputs on DTBA ..............................................................................................D-51 Figure D-42. and cores – Digital inputs on DTBB ..............................................................................................D-52 Figure D-43. and cores – Relay outputs on DTBC ..............................................................................................D-53 Figure D-44. and cores – Relay outputs on DTBD ..............................................................................................D-54 Figure D-45. core – Emergency Trip Pushbutton connections on PTBA ...........................................................................D-56 Figure D-46. core – Circuit breaker (52G) close circuit .....................................................................................................D-57 Figure D-47. core – Emergency Trip circuit ......................................................................................................................D-58 Figure D-48. core – Overspeed magnetic pick ups on PTBA.............................................................................................D-59
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/LVWRI)LJXUHV FRQW Figure D-49. Figure D-50. Figure D-51. Figure D-52. Figure D-53.
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core – Flame intensity inputs on PTBA ........................................................................................................D-60 core – Bus Generator PT and CT inputs on PTBA .......................................................................................D-60 core – Alarm Horn circuit and Bus Generator continued ..............................................................................D-61 core – Generator Voltage and Current signal interface .................................................................................D-62 Mark V LM Synchronize ........................................................................................................................................D-63
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/LVWRI7DEOHV Table 3-1. Power Source Requirements ..........................................................................................................................................3-2 Table 3-2. Power Supply Voltages and Test Points ........................................................................................................................3-7 Table 3-3. Stage Link Values. .........................................................................................................................................................3-9 Table 6-1. Contact Inputs ................................................................................................................................................................6-1 Table 6-2. Contact Outputs .............................................................................................................................................................6-2 Table 6-3. Electromechanical Relay Contacts.................................................................................................................................6-2 Table 6-4. Thermocouple Inputs .....................................................................................................................................................6-3 Table 6-5. Thermocouple Ranges ...................................................................................................................................................6-3 Table 6-6. RTD Inputs ....................................................................................................................................................................6-3 Table 6-7. RTD Statistics ................................................................................................................................................................6-4 Table 6-8. Seismic Vibration Measurement Device Inputs.............................................................................................................6-4 Table 6-9. Proximity Transducer Inputs..........................................................................................................................................6-4 Table 6-10. Flame Detector Inputs..................................................................................................................................................6-4 Table 6-11. Pulse Rate Inputs .........................................................................................................................................................6-5 Table 6-12. LVDT/LVDR Position Feedback Inputs......................................................................................................................6-5 Table 6-13. Servo Valve Outputs ....................................................................................................................................................6-6 Table 6-14. Analog Voltage and Current Inputs and Outputs .........................................................................................................6-7 Table 7-1. Solenoid Output .............................................................................................................................................................7-4 Table 8-1. General Troubleshooting Chart. ....................................................................................................................................8-3 Table 8-2. TIMN I/O Status Cfg Stat Column Codes. ....................................................................................................................8-5 Table 8-3. Mark V LM Board I/O State and Status Meanings. .......................................................................................................8-6 Table 10–1. Stage Link Addresses ..............................................................................................................................................10-15 Table A-1. X, Y, Z Card Definition Determined According to Binary Summation.......................................................................A-8 Table A-2. Binary Values for J28 and J29 .....................................................................................................................................A-9 Table A-3. Feedback Resistors ....................................................................................................................................................A-11 Table A-4. Feedback Resistors and Jumpers (R F) ........................................................................................................................A-11 Table C-1. DC Distribution............................................................................................................................................................ C-5 Table C-2. DC Distribution............................................................................................................................................................ C-5 Table C-3. AC Distribution............................................................................................................................................................ C-5
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CHAPTER 1
OVERVIEW 1-1. DEFINITION AND SCOPE This manual provides information about the Mark V LM turbine control panel. The information includes receiving and handling of the panel, installation of the panel, a summary of its basic operations, a description of the printed wiring boards, applications and specifications of the I/O, and information on renewal parts and troubleshooting.
1-2. EQUIPMENT OVERVIEW This section provides a basic overview of the equipment involved with the Mark V LM control panel. These include communications, the operator interface, and the control panel itself.
1-2.1. Mark V LM Control Panel GE Turbine Control Systems have been produced for several decades and have enjoyed widespread acceptance in both new unit and retrofit applications. The Mark V LM represents the latest in a line of microprocessor-based turbine control systems designed specifically for controlling turbines. The Mark V LM is used on aero-derivative gas turbines. Unit control and protection is accomplished by using the Mark V LM in combination with sensors and devices mounted on the unit and its auxiliaries. Printed wiring boards and terminal boards in a Mark V LM control panel are contained in or are mounted on cores. Cores are sheetmetal housings that can have stationary and movable printed circuit board holders called card carriers. The cores have a maximum of five printed circuit boards mounted on the card carriers. In addition, up to four I/O terminal boards can be mounted on a single core. The combination of boards contained in each core is dependent on the application. The control panel consists of a single control processor, known as . This control processor also functions as a communicator processor. Other cores which make up a typical Mark V LM control panel include a protective core, ; a power distribution core, ; control processor I/O cores, , , , and ; and digital I/O cores, and . (See Figure 1 - 1.).
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MARK V LM PANEL LAYOUT
Mark V LM I/O CONTROL 1-STCA/UCPB 2-TCQA 3-open 4-TCQC 5-TCPS 6-QTBA 7-TBQB 8-TB3 9-TBQC
3PL
I/O CONTROL 1-STCA/UCPB 2-TCQA 3-TCQE 4-TCQC 5-TCPS 6-QTBA 7-TBQE 8-TBQA 9-TBQC
3PL
I/O CONTROL 1-STCA/UCPB 2-TCCA 3-TCCB 4-open 5-TCPS 6-CTBA 7-TBCB 8-TBQA 9-TBCA
3PL
COREBUS(Arcnet)
Stagelink to
IONET
CONTROLLER 1-UCIA/UCPB/PANA 2-TCSA 3-open 4-open 5-TCPS 6-AAHA1 6-AAHA2 6-COM1,COM2,GENIUS
PROTECTIVE 1-TCEA 2-TCEB 3-TCEA 4-TCTG 5-TCEA 6-PTBA
POWER DISTRIBUTION
DIGITAL I/O 1-TCDA 2-open 3-open 4-TCRA 5-TCRA 6-DTBA 7-DTBB 8-DTBC 9-DTBD
DIGITAL I/O 1-TCDA 2-open 3-open 4-TCRA 5-TCRA 6-DTBA 7-DTBB 8-DTBC 9-DTBD
I/O CONTROL 1-STCA/UCPB 2-TCQA 3-open 4-TCQC 5-TCPS 6-QTBA 7-TBQB 8-open 9-TBQC
3PL
Figure 1-1. Mark V LM Panel Layout 1-2
1-TCPD
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1-2.2. Operator Interface The primary operator interface consists of a color monitor, keyboard, cursor positioning device (CPD), printer(s), and central processing unit (CPU). The interface is connected to the Mark V LM control panel via an ARCNET cable. The devices can be located in the installation’s central control room or a turbine’s control compartment. One operator interface can be used to control multiple turbines; also more than one operator interface may be used to control a single turbine. The operator can thereby select the units he wishes to monitor or issue commands to. All operator interfaces are capable of issuing commands to a unit at any time while communicating with Mark V LM control panels. For the purposes of this manual, it is assumed that the operator interface is controlling a single turbine and driven device. Using the operator interface, commands may be issued to the turbine and driven device (for example, START, STOP, COOLDOWN ON, AUTO, RAISE SPEED/LOAD, and so on) and displays may be accessed to view the status of the turbine and driven device (for example, ALARMS, WHEELSPACE TEMPERATURES, VIBRATION FEEDBACK, and so on). The associated printer(s) enable the operator to manually select and copy any display, to automatically log selected parameters, and to log alarms. The operator interface performs no control or protection functions of the turbine and driven device; it is a means of issuing commands to the Mark V LM control panel and monitoring unit operation. Turning the operator interface off, turning the computer on, re-booting the computer, or disconnecting or reconnecting the ARCNET cable linking the Mark V LM control panel and the operator interface (while the turbine and driven device are operating) will have no effect on the Mark V LM control panel or unit operation.
1-2.3. Communications Information is communicated, shared, and acted upon in the Mark V LM Control System via three separate networks. The one external network, the Stage Link, is the primary means of communication between the operator interface and the Control Engine located in the core of the control panel. This link uses ARCNET configuration. The COREBUS is a separate ARCNET communication network internal to the Mark V LM control panel. The function of the COREBUS is to provide a communication link between the I/O control processors (, , , ) and the Control Engine (). The third internal network is known as the I/O network (IONET). The IONET is a serial communications network that is connected in a daisy chain configuration. The purpose of the IONET is to transfer signals from the digital I/O cores (, ) and the protective core () to the I/O control processors. There are two separate IONETs, one connecting and and one connecting , , and (see Figure 1-1.). 1-2.3.1 STAGE LINK. The Stage Link consists of a coax cable that is terminated at both ends with BNC connectors. It runs from
the ARCNET interface board in the operator interface, to in the control panel. The ARCNET interface board is a high impedance source that enables the operator interface to communicate on the Stage Link. Connection to the Stage Link hardware requires the use of a "T" type BNC connector. This device also permits the Stage Link to continue to further processors on the network. It is necessary to terminate the cable of the last operator interface on the link with a 93 ohm termination resistor on the open connection of the "T" type BNC connector. See Chapter 10 of this manual for connectivity rules. The Stage Link connection on the core is an active three port repeater (see Figure 1-2). This device consists of three ports (two external and one internal). The internal port communicates from the processor to the external ports. Either external port receives a signal, amplifies it, and then passes it to the core and the other external port. Similarly, a signal originating in the core is amplified and sent out both external ports. In the event of interrupted power to the repeater, a bypass relay provides continuation of the Stage Link. Loss of the core results in a loss of communication between the control panel and the affected operator interfaces on the Stage Link. Due to the three port repeater design of , the Stage Link continues to operate between other devices, but is not able to communicate with the affected control panel.
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STAGE LINK
STAGE LINK
PORT
PORT
PROCESSOR
Figure 1-2. Three Port Active Repeater 1-2.3.2. COREBUS. The COREBUS is an ARCNET communication network linked between the control engine and the I/O
engines , , , and (See Figure 1-1.). The COREBUS has two main purposes: the BMS and the input/output communication between the control engine and the I/O cores. The BMS, or Basic Messaging system, is the backbone of the system that allows basic message packets to be transmitted from the control engine to the various I/O engines. Supported by the BMS is the UDM, or User Defined Memory system. The UDM is what allows the controller to send a message to one of the I/O cores, asking it for a memory allocation. The COREBUS also handles input/output traffic between the control engine and the I/O cores. Every 10 milliseconds (known as a frame), the I/O cores transmit a packet of the data to the control engine, which stores them all in the database. Included among ‘s data is information transmitted from the TCEA boards and TCDA board over the IONET. This information can come in the form of high speed data (once per frame) or low speed data (spread across 4-8 frames). Once every frame, towards the end of the frame, the control engine transmits all the output data in one packet across the COREBUS. Each I/O core receives this packet, then takes the information that it needs from it. 1-2.3.3. IONET. The I/O Network (IONET) is a communication network internal to the Mark V LM panel that permits data
exchange between the STCA boards located in the I/O control cores ( and ), the TCDA boards in the digital I/O cores ( and ) and the TCEA boards located in . This network allows the control to perform digital I/O (TCDA) and protection (TCEA) related functions. Information transmitted over the network is address-specific. As a result, data is sent to either the TCDA or TCEA boards according to their hardware jumper address settings. On start-up of the control panel, the control engine downloads unit parameters to the TCDA and TCEA boards for I/O configuration and internal diagnostics. During operation, operating parameters from these cards are sequentially exchanged with the STCA over the IONET for unit control.
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The configuration explained above allows TCEA and TCDA boards to be added to the network as necessary. Termination of the IONET is accomplished by setting the hardware jumpers on the last TCDA board of the network (See Appendix A for hardware jumper setting information). Each board must have a specific network address, also set by hardware jumpers, that matches a software description. If a board needs to be removed for service, the network connection is broken at that point. Three TCEA boards (known as , , and ) are required in the core. These three TCEA boards are linked in a daisy chain configuration. These boards operate on the same IONET and all communicate with the core. 1-2.3.4. THE ARCNET INTERFACE BOARD. The ARCNET interface board is a device that allows the operator interface to
communicate with the Mark V LM control panel via the Stage Link network. Located in a spare 16-bit slot in the PC, the board passes signals onto the network through a "T" type BNC connector (this latter device is located at the back of the PC). The last connection on the Stage Link requires a 93 ohm termination resistor on the open end of the "T" type connector. All supported ARCNET interface boards (several ARCNET boards are supported) are high impedance "BUS" type cards. Supported ARCNET controller boards may implement hardware jumpers or switches for hardware configuration. Each of these boards retains the ability to configure the dual-ported memory base address, the I/O base address, the PC’s ARCNET address, and the interrupt request level (IRQ). Other selectable features are card specific. Information regarding configuration of specific boards is provided in the operator interface manuals.
1-3. RELATED DOCUMENTATION Related technical documents include the User and Maintenance Manual (GEH-6354), which covers basic information necessary to run the operator interface; and the Applications Manual (GEH-6355), which has information about specific applications of the . Future operator interfaces will have different manuals and may be used for more information on related topics.
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CHAPTER 2
RECEIVING, HANDLING, AND STORAGE 2-1. INTRODUCTION This Chapter is a general guide to the receiving, handling, and storage of a Mark V LM Control system.
2-2. RECEIVING AND HANDLING
CAUTION Immediately upon receiving the system, place it under adequate cover to protect it from adverse conditions. Packing cases are not suitable for outdoor or unprotected storage. Shock caused by rough handling can damage electrical equipment. To prevent such damage when moving the equipment, observe normal precautions along with all handling instructions printed on the case.
GE inspects and packs all equipment before shipping it from the factory. A packing list, which itemizes the contents of each package, is attached to the side of each case of the equipment. Upon receipt, carefully examine the contents of each shipment and check them with the packing list. Immediately report any shortage, damage, or visual indication of rough handling to the carrier. Then notify both the transportation company and GE Industrial Control Systems. Be sure to include the serial number, part (model) number, GE requisition number, and case number when identifying the missing or damaged part. If assistance is needed contact: GE Industrial Control Systems Product Service Engineering 1501 Roanoke Blvd. Salem, VA 24153-6492 Phone 001 540-387-7595 Fax 001 540-387-8606
2-3. STORAGE If the system is not installed immediately upon receipt, it must be stored properly to prevent corrosion and deterioration. Since packing cases do not protect the equipment for outdoor storage, the customer must provide a clean, dry place free of temperature variations, high humidity, and dust.
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Use the following guidelines when storing the equipment: 1. Place the equipment under adequate cover with the following requirements: a. Keep the equipment clean and dry, protected from precipitation and flooding. b. Use only breathable (canvas type) covering material – do not use plastic. 2. Unpack the equipment as described in section 2-4, and label it. 3. Maintain the following environment in the storage enclosure: a. Ambient storage temperature limits from -20 °C (-4 °F) to 55 °C (131 °F). b. Surrounding air free of dust and corrosive elements, such as salt spray or chemical and electrically conductive contaminants. c. Ambient relative humidity from 5 to 95% with provisions to prevent condensation. d. No rodents. e. No temperature variations that cause moisture condensation on the equipment.
CAUTION Moisture on certain internal parts can cause electrical failure. Condensation occurs with temperature drops of 15 °C (27 °F) at 50% humidity over a 4-hour period, and with smaller temperature variations at higher humidity. If the storage room temperature varies in such a way, install a reliable heating system that keeps the equipment temperature slightly above that of the ambient air. This can include space heaters or panel space heaters (when supplied) inside each enclosure. A 100 watt lamp can sometimes serve as a substitute source of heat.
CAUTION To prevent fire hazard, remove all cartons and other such flammable materials packed inside units before energizing any heaters.
2-4. UNPACKING It is good practice to not completely unpack the equipment until it has been placed as near as possible to its permanent location. If the equipment has been exposed to low temperatures for an extended period of time, do not unpack it until it has reached room temperature. Save all instruction books, disks, and documentation provided. When unpacking, check the contents of each case against the packing list. Report any shortage to GE Industrial Control Systems.
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Use standard unpacking tools, including a nail puller. Carefully move the equipment from its container to avoid damaging or marring the part. Wipe off any particles of packing materials or foreign substances that may be lodged in or between the parts. Small parts (such as bolts and screws) are packed in special containers to keep them together. However, they may become separated. For this reason, carefully inspect packing material for loose parts before discarding it.
2-5. TIME LIMITATIONS The above specifications apply to shipping and storage duration’s of up to one year. Longer times may require additional treatment. For warranty information, refer to Chapter 9 of this manual.
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CHAPTER 3 INSTALLATION AND INITIAL POWERUP 3-1. INTRODUCTION This chapter contains environmental, mounting, and electrical guidelines for installing the Mark V LM control panel. It also includes basic circuit checks needed after installation and before start up. Before installation, consult and study all furnished drawings. These should include arrangement drawings, connection diagrams and a summary of the equipment.
3-2. OPERATING ENVIRONMENT The Mark V LM control panel is suited to most industrial environments. To ensure proper performance and normal operational life, the environment should be maintained as follows: Ambient temperature (acceptable): 0 °C (32 °F) to 45 °C (113 °F) Ambient temperature (preferred): 20 °C (68 °F) and 30 °C (87 °F)
NOTE Higher ambient temperature decreases the life expectancy of any electronic component. Keeping ambient air in the preferred (cooler) range should extend component life. Relative humidity: 5 to 95%, non-condensing. Environments that include excessive amounts of any of the following elements reduce panel performance and life: •
Dust, dirt, or foreign matter.
•
Vibration or shock.
•
Moisture or vapors.
•
Rapid temperature changes.
•
Caustic fumes.
•
Power line fluctuations.
•
Electromagnetic interference or “noise” introduced by: ∗
Radio frequency signals, typically from portable transmitters used near the equipment or its wiring.
∗
Stray high voltage or high frequency signals, typically produced by arc wielders, unsuppressed relays, contactors, or brake coils operating near control circuits.
The preferred location for the Mark V LM control panel would be in an environmentally controlled room or in the control room itself. The panel should to be mounted where the floor surface allows for attachment in one plane (a flat, level, and continuous surface). The mounting hardware is provided by the customer. Lifting lugs are provided and if used, the lifting cables must not exceed 45° from the vertical plane. Finally, the panel is equipped with a door handle which can be padlocked for security.
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Interconnecting cables can be brought into the panel from the top or the bottom via removable access plates. Convection cooling of the panel requires that conduits be sealed to the access plates. Also, air passing through the conduit must be within the acceptable temperature range, as listed above. This applies to both top and bottom access plates.
3-3. CABLING, WIRING, AND POWER SOURCES This section covers the basic electrical information involved with the Mark V LM control panel. All installations should meet the requirements of both the National Electrical Code and any applicable local codes. Use these codes to determine such factors as wire size, insulation type, conduit sizing, and enclosures.
WARNING Danger of electric shock or burn. Before handling and connecting any power cables to the equipment, make sure that all input power is turned off. Then check voltage levels on the wiring to ensure that it is not carrying hazardous voltages.
3-3.1. Spacing The following requirements ensure correct distance between cabling and wiring: • •
•
Signal wiring and power wiring may cross at right angles with a minimum 1-inch separation. Avoid parallel runs between signal level wires and power or control wires. If signal wires must be run parallel with control or power wires: ⇒ For distances up to 4 feet, maintain a minimum separation of 3 inches. ⇒ For distances over 4 feet, add 1/4 inch of additional spacing for every foot of additional distance. Within pullboxes and junction boxes, use grounded barriers to maintain the level separations.
3-3.2. Power Sources The Mark V LM control panel can accept power from multiple power sources. Each power input source (example: the dc and two ac sources) should feed through its own external 30 Ampere 2 pole thermal magnetic circuit breaker before entering the Mark V LM panel. The breaker ratings are 250 volts and 30 amperes with a minimum withstand of 10,000 amperes. The breaker should be supplied in accordance with EN61010-1 section 6.12.3.1 and marked as CE. Power sources can be any combination of a 125 V dc source and/or up to two 120/240 V ac sources. Each core within the panel has its own power supply board, each of which operates from a common 125 V dc panel distribution bus. For further detail on the panels power distribution system, refer to Appendix C. VOLTAGE
FREQUENCY
Nominal
Tolerance Range
Nominal
125 V dc
100 to 144 V dc (see Note 5) 108 to 132 V ac (see Note 6) 200 to 264 V ac
N/A
120 V ac 240 V ac
50/60 Hz 50/60 Hz
Tolerance Range N/A 47 to 53 Hz 57 to 63 Hz
Table 3-1. Power Source Requirements 3-2
CURRENT DRAW (measured at nominal voltage) Typical 7.0 A dc (see Note 1) 7.0 A RMS (see Notes 2 and 4) 3.5 A RMS (see Notes 3 and 4)
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Notes on Table 3-1: 1. Add .5 A dc continuous for each 125 V dc solenoid powered. 2. Add 6.0 A RMS for a continuously powered ignition transformer (2 maximum). 3. Add 3.5 A RMS for a continuously powered ignition transformer (2 maximum). 4. Add 2.0 A RMS continuous for each 120 V ac solenoid powered (inrush 10.0 A). 5. Ripple not to exceed 10 volts peak-to-peak. 6. Total Harmonic Distortion not to exceed 5.0%.
3-3.3. Equipment Grounding Within the Mark V LM control panel, each controller is equipped with a single control common wire which connects to the panel control common ground bar, abbreviated as CCOM. The control common ground (CCOM) bar along with the shield bars are connected to the panel ground bar located at the bottom of the panel through the panel’s steel structure. The panel ground bar must be attached to earth or grid ground with a minimum #4 AWG copper cable. This connection is a panel ground for safety and helps eliminate electrical noise.
WARNING Although the panel itself is metal and grounded, it is an unacceptable practice to use it as a grounding point in place of an earth or grid ground.
3-4. POWER-OFF CHECKS All Mark V LM control panels are factory-tested and operable when shipped to the installation site. However, final checks should be made after installation and before starting the equipment.
WARNING This equipment contains a potential hazard of electrical shock or burn. Power is provided by the Mark V LM control panel to various input and output devices. External sources of power may be present in the Mark V LM panel that are NOT switched by the control power circuit breaker(s). Before handling or connecting any conductors to the equipment, use proper safety precautions to insure all power is turned off.
3-4.1. Control Panel Inspection Inspect the control panel components for any damage which might have occurred during shipping. Check for loose cables or wires, connections or loose components such as relays or retainer clips. Report any damage that may have occurred during shipping to GEDS&TC Product Service. The ground lug in the bottom of the Mark V LM control panel must be connected to a suitable ground point, preferably plant ground grid.
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3-4.2. Board Inspections The following steps should be performed in order to inspect the printed circuit boards in each core: •
Inspect the boards in each core checking for loose or damaged components. Verify all plug in relays are firmly connected into their sockets.
•
Check to see that each board is held firmly.
•
Check ribbon cables and wire harnesses. Verify all ribbon cables are securely connected. ⇒ If it is necessary to unplug the connector, use the pull tabs on each ribbon cable to remove them. DO NOT pull directly on the ribbon cables or wires. ⇒ Note the orientation of the ribbon cable or wire harness "trace". (Trace is the colored wire on the edge of the ribbon cable, or the "odd"-colored wire on the edge of the wire harness.) ⇒ Check each wire harness power cable for proper location, checking the cable ID tag against the connector ID printed on the board and the drawings.
CAUTION
Ribbon cables and wire harnesses are always oriented with the trace connected to pin 1 of the receptacle. Refer to the core drawings for more information. Incorrect connection could damage board(s). Many ribbon cable connectors are not keyed. Use caution when connecting them. The connectors which do not fit into a receptacle must be aligned properly leaving no pins exposed. •
Verify that the board hardware jumpers match the on-line hardware jumper screen located on the operator interface that is supplied with the Mark V LM Control System and move the jumper(s) if necessary. The jumpers in the digital output circuits can provide power to an external device from the Mark V LM (solenoid output) or they can be configured as "dry" contacts, for example, power provided by an external source. Verify each digital output has only one source of power. If any questions arise, contact GEDS&TC Product Service.
•
Use appropriate caution while replacing each card carrier when the core inspection is complete. Avoid binding, pinching, or chafing the ribbon cables and wire harnesses. Prior to closing the core door, push in the two silver retaining clips at the lower front corners of the core to lock the card carriers in place.
3-4.3. Wiring and Circuit Checks The following steps should be completed in order to perform a check of the wiring and circuits of the Mark V LM control panel. •
Check that all incoming wiring agrees with the elementary drawings supplied with the panel, and is complete and correct.
•
Check that incoming power is the correct voltage and frequency.
•
Make sure that the incoming wiring conforms to approved wiring practices, as described previously (Section 3-3.).
•
Check that all electrical terminal connections are tight.
•
Make sure that no wiring has been damaged or frayed during installation. Replace if necessary.
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3-5. CONTROL PANEL INITIAL ENERGIZATION The following steps should be followed in order to perform an initial energization of the Mark V LM control panel. •
Verify no grounds exist in the control wiring.
•
Verify only one ground exists in the control panel by lifting the braided conductor and capacitor that connect CCOM to the panel ground. Measure with an ohmmeter between the CCOM bus and panel ground. If the ohms measured are low, resolve any extra grounds before continuing. Be sure the ground reference jumper in the core is in the correct position.
•
Reconnect the ground braided conductor and capacitor.
CAUTION Failure to check and resolve grounds on field-connected wiring and cabling can cause damage to either Mark V LM turbine control system components or field devices, or both. Do not connect the output of a battery charger directly to the Mark V LM turbine control panel without the battery being connected to the charger; serious damage can result to the Mark V LM power supplies. •
Verify polarity and voltage of dc and/or ac supplies. If the battery system is referenced to ground, verify in accordance with plant drawings.
•
Apply power to the control panel cores one at a time while monitoring source voltage. (Turn one on, check voltages, turn it off. Turn on next one, etc.) If a ground exists, resolve before continuing.
•
Verify LEDs and fuses in the core. See Appendix C of this manual.
•
If desired or necessary, the voltages of the individual power supplies can be checked using Table 3-2.
3-5
GEH-6353B Core
Card
AC or DC
Nominal
Positive or 1 “Hot”
DC
125
ST–DCHI
–
AC
120/240
–
AC DC DC DC DC DC DC DC DC DC DC DC
– PD
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R1 R2 R3 R R5
TCPS
P1
TCEA
Negative or 1 Neutral ST–DCLOW
Regulated?
Acceptable Range
Fuse Number or Other Comments
No
User Supplied
ST–AC1H
ST–AC1N
No
120/240
ST–AC2H
ST–AC2N
No
+15 -15 +24 +5 -24 -15 +15 +5 +24 +24 +335
TP-P15 TP-N15 TP-+24V TP-+5V TP--24V TP-N15 TP-P15 TP-P5 TP-P24 TP-P24A PL-JW1
TP-DCOM TP-DCOM TP-DCOM TP-DCOM TP--24V TP-COM TP-COM TP-COM TP-COM TP-N24A PL-JW2
Yes Yes No Yes No Yes Yes Yes No No No
100-144 108-132/ 200/264 108-132/ 200/264 14.25 - 15.75 -15.75 - -14.25 21.6 - 32 4.75 - 5.25 -32 - -21.6 -15.75 -14.25 14.25 - 15.75 4.75 - 5.25 21.6 - 32 21.6 - 32 300 - 375
User Supplied User Supplied – – FU1 -5A FU3 - 8A FU2 - 1.5A – – – – – –
Table 3-2. Power Supply Voltages and Test Points Notes on Table 3-2. : 1. TP - Test Point, PL - Plug, ST - Screw Terminal.
3-6. OPERATOR INTERFACE INSTALLATION AND STARTUP This section provides a brief overview of the installation and setup of an operator interface.
3-6.1 Equipment Overview A standard operator interface would consist of a PC with color monitor, keyboard and Central Processing Unit (CPU). The CPU would contain an ARCNET interface board, RS-232 ports, parallel port, cursor positioning device, and a printer. Other options may be included. See the operator interface manual for details about the equipment. (For example: GEH-6354 for the operator interface). The Mark V LM Stage Link is the communication link between a turbine control panel and the operator interface. This includes an ARCNET interface board in the CPU and may also include at least one Ethernet interface board. Communication with a distributed control system (DCS) LAN can be accomplished using MODBUS protocol over a serial communication link through LDDS’s or modems. See the operator interface manuals for details. Alarm and event logging is accomplished using a dot matrix printer. Optionally, additional dot matrix printer(s), laser printer(s), and/or color printer(s) may be supplied. Alarms, events, and/or normal printing functions can be directed to one or more printers connected to the operator interface.
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Note The auxiliary components of an operator interface such as printer(s), LDDS(s), and Ethernet board(s) may not be the same for all operator interfaces on a particular site.
3-6.2 Installation and Initial Startup This section briefly describes the installation and setup of an operator interface. More detailed information can be found in the manual for the operator interface. Schematics of the connections of the operator interfaces main components are provided as part of the core documentation. These schematics should be used in conjunction with the installation information located in the operator interface manual. (For example: GEH-6354 for the operator interface). •
Connect the components to the CPU with the cables provided.
•
Verify settings of any switches and hardware jumpers prior to applying power to the operator interface. Most of these are preset before shipping.
•
Configure the monitor.
•
Note the manufacturer, model number and serial number of the ARCNET interface board. This board is factory preset and settings should not be changed.
•
If an Ethernet interface board is provided, it has jumpers which are preset. These should only be checked when troubleshooting the Ethernet communication network.
•
Connect the operator interface components to the site AC power and turn them on.
•
Configure the operator interface per the instructions in the operator interface manual.
•
Verify the operator interface is functioning properly.
•
Configure the printer.
•
If requisition and product specific software was not pre-loaded, load the software now. Follow the procedures listed in the operator interface manual. (For example: GEH-6354 for the operator interface).
3-7 CONTROL PROCESSOR STARTUP This section briefly describes the control processor’s startup. These instructions require that at least one operator interface has been successfully started up in accordance with its startup directions in the operator interface’s manual. •
Energize the processors (, , , , ) and verify their state.
•
Verify the Stage Link ID of the control panel with the drawings supplied. This is set on UCPB board in the core. See section 3-7.1 for information on how to set the Stage Link address using DIP switches.
•
Establish ARCNET communication with the operator interface by connecting the Stage Link cable to the AAHA board on the core to the Tee adapter on the operator interface. A termination resistor must be located at the end of the Stage Link.
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•
Verify Stage Link communications using the operator interface displays. If no valid data is displayed, the ARCNET communication has failed. Verify the following is correct: ⇒ Cable and connector integrity. ⇒ Tee adapter and 93 Ohm termination resistor are installed correctly. ⇒ Stage Link ID and LAN unit number (LUN) match. The LUN is located on the Configuration file on the operator interface that tells the interface what the Stage Link ID(s) are for the units it is looking at. ⇒ Verify the switches and jumpers on the ARCNET interface board in the operator interface are correct. ⇒ Perform an ARCWHO on the operator interface to verify what units are “seen” on the Stage Link. If the network is experiencing problems, the message “The network is unstable” will appear.
•
Down load configuration files to the Mark V LM if necessary. Reset controller to make the changes active.
•
Back up the system using the operator interface. See the operator interface manual for more information.
3-7.1 Setting the Stage Link Each node on the Stage Link must have its own unique Stage Link ID. The core on the Mark V LM control panel and the operator interface have ranges which their Stage Link ID’s must be chosen. Stage Link ID’s are expressed in hexadecimal format. The operator interface Stage Link ID is the range from 01 to 2F hexadecimal, beginning with 2F. Typically, the Stage Link ID’s are set using DIP switches located on the ARCNET board mounted in the operator interface and on the UCPB board located in the core on the Mark V LM control panel. For example, the first operator interface would be assigned a Stage Link ID of 2F. To set the DIP switches to an ID of 2F, convert 2F from a hexadecimal to decimal (2F hexadecimal = 47 decimal). Then move the switches so that the sum of the switch values equal 47 decimal. There are eight numbered switches on the edge of the ARCNET board, or in the DIP switch on the UCPB board. The switches each have a value as follows: DIP Switch Value
8 128
7 64
6 32
5 16
4 8
3 4
2 2
1 1
Table 3-3. Stage Link Values. To enable a switches value (add that switches value to the total value), move the switch to the “UP” position. Using the Stage Link ID example above of 2F hexadecimal, the decimal value 47 would equal 32+8+4+2+1. Table 3-3 shows that the corresponding switches of 1, 2, 3, 4, and 6 would be in the “UP” or “1” position while switches 5, 7, and 8 would be in the “DOWN” or “0” position. The Stage Link ID’s for the operator interfaces and Mark V LM control panels should be set to their desired values. Refer to the ARCNET interface board manufacturers instructions and the operator interface manual for more information on setting the Stage Link ID for the operator interfaces. See Chapter 10 for Stage Link topology information.
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CHAPTER 4 FUNCTIONAL DESCRIPTION 4-1. INTRODUCTION This chapter describes the Mark V LM software and hardware structure and overall operation of the control panel. Refer to the sample connection diagrams in Appendix B. Chapter 5 contains descriptions of the printed wiring boards in the control panel.
4-2. HARDWARE STRUCTURE The Mark V LM control panel consists of several cores. Cores are sheetmetal housings that can have stationary and moveable printed wiring board holders called card carriers. The cores have a maximum of five printed wiring boards mounted on the card carriers. In addition, up to four high density I/O terminal boards can be mounted on a single core. The combinations of boards contained in each core is dependent on the application. See Figure 1-1 for a picture of a typical Mark V LM core layout.
Note The terms card and board both apply to the printed wiring boards. In this manual, board is the preferred term. However, card is used in some drawings and terms if it is pre-established nomenclature – for example, card carrier.
The Control Engine core, or core is the main control processor that is used to protect, monitor, and control the unit and to communicate to the operator interfaces. This core is commonly known as the core. The core contains a powerful 486DX CPU with companion circuitry to process the application software. The core contains the following printed wiring boards: •
UCIA – Motherboard where the UCPB, PANA, and µGENI boards are mounted. Contains a 196 processor that translates pressure transducer signals from the TCSA board for the UCPB board to use.
•
UCPB – Daughter board on the UCIA mother board that contains the 486DX processor, or CPU, and the ARCNET driver for external communications with the operator interfaces. Used in conjunction with the AAHA board.
•
TCSA – Optional board for Dry Low Emissions (DLE) applications. Contains decoders for communication between the XDSA board on the fuel skid and the UCIA board in the core.
•
TCPS – Power supply board.
•
PANA – The ARCNET driver for internal communications with the I/O cores. Mounted as a daughter board to the UCIA board.
•
AAHA – Board with two BNC connectors for ARCNET communication. Used for the Stage Link connections on the core via the UCPB board, and for the COREBUS connections between the core and the I/O Cores via the PANA board.
Other cores associated with a typical Mark V LM control panel include protective core, ; a power distribution core, ; I/O cores, , , ,and ; and two digital I/O cores, and .
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The core contains protective processors. Each of these processors are responsible for emergency overspeed detection and trip signal initiation, provide ultraviolet flame detector excitation voltage, and synchronization for generator drive applications. The status in each board of these functions are voted using a “two out of three” process and the voted value is used in the protection algorithms/sequencing. The core contains the following printed wiring boards: •
TCEA – Contains the microprocessor circuitry for critical protection, known as the “protective processors”.
•
TCEB – Expander board for the TCEA’s.
•
TCTG – The trip board which contains the units trip solenoids.
•
PTBA – Protective core terminal board.
The I/O cores are used to read and write analog signals. These cores contain the I/O Engine, a 486DX CPU with companion circuitry, that is used to communicate the I/O signals to the core. Microprocessors on the TCQA, TCQC, TCQE, TCCA and TCCB boards scale and condition the analog signals using I/O configuration information contained on the core’s RAM. The data is then sent across the COREBUS to the Control Engine in the core and into the Control Signal Database located in that core. After the signals have been used in the application software, the results are then sent back across the COREBUS to the I/O cores. These cores contain combinations of the following printed wiring boards: •
STCA – IONET master for the I/O cores. Performs I/O configuration on some signals. Provides synchronization check. UCPB board is mounted on this board.
•
UCPB – Contains a 486DX CPU used as the I/O engine.
•
TCQA, TCQE, TCCA, and TCCB – I/O boards containing the I/O configuration software.
•
TCPS – Power supply board.
•
TCQC – Contains the I/O expansion for the TCQA board and the IONET communication interface from to and .
•
QTBA – Terminal Board that contains the COREBUS communications and I/O termination’s in , , and .
•
CTBA – Terminal Board that contains IONET and COREBUS communication interface and I/O termination’s in .
•
TBQA, TBQB, TBQC, TBQE, TBCB, and TBCA, TB3 – I/O terminal boards.
The two digital I/O cores, and , are used to read and write digital I/O signals. These cores send their data through an I/O communication network, (IONET), to either cores or for transmission. The digital I/O cores contain the following printed wiring boards: •
TCDA – Conditions the digital I/O signals and communicates to the I/O cores through the IONET.
•
TCRA – Relay board.
•
DTBA, DTBB, DTBC, and DTBD – Digital I/O terminal boards.
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The core is used to distribute the 125 V dc to the TCPS power supply boards located in each I/O core and in the Control Engine core, , to the TCEA boards and the TCTG board in the core and to the DTBA, DTBC and DTBD terminal boards in the digital I/O cores. The core contains the following printed wiring board: •
TCPD – Contains the circuitry that distributes the 125 V dc.
Section 4-4 contains the overall operation of the Mark V LM. Chapter 5 describes the function and operation of the printed wiring boards. Appendix C contains the Power Distribution Core diagrams.
4-3. APPLICATION SOFTWARE STRUCTURE The Mark V LM controller stores on the hard drive or flash memory in the core the application specific control software, operating system and control constants and loads them on to RAM when the core is rebooted. The 486DX CPU calls the Control Sequence Program (CSP), associated Big Blocks, and Control Constants from the RAM as they are used. The 486DX CPU in controls memory access to the Control Signal Database. The Control Signal Database is an area of memory reserved in the core’s RAM for storage of values that are used by the sequencing program and for viewing by the operator interfaces. Major elements of the software configuration are: •
Use of functional blocks, or Big Blocks, for specific control, monitoring and protection of the unit.
•
Use of Relay Ladder Logic to build the control sequencing.
•
Use of the control signals names that correspond to memory locations in the panels RAM that are used for calculations, I/O values, control constants and alarms.
•
Use of the constants that are the parameters for I/O configuration, unit control and process alarms.
4-3.1. Big Block System The Control Sequence Program (CSP), used by the Mark V LM as its application software, uses a programming language known as Big Block Language, or BBL. BBL is a relay ladder logic based software structure that defines data flow and function execution. The software structure is made up of a series of rungs that can contain combinations of comments, contacts, coils and Big Blocks. Big Blocks are software modules that perform standardized control functions. There are three different types of Big Blocks: Primitive, Generic and Application Specific. Primitive blocks perform simple functions such as add and multiply. These blocks can be added to the end of a rung of ladder logic. Generic blocks are more complex, and can only be used in a rung by themselves. Application Specific blocks are used for certain control applications. Big Blocks are located on the hard drive or flash memory in the controller and loaded onto RAM on startup of the controller for execution. CSP’s downloaded to the Control Engine call the Big Blocks as needed. The Control Sequence Editor can be used to create new CSP’s or to edit existing ones. The Control Sequence Editor has an on line help system available. The operator interface manual explains the use of the Control Sequence Editor as well as the BBL language itself.
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4-4. CONTROLLER OPERATION The Mark V LM provides programmable microprocessor unit control and protection. Control parameters are stored in RAM. Field signals are brought in through the various terminal boards on the I/O cores, digital I/O cores and the protective core. In the digital cores, the TCDA board scales and conditions the signals and sends them via the IONET to the I/O cores and through the TCQC board and CTBA terminal board respectively. The signals from the TCEA boards in the core are also sent across the IONET to the core. The analog signals are brought directly into the terminal boards of the I/O cores and are scaled and conditioned by the TCQA, TCQC, TCQE, TCCA and/or TCCB boards. All of the I/O signals are sent to across the COREBUS through the QTBA or CTBA terminal boards. The I/O configuration constants are sent from RAM in the core to the I/O cores 486DX CPU (I/O Engine) via the COREBUS. The I/O Engine stores the configuration constants on RAM located on the I/O boards in the I/O cores and the digital I/O cores on rebooting of the cores. Microprocessors on the I/O boards use the configuration constants along with the configuration software to perform the scaling and conditioning of all the I/O signals read from the terminal boards. The I/O Engine sends the calculated values across the IONET. The I/O boards also scale and condition the values to be written to the terminal boards as outputs. See Chapters 6 and 7 for the Mark V LM’s I/O specifications and applications and the operator interface manual for more information on the I/O Configurator. The Control Sequence Program (CSP), Control Constants, and I/O Configuration Constants are downloaded from the operator interface across an ARCNET communication link, called the Stage Link, located on the AAHA board. The Stage Link downloads these files to the Control Engine, a 486DX CPU located on the UCIA/UCPB board in the core. The Control Engine is responsible for sending the I/O Configuration Constants across the COREBUS to the I/O Engines in the I/O cores, running the CSP, and for storing values in the Control Signal Database memory locations. Communication transfers and frame rates are generally done at 100 Hz, (10 ms). QNX is the operating system for the Control Engine. The Control Engine converts the fixed point I/O signals obtained from the COREBUS to floating point values for use in the application software. The Control Engine also converts the values back to fixed point for transfer back across the COREBUS to the I/O cores and digital I/O cores. Some additional scaling is done by the Control Engine during these conversions. More information on the communication networks can be found in Chapter 1 of this manual.
4-5. CORE CONNECTION DRAWINGS Appendix B contains sections of sample Hardware Documents showing the core interconnection diagrams. Site specific Hardware documents are shipped with each Control Panel.
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CHAPTER 5 PRINTED WIRING BOARD DESCRIPTIONS AND INTERCONNECTIONS 5-1. INTRODUCTION This chapter describes the functions of the printed wiring boards (PWB) and terminal boards used in the Mark V LM control panel and their interconnections. A sample interconnection diagram (hardware document) can be found in Appendix B. The signal flow diagrams are located in Appendix D. The Mark V LM control panel can be application specific, thus the equipment associated with the control panel and their interconnections may change.
5-2. BOARD IDENTIFICATION A printed wiring board is designated by an alphanumeric part (catalog) number. Two part numbering series are commonly used for printed wiring boards at GE Industrial Control Systems. Most of the boards contained in the Mark V LM are designated with part numbers beginning with the characters DS200 or DS215. For example, the protective processor board is identified by part number DS200TCEAG#ruu. The characters in the part number provide information about the board, as shown by Figure 5-1. All characters are important when ordering or replacing any board. Chapter 9 contains information on spare and renewal parts.
Note The terms card and board both apply to the printed wiring boards. In this manual, board is the preferred term. However, card is used in some drawings and terms if it is pre-established nomenclature – for example, card carrier.
5-3. INITIAL CONFIGURATION The I/O boards on the Mark V LM control panel are configured using a combination of hardware jumpers and software. Some printed wiring boards and terminal boards in the Mark V LM include hardware jumpers for setting functions and configuring the boards. The board layout drawings in this chapter show the hardware jumper locations on the boards. Appendix A lists and describes the hardware jumper settings. Site specific hardware jumper settings are included on-line in the operator interface.
WARNING Potentially hazardous voltages are present in the panel circuits. Ensure that power is off before touching a board or any connected circuits.
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CAUTION Some boards contain static-sensitive components. To prevent component damage caused by static electricity, use static-sensitive handling techniques with all boards.
Note Board layouts and hardware jumper settings may change with product upgrades and revisions. Site specific hardware jumper settings are located on-line in the operator interface. Any field changes to these settings should be noted on the site specific operator interface hardware jumper screen.
5-3.1. Initial Hardware Jumper Settings The factory sets most hardware jumpers when manufacturing and testing the controller. For adjustments that are not factory-set, refer to the operator interface hardware jumper screen or to Appendix A. Typically these jumpers are designated with a J, BJ or JP nomenclature.
CAUTION All hardware jumper settings should be verified prior to energizing the Mark V LM panel.
5-3.2. Adjusting Replacement Boards When replacing a board, set the hardware jumper settings on the new board to match the settings on the board being replaced. Chapter 9 provides instructions for replacing a board.
Note Boards being replaced should be kept until the new replacement board arrives. Before returning any board, verify the hardware jumper settings. EPROMs from the old board should be removed and used on the new board.
5-3.3. I/O Board Software Configuration The I/O boards scale and condition I/O signals using firmware contained in EPROMs and I/O configuration constant values and configuration data stored in RAM. The I/O configuration constant values and configuration data load during a reboot/startup from their corresponding I/O Engines. Each I/O Engine receives these values from the Control Engine in the core. The Control Engine maintains the data until changed by downloading from the operator interface over the Stage Link. The user sets the I/O configuration constant values and configuration data using the I/O Configurator located on the operator interface. More information on the I/O Configurator is located in the operator interface manuals. (For example: GEH 6355 for the manual.)
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5-4. PRINTED WIRING BOARDS This section describes the printed wiring boards used in the Mark V LM control panel. The sample hardware document in Appendix B shows the locations of these boards in the panel and the interconnection information. 5-4.1. DS200AAHA – ARCNET Connection Board The ARCNET Connection Board (AAHA) provides the interface connection for ARCNET data, linking the Control Engine with the I/O cores and external devices. Two BNC connections (channels A and B) are provided for communication. One plug connector, the APL connector, is provided for communication with the boards containing the ARCNET drivers in the core. The core uses two AAHA boards. One is used for the Stage Link between the core and the operator interfaces. When both BNC connectors on this board are used, either two independent Stage Links can be connected to one panel or another panel can be connected to the Stage Link. The APL connector links the AAHA board with the UCPB board. The UCPB board is a daughter board on the UCIA board in the core. The UCPB board communicates to the operator interfaces across the Stage Link. The ARCNET driver for the Stage Link is located on the UCPB board. The second AAHA board connects the core with the COREBUS and allows the Control Engine in the core to communicate to the I/O cores. The APL connector on the second AAHA board connects to the PANA board, another daughter board on the UCIA board in the core. The ARCNET driver for the COREBUS is located on the PANA board. Figure 5-2 shows a typical layout of the AAHA board. 5-4.1.1. AAHA CONNECTORS.
• • • • • •
2PL − Distributes power from the TCPS board in the core. APL − ARCNET communication link between the AAHA board and the boards containing the ARCNET driver in . ARCBNC A − BNC connector for ARCNET communication. ARCBNC B − BNC connector for ARCNET communication. EBNC – Typically not used. EPL – Typically not used.
The site specific hardware document and the signal flow diagrams in Appendix D contain more specific information on the connectors. 5-4.1.2. AAHA CONFIGURATION. There is no hardware or software configuration done on the AAHA board.
5-4.2. DS200PANA – ARCNET No-LAN Driver Board The No-LAN Driver Board (PANA) provides ARCNET communication for the COREBUS and sets the COREBUS ARCNET address for the core. Located as a daughter board on the core’s UCIA board, the PANA board connects to the AAHA board via the APL connector. The PANA board transfers the data to the Control Engine on the UCPB board via the P1 and P2 bus connectors. The P1 and P2 bus connectors on the PANA board connect to the J2 and J4 bus connectors on the UCIA board. The UCIA board writes the signals directly to the UCPB board via the J1 and J3 bus connectors. Figure 5-3 shows a typical layout of the PANA board.
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5-4.2.1. PANA CONNECTORS.
• • • •
APL – ARCNET communication link to the AAHA board. BPL – ARCNET communication link to the AAHA board. P1 – Bus connection to the UCIA board. P2 – Bus connection to the UCIA board.
The site specific hardware document and the signal flow diagrams in Appendix D contain more specific information on the connectors. 5-4.2.2. PANA CONFIGURATION.
Hardware. The four switches on the PANA board are used to set the ARCNET COREBUS address for the core. Two are for BNC connector A and two are for BNC connector B. Hardware jumpers are used to set the interrupt, I/O address and memory address for each ARCNET channel. These settings are all factory specific to the internal software settings. Hardware jumper settings on replacement boards should be verified that they are configured the same as the hardware jumper settings on the old board. Refer to Appendix A and the hardware jumper screen on the operator interface for information on the hardware jumper settings for this board. Software. There is no software configuration used on the PANA board.
Note ARCNET addresses for both BNC connectors should be set to the same address. Some PANA boards may not include the components for the second ARCNET channel.
5-4.3. DS200STCA – Turbine Communication Board The Turbine Communication Board (STCA) functions as the IONET master for the I/O cores. Each of the I/O cores has an STCA board. Signals are read through the various connectors, conditioned and written to the I/O Engine located on the UCPB daughter board via the bus connectors J1 and J3. The signals are written to the COREBUS connections located on the QTBA or CTBA boards via the JEE connector. Figure 5-4 shows a typical layout of the STCA board.
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5-4.3.1. STCA CONNECTORS.
• • • •
• • • • • • •
2PL – Distributes power from the TCPS board in each I/O core. 3PL – The Data Bus between the STCA and TCQA boards in cores and , between STCA, TCQA, and TCQE boards in core , and between STCA, TCCA and TCCB boards in core . Conditioned signals are transferred to the COREBUS on the 3PL connector. 8PL – I/O connector to the TCQC boards in cores , , and and to the CTBA board in . Signals may include the COM1 RS232 output signals, the serial I/O signals, the AC and DC power monitoring signals (TCPD), and an auxiliary pulse rate magnetic pick up signal. 19PL – I/O connector to the TCQC board. The I/O signals may include megawatt, generator, and bus signals, and the magnetic pick up pulse rate signals from the high pressure shafts. Power bus and neutral bus signals may also be carried in this connector (TCPS). The 19PL connector may not be used in every core. Other signals could be carried on this connector. ARCNET – Interfaces the ARCNET signals from the UCPB daughter board in the I/O cores. COM1 – RS232 interface signals used for the terminal interface. FAN – Power connection to the fan that cools the 486DX CPU on the UCPB board. (Typically not used.) J1 – Bus connection to the UCPB daughter board. J3 – Bus connection to the UCPB daughter board. JEE – Communicates between the STCA board and the QTBA or CTBA terminal boards for the COREBUS. 2PLX – Parallels 2PL connections. (Typically not used.)
The site specific hardware document and the signal flow diagrams in Appendix D contain more specific information on the connectors. 5-4.3.2. STCA CONFIGURATION.
Hardware. Hardware jumper JP2 enables the test points for factory test. Hardware jumper JP4 selects the voltage needed for the flash EPROM. Refer to Appendix A and the hardware jumper screen on the operator interface for information on the hardware jumper settings for this board. Software. I/O configuration constants for the pulse rate inputs, compressor stall detector and synchronization settings are entered in the I/O Configurator on the operator interface as described in section 5-3.3. 5-4.3.3. STCA PULSE RATE INPUT CIRCUIT. The STCA board scales and conditions the pulse rate inputs read from the TCQC board. These signals originate from magnetic pick up devices whose signals are written to the TCQC board by the QTBA, TBQB, and/or PTBA terminal boards. The core reads the high pressure shaft pulse rate inputs. The pulse rate inputs in each core are independent and are used for different purposes. 5-4.3.4. STCA SYNCH CHECK CIRCUIT. The generator and bus voltage inputs are read from the TCQC board via the 19PL
connector. These signals originate on the PTBA terminal board in the core and are written to the TCTG board in the core via the JN connector. The signals are then passed through the TCTG board via the JDR/S/T connectors to the JD connector on the TCQA board in the core. The signals are passed through again to the TCQC board in the core via the JE connector. The TCQC board provides scaling and conditioning of the signals prior to writing them to the STCA board via the 19PL connector. The synchronizing check (synch check) is done on the STCA board and the results are sent back across the same path to the TCTG board where they are used in conjunction with the automatic sync signals for generator breaker commands.
5-4.4. DS200TCCA – COMMON ANALOG I/O BOARD The Common Analog I/O Board (TCCA), located in the core, scales and conditions analog signals from the CTBA, TBQA, and TBCA terminal boards mounted in the core. These signals include 4–20 mA inputs and outputs, RTD inputs , thermocouple inputs, shaft voltage inputs, and shaft current inputs. The signals are written to the STCA board via the 3PL connector.
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Figure 5-5 shows a typical layout of the TCCA board. 5-4.4.1. TCCA CONNECTORS.
• • • • • • • • •
2PL – Distributes power from the TCPS board in the core. 3PL – The Data Bus between the STCA, TCCA and TCCB boards in core . Conditioned signals are carried on 3PL for transferring to the COREBUS. JAA – Carries the 4–20 mA output signals to the CTBA terminal board. JBB – Carries the shaft voltage and current signals and 4–20 mA input signals from the CTBA terminal board. JCC – Carries RTD input signals from the TBCA terminal board. JDD – Carries RTD input signals from the TBCA terminal board. JAR/S/T – Carries Thermocouple input signals and cold junction inputs from the TBQA terminal board. JC – Carries the Power supply diagnostic signals from TCPS. JEE – Typically not used.
