vlsi qs

VLSI Interview Questions, VLSI Questions for ECE / Electronics / Nanotechnology / Chip designing technical interview for Electronics engineer job recruitment written test or tech interview.

Describe the working of a MOSFET. What is the sizing of an inverter? What are the different capacitances in a MOSFET. What is their significance? Draw the circuit design of a CMOS Inverter. Describe the transfer characteristics of a CMOS Inverter. What do you know about the Vds-Ids curve. Explain the variation variat ion of this curve (a) with increase in vgs (b) with increase in transistor width. What do you know about the channel length modulation? Why do we use small transistors transistors in parallel in case of o f a big inverter. Explain the method of o f sizing NMOS and PMOS transistors. How can we increase their thresho ld voltage? What do you understand by Noise margin? How can you find the noise margin? What do you understand by the CMOS switching power dissipation? What is meant by Body effect? What is scaling? How can you calculate the delay in case of CMOS Circuit? How is delay affected if we increase the load capacitance? How is the delay affected in case we put a resistance at the cmos circuit output? What precautions do we have to take while increasing the po wer supply to reduce the delay? How does the resistance of metal lines change with increase in length and thickness? Explain the working and diagram d iagram of a transistor level 2 input nand gat e. Exlain the sizing and characteristics for equal rise and fall time.

Let

X & Y be two inputs of the NAND gate. If signal X arrives at the Nand gate after the signal Y. To optimize delay, of the two series NMOS inputs X & Y, which one of these should be  placed near the output? How can we reduce the power consumption for a CMOS logic? What do you mean by charge sharing? Why do we experience this problem during sampling data from a bus. Incase of inverters, why don¶t we increase the size in buffer design? WHy can¶t we provide the output of one circuit to a large inverter? A layout is provided. You have to draw the transistor level circuit. Example: 3 input And Gate and 2 input multiplexer are pro vided) Prepare the transistor level equivalent of a AOI gate. Explain with a stick diagram. Why can¶t an NMOS transistor serve the purpose of a transmission gate? Describe the read and write operations of a 6-T SRAM cell. In a NMOS transistor, what will be the o/p for a square pulse input from 0 to VDD if the gate is  joined to VDD. Can we use an inverter in place of a Differential Sense Amplifier? Can we use channel length modulation to size the c ircuit of a differential sense amplifier? Describe the SRAM write circuitry. How can you select the size of the transistros in the SRAM Cell. What is the relation between the size o f PMOS pull up transistors and the resulting performace of  SRAM? Explain the critical path of a SRAM. What do you understand by Latch Up? How can you avoid Latch up in CMOS Inverter? Explain the difference between Testing and Verification? Can a SRAM be modelled at RTL Level?

Which metal layers are used for bit lines and word lines in case of SRAM layout? Why do we use these metal layers? Explain and draw the timing diagram of a SRAM Read. What are the affects of a delay in the clock signal enable? Can be asked to draw an draw / analyse an entire SRAM Layout consisting of Cells, Row and Column decoders and R/W Circuits, Buffers, etc. Circuit Problem: Test the stuck at 0 and stuck at 1 problems at the internal nodes for an ANDOR implementation of a two input Mux