1
2
3
4
PCB STACK UP
5
6
7
8
01
BLB Block Diagram
LAYER 1 : TOP LAYER 2 : GND LAYER 3 : IN1 LAYER 4 : IN2 A
LAYER 5 : VCC
A
LAYER 6 : BOT
USB-11
intel
INT_LVDS
P12,13
Dual Channel DDR III 1066/1333 MHZ
Sandy Bridge rPGA 989
(37.5mm X 37.5mm)
LCD/CCD Con. P15
LVDS Port-A
Graphics Interfaces
DDRIII-SODIMM1 DDRIII-SODIMM2
DDR SYSTEM MEMORY
INT_CRT
CRT Con. P15
HDMI Level Shift
INT_HDMI Port-B
HDMI
HDMI Con. P14
P14
FDI
P2~P5
DMI
SATA - HDD P18
DMI(x4) PCIE-2
B
FDI
SATA - ODD
SATA
SATA 4
B
P17
intel
SATA 0
P18
USB 3.0 (BTO)
DMI
POWER SYSTEM PCIE-3
USB-1
USB Con. (BTO)
USB 2.0 (Port0~13)
P16
CougarPoint
P17 USB-4
Cardreader
ISL88731CHRTZ-T ISL95835HRTZ-T RT8207LGQW RT8240BGQW G9661-25ADJF12U PM6686TR ISL95870AHRUZ-T
3G
USB-3
USB PCI-E
PCI-Express
RTC P21
USB-5
SIM Card Cardreader Con. P21 3 IN 1
mBGA 989
BATTERY
P16
P7
USB-8
USB Con.
PCIE-6
(25mm X 25mm)
Azalia
WLAN
USB-13
HDA
P23
+VCC_CORE
P16
P6~P11 LPC
C
P.25 P.30 P.27 P.28 P.31 P.26 P.29
+1.5V +1.5VSUS
USB-9
USB Con. P23
PCIE-7
C
+VTT +1.05V
Giga/10/100 Lan P20
+1.8V LPC
Audio Codec
EC P22
Port-A
Port-B
P19
FAN D
MIC JACK
MDC Con. P19
+3VPCU +3V_S5 +3V +5VPCU +5V_S5 +5V +SMDDR_VTERM +SMDDR_VREF +VGPU_CORE +VAXG +VCCSA
P19
HP
K/B Con.
HALL Sensor
SPI Flash
SPK Con. P19
P19
P2
P23
P22
P15
Touch Pad /B Con.
Power /B Con.
P23
D
P23
Quanta Computer Inc. PROJECT : BLB Size
Document Number
Rev F3A
Block Diagram Date: 1
2
3
4
5
6
7
Friday, December 24, 2010
Sheet 8
1
of
36
5
4
3
2
1
02
Sandy Bridge Processor (DMI,PEG,FDI) U17A
[6] [6] [6] [6]
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
G22 D22 F20 C21
[6] [6] [6] [6] [6] [6] [6] [6]
FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7
A21 H19 E19 F18 B21 C20 D18 E17
[6] [6] [6] [6] [6] [6] [6] [6]
FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7
A22 G19 E20 G18 B20 C19 D19 F17
[6] FDI_FSYNC0 [6] FDI_FSYNC1
J18 J17
[6] FDI_INT
H20 J19 H17
[6] FDI_LSYNC0 [6] FDI_LSYNC1
DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]
FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC
B2A 10/05 A18 A17 B16
eDP_COMP INT_eDP_HPD_Q
TP89
C15 D15 C17 F16 C16 G15 C18 E16 D16 F15
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]
eDP_COMPIO eDP_ICOMPO eDP_HPD eDP_AUX eDP_AUX#
PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
eDP
C
DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]
eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]
U17B
B2A 10/05 C26
[7] H_SNB_IVB# SKTOCC#
TP5
TP_CATERR#
TP3
J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32
AN34
AL33
AN33
[22] EC_PECI
R58
[22,30] H_PROCHOT#
H_PROCHOT#_R
56_4
AL32
PM_THRMTRIP#_R AN32
R49
[6] PM_SYNC
M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25
0_4
AP33
R61
10K_4 C945 0.1U/10V_4X
PECI
PROCHOT#
AR33
M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25
+VTT
R66
R67
*43_4
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
CPU_PLTRST#_R
*75/F_4 C117
CLK_CPU_BCLKP [8] CLK_CPU_BCLKN [8]
R443
1K_4
R444
1K_4
D
+VTT
B2A 10/05 CPU_DRAMRST#
R8
SM_DRAMRST#
B2A 10/05 AK1 A5 A4
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
SM_RCOMP_0 R452 SM_RCOMP_1 R441 SM_RCOMP_2 R442
140/F_4 25.5/F_4 200/F_4
THERMTRIP#
PM_DRAM_PWRGD_R CPU_PLTRST#
4 2 0X2
CATERR#
H_PWRGOOD_R V8
3 1 R440
A16 CLK_DPLL_SSCLKP_R A15 CLK_DPLL_SSCLKN_R
DPLL_REF_CLK DPLL_REF_CLK#
B2A 10/05
AP29 XDP_PRDY#_R AP27 XDP_PREQ#_R
PRDY# PREQ#
AM34
R63
SKTOCC#
A28 CLK_CPU_BCLKP_R A27 CLK_CPU_BCLKN_R
BCLK BCLK#
PM_SYNC_R
0_4
When XDP connect be use must change to 1K [9] H_PWRGOOD
PROC_SELECT#
CLOCKS
G21 E22 F21 D21
K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32
DDR3 MISC
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
TP80 TP81
AR26 XDP_TCLK_R AR27 XDP_TMS_R AP30 XDP_TRST#_R
TCK TMS TRST#
JTAG & BPM
[6] [6] [6] [6]
DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]
Sandy Bridge Processor (CLK,MISC,JTAG)
MISC
B28 B26 A24 B23
PEG_COMP
THERMAL
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
J22 J21 H22
PWR MANAGEMENT
[6] [6] [6] [6]
PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO
DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]
PCI EXPRESS* - GRAPHICS
B27 B25 A25 B24
DMI
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
Intel(R) FDI
D
[6] [6] [6] [6]
AR28 XDP_TDI_R AP26 XDP_TDO_R
TDI TDO
B2A 10/05 AL35
DBR#
XDP_DBR#_R
R917
AT28 XDP_OBS0_R AR29 XDP_OBS1_R AR30 XDP_OBS2_R AT30 XDP_OBS3_R AP32 XDP_OBS4_R AR31 XDP_OBS5_R AT31 XDP_OBS6_R AR32 XDP_OBS7_R
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
0_4
TP82 TP83 TP84 TP85 TP86 TP87 TP88 TP90
XDP_DBRST# [6]
C
B2A 10/05
0.1U/10V_4X ACA-ZIF-069-K01
E3A 1208
ACA-ZIF-069-K01 +VTT
Level Shift
3
Thermal Trip
S3 Power Reduction (SM_DRAMPWROK)
S3 Power Reduction (SM_DRAMRST#)
+3V_S5
+3V_S5 Q48
+1.5VSUS C143 *0.1U/10V_4X
U3 1
1
NC VCC
2
[8,16,17,20,22] PLTRST#
3
B
R524 1K_4
R507 100K_4
GND OUT
R471 1K/F_4 4
2
1.5K/F_4
R477
[12,13] DDR3_DRAMRST#
1 Q50
1K/F_4
C605 [email protected]/10V_4X
NS3@0_4
3
CPU_PLTRST#_R R479
1
CPU_DRAMRST#
Q43 S3@2N7002_200MA
S3@0_4
[6] SYS_PWROK
2
[6] PM_DRAM_PWRGD
1
SYS_SHDN# 3 MMBT3904-7-F_200MA
R784
SYS_SHDN# [26]
C651 [email protected]/10V_4X
750/F_4
R467 200/F_4
U19 PM_DRAM_PWRGD_Q
4
3
[8] DRAMRST_CNTRL_PCH PM_THRMTRIP#_R
R470
CPU_PLTRST#
*74LVC1G07GW R783
+1.5V_CPU
B2A 10/14
5
IN
S3@TC7SH08FU(F)
R469 [email protected]/F_4
PM_THRMTRIP#
R465
PM_THRMTRIP# [9]
R918
*S3@39/F_4
3
1
DP & PEG Compensation +VTT R20
24.9/F_4
C114
0.1U/10V_4X
3mA(40mils)
+VTT
+VTT
W=12mil; S=15mil; L<500mil
24.9/F_4 PEG_COMP
R446
R431
+5V
eDP_COMP
+VTT
H_PROCHOT# R54
62_4
XDP_TMS_R XDP_TDI_R XDP_TDO_R XDP_TCLK_R XDP_TRST#_R
51_4 51_4 *51_4 51_4 51_4
R111 R103 R110 R108 R97
+3V
+3V
E3A 1208 0.1U/10V_4X
MAINON_ON_G [3,4,12,31]
NS3@0_4
Processor pull-up FAN Control-->For one FAN solution C113
*S3@2N7002_200MA
B2A 10/01
[9,22] TEMP_ALERT#
TEMP_ALERT#
C33 CPUFAN#_ON_R_1 3 *2N7002_200MA
1 Q33
2.2U/6.3V_6X
2 1 4
[22] VFAN1
VIN
VO GND /FON GND GND VSET GND
3 5 6 7 8
G991P11U
CN11
*10K_4
40mils
U16
2
0_4
PM_DRAM_PWRGD_R
130/F_4
Q41 R523
B
R466
2
2N7002_200MA
5
[6,30] DELAY_VR_PWRGOOD
2
2
FANSIG1
[22] FANSIG1 TH_FAN_POWER1
1 2 3
C512
C511
C513
10U/6.3V_8X
*0.01U/25V_4X
*0.01U/25V_4X
85205-0300L
FANPWR = 1.6*VSET
W=12mil; S=15mil; L<500mil
+3VPCU
+3VPCU
A
A
CPU Thermal sensor / MB Local TEMP R807
R808
10K_4
330_4
U39 R809
+3VPCU_HW_SD
150_4
5
VCC
C891
SET GND
1
R810
24.9K/F_4
2
2
+3VPCU
0.1U/10V_4X 4
HYST
OT#
3
THER_SHD#
Q77
1
3
MMBT3904-7-F_200MA
SYS_SHDN#
Quanta Computer Inc.
G708T1U
PROJECT :BLB
Rset(Kohm)=0.0012T*T-0.9308T+96.147,Shut down on 86dgree Hysteresis is 30C
Size
Rev F3A
Sandy Bridge 1/4 Date:
5
Document Number
4
3
2
Friday, December 24, 2010 1
Sheet
2
of
36
5
4
3
2
1
03
Sandy Bridge Processor (DDR3) U17C
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
C
B
[12] M_A_BS#0 [12] M_A_BS#1 [12] M_A_BS#2
[12] M_A_CAS# [12] M_A_RAS# [12] M_A_WE#
C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15
SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
AE10 AF10 V6
SA_BS[0] SA_BS[1] SA_BS[2]
AE8 AD9 AF9
SA_CAS# SA_RAS# SA_WE#
SA_CLK[0] SA_CLK#[0] SA_CKE[0]
SA_CLK[1] SA_CLK#[1] SA_CKE[1]
AB6 AA6 V9
M_A_CLKP0 [12] M_A_CLKN0 [12] M_A_CKE0 [12]
AA5 AB5 V10
M_A_CLKP1 [12] M_A_CLKN1 [12] M_A_CKE1 [12]
RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]
AB4 AA4 W9
RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]
AB3 AA3 W10
SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8]
AK3 AL3 AG1 AH1
M_A_CS#0 [12] M_A_CS#1 [12]
SA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10]
AH3 AG3 AG2 AH2
M_A_ODT0 [12] M_A_ODT1 [12]
C4 G6 J3 M6 AL6 AM8 AR12 AM15
M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7
SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]
D4 F6 K3 N6 AL5 AM9 AR11 AM14
M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
[13] M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
M_A_DQSN[7:0] [12]
M_A_DQSP[7:0] [12]
M_A_A[15:0] [12]
[13] M_B_BS#0 [13] M_B_BS#1 [13] M_B_BS#2
[13] M_B_CAS# [13] M_B_RAS# [13] M_B_WE#
ACA-ZIF-069-K01
C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15
SB_CLK[0] SB_CLK#[0] SB_CKE[0]
SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]
AA9 AA7 R6
SB_BS[0] SB_BS[1] SB_BS[2]
AA10 AB8 AB9
SB_CAS# SB_RAS# SB_WE#
SB_CLK[1] SB_CLK#[1] SB_CKE[1]
DDR SYSTEM MEMORY B
[12] M_A_DQ[63:0]
DDR SYSTEM MEMORY A
D
U17D
AE2 AD2 R9
M_B_CLKP0 [13] M_B_CLKN0 [13] M_B_CKE0 [13]
AE1 AD1 R10
M_B_CLKP1 [13] M_B_CLKN1 [13] M_B_CKE1 [13]
RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]
AB2 AA2 T9
RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]
AA1 AB1 T10
SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18]
AD3 AE3 AD6 AE6
M_B_CS#0 [13] M_B_CS#1 [13]
SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20]
AE4 AD4 AD5 AE5
M_B_ODT0 [13] M_B_ODT1 [13]
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
D7 F3 K6 N3 AN5 AP9 AK12 AP15
M_B_DQSN0 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
C7 G3 J6 M3 AN6 AP8 AK11 AP14
M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7
SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
D
C
M_B_DQSN[7:0] [13]
M_B_DQSP[7:0] [13]
M_B_A[15:0] [13]
B
ACA-ZIF-069-K01
S3 Power Reduction Sequence B2A 10/14
D3A 1111
NS3@0_6
D3A 1111
A
MAINON [22,28,31] +3V_S5
U23
5
R548
[27] S3_1.5V
A
2 *S3@0_4
R842
R550
S3@100K_4 4
3
3
1
HWPG_1.5V_CPUVDDQ [4]
S3@TC7SH08FU(F)
2
1
[22] S3_Power Sequence
Quanta Computer Inc.
MAINON_ON_G [2,4,12,31]
PROJECT : BLB
Q52 S3@2N7002K_300MA
Size
Document Number
Rev F3A
Sandy Bridge 2/4 Date: 5
4
3
2
Friday, December 24, 2010
Sheet 1
3
of
36
4
3
2
Sandy Bridge Processor (POWER)
POWER
POWER U17G
C55 C@10U/6.3V_6X
C544 10U/6.3V_8X
C545 C@10U/6.3V_6X
C83 10U/6.3V_8X
C574 10U/6.3V_8X
C551 C@10U/6.3V_6X
C563 *10U/6.3V_8X
B
B2A 10/07
C543 10U/6.3V_8X
C553 10U/6.3V_8X
C554 C@10U/6.3V_6X
C97 *10U/6.3V_8X
A
VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40
C77 10U/6.3V_8X
C567 10U/6.3V_8X
C43 10U/6.3V_8X
C96 10U/6.3V_8X
C67 10U/6.3V_8X
C539 10U/6.3V_8X
C149 IV@22U/6.3V_8X
C565 IV@10U/6.3V_8X
C168 IV@10U/6.3V_8X
C564 IV@10U/6.3V_8X
C95 IV@22U/6.3V_8X
C159 IV@10U/6.3V_8X
C158 IV@10U/6.3V_8X
C177 IV@10U/6.3V_8X
E3A 1210
B2A 10/07
E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11
C46 *10U/6.3V_8X
C42 10U/6.3V_8X
C169 C@10U/6.3V_8X
C519 *10U/6.3V_8X
C44 *10U/6.3V_8X
C98 IV@22U/6.3V_8X
C99 IV@22U/6.3V_8X
C566 C@10U/6.3V_8X
C45 *10U/6.3V_8X
E3A 1210
R445
J23
0_4
+VTT
B2A 10/07 R463
*EV@0_4
B6 A6 A2
+1.8V
VIDALERT# VIDSCLK VIDSOUT
AJ29 AJ30 AJ28
H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT
C518 C@10U/6.3V_8X
C517 1U/6.3V_4X
C521 1U/6.3V_4X
+ C515 C@330U/2V_7343P_E6b
VREF
C520 10U/6.3V_8X
VCCPLL1 VCCPLL2 VCCPLL3
+VDDR_REF_CPU
AL1
SM_VREF
AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15
+1.5V_CPU C526 C561 C570 C573 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X
C527 C556 10U/6.3V_8X 10U/6.3V_8X
VCC_SENSE VSS_SENSE
VCCIO_SENSE VSSIO_SENSE
AJ35 AJ34
B10 A10
R42 R45
R892 R893
R44
100_4
R891
*100_4
R894
*100_4
0_4 0_4
C
M27 M26 L26 J26 J25 J24 H26 H25
VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8
+VCCSA + C514 C59 C54 C530 *330U/2V_7343P_E6b 10U/6.3V_8X 10U/6.3V_8X C@10U/6.3V_8X
H23
VCCSA_SENSE
R18
0_4
VCCSA_VCCSSENSE
FC_C22 VCCSA_VID1
*0_4 *0_4
R40
3 0_4
VR_SVID_CLK
VCCP_SENSE [28] VSSP_SENSE [28]
+VTT
[29]
B2A 10/05
+1.5VSUS
Q39 S3@2N7002_200MA R454 100K_4
B
+1.5V_CPU
[26,27,31]
0_4
+1.5V_CPU
VR_SVID_DATA
NS3@0_1206
E3A 1207
4.5A 4 Q36 S3@AO6402A
C536 *S3@470P/50V_4X
R451 S3@220_8
+3V_S5
[30]
Q38 S3@2N7002_200MA
HWPG_1.5V_CPUVDDQ
D3A 1111
2
MAINON_ON_G
R65 S3@10K_4
R64 S3@10K_4
+VTT
R907
MAIND
MAIND
[2,3,12,31]
R35
NS3@0_1206
6 5 2 1
S3 Power Reduction Sequence
0.1U/10V_4X
R930
+1.5V_CPU
B2A 10/14
E3A 1208 C116
C557 C528 C549 [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X
R37 130/F_4 H_CPU_SVIDDAT
10K_4
1
[30]
+VTT
B2A 10/22
10K_4
R919
+VDDR_REF_CPU
C534 [email protected]/10V_4X
Place PU resistor close to CPU
D3A 1117
R19
NS3@0_8
MAIND VCC_SENSE [30] VSS_SENSE [30]
[29]
B2A 10/07 C22 VCCSA_VID0 C24 VCCSA_VID1
VCCSA_VID1
R456
+VCC_CORE
+VTT
+ C523 C@330U/2V_7343P_E6b
B2A 10/07
Place PU resistor close to CPU ACA-ZIF-069-K01
A
[3]
Q3 S3@2N7002_200MA R3028 R38 75/F_4 H_CPU_SVIDALRT# R34
5
+VDDR_REF_CPU
B2A 10/07
+SMDDR_VREF
100_4
D
+1.5VSUS
Layout note: need routing together and ALERT need between CLK and DATA
R41
VCC_AXG_SENSE [30] VSS_AXG_SENSE [30]
S3 Power Reduction (CPU POWER)
SVID
+VAXG
W=20mil; S=20mil; L<500mil
ACA-ZIF-069-K01
H_CPU_SVIDCLK
IV@100_4
3
C80 C@10U/6.3V_6X
C546 10U/6.3V_8X
C547 10U/6.3V_8X
C60 10U/6.3V_8X
C88 10U/6.3V_8X
R888
3
C61 10U/6.3V_8X
C531 10U/6.3V_8X
C68 10U/6.3V_8X
C47 10U/6.3V_8X
4
3
43_4
S3@1K_4
2
2
VR_SVID_ALERT#
Quanta Computer Inc.
Q1 S3@FDV301N_200MA
B2A 10/01 C3044 *[email protected]/10V_4X
[30]
1
C555 10U/6.3V_8X
C571 10U/6.3V_8X
C57 10U/6.3V_8X
IV@100_4
IV@0_4 IV@0_4 R51
3
C552 10U/6.3V_8X
C87 10U/6.3V_8X
C532 10U/6.3V_8X
1
C537 10U/6.3V_8X
C580 10U/6.3V_8X
AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12
2
C
C538 10U/6.3V_8X
PEG AND DDR
C74 10U/6.3V_8X
SVID
E3A 1210
VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24
SENSE LINES
+ C592 *470U/2V_7343P_E6b
CORE SUPPLY
+ C591 330U/2V_7343P_E9c
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100
+ C516 C@330U/2V_7343P_E6b
DDR3 -1.5V RAILS
+ C606 IV@330U/2V_7343P_E9c
R887 R48 VCC_AXG_SENSE_R VSS_AXG_SENSE_R
AK35 AK34
VAXG_SENSE VSSAXG_SENSE
SA RAIL
+VCC_CORE D
MISC
+VTT
VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54
GRAPHICS
AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17
SENSE LINES
E3A 1207 +VAXG
1.8V RAIL
B2A 10/07
AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26
04
Sandy Bridge Processor (GRAPHIC POWER) B2A 10/07
B2A 10/07
1
U17F
1
3
5
PROJECT : BLB Size
Document Number
Date:
Friday, December 24, 2010
Rev F3A
Sandy Bridge 3/4 2
1
Sheet
4
of
36
4
3
2
Sandy Bridge Processor (GND) U17H
D
C
B
AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25
VSS
VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160
AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W 35 W 34 W 33 W 32 W 31 W 30 W 29 W 28 W 27 W 26 U9 U8 U6 U5 U3 U2
ACA-ZIF-069-K01
Processor Strapping
VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233
A
VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285
VSS
F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3
CFG0
TP91 TP2
CFG2
TP6
CFG4 CFG5 CFG6 CFG7
[12] DDR_VREF_DQ0 [13] DDR_VREF_DQ1
R12 *1K_4
R13 *1K_4
+3V
AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29
CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]
AJ31 AH31 AJ33 AH33
VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE
AJ26
RSVD5
B4 D1
RSVD6 RSVD7
F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29
RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23
J20 B18 A19
RSVD24 RSVD25 VCCIO_SEL
J15
RSVD27
R17 10K_4
RSVD28 RSVD29 RSVD30 RSVD31 RSVD32
L7 AG7 AE7 AK2 W8
RSVD33 RSVD34 RSVD35
AT26 AM33 AJ27
RSVD37 RSVD38 RSVD39 RSVD40
T8 J16 H16 G16
RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
AR35 AT34 AT33 AP35 AR34
RSVD46 RSVD47 RSVD48 RSVD49 RSVD50
B34 A33 A34 B35 C35
RSVD51 RSVD52
AJ32 AK32
VCC_DIE_SENSE
AH27
RSVD54 RSVD55
AN35 AM35
RSVD56 RSVD57 RSVD58
AT2 AT1 AR1
D
C
CLK_XDP_ITPP CLK_XDP_ITPN
TP92 TP93
B2A 10/05
B
KEY
B1
ACA-ZIF-069-K01
ACA-ZIF-069-K01
B2A 10/05
The CFG signals have a default value of '1' if not terminated on the board.
1 CFG2 (PEG Static Lane Reversal)
U17E
B2A 10/05 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29
05
Sandy Bridge Processor (RESERVED, CFG)
U17I
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80
1
RESERVED
5
0
Normal Operation
Lane Reversed
CFG4 (DP Presence Strap)
Disable; No physical DP attached to eDP
Enable; An ext DP device is connected to eDP
CFG7 (PEG Defer Training)
PEG train immediately following xxRESETB de assertion
PEG wait for BIOS training
CFG2
R74
*EV@1K/F_4
CFG4
R68
*1K/F_4
CFG7
R71
*1K/F_4
CFG[6:5] (PCIE Port Bifurcation Straps) CFG5 CFG6
R69 R70
11: 10: 01: 00:
*1K/F_4 *1K/F_4
(Default) x16 - Device 1 functions 1 and 2 disabled x8, x8 - Device 1 function 1 enabled ; function 2 disabled Reserved - (Device 1 function 1 disabled ; function 2 enabled) x8,x4,x4 - Device 1 functions 1 and 2 enabled
A
Quanta Computer Inc. PROJECT : BLB Size
Document Number
Rev F3A
Sandy Bridge 4/4 Date: 5
4
3
2
Sheet
Friday, December 24, 2010 1
5
of
36
5
4
3
2
Cougar Point (DMI,FDI,PM)
U25D
[2] [2] [2] [2]
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
AW24 AW20 BB18 AV18
DMI0TXN DMI1TXN DMI2TXN DMI3TXN
[2] [2] [2] [2]
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
AY24 AY20 AY18 AU18
FDI
DMI0TXP DMI1TXP DMI2TXP DMI3TXP
BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9
FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7
[2] [2] [2] [2] [2] [2] [2] [2]
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7
BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9
FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7
[2] [2] [2] [2] [2] [2] [2] [2]
FDI_INT BJ24 +1.05V
FDI_INT
AV12
FDI_FSYNC0
[2]
FDI_FSYNC1
BC10
FDI_FSYNC1
[2]
R204
750/F_4
BH21
DMI2RBIAS
FDI_LSYNC0
AV14
FDI_LSYNC0
[2]
BB10
FDI_LSYNC1
[2]
System Power Management
[2] XDP_DBRST#
R380
0_4
XDP_DBRST#
K3
SYS_PWROK
P12
EC_PWROK_R
L22
MPWROK
L10
B2A 10/05 [2] PM_DRAM_PWRGD
PM_DRAM_PWRGD
B13
RSMRST#
C21
[22] RSMRST#
SUS_PWR_ACK_R K16
E20
[22] DNBSWON# AC_PRESENT_R
H20
SYS_RESET#
WAKE#
+3V
SYS_PWROK PWROK
DPWROK
+3V_S5
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
APWROK
+3V_S5
SUSCLK / GPIO62
DRAMPWROK
+3V_S5
SLP_S5# / GPIO63
RSMRST#
SUSWARN#/SUSPWRDNACK/GPIO30
+3V_S5 SLP_S3#
PWRBTN#
SLP_A#
ACPRESENT / GPIO31
DSW
DSWVREN
SLP_SUS#
PM_RI#
[15] INT_TXLOUT0[15] INT_TXLOUT1[15] INT_TXLOUT2-
AN48 AM47 AK47 AJ48
[15] INT_TXLOUT0+ [15] INT_TXLOUT1+ [15] INT_TXLOUT2+
AN47 AM49 AK49 AJ47
PCIE_WAKE#
PCIE_WAKE#
N3
CLKRUN#
CLKRUN#
G8
RSV_SUS_SATA#
SUSCLK [22]
D10
INT_CRT_BLU INT_CRT_GRE INT_CRT_RED
[15] INT_CRT_BLU [15] INT_CRT_GRN [15] INT_CRT_RED
SUSC# [22]
F4
SUSB# [22] R696
[15] INT_CRT_DDCCLK [15] INT_CRT_DDCDAT
[15] INT_HSYNC [15] INT_VSYNC
R293 R296
IV@33/F_4 INT_HSYNC_R IV@33/F_4 INT_VSYNC_R
A10
BATLOW# / GPIO72 +3V_S5
PMSYNCH
+3V_S5
SLP_LAN# / GPIO29
RI#
DAC_IREF
AP14 K14
LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3
N48 P49 T49
CRT_BLUE CRT_GREEN CRT_RED
T39 M40
CRT_DDC_CLK CRT_DDC_DATA
M47 M49
CRT_HSYNC CRT_VSYNC
PM_SYNC
[2]
SLP_LAN#
R290
IV@150/F_4 INT_CRT_BLU
R283
IV@150/F_4 INT_CRT_GRN
R271
IV@150/F_4 INT_CRT_RED
T43 T42
R643 1K/F_4
AP43 AP45 AM42 AM40
D
AP39 AP40
P38 M39
SDVO_CTRLCLK [14] SDVO_CTRLDATA [14]
DDPB_AUXN DDPB_AUXP DDPB_HPD
AT49 AT47 AT40
Port-B_HPD [14]
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49
TMDSD_DATA2# [14] TMDSD_DATA2 [14] TMDSD_DATA1# [14] TMDSD_DATA1 [14] TMDSD_DATA0# [14] TMDSD_DATA0 [14] TMDSD_CLK# [14] TMDSD_CLK [14]
DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
*0_4
SLP_SUS#_R
R place close to PCH E10
LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3
T35
H4
G16
32.768K output
SDVO_CTRLCLK SDVO_CTRLDATA
LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3
AH43 AH49 AF47 AF43
*33P/50V_4N
SDVO_INTN SDVO_INTP
LVDSA_CLK# LVDSA_CLK
TP30
N14
G10
[17,20]
SDVO_STALLN SDVO_STALLP
LVD_VREFH LVD_VREFL
AH45 AH47 AF49 AF45
[22]
SDVO_TVCLKINN SDVO_TVCLKINP
LVD_IBG LVD_VBG
AK39 AK40
E22 DPWROK_R B9
AF37 AF36
AF40 AF39
B
PM_BATLOW#
LVD_IBG
DSWVREN [7]
C445
SLP_S4#
[email protected]/F_4
[2]
FDI_FSYNC0
SUSACK#
L_CTRL_CLK L_CTRL_DATA
[email protected]_4 [email protected]_4
L_BKLTEN L_VDD_EN
AE48 AE47
DMI_IRCOMP
C12
T45 P39
R654 R685
T29
DMI_ZCOMP
SUSACK_R
L_DDC_CLK L_DDC_DATA
+3V
BG25
C
L_BKLTCTL
T40 K47
[15] INT_TXLCLKOUT[15] INT_TXLCLKOUT+
AW16
A18
[15] INT_LVDS_PWM
P45
R248
49.9/F_4 DMI_COMP
DSWVRMEN
J47 M45
[15] INT_LVDS_EDIDCLK [15] INT_LVDS_EDIDDATA
R209
FDI_LSYNC1
[22] INT_LVDS_BLON [15] INT_LVDS_DIGON
Digital Display Interface
DMI0RXP DMI1RXP DMI2RXP DMI3RXP
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
LVDS
[2] DMI_RXP0 [2] DMI_RXP1 [2] DMI_RXP2 [2] DMI_RXP3
BE24 BC20 BJ18 BJ20
DMI0RXN DMI1RXN DMI2RXN DMI3RXN
CRT
BC24 BE20 BG18 BG20
DAC_IREF CRT_IRTN
INT. HDMI
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI
D
06
Cougar Point (LVDS,DDI)
U25C
[2] [2] [2] [2]
1
P46 P42 AP47 AP49 AT38
C
AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 M43 M36 AT45 AT43 BH41 BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 B
CougarPoint_R1P0
CougarPoint_R1P0
PCH Pull-high/low
*IV@0_4
System PWR_OK
R922
Deep Sx
E3A 1210 HWPG_VAXG [30]
+3V_S5
+3V
D48
+3V_S5 CLKRUN# XDP_DBRST#
R674 R675
PM_RI#
8.2K_4 10K_4
R713
10K_4
PM_BATLOW#
R332
8.2K_4
PCIE_WAKE#
R712
10K_4
0_4
*IV@SW1010CPT_100MA
R381
10K_4
+3V_S5
R391
*10K_4
+3V_DSW
R365
*0_4
Net Name
R929 DELAY_VR_PWRGOOD
[2,30]
AC_PRESENT_R
AC_PRESENT
RSMRST#
R717
10K_4
SLP_LAN#
R710
10K_4
SYS_PWROK
R330
10K_4
SUS_PWR_ACK_R
R736
10K_4
A
INT_LVDS_BLON R889
PM_DRAM_PWRGD R715
*100K_4
S3@200/F_4
U14 [2] SYS_PWROK
SYS_PWROK
*SW1010CPT_100MA R744
D3A 1111
5
B2A 10/05
SUS_PWR_ACK_R
R747
1
MPWROK
MPWROK [22,30]
DPWROK_R
0_4
R360
0_4
R376
*0_4
R381 stuff
SUS_PWR_ACK
R744 stuff
R747 stuff
DPWROK
R376 stuff
R360 stuff
SLP_SUS
R738 stuff
R738 No stuff
SUSACK_R
*0_4
SUS_PWR_ACK
A
[22]
2 4
RSMRST#
*TC7SH08FU(F)
Quanta Computer Inc.
3
B2A 10/05
R344 *100K_4
SYS_HWPG
[22,26]
B2A 10/05
PROJECT : BLB SLP_SUS#_R
R785
R738
*0_4
SLP_SUS# [22]
Size
4
3
2
Document Number
Rev F3A
Cougar Point 1/6
0_4 Date:
5
Deep Sx No Support
R391,R365 stuff
[22]
D49 C444 *0.1U/10V_4X
Deep Sx Support
AC_PRESENT
Sheet
Friday, December 24, 2010 1
6
of
36
5
4
(30mils) +3V_RTC
D16
SDM10K45-7-F_100MA
R404
C486
G2
1U/6.3V_4X
*SHORT_ PAD
C815
SDM10K45-7-F_100MA
R401
U25A Y4 32.768KHZ_20
SRTC_RST#
20K_6
R737 10M_4
3 4
D15
C478
G1
1U/6.3V_4X
*SHORT_ PAD
C816
18P/50V_4C
RTC_X1
A20
RTC_X2
C20
C490 R415
RTC_RST#
D20
SRTC_RST#
G22
1U/10V_6X
+3V_RTC
R361
1M_4
+3V_S5
(20mils)
SM_INTRUDER#
K22
PCH_INVRMEN
C17
ACZ_BITCLK_R
N34
ACZ_SYNC_R
L34
PCBEEP
T10
ACZ_RST#_R
K34
ACZ_SDIN0_AUDIO
E34
RTCX1 RTCX2
FWH0 / FWH1 / FWH2 / FWH3 /
LAD0 LAD1 LAD2 LAD3
RTCRST# FWH4 / LFRAME# SRTCRST# INTRUDER#
LDRQ0# LDRQ1# / GPIO23
+3V
INTVRMEN
SERIRQ
C38 A38 B37 C37
LAD0 LAD1 LAD2 LAD3
D36
LFRAME# [16,22]
E36 PCH_DRQ#0 K36
+3V SERIRQ GPIO21 GPIO19
R272 R686 R671
8.2K_4 10K_4 10K_4
TP32 D
LDRQ#1 [16]
SERIRQ
V5
[16,22] [16,22] [16,22] [16,22]
SERIRQ [16,22]
1
RTC_N02
1K_4 D
07
Cougar Point (HDA,JTAG,SATA)
18P/50V_4C
(20mils) R_3VRTC
1
RTC_RST#
20K_6
LPC
(20mils)
2
RTC
+3VPCU
3
PCH2
2 1
RTC Circuitry