TAREA 2 VHDL 2018 - II Curso: Circuitos Digitales Profesor: RUBEN ALARCON MATTUTI Integrantes: -GUERRA RAMOS JURGUEN 17190099 -VALERIANO -V ALERIANO MUÑOZ ERICK HEBERT 17190141 -MAMANI GONGORA JAIRO CESAR 17190001
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TAREA 2 VHDL - 2018
TAREA 2 VHDL CONTENIDO PROBLEMA 2.................................................................... 2.......................................................................................................................................... ................................................................................... ............. 3 PROBLEMA 5.11 .............................................................. .................................................................................................................................... ................................................................................... .............4 PREGUNTA 5.17 .................................................................................................................................................. ..................................................................................................................................................6 PROBLEMA 5.37 .............................................................. .................................................................................................................................... ................................................................................... .............8 PREGUNTA 6.18 ................................................................................................................................................ ................................................................................................................................................10 PROBLEMA 6.26 .............................................................. .................................................................................................................................... ................................................................................. ...........13
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TAREA 2 VHDL - 2018
PROBLEMA 2
A. En el caso de binario natural el codigo VHDL viene equipado con un comparador
de numeros en binario natural para el cual basta con colocar los simbolos <, > == . LIBRARY ieee; USE ieee.std_logic_1164.all; ieee.std_logic_1164.all; ENTITY DOSA IS PORT( A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Mayor, menor, igual : OUT STD_LOGIC) ; END DOSA; -- COMPARADOR PARA BINARIO NATURAL ARCHITECTURE situacion OF DOSA IS BEGIN mayor <= '1' when (A>B) else '0'; -- A > B, salida mayor a 1 menor <= '1' when (A
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TAREA 2 VHDL - 2018
PROBLEMA 5.11 Escriba el código VHDL para especificar el circuito de la figura 5.43
VHDL
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TAREA 2 VHDL - 2018 Y2 Y3 X0 X1 X2 X3
: in : in : in : in : in : in
STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; C0 : in STD_LOGIC; STD_LOGIC; V : out STD_LOGIC; STD_LOGIC; N : out STD_LOGIC; STD_LOGIC; Z : out STD_LOGIC); STD_LOGIC); end Sum_4_bits; architecture Behaviora Behaviorall of Sum_4_bits is signal S0,S1,S2,S3,C1,C2,C3,C4 S0,S1,S2,S3,C1,C2,C3,C4 : STD_LOGIC; STD_LOGIC; begin S0 <= ((not Y0) xor X0) xor C0; C1 <= ((not Y0) and X0) or (C0 and ((not Y0) xor X0)); S1 <= ((not Y1) xor X1) xor C1; C2 <= ((not Y1) and X1) or (C1 and ((not Y1) xor X1)); S2 <= ((not Y2) xor X2) xor C2; C3 <= ((not Y2) and X2) or (C2 and ((not Y2) xor X2)); S3 <= ((not Y3) xor X3) xor C3; C4 <= ((not Y3) and X3) or (C3 and ((not Y3) xor X3)); Z <= not (S0 or S1 or S2 or S3); V <= C4 xor C3; N <= S3; end Behavioral;
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TAREA 2 VHDL - 2018
EN DSCH
:
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TAREA 2 VHDL - 2018 Considere el código de VHDL de la fi gura P5.2. Dada la relación entre las señales IN y OUT, ¿cuál es la funcionalidad del circuito descrito por el código? Comente si este código constituye o no un buen estilo para la funcionalidad que representa. LIBRARY ieee ; USE ieee.std_logic_1164.all ieee.std_logic_1164.all ; ENTITY problem5 IS PORT ( Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END problem5 ; ARCHITECTURE LogicFunc OF problem5 IS BEGIN WITH Input SELECT Output<= "0001" WHEN "0101", "0010" WHEN "0110", "0011" WHEN "0111", "0010" WHEN "1001", "0100" WHEN "1010", "0110" WHEN "1011", "0011" WHEN "1101", "0110" WHEN "1110", "1001" WHEN "1111", "0000" WHEN OTHERS ; END LogicFunc ;
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TAREA 2 VHDL - 2018
El código representa un multiplicador, multiplica los dos bits inferiores o la entrada por los dos superiores bits de entrada, produciendo la salida de cuatro bits. Por ejemplo 01 x 01 = 0001; 11x11=1001 El estilo del código no es adecuado, porque no es evidente lo que está tratando de describir.
PROBLEMA 5.37 Escriba el código de VHDL para especificar el circuito de la figura 5.36
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TAREA 2 VHDL - 2018
VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SUMA_BCD is Port ( Y0 Y0 : in STD_LOGIC; STD_LOGIC; Y1 : in STD_LOGIC; STD_LOGIC; Y2 : in STD_LOGIC; STD_LOGIC; Y3 : in STD_LOGIC; STD_LOGIC; X0 : in STD_LOGIC; STD_LOGIC; X1 : in STD_LOGIC; STD_LOGIC; X2 : in STD_LOGIC; STD_LOGIC; X3 : in STD_LOGIC; STD_LOGIC; C0 : in STD_LOGIC; STD_LOGIC; S0 : out STD_LOGIC; STD_LOGIC; S1 : out STD_LOGIC; STD_LOGIC; S2 : out STD_LOGIC; STD_LOGIC; S3 : out STD_LOGIC; STD_LOGIC; C4 : out STD_LOGIC); STD_LOGIC); end SUMA_BCD; architecture Behavioral of SUMA_BCD is signal SS0,SS1,SS2,SS3,CC4,CC1,CC2,C SS0,SS1,SS2,SS3,CC4,CC1,CC2,CC3,C1,C2,C3,BB1 C3,C1,C2,C3,BB1 : STD_LOGIC; STD_LOGIC;
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TAREA 2 VHDL - 2018 C2 <= (SS1 and BB1) or (C1 and (SS1 xor BB1)); S2 <= (SS2 xor BB1) xor C2; C3 <= (SS2 and BB1) or (C2 and (SS2 xor BB1)); S3 <= (SS3 xor C0) xor C3; C4 <= (SS3 and C0) or (C3 and (SS3 xor C0)); end Behavioral;
EN DSCH:
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TAREA 2 VHDL - 2018 Considere el código de VHDL de la figura. figura. ¿Qué tipo de circuito representa? Comente si el estilo de código usado es una buena elección para el circuito que representa. LIBRARY ieee ; USE ieee.std_logic_1164.all ieee.std_logic_1164.all ; ENTITY problem IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y0, y1, y2, y3 : OUT STD_LOGIC STD_LOGIC ) ; END problem ; ARCHITECTURE Behavior OF problem IS BEGIN PROCESS (w, En) BEGIN y0 <=’0’ ; y1 <=’0’ ; y2 <=’0’ ; y3 <=’0’ ; IF En ’1’ THEN IF w ”00” THEN y0 <= ’1’ ; ELSIF w ”01” THEN y1 <= ’1’ ; ELSIF w ”10” THEN y2 <=’1’ ; ELSE y3 <=’1’ ; END IF ; END IF ; END PROCESS ; END Behavior ;
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TAREA 2 VHDL - 2018 USE ieee.std_logic_1164.all ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw<= En & w ; WITH Enw SELECT y <= ”1000” WHEN ”100”, ”0100” WHEN ”101”, ”0010” WHEN ”110”, ”0001” WHEN ”111”, ”0000” WHEN OTHERS ; END Behavior ;
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TAREA 2 VHDL - 2018
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TAREA 2 VHDL - 2018
Código en VHDL
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TAREA 2 VHDL - 2018 END Behavior ; ---- CODIGO PARA CONVERTIR EL VHDL EN UN COMPONENTE QUE REUTILIZAR EN OTRO COMPONENTE LIBRARY ieee ; USE ieee.std_logic_1164.all ieee.std_logic_1164.all ; PACKAGE if2to4_package IS COMPONENT if2to4 PORT ( w : IN STD_LOGIC_VECTOR(1 STD_LOGIC_VECTOR( 1 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT ; END if2to4_package ;
SE PUEDA
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TAREA 2 VHDL - 2018 BEGIN aux(0) <= w(2); aux(1) <= w(1); Ifto1: if2to4 PORT MAP ( aux, w(2), Oua ) ; Ifto2: if2to4 PORT MAP ( aux, Not (w(2)), Oub ) ; END Behavior ;