Simplification of Boolean Functions

4. Simplification of Boolean Functions

4-1

Chapter 4. Simplification of Boolean Functions Boolean Cubes and Boolean Functions 0

1

00

01

10

11

(a) n = 1

(b) n = 2

011

010

001

000

(c) n = 3 110

100

111

101

0011

0010

0001

0000

0110 0111

(d) n = 4 0100 0101

1110 1111

1100

1110 1011

1000

1001

Figure 1: Boolean cubes [Gajski].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005


4-2



A Boolean -cube uniquely represents a Boolean function of each vertex is assigned a 1 (marked) or 0 (unmarked).



Each vertex of the -cube represents a minterm (a row in the truth table).

variables if

Example 1 Fig. Fi g. 2 sh show owss the tr truth uth ta table ble an and d th thee co corre rresp spon ondin ding g cu cube be rep repre rese senta ntatio tions ns of the ca carry rry and sum functions. c i x i y i

c i+1 s i

0 0 0 0 1 1 1 1

0 0 0 1 0 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 1 0 1 0 0 1

(a) Truth table 011

010

001

000

110

111

101

100

(b) Carry function c i+1 011

010

001

000

110

100

111

101

(c) Sum function function s i

Figure 2: Boolean-cube representations for carry and sum functions [Gajski]. 

(a) Each -subcube of the -cube represents minterms with the same literals, literal s, where ; (b) each -subcube with 1-minterms represents a product term of literals.



A prime implica implicant nt (PI) is a subcube (of 1-minterms) that is not contained in any other subcube (of 1-minterms); an essential prime implicant (EPI) is a PI that contains a 1-minterm that is not contained in any other PI.


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4-3

Map Representation 

Complexity of digital circuit (gate count) sion (literal count).



A function’s truth-table representation is unique; its algebraic expression is not. Simplifi Simplification cation by algebraic means is awkward (from algorithmic algorithmic point of view).



A Karn Karnaug augh h map (K-m (K-map) ap) is an ar arra ray y of sq squa uare ress ea each ch re repr pres esen enti ting ng on onee mi mint nter erm. m. Simplificatio Simpli fication n by the map method is straigh straightforwa tforward. rd.

complexity of algebraic expres-

x 0

1 (a) n = 1

y 0 m0

x

1 m1

0 1

(b) n = 2

m3

m2

yz 00 m0

x 0

01 m1

11 m3

10 m2 (c) n = 3

1 m4

zw xy 00 01

00

m5

01

m7

11

m6

10

m0

m1

m3

m2

m4

m5

m7

m6

m12

m13

m15

m14

m8

m9

m11

m10

11 10

(d) n = 4

Figure 3: Boolea Boolean n cubes and corresponding corresponding Karnaugh maps [Gajski].



Each K-map defines a unique Boolean function. 

A Boolean function can be represented by a truth table, a Boolean expression, pressio n, an -cube, or a map.


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4. Simplification of Boolean Functions 

4-4

K-map is in fact a visual diagram of all possible ways a function may be expressed—the simplest one can easily be identified.  

K-maps provide visual aid to identify PIs and EPIs. They are used for manual minimization minimization of Boolean functions. functions.

Exercise 1 How Ho w do yo you u transfo transform rm a K-m K-map ap into into a tru truth th table? table? Is it unique unique?? Ho How w do yo you u transform a K-map into an -cube? Is it unique?

Two- and Three-Variable Maps 0 0 0 1 1

0 1 0 1

2-var map

1

0

0

0

1

1

1 1

0

0 0 1

1

0

1 1

1 1

1

1

1

2-var map

Figure 4: Two-variable maps. 00 01 11 10

3-var map

0

00 01 11 10 0 1 1

00 01 11 10 0 1 1

1

1

1 1

1

1

1

3-var map Figure 5: Three-v Three-variabl ariablee maps. YZ X

Y 00

01

11

10

m0

m1

m3

m2

0 XY Z XY Z XY Z XY Z

m4

m5

m7

m6

X 1 XY Z XY Z XY Z XY Z Z

(a)

(b) Fig. 2-10 Three-V Three-Variable ariable Map

Figure 6: Three-variable map simplification [Mano & Kime].


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4-5



Minterms are arranged in the Gray-code sequence. (Why?)



Any 2 (horizontally or vertically) adjacent squares differ by exactly 1 variable, which which is complemente complemented d in one square and uncompleme uncomplemented nted in the the other other..



Any 2 minterms in adjacent squares that are ORed together will cause a removal of the different variable, e.g., , because . x iyi 0

ci

01 0

11 1

10 3

2

7

6

1

0 4

5

1

1

1

1

x iyi ci

0

01 0

10 3

2

1

0 4

1

11 1

1

1 7

5

6

1

Figure 7: K-maps for the carry and sum functions functions [Gajski]. [Gajski].

Example 2 Simplify Simplif y the following Boolea Boolean n functions: (a) . YZ 00 X

Y 01

11

0 X 1

10

1 1

1

1

; (b)

YZ 00 X 0

1

X 1

1

Z

Y 01

11

10 1

1

1 Z

(a) F1 (X, Y, Z) = Σm (3, 4, 6, 7) = YZ + XZ

(b) F2 (X, Y, Z) = Σm(0, 2, 4, 5, 6) = Z + XY

Fig. 2-14 Maps for Example 2-4


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4-6

Example 3 Simplify the Boolean function YZ 00 X 0 X 1

1

. Y 01

11

1

1

10

1

1 Z

(1, 3, 4, 5, 6) Fig. Fi g. 22-15 15 F( X, Y , Z ) = Σm (1,

Example 4 Simplify the Boolean function YZ 00 X

. Y 01

11

10

0

1

1

1

X 1

1

1 Z

Fig.. 2-1 Fig 2-16 6 F( X , Y ,Z ) = Σ m (1 ,2 , 3, 5, 7)

Four-Variable Maps yz wx 00 01 11 10 00 0 1 3 2

yz wx 00 01 11 10 00 1 1 1

yz wx 00 01 11 10 00 1 1 1

01 4

6

01 1

1

1

01

11 12 13 15 14

11 1

1

1

11

10 8

10 1

1

5

7

9 11 10

10 1

1 1

1

Figure 8: Four-variable maps.


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4-7

The map is considered to lie on a surface with the top and bottom edges, as well as the right and left edges, touching each other to form adjacent squares. squares. 

One square



Two adjacent squares

a term of 3 literals.



Four adjacent squares

a term of 2 literals.



Eight adjacent squares

a term of 1 literal.



Sixteen adjacent squares

a minterm of 4 literals.

the constant ‘1’.

Example 5 For the maps shown above,

and .



A PI is a product term obtained by combining the maximum possible number of adjacent squares in the map.



Pick the EPIs that minimize the number of literals.

Minimize the number of groupings. Maximize their sizes.


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4-8

Example 6 Show the region in the K-map that is represented by YZ 00 WX 00 01

0 4

.

Y 01

11

10

1

3

2

5

7

XZ 2

0

10

8

6 X

11

12

13

15

14

W 10

8

9

XZ

11

11

9

10

3

1

Z (a)

(b)

Fig. 2-18 Four-V Four-Variable ariable Map: Flat and on a Torus Torus to Show Adjacencies

Example 7 Simplif Sim plify y the Boo Boolea lean n fun functio ction n

.

YZ 00 WX

Y 01

11

10

00

1

1

1

01

1

1

1 X

11

1

1

10

1

1

1

W

Z Fig. 2-19 Map for Examp Example le 2-5: F = Y + WZ + XZ


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4-9

Example 8 Simplify the Boolean function

. C

CD AB 00

00

01

1

1

11

10 1

01

1 B

11 A 10

1

1

1 D

Fig. 2-20 Map for for Example Example 2-6: F = BD + BC + ACD

*Five-Variable Maps DE BC

A = 0

A=1

A = 0

00 01 11 10

DE

DE

BC

00 01 11 10

A=1

DE

00 BC01 11 10

00 BC01 11 10

00 0

1

3

2

00 16 17 19 18

00 1

1

00

01 4

5

7

6

01 20 21 23 22

01 1

1

01

1

1

11 12 13 15 14

11 28 29 31 30

11

1

11

1

1

10 8

10 24 25 27 26

10

1

10

1

9 11 10

Figure 9: Five-variable maps.



Imagine that the 2 maps are superimposed on one another.



It is possible to construct a 6-variable map with four 4-variable maps by following a similar procedure.



Maps of 6 or more variables are hard to read, and thus are impractical. 



(1) Variable-entered maps (VEMs); (2) CAD programs.

Any adjacent squares, area that gives a product term of

, in an -variable map represent an literals.


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{ {


v=0

4-10

v=1

zw xy

u=0

u=1

00

01 0

{ {

00 m0

11 10 1

m1 4

01 m4

m3 7

m5

m7

13

2

6

20

8

9

11

14

32

33

35

37

39

10

45

47

23

22

29

31

30

24

25

27

26

m24 m25 m27 m 26

34

48

49

51

50

m48 m49 m51 m50

38

52

01 m36 m37 m39 m38 44

21 21

28

00 m32 m33 m35 m34 36

18

m28 m29 m31 m 30

m1 1 m 1 0

m9

19

m20 m21 m23 m 22

11 m12 m13 m15 m14 10 m8

11 10 17

m16 m17 m19 m18

m6 15

01 16

m2

5

12

00

3

53

55

54

m52 m53 m55 m54

46

60

61

63

62

{ { 11 m44 m45 m47 m46 40

41

43

m60 m61 m63 m62

42

56

10 m40 m41 m43 m42

57

59

58

m56 m57 m59 m58

v=0

v=1

zw xy

u=0

u=1

{ {

00

01

11

10

00

01

11 10

0

1

3

2

16

17

19

18

4

5

7

6

20

21 21

23

22

12

13

15

14

28

29

31

30

8

9

11

10

24

25

27

26

32

33

35

34

48

49

51

50

36

37

39

38

52

53

55

54

44

45

47

46

60

61

63

62

40

41

43

42

56

57

59

58

00 01 ’

xv

11 10

00 01 xz

11 10 ’

zw

’

Figure 10: Six-variable K-maps [Gajski].


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4-11

Theorem 1 In a K-map, 2 minterms are adjacent iff they differ in exactly 1 variable. B

In general, for an -variable function, where K-map such that:

, we can construct a -D

6

the map is extended in each dimension on 2 of the variables;

6

the extension sequence in each dimension is a Gray sequence.

Simplification Using K-Maps 

The complement of a function is represented in the map by the squares not marked by 1s (they usually are marked by 0s). CD AB

00 01 11 10

CD AB

00 01 11 10

00 1

1

1

00

0

01 1

1

1

01

0

11 1

1

1

11

0

10 1

1

10

0

Figure 11: The complement complement of

gives

0

in pos.

Example 9 We want to simplify the following function in sop & pos:

(a) Mark the map with 1s and 0s according to the function. (b) Use the 1s to determine the EPIs of , which immediately give the sop form:

(c) Use the 0s to determine the EPIs of , and complement it to give the pos form:


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B’ D’

4-12

A’ B’ f

C’ A’ D

C’ D’

f

D

Figure 12: Two-level implementation.

The 2-level (sop/pos) implementations using the AND/OR gates are shown below. Note that NOT gates (inverters) are required if complemented inputs are not available. 

The 1s of the function in the K-map or the truth table represent represent the minterm minterms, s, and the 0s represent the maxterms.



Entering a function in the map:





Entering a function expressed in sop in the map is straightforward.



To enter a function expressed in pos in the map, take the complement of the function (to get sop) and from it find the squares to be marked by 0s. The remaining squares are marked by 1s.

Simplification procedur proceduree: 

Obtain truth table, canonical form, or standard form.



Generate K-map.



Determine PIs.



Select EPIs.



Find minimal cover (set) of PIs.


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C

CD 00

AB 00

4-13

11

01

10

00

AB 00

1

01

C

CD

10

1

01

1

11

01

1

B 11

1

1

B 11

1

A

1

1

1

A 10

1

10

1

D

1

1

D

(a) Plotting the minterms

(b) Essential prime implicants

Fig. 2-22 2-22 Simplification with Prime Implicants Implicants in Example 2-8

Figure 13: Simplification with PIs for

C

CD 00

01

00

1

1

01

1

1

AB

[Mano & Kime].

11

10

3

1

B 11 A

1

1

10

1

1

D 1

2

Fig. 2-23 Map for for Example 2-9

Figure 14: Simplification with PIs for


[Mano & Kime].

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4-14

Exercise 2 Does the minimal cover of PIs contain only EPIs? Example 10 Simplify the following Boolean function in the pos form: . C

CD 00

01

11

10

00

1

1

0

1

01

0

1

0

0

AB

B 11

0

0

0

0

1

1

0

1

A 10

D Fig. 2-24 Map for Example 2-10: F = (A + B ) (C + D ) (B + D )

Exercise 3 Simplify

in the pos form.

Don’t-Care Conditions 

In practice, there are applications where the function is not specified for certain combinations combinations of the input variables. variables. For example, example, in the 4-bit BCD code for the decimal digits, the outputs are unspecified for the input combinations 1010-1111.



Functions that have unspecified outputs for some input combinations are called incompletely specified functions. functions.



The unspecified minterms of a function are called the don’t-care conditions, or simply the don’t-cares, and are denoted as Xs.



These don’t-care conditions can be used on a map to provide further simplification ficatio n of the Boolean expression. expression.


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4-15

Each X can be assigned an arbitrary value, 0 or 1, to help the simplification procedure.

Example 11 Simplif Sim plify y the Boo Boolea lean n fun functio ction n care conditions

that th at ha hass th thee do don’ n’tt.

00 01 11 10 00 X 1

00 01 11 10

1

X

00 X 1

1

X

01 0

X 1

0

01 0

X 1

0

11 0

0

1

0

11 0

0

1

0

10 0

0

1

0

10 0

0

1

0

Figure 15: Simplification using don’t-cares.



Either one of the above expressions satisfies the conditions stated.



Note that the above 2 expressions represent 2 functions that are algebraically unequal: each covers different don’t-care terms.



We may or may not include any of the Xs, while all the 1s must be included.



It is also possible to obtain a simplified pos expression using the don’t-cares.

Tabulation (Quine-McCluskey) Method 

The map method is convenient when the number of variables does not exceed 5 or 6.



The map method is essentially a trial-and-error method that does not offer any guarantee of produc producing ing the best realization.



The map method’s dependence on the somewhat intuitive human ability to recognize patterns makes it unsuitable for design automation (programming for a digital computer).


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4-16



The tabulation method is a specific step-by-step (algorithmic) procedure that is gu guara arant ntee eed d to produ produce ce a sim simpli plifie fied d sta stand ndard ard-f -form orm ex expr pres essio sion n for a fun funct ction ion..



It can be applied to problems with any number of variables.



It is suitable for machine computation.



It however is quite tedious for human use.



The tabulation method was first formulated by Quine (1952) and later improved by McCluskey (1956), thus known as the Quine-McCluskey method. 



Step 1: Exhaustive search of all PIs. 

Group minterms by number of 1s.



Compare minterms and find pairs with distance 1.



Generate subcubes.



Repeat the above procedure on generated subcubes until no more subcubes subcub es can be generated.

Step 2: Choose among the PIs which give an expression with the least amount of literals (minimal cov cover er genera generation). tion). 

Find EPIs through a selection table.



Find minimal cover through the pos of the PIs.

Determinatio Dete rmination n of PIs 

The goal of the Quine-McCluskey algorithm is a special case of the following: Selec Selectt the small smallest est possible possible subset subset,, , of a set of objects, , so that some criterion, , is satisfied .



The se The sett will consi consist st of all produ products cts in the min minimal imal sop sop realizat realization ion of a gi give ven n Boolean function , of which the set contain containss all possibl possiblee produc products. ts.


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Let

4-17

. ( a) 0 1 2 8 10 11 14 15

0000 0001 0010 1000 1010 1011 1110 1111

(b)  

0,1 0,2 0,8

000– 00–0 –000

(c )



–0–0 –0–0

10,11,1 10,11 ,14,1 4,15 5 10,14 10 ,14,1 ,11,1 1,15 5

1–1– 1–1– 1–1– 1– 1–



 

0,2,8,10 0,8,2,10

2,10 8,10

–010 10–0



10,11 10,1 1 10,1 10 ,14 4

101– 101– 1–10 1– 10



11,15 11,1 5 14,1 14 ,15 5

1–11 1–11 111– 11 1–





 



 



x

Group the minterms according to the number of 1s (see Column (a)).

y

Combine any 2 minterms that differ from each other by exactly one variable (i.e., dist-1), the unmatched variable removed (see Column (b)). Try this for alll po al poss ssibl iblee pa pairs irs of mi minte nterm rms. s. A ch chec eck k () is placed to the right of both minterms if they have been used in a match.

z

Repeat the pro Repeat proces cess. s. Com Combin binee any 2 prod product uct terms from Step y that differ from each other by exactly one variable, the unmatched variable removed (see Column (c)).

{

The unchec unchecked ked terms terms in the table form the PIs. Som Somee of the product product terms may appear appear twice in the tabl table. e. It of cou course rse is unnecessa unnecessary ry to use the sam samee term twice.



When comparing 2 terms to decide if they can be combined, the comparison can be done directly directly on the dec decima imall num number bers. s. We com combin binee 2 ter terms ms iff the difference of their corresponding decimal numbers is a power of 2.


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4-18

In most cases, the sum of PIs obtained obtained from from the procedure procedure show shown n above above is not necessarily necess arily a standard form (which is minimized). The reason is that some of the PIs may be redundant.

Exercise 4 Use the map method to simplify result with the tabulation method.

, and compa compare re the

Minimal Cover Generation The selection of PIs that form the minimized function is made from a PI table: table: each PI is represented in a row and each minterm in a column. Suppose Suppo se we hav havee the following PIs: PI  



,

,

,

,

, and

.

Minterms 1 4 6 7 8 9 10 11 11 15 15 1,9 X X 4,6 X X 6,7 X X 7,15 X X 11,15 X X 8,9,10,11 X X X X 













x

Check the PIs that cover Check cover minterms minterms with a sing single le X in their columns. columns. The These se PIs are the EPIs.

y

Check each column whose minterm is covered by the selected EPIs.

z

If there are minterms left uncovered (7 & 15 in this example), some nonessential PIs have to be selected to cover them. We of course will select the PIs with a smallest total number of literals ( in this example).


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4-19

*Multi-Output Minimization Using Maps 

Identify all possible PIs that cover each implicated minterms in each output expression, expr ession, and search for a minimal cov cover er by using shared terms.



The Quine-McCluskey method also can be extended for this purpose.

BC A 00 01 11 10 0 1 1 1

1

1

1

BC A 00 01 11 10 0 1 1 1

1

1

1

BC A 00 01 11 10 0 1 1

1

1

1

1

Figure 16: Simplification of multiple output functions.


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4-20

*XOR & XNOR Patterns on the Map 

Inspect the K-map to detect XOR/XNOR patterns: Inspect patterns: 1) kitty-corner kitty-corner adjacencies; 2) offset adjacencies. BC A 00 01 11 10 0 1

1

BC A 00 01 11 10 0

1

1

1

kitty-corner

CD 00 01 11 10 AB 00 1 1

01 1

1

offset

CD 00 01 11 10 AB 00 1

01

11

11 1

10

10 1

1

1

1

1

CD 00 01 11 10 AB 00 1

01

1

11 1 1

1

10

1

Figure 17: XOR/X XOR/XNOR NOR patterns patterns on the map.


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4-21

Two-Level Implementations 

Digital circuits are more frequently constructed with NAND/NOR gates than with AND/OR/N AND/OR/NO OT gat gates es due to eas easee of fabricat fabrication ion.. Fo Forr ex examp ample, le, in gate arrays, only NAND (or NOR) gates are used.



The conversion process from an expression/schematic with AND, OR, and NOT gates to one with only NAND or NOR gates is an example of technolof technology mapping. mapping.

NAND gate

or

NOR gate

or

Figure 18: NAND/NOR gates.

B

NAND-NAND NAND-N AND implementation: 6

Simplify the function and express it in sop:

6

Transfer it to 2-level NAND-NAND expression (DeMorgan’s Thm):

6

Draw th Draw thee co corre rresp spon ondin ding g NAN AND D ga gate te imp imple leme ment ntati ation on.. Not Notee th that at a 11-in inpu putt NAND gate can replace an inverter.


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AND-OR

NAND-NAND



The process can be done directly on the logic diagram.

B

NOR-NOR implementation:

 

4-22

6

Simplify the function and express it in pos:

6

Transfer it to 2-level NOR-NOR expression (DeMorgan’s Thm):

6

Draw the corresponding NOR gate implementation. Note that a 1-input NOR gate can replace an inverter.

It is the dual of the NAND-NAND implementation. OR-AND

NOR-NOR



The process can be done directly on the logic diagram.



The types of gates most often found in ICs are NAND & NOR, so NAND & NOR logic implementations are the most important from a practical point of view.

B

NAND-AND & AND-NOR implementations: 6

B

OR-NAND & NOR-OR implementations: 6



Both perform the AND-OR-INVERT (AOI) function.

Both perform the OR-AND-INVERT (OAI) function.

Because of the INVERT part in each case, it is convenient to use the simplification of (the complement of the function) instead of .


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4-23

00 01 11 10 0 1 0 0 0 1 0

0

0

1

Figure 19: NAND/NOR gates.

Example 12 Consider Consid er the functio function n

given in Fig. 19.

AND-OR: NAND-NAND: OR-NAND: NOR-OR: AND-NOR: NAND-AND: OR-AND: NOR-NOR:

. . . . . . . .

Example 13 Implement

with NAND gates. YZ 00 X 0

Y 01

11

10

1

1

1 F = XY + XY + Z

X 1

1

1

1 Z (a)

X Y

X



Y

X

F

X

Y

Y

Z

Z (b)

F

(c) Fig. 2-30 Solution to Example 2-12


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4-24

Example 14 Implement

with NOR gates.

A B A

F

B

E

C D (a) AND – OR gates A B A

•

B

E

C

X

F

•

D (b) NAND gates Fig. 2-32 Implementing F = ( A B + A B ) E (C + D )

Exclusive-OR (XOR) Gates 

Some identities for XOR: 6

;

.

6

;

.

6 

;

.

The XOR function is both commutative and associative. 6 6

. .

Exercise 5 (a) How do you implement the Even function with XOR (XNOR) gates?

(b) Design an -bit even-parity even-parity generator generator.. Calcul Calculate ate the hardw hardware are cost (in terms of primitive gates) and performance (in terms of primitive-gate delays).


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4-25

•

X

•

F=X

Y



Y

Fig. 2-37 Exclusive-OR Constructed with NAND Gates

Figure 20: Implementing the XOR function with NAND gates [Mano & Kime].

YZ 00 X

Y 01

0 X 1

11

1

10

00

AB 00

1

1

C

CD

01

1

11

01

10

1

1

1

1 B

11

Z (a) X

Y

1

1

A Z

10

1

1 D

(b) A

B

C

D

Fig. 2-38 Maps for MultipleMultiple-Variable Variable Odd Functions

Figure 21: Implem Implementing enting the Odd function with XOR gates [Mano & Kime].


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4-26

*Technology Mapping 

A gate array is a 2-dimen 2-dimensional sional array of cells within which each cell contains a single NAND (NOR) gate that has a fixed number (usually 3) of inputs.



The conversion process from an expression/schematic with AND, OR, and NOT gates to one with only NAND or NOR gates is an example of technolof technology mapping. mapping.

Rule 1 Rule 2 Rule 3 Rule 4 Standard form

NAND implementation

NOR implementation

sum−of−products

product−of−sums

Figure 22: Conversion standard forms to NAND and NOR implementations [Gajski].


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4-27

Example 15 Consider Consid er the carry function again:

The NAND and NOR implementations of the carry function are shown in Fig 23.

xi yi ci

2.4

ci+1 2.4

2.4

2.4

xi yi ci

1.4

1.4

1.4

ci+1

1.4

(c) NAND implementation

xi yi ci

2.4

ci+1 2.4

2.4

2.4

xi yi ci

1.4

ci+1 1.4

1.4

1.4

(d) NOR implementation Figure 23: NAND and NOR implementations of the carry function [Gajski].



Replace AND and OR gates with NAND gates by using Rules 1 and 2, and eliminate double inverters whenever possible.



Replace AND and OR gates with NOR gates by using Rules 3 and 4, and eliminate double inverters whenever possible.



Term decomposition: decomposition: each -input gate is decomposed into a tree of -input gates, where . Fo Forr example, example, Fig 24 shows shows the decompo decompositi sition on of a 10-input AND gate into 3-input AND gates. 

The tree has

levels and


-input gates.

2005


2.4

2.4

4-28

2.4

2.4

2.4

2.4

2.4

2.4

2.4

2.4

(b) One possible decomposition

(c) Alternative decomposition

Figure 24: Decom Decompositi position on of a 10-input AND gate into 3-input AND gates [Gajski]. [Gajski]. 

Retiming: performance Retiming: performance optimiza optimization tion (delay time minimiz minimization)— ation)—decomp decomposition osition of a large gate can produce a tree in which different paths may incur different delays. For example, Fig 25 shows two NAND implementations of the 4-bit carry-look-ahead function:



Carry generate function:



Carry propagate function:



Carry look-ahead function:

. . .



Critical path: path: the delay on the longest input-output path.



The rule of thumb is to minimize delay on critical paths and minimize cost on non-critical paths. paths. A technology mapping example is shown in Fig 26.


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4-29

g3 p

g2

3

p

p2

3

g1

p

p2

3

p1

c4

g0

p 3 p p1 2 p c0 0

(a) AND−OR implementatio n g3 p g2 p2

3

p

3

g1

p

3

p1 p

3

p1 c0

c4

p2 g0 p2 p0

(b) Decomposition Decomposition of (a) g3 p g2 p2

3

1.8

p

3

1.8

g1

p

3

p1 p

3

p1 c0

p2

1.8

1.8

c4

1.8

1.8

g0 p2

1.8

Max delay = 9.2 ns

p0

1.8

(c) NAND implementati on of (b) g3 p g2 p2 p

3

p1 p

3

p1 c0

3

p

3

g1 p2

c4

g0 p2 p0

(d) Performance Performance optimized decomposition g3 p g2 p2

3

3

g1

p

3

p1 p

3

p1 c0

1.8

1.8

p

p2

1.8

1.8

g0 p2 p0

1.8

1.8

1.8

c4

Max delay = 6.4 ns 1.8

(e) Performance optimized optimized NAND implementation

Figure 25: Two NAND implementations of the 4-bit carry-look-ahead function [Gajski].


2005


y

4-30

2.4

2.4

w z

2.4

1

F

2.4

1

(a) AND−OR implementation implementation (Delay = 7.2ns, Cost Cost = 28) y

1

1.4

1.4 1.4

w z

1

F

1.4

1

(b) NAND implementation implementation (Delay = 5.2ns, 5.2ns, Cost = 22) 22)

B

y

1

1.4

A 1.4 1.4

w z

1

F

1.4

1

(c) Two possible possible conversions conversions y

1

1.4

w z

2.0

1

1

F

1

(d) Alternative A (Delay (Delay = 5.4ns, Cost Cost = 20) y 2.0 1.4

w z

1

F

1.4

1

(e) Alternative B (Delay (Delay = 3.8ns, Cost Cost = 20) y 2.0 1.4

w z

1.4

F

1

(f) Cost optimized alterna alternative tive B (Delay = 3.8ns, Cost = 18)

Figure 26: Technology mapping example [Gajski].


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Hazard-Free Design Definition 1 Hazards are unwanted switching transients (glitches (glitches)) that appear at the output of a circuit because of different propagation delays on different but converging paths through the circuit.

. .

. . static 0-hazard static 1 hazard

dynamic hazards

Figure 27: Hazard Hazards. s. 

Hazards can cause malfunction.



Static-1 hazard: hazard: there are two 1-minterms that differ in only one variable but are not covered covered by a common product product term in a sop implementation implementation (Fig. 28). 

It can be eliminated by including an additional PI covering both adjacent 1-minters 1-minte rs (called the consensus term) term) (Fig. 29).



Static-0 hazard: hazard: there are two 0-minterms that differ in only one variable but are not covered by a common sum term in a pos implementation.



Static hazards are caused by two complementary signals which become equal for short periods of time due to different delays on different paths through the circuit.



Dynamic hazard Dynamic hazard:: two signals that always have the same value (even during the transition) become different for a short period of time. 

It is a static hazard that occurs during the output transition.



It occurs when the same variable value propagates through the circuit on two different paths with different delays.



See Fig. 30 for an example. 

It can be eliminated by introducing a redundant (consensus) PI.



It also can be eliminated by inserting a delay element.


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4-32

y z 01

0

x

11

0

1

2

7

6

1

0 4

1

10 3

5

1

1

1

F = xy’ + yz (a) Map representation

a

x y

2.4

1

2.4 2.4

z

F

b

(b) Logic schematic

x

y

z

a

3.4

b

2.4

F

4.8

t 0

1.0

t 1 t 2

(c) Timing diagram

Figure 28: A design with static-1 hazard [Gajski].


2005


4-33

y z 01

0

x

0

11 1

10 3

2

7

6

1

0 4

5

1

1

1

1

F = xy’ + yz + xz (a) Map representation

x y

2.4

1

2.4

z

2.4

a b 2.4

F

c

(b) Logic schematic

x

y

z

a

3.4

b

2.4

c F (c) Timing diagram

Figure 29: Hazard-free design [Gajski].


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4-34

Static 1−hazard x y

1

a

2.4

2.4

z

e

2.4

b

2.4

d

2.4

w

F

(a) Logic schematic

x y

z w 4.8

e

1.0

3.4

d

2.4

F t 0

t 1

1.4 1.0

t 2

(b) Timing diagram Figure 30: A design with dynamic hazard [Gajski].


2005

Simplification of Boolean Functions

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