Maven Silicon Evolved in VLSI technologies, Maven Silicon is a VLSI Design services company that offers wide range of ASIC and FPGA verification consultancy services, corporate and professional training. With over a year of establishment, Maven Silicon is the only VLSI training center in India that offers SystemVerilog based advanced verification courses. It is currently training more than 150 engineers per year, focusing on training solutions as forethought to offering design services in semiconductor industry. Maven Silicon provides pioneering solutions that help engineers triumph over design challenges in the complex world of semiconductors. The workplace comprises of highly skilled professionals who efficiently and accurately administer every facet of the design process with unique solutions. Envisioned by company's name, Maven meaning expert, the novice or professionals gets trained by specialists in the semiconductor industry. With hands-on experience in the realm of semiconductor industry, our founder and CEO, Sivakumar P R has worked extensively on ASIC verification for over 10 years. His expertise adds incredible value to Maven Silicon in providing customized training solutions. To know more about our CEO, please pleas e visit http://www.linkedin.com/in/sivapr
Why Maven Silicon? At Maven Silicon, we train engineers on the advanced VLSI design methodologies and various ASIC verification technologies. We provide great opportunities for learners to equip themselves with latest verification technologies that are in use as well as those setting trends in the semiconductor industry. Five reasons to muse on Maven Silicon includes, 1.SystemVerilog based Advanced Verification
Maven Silicon as the training centre edifies engineers on the advanced ASIC verification verification methodologies and SystemVerilog. SystemV erilog. In addition to the advanced technologies, we also impart the basic VLSI technologies like advanced advanc ed Digital Design Des ign Methodology, Methodolo gy, Verilo erilog, g, VHDL, ASI & FPGA's design flows, flows , STA STA and CMOS fundamentals.
2.Course Delivered by Industry Experts
As courses such as VLSI-RN are composed of advanced VLSI design and verification technologies, only experienced VLSI engineers can deliver it. At Maven Silicon, industry experts share their experience and guide you on how to enhance your skills in VLSI Industries.
Tel : 080 4130 5692 Email :
[email protected] www.vlsitraining.com
3.Superior Training Methodology
At Maven Silicon, the experienced engineers who work in the top semiconductor industries share their experience with you and demonstrate how the concepts are applied in the real environment. Only 30% of 455 hours of VLSI-RN course is dedicated to impart concepts and remaining 70% for labs, mini projects and final project. 4.Excellent Placement Assistance
Our CEO has worked in the top EDA companies like Mentor Graphics, Cadence and Synopsys and helped various semiconductor industries to use EDA solutions for the successful implementations of ASICs and FPGAs. We work closely with various semiconductor companies and identify the right opportunities for students who successfully complete our training program. Most of our students have been successfully placed in renowned semiconductor companies. 5.Excellent work environment
We provide excellent work environment, which has adequate hardware and software infrastructure. Maven Silicon has chosen Mentor Graphics as its EDA partner and provides great opportunities to engineers to work on verification platform like Questa and explore the advanced ASIC verification technologies and methodologies.
EDA Partner - Mentor Graphics Mentor Graphics is leader in Electronic Design Automation. Its innovative products and solutions help engineers conquer design challenges in seemingly daunting world of board and chip design. To know more about Mentor Graphics, please visit www.mentor.com
Maven Silicon Confidential This document is the proprietary work of Maven Silicon and is fully protected under copyright and trade secret laws.You may not view, use, disclose, copy, or distribute the materials or any information except pursuant to a valid written license from Maven Silicon.
Tel : 080 4130 5692 Email :
[email protected] www.vlsitraining.com
Maven Silicon Certified VLSI Design and Verification course Module 1
Module 4
Module 5
Introduction to VLSI VLSI Design Flow ASIC Vs FPGA RTL Design Methodologies Introduction to ASIC verification methodologies
Verilog HDL – RTL Coding and Synthesis
Mini Project – RTL Coding and Synthesis
§ § § §
VLSI Design Flow Steps – Demo
Module 2 Advanced Digital Design
Introduction to Digital Electronics Arithmetic Circuits Data processing Circuits Universal Logic Elements Combinational Circuits - Design and Analysis Latches and Flip flops Shift Registers and Counters Sequential Circuits - Design and Analysis Memories and PLD Finite State Machine Microcontroller Design
§ § § § §
§ § §
§ § §
Module 3 FPGA Architecture
Introduction to PLD Xilinx CPLD - Xc9500 Xilinx FPGA - XC 4000E Xilinx Spartan 3 ACTEL Architecture
Introduction to Verilog HDL Applications of Verilog HDL Verilog HDL language concepts Verilog language basics and constructs Abstraction levels
§
§
§
§
§
§
§
Data Types Type concept Nets and registers Non hardware equivalent variables Arrays §
Module 6
§
VHDL – RTL Coding and Synthesis
§ §
Verilog Operators Logical operators Bitwise and Reduction operators Concatenation and conditional Relational and arithmetic Shift and Equality operators Operators precedence
§ § § § § §
Assignments Types of assignments Continuous assignments Timing references Procedures Blocking and Non-Blocking assignments Execution branching Tasks and Functions
§ § §
VHDL introduction and applications Comparison with Verilog Design units Data types Operators Concurrent and Sequential statements File I/O Operations Test Bench Synthesis issues FSM coding styles
§ § § § § § § § § §
§ § § § § § §
§ §
Project Specification Analysis Understanding the architecture Module level implementation and verification Building the top level module Implementing the design onto the FPGA board
§
§
Advanced Verilog for Verification System Tasks Internal variable monitoring Compiler directives File input and output § § § §
Finite State Machine Basic FSM structure Moore Vs Mealy Common FSM coding styles Registered outputs § §
Module 7 CMOS Fundamentals
Non Ideal characteristics BJT vs FET CMOS Characteristics CMOS circuit design Transistor sizing Layout and Stick Diagrams CMOS Processing Steps Fabrication CMOS Technology - Current Trends
§ § § § § § § § §
EDA Partners
§ §
Synthesis Coding Style Registers in Verilog Unwanted latches Operator synthesis RTL Coding Style §
Mentor Graphics Xilinx
Operating System
§ § §
LINUX - RHEL 5.0
Tel : 080 4130 5692 Email :
[email protected] www.vlsitraining.com
Maven Silicon Certified VLSI Design and Verification course
Module 8 ASIC Verification Methodologies
Directed Vs Random Functional verification process Stimulus Generation Bus function model Monitors and reference models Coverage Driven Verification Verification Planning and management
§ § § § § § §
SystemVerilog HVL Introduction to SystemVerilog New Data types Tasks and Functions Interfaces Clocking blocks OOP Basics Classes – Objects and handles Polymorphism and Inheritance Randomization Constraints §
Module 9
Module 12
Mini Project: Verification and RTL sign-off
Perl
Router specification analysis Defining verification plan Creating Testbench architecture Defining Transaction Implementing the transactors Generator, Driver, Receiver and Scoreboard Implementing the coverage model Building the top level verification environment Defining weighted random, corner case and directed testcases Building the regression testsuite Generating the functional and code coverage reports
§ §
§ § § § § §
Threads and Virtual Interfaces Fork Join Fork Join_any Fork Join_none Event controls Mailboxes and semaphores Virtual Interfaces Transactors Building verification environment Testcases § § § § § § §
§
§
§
§
§
§ § § §
§ §
Module 13 Static Timing Analysis
Introduction to STA Comparison with DTA Timing Path and Constraints Different types of clocks Clock domain and Variations Clock Distribution Networks How to fix timing failure
§ § § §
Module 10
§
Introduction to VMM
§ §
VMM – Layered Architecture VMM Message Services and Utilities VMM Environment Atomic and Scenario Generators VMM Channel Callbacks Testcases VMM Tutorial
§ § § § § § § §
Module 14 Industry Standard Project
Design specification analysis Creating the design architecture Partitioning the design RTL coding in Verilog/VHDL RTL functional verification RTL Synthesis Place & Route the netlist Timing Simulation Implementing design onto the FPGA Verifying design on FPGA Board
§ § § § §
Module 11
§
Assertion Based Verification Property Specification Language
§ § §
§ §
§
§
§ §
Introduction to Perl Functions and Statements Numbers, Strings, and Quotes Variables Comments and Loops
§
Introduction to ABV PSL Flavours Implication Operators Simple properties PSL SERE Complex Sequences Verification Unit Reusable Assertion Ips
§
§
§
Functional Coverage Coverage models Coverpoints and bins Cross coverage Regression testing § § § §
§ § § § § §
Tel : 080 4130 5692 Email :
[email protected] www.vlsitraining.com
