Laptop Power Sequencing

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Laptop Power sequencing

Notebook INTEL INTEL Timing Timing (SEQUENCE) (SEQUENCE) Notebook INTEL INTEL Timing Timing (SEQUENCE) (SEQUENCE)

Usuall t!e boot process NTEL notebook c!ipset (t!e re" part is a circuit "iagram C!atur#e"i use) $% in t!e absence o& an electrical equipment w!en t!e power suppl (no batter an" power)% b ' button batter to generate CCTC suppl Sout!bri"ge TC circuitr to *eep *eep runn runnin ing g an" an" keep keep t!e t!e C+,S C+,S inte intern rnal al time time in&o in&orm rmat atio ion n '-./01 TC TC circuit circui t measuring meas uring points2 poi nts2 CCTC3.CPTC CCTC3.CPTC 4 TCST 5 4 STCST 5 4 '-6/01*78 9:TL,; 5 '6' EC to Sout!bri"ge -6 :&ter inserting t!e batter or a"apter to pro"uce a common point% t!en generates EC stan"b power suppl (usuall linear suppl '6' Current <6<1:) isolation protection Circuit common small #alue resistor ' to gi#e t!e stan"b power suppl EC (:CC 4 CC<) an" get stan"b clock% ('-6/01*7= '6') an" reset ('6' EC>ST 5 4 ECST 5 ;ST 5 CC>P, 5



CC$>ST 5) a&ter rea"ing (9I,S) con&iguration itsel& pin (oscilloscope wa#e&orm can be measure") ?% i& t!e EC "etecte" power a"apter (generall a goo" signal &rom t!e c!arging c!ip :C,* con#ersion :CIN 4 :.>IN 4 :C>IN 4 I- 4 ;UI$ 4 @P.$ 4 :C:>IN)% Sout!bri"ge will automaticall sen" a signal to open t!e stan"b #oltage (CCSUS'>'% AEB>SUS)% t!en sent Sout!bri"ge calle" S+ST 5 ('6') to be electromec!anical @oo" pressure signale" Sout!bri"ge stan"b #oltage normalD i& t!e EC "oes not "etect t!e a"apter (batter mo"e)% EC nee" to recei#e t!e switc! trigger% onl to open Sout!bri"ge stan"b power suppl to sa#e power current <6<-3 <6<' A% press t!e switc!% EC recei#e" signal a&ter t!e switc! (connecte" to t!e EC names @PI,<' 4 @PI,<0 P;UEQ 5 4 @PC/ 4 P;>S; 5 3 7ua S!uo T+I< 4 ;UI- 4 @PC? 4 EC>@PI,.' 4 *9C>P;9TN 5) "ela sen"ing a !ig! 3 low 3 !ig! power signal to P;9TN 5 Sout!bri"ge no power is also a&&ecte"%2 44www6wen"angwang6com4"oc4c$"1?&-&<<&&0$?1A1Ac0e"?par Li" switc! control (C,E>S; 5 4 LI.>S; 5) 0% Sout!bri"ge recei#e" successi#el pulle" a&ter P;9TN 5 signal SLP>SA 5% SLP>S? 5% SLP>S' 5 signal% SLP>SA 4 S? 5 memor power suppl an" control t!e generation '6'SUS (.I++) (can "irectl control% t!e control can also go t!roug!



EC) (<6S' 5 generates control '6'>UN% A>UN% bri"ge power suppl ($6 F ) bus3powere"% (CCP) <6-:3<6': $6C,E) (et (can "irectl control % ou can also go t!roug! t!e EC control) /% signale" EC ($6 F ) or ot!er con#ersion circuit to turn t!e CPU core #oltage (C,E) alone was no current <60:% (t!ere was onl a current increase <6'3<6A:)6 :t t!is point% t!e w!ole #oltage !as been &ull opene"6 1% a&ter t!e normal CPU power% CPU power management c!ip emits P@ e#entuall ser#e" Sout!bri"ge +P;@. 4 SGS>P;,* 4 +EP;,* &oot ('6' CPU @oo" power suppl signal) H% t!e CPU power suppl is normal to start t!e clock circuit c!ip t!roug! t!e con#ersion% t!e brig!test generate" clock (H?A or less% an" 7+AA series is t!e CPU power suppl CL*>EN 5 .irectl start t!e clockD H0A an" H?A series a&ter +P;@. to Sout!bri"ge% Sout!bri"ge issue C*>P;@. start t!e clock '6') $<% Sout!bri"ge recei#e" power% clock% +P;@.% an" recei#e" EC or circuit3switc!e" power suppl circuit to P;,* ('6')% will be issue" Sout!bri"ge CPUP;@. 4 P,CP;@. 4 .:+P;,* $6


:n" PCIST 5 ('6') signal $$% Nort! 9ri"ge a&ter recei#ing PLTST 5% issue" CPUST 5 ($6


power suppl to t!e crstal% t!e crstal S!ake3#ibration6 Crstal &eet #oltage between <6$3<6A AEB>SUS2 A stan"b #oltage CCSUS'>'2 '6' stan"b #oltage SA state CCSUS$>SA 52 '6'% Sout!bri"ge eit o&& t!e bri"ge control signal power suppl EC !as SLP>S? 52 '6'% Sout!bri"ge eit control signal sleep state6 (@eneral SA 5 an" S? 5 using onl one power suppl is use" to control t!e generation o& memor% anot!er empt) SLP>S' 52 '6'% Sout!bri"ge eit sleep state control signal6 (@enerall use" to control t!e bri"ge power suppl% bus3powere"% single signi&icant power% CPU power suppl% etc6) .I++2 memor power suppl C,E 4 CC2 power suppl means bri"ge% bus3powere"% single signi&icant power% CPU suppl !ttp244www6wen"angwang6com4"oc4c$"1?&-&<<&&0$?1A1Ac0e"? electricit +P;@.2 Sout!bri"ge in&orm t!e CPU power



suppl is normal% '6' CL* @EN2 clock c!ip to work% to issue t!e brig!test clock P;,*2 Noti& Sout!bri"ge suppl are normal at t!is time (SLP>S' 5 task completion) '6' CPUP;@.2 P@ Sout!bri"ge issue" to t!e CPU6 $6>>>> -% '6' main power suppl Sout!bri"ge measure" in >>>>> '% $6>>>> ?% Sout!bri"ge ''+ clock measuring points >>>>> $60 A% P;,* Sout!bri"ge measuring point in >>>>>% >>>>>  normal #oltage 0% +P;@. Sout!bri"ge measuring point in >>>>>% >>>>>  normal #oltage

:CPI :"#ance" Con&iguration an" Power +anagement Inter&ace



:CPI power an" control signals @'2 stan"b power o&& state EC SA2 @' electricit t!ere% more power Sout!bri"ge S'2 @' SA !a#e electricit% more memor power S<2 @' SA S' S< all3electric 'S93'6' stan"b #oltage to wit!in t!e Sout!bri"ge controller :CPI 4 NIC 4 PCI wake like to pro#i"e power 'S9 name t!ree c!ipset INTEL2 CCSUS'>' N#i"ia2 '6'>.U:L:+.2 SA>'6' 4 ..I,>''>S S+ST 5 3 normal stan"b #oltage signal% #oltage '6' Intel% :+.2 S+ST N#i"ia2 P;@.>S9 SLP>S' 5 4 SUS9 5 (:sus use)% SLP>S? 5 !ttp2 44www6wen"angwang6com4"oc4c$"1?&-&<<&&0$?1A1Ac0e"?4SUSC 5%SLP>SA5 Low into t!e S'% S?% SA signal state ' signal S< state are in#ali" P;9TN 5 3 P,;E 9UTT,N #oltage button% s!ut"own% low P;9TN 5 signal% :CPI will in turn set !ig! SLP>SA% SLP>S?% SLP>S' To '6'6 I& P;9TN 5 ? secon"s low% t!e sstem will be &orce" into SA state



C' &our states STPCL* 52 Sout!bri"ge "istribute" CPU% stop CPU internal clock% acti#e low% t!e !ost normal working% t!is signal is !ig! will cause t!e co"e "oes not run STP>CPU 52 Sout!bri"ge c!ip "istribute" clock% eternal clock "own t!e CPU% low acti#e% T!e !ost normal working% t!is signal is !ig! (no CPU clock) .PSTP 52 Sout!bri"ge "istribute" CPU% it sai" it is in .eep Sleep mo"e% acti#e low% t!e !ost normal working% t!is signal is !ig! (cause co"e "oes not run) .PSLP2 Sout! 9ri"ge to t!e CPU power suppl IC% "irecte" into .eep Sleep mo"e% acti#e !ig!% is low w!en t!e !ost is working properl (causing no CPU power) :CPI C3state

Notebook power suppl is "i#i"e" into &our le#els 333 important suppl Name2 C!arles sc!ematic con#enient C!atur#e"i .ell S' SA out simultaneousl @' 333 EC stan"b power suppl #oltage :CC CC: Just plug in t!e power generate" w!en t!e general power suppl switc! an" EC% are usuall pro"uce" in a linear &as!ion SA 333 Sout!bri"ge stan"b power suppl% CCSUS'>' AEB>SUS supplie" un"er Sout!bri"ge CCSUS'>' o&& electricit% usuall generate" P;+ mo"e



S' 333 memor power suppl .. S' sleep state% T!e main power suppl S< 333 bri"ge core suppl CC$>A>9 mac!ine uptime nee"e" electrical power S< state% inclu"ing power suppl bri"ge% bus% CPU power suppl 9us3powere" CCP b &irst looking to &in" CPU power suppl bus an" bri"ge CPU power suppl CC Sometimes% ou can put P;+ mo"e @' or SA state calle" out ' A sstem power suppl2 44www6wen"angwang6com4"oc4c$"1?&-&<<&&0$?1A1Ac0e"?r I9+ #oltage re&erre" to as2 @' S; SA + S' : S< 9 INTEL C!ipset Series Bi#e "i&&erent timings oltage laere" @' SA S' S< CCTC   SLP>S' 5



SLP>+ 5 bri"ge mo"ule +E issue" a control signal &or turning on t!e power suppl% '6' I& t!e mot!erboar" !as +E &irmware :+T &unction is turne" on% t!e signal will be generate" be&ore t!e triggerD close" :+T &unction timing an" SLP>S' 5 Consistenc I& t!e mot!erboar" "oes not support :+T &eature% SLP>+ 5 #acant not use" SLP>L:N 52 L:N subsstem sleep control% power control car"% snc!roni8e" wit! t!e timing SLP>+ 5 CC+E2 $6+ 56 ;!en SLP>+ 5 #acant (no +E mot!erboar" &irmware)% Power CC+E "irectl S< state .I++2 re&ers to t!e memor power suppl% controlle" b SLP>S? 5 CC2 re&ers to t!e main power suppl bri"ge% etc6 S< state #oltage controlle" SLP>S' 5 CC>CPU2 t!e mot!erboar" to t!e CPU core power suppl% controlle" b SLP>S' 5% t!ere is a "ela SGS>P;,*2 b t!e power management c!ip CPU is sent bri"ge '6' !ig! le#el% equi#alent to +P;@.



P;,*2 9oar" issue" '6' !ig! le#el bri"ge% s!owing S< state #oltages are ,* +EP;,*2 +E goo" power mo"ule% '6'% w!en open t!e :+T &unction% +EP;,* b t!e :+T power control% close" :+T &unction% +EP;,* Snc!roni8e" wit! P;,* L:N>ST 52 +ot!erboar" Integrate" NIC reset signal sent to t!e bri"ge% t!e car" can be un"erstoo" as power3goo" signal Clock C!ip ,utputs2 clock c!ip is turne" on% t!e output clock o& eac! group P,CP;@.2 9ri"ge issue" to t!e CPU P@% represents ,*S CPUKs core #oltage !ttp244www6wen"angwang6com4"oc4c$"1?&-&<<&&0$?1A1Ac0e"? .:+P;,*2 bri"ge to t!e CPU &or P@% noti& t!e CPU% memor% power suppl mo"ule ,* PLTST 52 9ri"ge issue" plat&orm reset '6'% con#erte" as t!e CPU reset INTEL c!ipset series si "i&&erent timings CCTC2 TCST 5 4 STCST 5 CC.S;'>'2 .eep Sleep 9oar" to pro#i"e a wake3up bri"ge power suppl (.eep Sleep ;ell)% '6'6 It "oes not support "eep sleep% t!is electricit Pressure an" connecte" toget!er CCSUS'>'



.P;,*2 9oar" to bri"ge '6' !ig!% in"icating t!at t!e power CC.S;'>' goo"% '6'6 Tr not support sleep6 T!is signal E#en toget!er S+ST 5 SLP>SUS 52 .eep Sleep mo"e in"ication signal can be use" to open t!e SA state #oltage% suc! as CCSUS'>' not support "eep sleep6 SLP>SUS 5 #acant CCSUS'>'2 9oar" to bri"ge t!e stan"b power suppl '6' S+ST 52 9oar" to bri"ge '6' !ig! le#el :CPI a reset signal SUSCL*2 9ri"ge issue" '-6/01*78 clock% but not necessaril t!e mot!erboar" uses P;9TN 52 &alling bri"ge recei#es a trigger signal% '6'3<3 '6'% can eit t!e sleep state noti&ication bri"ge SLP>SA2 rear ale recei#e P;9TN 5% set !ig! SLP>SA 5 to '6'% s!owing o&& Eit SLP>S?2 bri"ge set !ig! SLP>S? 5 to '6'% s!owing out o& !ibernation   .I++2 memor power suppl CC2 ale main power suppl% etc6



CPU SI.2 Serial I. signal CPU issue" &or a"Justing t!e CPU core #oltage an" power control set was :&ter t!e CPU get P,CP;@.% will be issue" SI. CCC,E>CPU2 +ot!erboar" CPU power suppl to t!e core SGS>P;,*2 b t!e power management c!ip CPU is sent bri"ge '6' !ig! le#el% equi#alent to +P;@!ttp2 44www6wen"angwang6com4"oc4c$"1?&-&<<&&0$?1A1Ac0e"?. P;,*2 :P;,*2 +E mo"ule power is goo"% open :+T mo"ule .:+P;,*2 bri"ge to t!e CPU &or P@ -A+78 Crstal ,sc2 0 series c!ipset no clock c!ip% increasing t!e -A+ crstal bri"ge to bri"ge internal clock mo"ule pro#i"es t!e re&erence &requenc PC7 ,utput Clocks2 bri"ge output clock o& eac! group P,CP;@.2 bri"ge to t!e CPU &or P@% in"icates t!at t!e CPU core #oltage ,* PLTST 52 9ri"ge plat&orm issue" reset '6'% con#erte" paper consists &ast as t!e CPU reset "imension 3 .ream struggle 3 Pro"uction



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Laptop Power Sequencing

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