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Chapter 15. Operational Amplifier > Amplifier > SOLVED PROBLEMS

15.17. SOLVED PROBLEMS

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1. The output of an op-amp integrator can swing from +15 V to −15 V. The step input shown in Fig. 15.100(a) is 15.100(a) is v i i = 0 for t < 0 and switched at t = = 0 to 5 V. The output voltage v o = +15 V for t < < 0. Plot the waveform.

Solution:

Table of Contents Index Copyright Dedication Preface Acknowledgements Ch. 1. Physics of Semiconductors Ch. 2. Physical Phenomenon in Homojunction Ch. 3. Diode as Circuit Element Ch. 4. Junction Diode Rectifier

Figure 15.100(a). Figure 15.100(a)

Ch. 5. Physical Phenomenon in BJT Ch. 6. Physical Phenomenon in JFET and MOSFET Ch. 7. Biasing Ch. 8. BJT Amplifiers Ch. 9. FET Amplifiers Ch. 10. Frequency Response of BJT Amplifiers Ch. 11. Multistage Amplifiers Ch. 12. Feedback in Amplifiers Ch. 13. Oscillators Ch. 14. Power Amplifiers Ch. 15. Operational Amplifier 15.1. Introduction 15.2. Ideal Characteristics of Operational Amplifier 15.3. Frequency Response of Op-amp

The time at wich the v o = −15

15.4. Offset Voltage 15.5. Inverting Op-amp Circuit 15.6. Summing Op-amp Circuit 15.7. Op-amp Integrator & Differentiator 15.8. Non-linear Applications of Op-amps 15.9. Precision Rectifier 15.10. Square Waveform Generation

Solution:

15.11. Analog Multiplier

Writing node equations at node v (−) of A1

15.12. Filters 15.13. Simulated Inductance Approach 15.14. DVCVS/DVCCS 15.15. BiFET and BiMOS Circuits 15.16. Analog Computer 15.17. SOLVED



PROBLEMS Ch. 16. Regulated Power Supplies Ch. 17. Integrated Circuit Timers

Figure 15.100(b). Figure 15.100(b)

Ch. 18. Special Two-terminal Devices Ch. 19. Tuned Amplifier Bibliography Index

Now the waveform is plotted as in Fig. 15.100(b). 15.100(b). 15.101, using two ideal 2. For the instrumentation amplifier shown in Fig. 15.101, op-amps op-amps verify the following equation (GKP Univ. 1994).

Figure 15.101. Two op-amp instrumentation instrumentation amplifier

At node v (−) of A2

Subtracting this equation from previous one yields

Solution: From Fig. 15.102



3. Show that the cross coupled differential voltage follower instrumentation amplifier shown in Fig. 15.102 produces 15.102 produces output voltage v o = (1 + a + b) (v (v 2 − v 1).

Figure 15.102. Three op-amp instrumentation amplifier

15.103. (AMI 1992). 4. Obtain the voltage v o for the circuit of Fig. 15.103.

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Solution: Writing node equations as

Figure 15.103. Figure 15.103

This illustrates that using only few kilo ohm resistances in the form of T -network provides very large feedback resistance resulting into very large gain. Fig. 15.104(a). 5. Obtain the voltage gain v o /v i for Solution:




Combining above equations yield

Fig. 15.104(b). 6. Obtain the voltage gain v o /v i for Solution:




7. Obtain the voltage gain v o /v io for Fig. 15.105.

Solution:




8. Prove that the voltage gain and input resistance with feedback in Fig.

15.106 is given by the expressions

and

, where Ri is the internal input resistance of the op-amp Solution:




This input resistance comes in parallel to the op-amp's internal input resistance Ri . Hence, effective input resistance is equal to

. 9. Show that if Ri = ∞, Ro = 0 and A1 and A2 < 0 in Fig. 15.107, then v o = A2{ A1(v f −v 1) + v 2}.


Solution: The output of fir st op-amp is expressed as (v 1 − v f ) A1 = V o1 The output of the second op-amp is




10. For the dc level shifter circuit shown in Fig. 15.108(a), determine the level shift between input and output vol tages.

Solution:




11. Obtain the level shift V o in Fig. 15.108(b).

Solution:

12. Draw the output wave shapes of the voltage follower using op-amp with 1 V/ms slew rate with the square wave input shown in Fig. 15.109(a).

Solution: It is seen from the wave shapes of v o that remarkable distortion occurs for slew rate at high frequency. Fig. 15.109(b) is100 Hz signal that does not produce appreciable distortion. A 10 kHz signal produces appreciable distortion as shown in Fig. 15.109(c). A 1 MHz signal becomes sawtooth wave as in Fig. 15.109(c).





Figure 15.109(c). Figure 15.109(c)

13. A square wave input of 8 V peak to peak magnitude and frequency 2 MHz is applied to a voltage follower which produces the triangular output as shown in Fig. 15.110. What is its slew rate?

Solution:


14. The 741 op-amp is used as an inverting amplifier with its gain = 50. What would be the maximum input signal magnitude applied to it if i ts voltage gain is flat upto 100 kHz?

Solution:

The maximum input signal to get undistorted output should be 15.9 mV.

=

15. A peak to peak input signal of 500 mV has to produce a peak to peak undistorted output voltage of 3 V with a rise time of 4 ms. Can 741 be used for such application?

Solution: Rise time = 3 V (90% − 10%) = 3 V (0.90 − 0.10) = 2.4 V



The 741 cann ot be used. 16. The characteristic of the diode is given by the relationship as I D = I S(eqV/ ηKT – 1), where V is the forward voltage an d η is the ideality factor = 1 (Ge) and 2 (Si). Express V o as a function of V i. What is the value of input voltage to

result in output voltage V o = 0, if R = 100 K Ω, I S = 1 μA and

= 26 mV.


17. In the circuit of Fig. 15.112 the output voltage V o is initially zero. The switch is connected first to A to charge the capacitor C 1 to the voltage V . It is then connected to point B. This process repeats f times per second. Calculate (a) transfer of charge per second from A to B, (b) Derive the average rate of change of the output voltage V o, (c) If the switch and capacitor are removed and a resistor is connected between point A and B, what will be the value of resistor to get the same average rate of chan ge the output voltage, (d) If the repetition rate of the switching action is 10 4 times per second, C 1 = 100 pF, C 2 = 10 pF and V = 10 mV, what is the average rate of change of the output voltage?

Solution: (a) When th e switch changes from B to Af times per second, the charge transferred to the capacitor C 1 = Qf = C 1Vf . The capacitor charges exponentially, but the time constant of charging is zero and hence capacitor charges instantaneously.




(b)

(c)

Equating dV o yields as

,

The integration of the steady input voltage gives ramp (rate of change) voltage. (d)

18. Show that the circuit in Fig. 15.113 simulates an inductance across its input terminals.


Solution:




Solution: When input is changing from −12 V to +12 V, the capacitor gets charged to the maximum voltage exponentially with the time constant = 12 K × 0.1 × 10−6 = 1.2 ms. In order to fin d out the time taken by the capacitor to reach final value = 12 V, we have to see the following expression

19. Draw the waveform of v o(t ) as function of v i. Specifying the output voltage v o(t ), determine the voltage levels and time constants involved.



As the capacitor gets charged from −12 V to slightly above 0 V, the output amplifier gets saturated. When the capacitor is charged to +12 V, the capacitor starts discharging through saturated transistor with a time constant = 100 × 0.1 × 10 −6 = 0.01 ms

20. Show that circuit of Fig. 15.115 simulates an inductor i.e. inductive.

is


Solution:

21. How much is the output voltage in the circuit of Fig. 15.116.

Solution: Writing node equation at the inverting input terminal of the op-amp results as




22. Obtain the value of resistor R for the condition that both inputs V − and V + should be amplified by the same amount in Fig. 15.117.


23. Derive a relationship between the input and output voltages for the circuit shown in Fig. 15.118. Also obtain the output waveform for a symmetrical square wave input voltage of amplitude V p and frequency f .




Solution:

If the input voltage is square wave, the output voltage is a triangular wave of magnitude ±V P and frequency f . 24. Find out the value of two resistors used in a non-inverting op-amp to result in the voltage gain of 21 dB.

Solution:

25. Obtain the transfer function between input and output voltages of Fig. 15.119. What will be the value of the capacitor required to yield a phaseshift of 270° at a frequency of 1 kHz with R = 10 K?


Solution:



The plots of magnitude and phase shift are shown in Fig. 15.120.

Figure 15.120. Phase and magnitude p lot of given circuit

26. Obtain the transfer function between input and output voltages of Fig. 15.121.




Solution:

Phase shift = 180° − tan−1

ωCR

− tan−1ωCR = 180° − 2 tan−1 ωCR

The plots of its magnitude and phase-shift are shown in Fig. 15.122.

Figure 15.122. Phase and magnitude p lot of given circuit

27. What value of the resistance RB will provide balance of the bridge yielding V o = 0 for R A = RC = RD = 1 KΩ. What will be the value of output voltage, if now RB is set to 0.5 K?


Solution:



28. Sketch the waveform of the output voltage for the circuit of Fig. 15.124. What portion of the current i o coming out from the operational amplifier flow as the load current i L?

Solution:




Hence, i o = 1mA cos 2 π × 100t , now i L = i o (max) − i f = 1 mA − 0.1 mA = 0.9 mA Hence, total i L(max) = 0.9 mA + 0.9 mA = 1.8 mA. 29. Determine the output voltage v o for the circuit shown in Fig. 15.125.


Solution:

or, V o = (2 − 1.99)1.99 = 0.02 V 30. Show that the system shown in Fig. 15.126 is a double integrator. In other

words, prove that the transfer gain is given ideal op-amp.


Solution:

, assume an



and Z 2 are series elements and Z 1 is shunt element.

31. Obtain the voltage transfer function between output and input voltages of Fig. 15.127. When switch is open, the opamp does not draw any current and hence I 2 = 0.

Solution:




When the switch is closed, the non-inverting input terminal is pulled to ground and hence its gain

32. Obtain voltage gain under the control of voltage applied at the gate of the JFET in Fig. 15.128. When control signal = 0, the JFET offers minimum drain resistance and hence non-inverting input terminal is pulled to approximately

ground. Thus,

.

Solution:


When the control signal is high, it reduces the channel width and provides very large resistance to provide open circuit, thus V 1 = V 2 = V i.

33. Find the condition of input voltage for making the LED ON in Fig. 15.129.

Solution:

Hence, LED will glow if V i > 5 V.




that the LED in Fig. 15.130 34. What will be the value of input voltage V i such starts glowing. LED will glow if V i > 5 V.


35. An op-amp with a slew rate of 1.5 V/ms has been used as an inverting amplifier with gain of 10. What is the maximum input signal if the frequency of input signal is 1 kHz?

36. Calculate the voltages V 1 and V O in Fig. 15.131.


37. When will the output get saturated in Fig. 15.132?




38. The switch was closed initially for 0.5 minutes and then opened. What will be the input voltage if the output in Fig. 15.133 is initially 0 and −5.4 V after the switch is opened.


39. A differential amplifier converted to difference amplifier has feedback and input resistor of equal values as in Fig. 15.134. What will be the output, if inputs to inverting and non-inverting terminals are 1.5sin ωt and 1.5 cos ωt .

Solution:


40. The integrator shown in Fig. 15.135 produces an output voltage = V o = V m sin (100t + φ) in response to an input voltage of V i = 0.1 sin(100t). What is the maximum value of the output voltage?




41. What is the relationship between resistors R and R1 and R2 in Fig. 15.136.

Solution:



42. The offset voltage to the circuit of Fig. 15.137 is 1 mV. How much output voltage will be displayed?

Solution:



43. What would be the frequency of oscillation in Fig. 15.138, if μF and R = 1 K? What would be the minimum gain of the amplifier to sustain oscillations?


44. Calculate the ratio of ON duration to OFF duration of the output waveform of circuit in Fig. 15.139.




45. Obtain CMRR for the circuit shown in Fig. 15.140.




46. Obtain the output voltage of the amplifier shown in Fig. 15.141


47. The output voltage of Schmitt trigger drawn in Fig. 15.142 is limited to 10 V and −5 V connecting sui tably chosen Zener diodes across the output. What are the upper trip and lower trip voltages of the circuit?




sinωt applied to the circuit in 48. Obtain the output voltage for input voltage v i = Fig. 15.143. Solution: For v i > 0 V, diode is reverse biased, no loop closes. v o = v i For v i < 0 V, diode is forward biased, loop closes. v o = − v i


49. Obtain the output voltage of Fig. 15.144. What is the name of this circuit?

Solution: For V i > 0, D1 is forward biased and D2 is reverse biased, V o = 0.

For V i < 0, D1 is reverse biased and D2 is forward biased, . The circuit is a half wave rectifier and conducts for negative half cycle only.


50. What is the ratio of current

in Fig. 15.145.




51. Obtain the value of R A such that V O =

in Fig. 15.146.


52. What is the value of the output voltage in Fig. 15.147.




in Fig. 15.148 assuming all op-amps are ideal. Also 53. Show that show that D represents a frequency dependent negative resistance.

Figure 15.148. Riordan circuit

The circuit of Fig. 15.148 can now be analyzed for its input impedance as



= negative conductance. 54. Find out the output voltage v o for the circuit in Fig. 15.149.


55. Obtain the output vol tage of an op-amp summer shown in Fig. 15.150.


56. Circuit of summing integrator

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