DOC/LP/01/21.01.05 LP – EC2354 LESSON PLAN LP Rev. No: 01 Date: 15/12/11 Sub Code/Name: EC2354-VLSI DESIGN Unit : I Branch : EC Semester: VI Page 01 of 06
UNIT I
CMOS TECHNOLOGY
9
Syllabus:
A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal I-V effects, DC transfer characteristics - CMOS CMOS technologies, Layout design Rules, CMOS process enhancements, Technology related CAD issues, Manufacturing issues. Objective: To understand the MOS transistor theory, CMOS technologies and the Layout Session No.
Time
Page No
Re f
Topics to be covered
Teaching Method
1.
Introduction –VLSI Design
50m
1-4
1
BB
2.
NMOS, PMOS Enhancement transistor
50m
5-7,40
1
BB
3. 4. 5.
MOS transistor-Ideal I-V characteristics MOS transistor-C-V characteristics Non ideal deal I-V I-V char charac actteri eristi sticscs- vel velocit ocity y satu satura rati tion on and mobility degradation, channel length modulation, sub threshold conduction, Body effect Thres reshold vo voltage, Ju Junction le leakage, Tu Tunneling, temperature dependence, Geometry dependence CMOS inver verter DC charac racteristics, Beta rat ratio effects
50m 50m 50m
42-45 45-51 51-55
1 1 1
BB BB BB
50m
55-60
1
BB
100m
60-65
1
BB
CMOS te technology : nwell, P well Tw Twin we well, triple well, Layout design rules-NAND,NOR gate
50m
1,3
BB, OHP
50m
83, 15-21 83-91
1
BB,OHP
CMOS Proc rocess enhancement-SO -SOI Proc rocess, Interconnects, circuit elements: Resistors Circuit el element: ca capacitor, CA CAD an and manufacturing issues Tutorial CAT-I
50m
91-100
1
BB
50m
107109,149 -
1,2
BB
1,3 -
BB -
6. 7. 9. 10. 11. 12. 13.
50m 50m
DOC/LP/01/21.01.05 LP – EC2354 LESSON PLAN LPRev. No: 01 Date: 15/12/11 Sub Code/Name: EC2354-VLSI DESIGN Unit : II Branch : EC Semester: VI Page 02 of 06
UNIT II
CIRCUIT CHARACTERIZATION AND SIMULATION
9
Syllabus:
Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling- SPICE tutorial, Device models, Device characterization, Circuit characterization, Interconnect simulation. Objective: •
To study the circuit characterization and performance estimation of CMOS technology .
Session No.
14.
Topics to be covered
Time
Page No
Ref
Teaching Method
50m
1,2
BB
1,2 1 1,2
BB BB BB
1 1 1,2 1 1
BB BB BB BB BB,OHP
1
BB,OHP
1,3
BB,OHP
-
-
18. 19. 20. 21. 22.
Delay estimation-RC delay model, Linear delay model Logical effort ,Transistor sizing Power dissipation-static and dynamic power Interconnect –Estimation of resistance capacitance, delay cross talk delay effects,Design margin Reliability Scaling, SPICE tutorial SPICE tutorial, Device models Device& Circuit characterization
50m 50m 50m 50m 50m
23.
Interconnect simulation
50m
24.
Tutorial
50m
111117,245 118,313 129-135 142148,525 145-148 148-159 159,229 181-193 193 -213 193 -213 -
CAT-II
50m
-
15. 16. 17.
50m 50m 50m
LESSON PLAN SubCode/Name EC2354 -VLSI DESIGN Unit : III Branch : EC
UNIT III
DOC/LP/01/21.01.05 LP – EC2354 LP Rev. No: 01 Date: 15/12/11 Semester: VI Page 03 of 06
COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN
9
9
Syllabus:
Circuit families –Low power logic design – comparison of circuit families – Sequencing static circuits, circuit design of latches and flip flops, Static sequencing element methodology- sequencing dynamic circuits – synchronizers Objective: To Understand the concepts of designing combinational and sequential circuit using CMOS logic configuration Session No. 25.
Topics to be covered
Time
1,2
Teaching Method BB
1,2,3
BB
50m 50m
Page No 215224,342 225,361 , 353 233-240 241-245
Circuit families-static CMOS,ratioed circuit
50m
26.
Cascode voltage swing logic,Dynamic circuits
50m
27. 28. 29.
Pass transistor,Differential circuits BiCMOS,Low power logic design – comparison of circuit families Sequencing static circuits
30.
Ref
1 1
BB BB
50m
252-265
1
BB
Circuit design of latches and flip flops
100m
265-274
1
BB,OHP
32.
Static sequencing element
50m
275-283
1
BB
33.
Sequencing dynamic circuits
50m
284-289
1
BB
34.
Synchronizers
50m
289-294
1
BB
CAT-III
50m
-
-
-
DOC/LP/01/21.01.05 LESSON PLAN Sub Code/Name: EC2354 -VLSI DESIGN Unit : IV
UNIT IV
Branch : EC
LP – EC2354 LP Rev. No: 01 Date: 15/12/11 Page 04 of 06
Semester: VI
CMOS TESTING
9
Syllabus: Need for testing- Testers, Text fixtures and test programs- Logic verificationSilicon debug principles- Manufacturing test – Design for testability – Boundary scan. Objective: To understand the concepts of CMOS testing
Session No. 35.
Time
Page No
Ref
50m
531-541
1
50m
541-547
1
BB
37.
Need for testing Text fixtures and test programs Logic verification-- Silicon debug principle, Manufacturing test Manufacturing test
Teaching Method BB
50m
1,2,4
BB
38. 39. 41.
Design for testability-adhoc tesing Scan design Built in self test, IDDQ testing
50m 100m 50m
547549,621,23 9 548-550 550-555 555-558
1 1 1
BB BB BB
42.
Boundary scan CAT-IV
100m 75m
559-570 -
1 -
BB -
36.
Topics to be covered
DOC/LP/01/21.01.05 LESSON PLAN LP – EC2354 SubCode/Name: EC2354 VLSI DESIGN LP Rev. No: 01 Date: 15/12/11 Unit : V Branch : EC Semester: VI Page 05 of 06 9
UNIT V SPECIFICATION USING VERILOG HDL
Syllabus:Basic concepts-
identifiers- gate primitives,
gate delays,
operators, timing
controls,procedural assignments conditional statements, Data flow and RTL, structural gate level,switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches,Structural
gate
level
description
of
decoder,
equality detector,
comparator,
priorityencoder, half adder, full adder, Ripple carry adder, D latch and D flip flop. Objective: To understand the concepts of modeling a digital system using Hardware
Description Language.
Session Topics to be covered No. 44. Basic concepts- identifiers- gate primitives,, Design hierarchies
Time
Page No
Ref
50m
8,2
Teaching Method BB
8 8 8
BB BB BB
45. Gate delays 46. Operators 47. Chip Timing controls
50m 50m 50m
4748,72,106,38 8 121 138 171-178
48.
50m
166,179
8
BB
50m 50m 50m 50m
131 373 383 385
8 8 8 8
BB BB BB BB
50m
136
8
BB
50m
452,414
2,4
BB
50m
-
-
-
49. 50. 51. 52. 53. 54.
Procedural assignments ,conditional statements Data flow and RTL Structural gate level Switch level modeling Behavioral and RTL modeling, Test benches Gate level verilog code-Decoder, equality detector, comparator, priorityencoder Half adder, full adder, Ripple carry adder, D latch and D flip flop . CAT-V
DOC/LP/01/21.01.05 LESSON PLAN
LP – EC2354 LP Rev. No: 01 Date: 15/12/11 Page 06 of 06
SubCode/Name: EC2354-VLSI DESIGN Branch : EC Semester: VI
Course Delivery Plan:
Week
Units
1
2
3
4
I II 1 1
I II I II I II I II I II I II I II I II I II I II I II 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 2 5 C A T 1
5
6
7
C A T 2
8
9
C A T 3
10
11
12
C A T 4
13
14
15
I II I II I II 5 5 5 - - C A T 5
TEXT BOOKS: 1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pears on Education, 2005 2. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002.
REFERENCES: 3. D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003 4. Wayne Wolf, Modern VLSI design, Pearson Education, 2003 5. M.J.S.Smith: Application specific integrated circuits, Pearson Education, 1997 6. J.Bhasker: Verilog HDL primer, BS publication,2001 7. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003 8.Samir palnitkar, Verilog HDL , Pearson Education,second edition
Name Designation Date Signature
Prepared by M.ANUSHYA Asst- professor
Approved by Prof.E.G .Govindan HOD, Department of EC
