Progress Report

Progress Report on

“VLSI Implementation of Convolution and DSP Algorithm using Vedic Mathematics” Submitted  in  partial fulfillment   for the award of the Degree of 

 Doctor of Philosophy in  Department of Electronics Engineering 

Supervisor:

Submitted By:

Dr. R. S. Meena,

Rajesh Bathija

Associate Professor, ECE Deptt

Enrolment No.: 11/1011

Department of Electronics Engineering

University College of Engineering, Rajasthan Technical University, Kota December- 2012

ABSTRACT In any processor the major units are Control Unit, ALU and Memory read write. Among these units the performance of any processor majorly depends on the time taken by the ALU to perform the specified operation. Multiplication is an important important fundamental fundamental function function in arithmetic arithmetic operations. operations. Multiplication Multiplication- based operations such as Multiply and Accumulate (MAC) and inner product are among among some some of the frequen frequentl tly y used used Comput Computati ation on Intensi Intensive ve Arithm Arithmeti eticc Functions (CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform (FFT), filtering etc. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Vedi Vedicc Math Mathem emat atic icss is the the nam name give given n to the the anci ancien entt syst system em of  mathematics, or to be precise, a unique technique of calculations based on simple simple rules rules and princi principle pless with with which which any mathem mathemati atical cal proble problem m can be solved – be it arithmetic, algebra, geometry or trigonometry. The system is  based on 16 Vedic sutras or aphorisms, which are actually word formulae describing natural ways of solving a whole range of mathematical problems. The task in this progress report is to show the novel multiplier design developed in the Tanner tool software of Very Large Scale Integration (VLSI). Performance of this multiplier is much faster and consumes less power than the recently developed multiplier architectures. ii

ACKNOWLEDGMENTS

I would like to express my sincere thanks to my supervisor, Dr. R.S. Meena, Asso. Proff., Department of Electronics Engineering, University College of  Engineering, Rajasthan Technical University, Kota. Dr. R.S. Meena provided me with with nece necess ssar ary y supp support ort,, advi advice ce,, faci facili liti ties es and and enth enthus usia iasm sm requi required red to successfully complete this phase of progress report of the PhD. His efforts in helping me in the development of the project, through technical difficulties and in search for relevant literature are much appreciated. I would also like to thank  Dr. Rajeev Gupta, Professor & Head,

Department of Electronics Engineering, Dr. Mithilesh Kumar, Dr. Ranjan Maheshwari for their valuable support and providing me necessary guidance. I am much obliged to the people that provided appreciated feedback on drafts of this Progress Report.

(Rajesh Bathija) iii

TABLE OF CONTENTS Description

Page No.

Abstract

ii

1. Introduction

01

2. Historical Development of Multiplication Algorithms

04

3. Vedic Mathematics

08

4. Objective of PhD Work

12

5. Research Plan

14

5.1 Research Problem

14

5.2 Research Hypothesis

14

5.3 Research assumptions

14

5.4 Research method

15

5.5 Research strategy

15

6. Publication

17

7. Future Planning

29

8. References

32

iv

CHAPTER -1

INTRODUCTION

All of us are familiar with the digital circuitry. Now days the digital circuitry has replaced most of the analog circuitry in various places because technically digital domain is much better than the analog domain. To operate these digital signals we use the Digital Signal Processors (DSP). Convolution in DSP is the basic operations to find out the output of an LTI system. In DSP to  perform different types of operations we use various algorithms, out of these algorithms Fast Fourier Transform (FFT) is the most important and significant algorithm. Basically the FFT algorithm is used as an efficient means to compute the DFT and IDFT. The FFT algorithm is used in variety of areas, including linear filtering, correlation and spectrum analysis, because of  its capability to perform efficient computation in comparison to the DFT. There are mainly two ways, through which FFT algorithm can be performed, which are DIT and DIF whose acronyms are Decimation In Time and Decimation In Frequency respectively. Speed of both of  these FFT algorithms mainly rely on the multiplier used in it. So performance of FFT processor  can enhanced with the use of highly speed efficient multiplier [1] Digital signal processing (DSP) is the technology that is omnipresent in almost every engineering discipline. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing application. The core computing process is always a multiplication routine in DSP; therefore, it’s necessary for a multiplier to be fast and power efficient and so, development of a fast and low power multiplier has been a subject of interest over decades.

In this Phd Progress Report-I, different multiplier architectures are present. Multiplier   based on Vedic Mathematics is one of the fast and low power multiplier. The work presented here, makes use of Vedic Mathematics and goes step by step, by first designing a Vedic Multiplier, then a Multiply Accumulate Unit, then an Arithmetic module which uses this

multiplier and MAC unit, and finally convolution and other algorithms of Digital Signal Processing (DSP) like FFT, DCT, etc.

CHAPTER- 2 HISTORICAL BACKGROUND OF MULTIPLICATION ALGORITHMS 2.1 Booth Algorithm: An algorithm for multiplication of two signed bit numbers was invented by Andrew Donald Booth in 1950[6]. Booth’s algorithm works on the principle of shift and adds. Fig.2.1 illustrates multiplication of two 4 bit nos. m and n using Booth’s Algorithm. Initially a new number ‘P’ is formed by appending 0s, equal to one more than the number of bits of multiplier to the MSB of  multiplicand. Also duplication of MSB i.e. sign bit of multiplier n and multiplicand m is done along with which 0s are appended to the LSB of multiplier and multiplicand so as to make length of multiplicand and multiplier equal to P, consider they be X and A respectively. Let S  be 2’s compliment of X for subtraction purpose. In Fig.1 for simplicity purpose the LSB bit of  multiplier (n) and nlsb are shown in bold, these are the pair of bits of multiplier which are analyzed and a respective operation of shift and add is performed on P depending on the following four conditions. If pair of bits is: 00 or 11, circular right shift is performed on P, 01, multiplicand is added to the MSB of P and then circular right shift is performed on P, 10, subtract Multiplicand from the MSB of P and then circular right shift is performed on P. Initially, nlsb bit is considered 0, in the immediate next cycle, a copy of lsb bit of multiplier is made in nlsb column and circular right shift operation is performed on multiplier. The process continues until the no. of cycles is equal to the no. of bits in the multiplier. The result so obtained in P at the end of the last cycle is the final result of multiplication.

Figure 2.1. Illustration of Booth’s Algorithm

2.2 Wallace Algorithm Another algorithm for multiplication of two numbers was implemented by Chris Wallace in 1964 [11]. Fig.2.2 illustrates the working of Wallace Algorithm for multiplication of two 4 bit nos. At first, the partial products P1,P2, P3, P4 are computed. As demonstrated in Fig. 2.2(a) first three partial products are selected where P3 is right shifted left by 2 bits and P2 by 1 bit and finally is column-wise added with P1 to give an intermediate result as shown in Fig. 2.2(b). This intermediate result is column-wise added with the immediate next partial product term P4 which is shifted left by 1 more bit as shown in Fig.2.2(c). The process continues until all the  partial product terms are added to give the final result.

Fig2.2 Illustration of Wallace Algorithm (a) Computation of Partial Products

Fig2.2 Illustration of Wallace Algorithm (b) Addition of first three Partial Product Terms

Figure 2.2. Illustration of Wallace Algorithm (c) Result

2.3 Karatsuba Algorithm Another algorithm was proposed by Anatolii Alexeevitch Karatsuba in 1960 [8] the flow graph of which is shown in Fig.2.3. Initially both the multiplicand and the multiplier say m and n are divided into two equal parts m0,m1 and n0,n1. Algorithm proposes evaluation of three

intermediate terms u0, u1 and u2. They are computed as shown in Fig 2.3. The final result is obtained following the equation mentioned in the last layer of the flow chart. The base mentioned in the equation depends on the number system in which the two numbers are, i.e. 2 for binary and the shift mention in the equation is half the length.

2.4 Toom-Cook Algorithm It was first described by Andrei Toom[9] in 1963 and was implemented by Stephen Cook in 1966 in his PhD thesis[10]. The algorithm is similar to that Karatsuba Algorithm with only one modification which is dividing the given number into multiple equal parts. As seen in Fig.2.3, where numbers are divided into two parts m0,m1 and n0,n1 similarly, numbers could be divided into multiple equal parts, say 3. Consider two numbers m and n, divided in 3 equal  parts m0,m1,m2 and n0,n1 ,n2. The product of m and n could be obtained from the intermediate terms, which are obtained from the smaller terms m0,m1,m2 and n0,n1,n2.

Figure 2.3. Flowchart illustrating working of Karatsuba Algorithm

2.5 Vedic Algorithm Vedic Algorithm, specifically Urdhva Tiryagbhyam (vertical and crosswise multiplication) is one of the 16 sutras found in ancient hindu text dated back to 500B.C [12]. As shown in Fig 2.4 each and every bit of multiplicand and multiplier are ANDed with each other producing an intermediate result, this result is ORed with another intermediate result similar to what is  pictorial representation in Fig.4 to produce partial products P1,P2,P3,…,P7. Final Result thus is obtained by adding each of the partial product terms by sequentially left shifting each term.

2.6 Chinese Algorithm It finds its origin in the mathematical text Zhou Bi Suan Jing which goes back to 300B.C. [7].The working of the algorithm is similar to that of Vedic. Fig.2.5 illustrates evaluation of   partial products as per the algorithm. Initially, a table is drawn whose rows and columns are

Figure 2. 4. Illustration of Vedic Algorithm[13] equal to the length of multiplier and multiplicand resp. and diagonals are drawn for each cell as shown in the Fig. 2.5. Diagonal divides the cell into upper and lower triangle. The bits of  multiplier and multiplicand are arranged across the table as shown in the Fig.2.5, these individual bits of multiplier and multiplicand are multiplied with each other to produce a result, quote the carry of result in the upper triangle and sum in the lower triangle of the corresponding cell. The partial products P1,P2,…,P8 thus will be obtained by adding elements as shown in the Fig 2.5. Similar to Vedic algorithm these partial product terms are added to produce final result

Figure 2.5. Evaluation of Partial Products using Chinese Algorithm

2.7 Array multiplier It is an efficient layout of a combinational multiplier. Multiplication of two binary number can  be obtained with one micro-operation by using a combinational circuit that forms the product  bit all at once thus making it a fast way of multiplying two numbers since only delay is the time for the signals to propagate through the gates that forms the multiplication array. In array multiplier, consider two binary numbers A and B, of m and n bits (3). There are mn summands that are produced in parallel by a set of mn AND gates. n x n multiplier requires n(n-2) full adders, n half-adders and n2 AND gates. Also, in array multiplier worst case delay would be (2n+1) td. Array Multiplier gives more power consumption as well as optimum number of components required, but delay for this multiplier is smaller. It also requires larger number of gates because of which area is also increased; due to this array multiplier is less economical [2] [11].Thus, it is a fast multiplier but hardware complexity is high [4]

Fig. 2.6 Array Multiplier 

CHAPTER- 3 VEDIC MATHEMATICS Vedic mathematics was rediscovered from the ancient Indian scriptures between 1911 and 1918 by Sri Bharati Krishna Tirthaji (1884-1960), a scholar of Sanskrit, mathematics, history and  philosophy [2]. He studied these ancient texts for years and, after careful investigation, was able to reconstruct a series of mathematical formulae called sutras. Bharati Krishna Tirthaji, who was also the former Shankaracharya (major religious leader) of Puri, India, delved into the ancient Vedic texts and established the techniques of this system in his pioneering work, Vedic Mathematics (1965), which is considered the starting point for all work on Vedic mathematics. Vedic mathematics was immediately hailed as a new alternative system of mathematics when a copy of  the book reached London in the late 1960s. Some British mathematicians, including Kenneth Williams, Andrew Nicholas and Jeremy Pickles, took interest in this new system. They extended the introductory material of Bharati Krishna’s book, and delivered lectures on it in London. In 1981, this was collated into a book entitled Introductory Lectures on Vedic Mathematics [3]. A few successive trips to India by Andrew Nicholas between 1981 and 1987 renewed interest in Vedic mathematics, and scholars and teachers in India started taking it seriously. According to Mahesh Yogi, The sutras of Vedic Mathematics are the software for the cosmic computer that runs this universe. A great deal of research is also being carried out on how to develop more powerful and easy applications of the Vedic  sutras in geometry, calculus and computing. Conventional mathematics is an integral part of engineering education since most engineering system designs are  based on various mathematical approaches. All the leading manufacturers of microprocessors have developed their architectures to be suitable for conventional binary arithmetic methods. The need for faster processing speed is continuously driving major improvements in processor technologies, as well as the search for new algorithms. The Vedic mathematics approach is totally different and considered very close to the way a human mind works. In table 3.1 Vedic Sutra, their Meaning and Applications.

Table 3.1 Vedic Sutra, their Meaning and Applications S. No.

Sutra

Meaning

Application

1.

(Anurupye) Shunyamanyat

If one is in ratio, the other is zero

Factorization

2.

ChalanaKalanabyham

Differences and Similarities

Differential Calculas

3.

Ekadhikina Purvena

By one more than the previous One

Integration, division

4.

Ekanyunena Purvena

By one less than the previous one

Multiplication

5.

Gunakasamuchyah

The factors of the sum are equal to the sum of the factors.

Successive differentiations, Factorization

6.

Gunitasamuchyah

The product of the sum is equal to the sum of the product.

Factorization of cubic

7.

Nikhilam  Navatashcaramam Dashatah

All from 9 and last from 10

Multiplication, division

8.

Paraavartya Yojayet

Transpose and adjust

Division, factorization,  partial fraction,  polynomial division

9.

Puranapuranabyham

By the completion or   noncompletion

Cubic and forth degree eq.

10.

Sankalanavyavakalanabhyam

By addition and by subtraction

H.C.F

11.

Shesanyankena Charamena

The remainders by the last digit

Recurring decimal division calculus

12.

Shunyam Saamyasamuccaye

When the sum is the same that sum is zero

Factor & simple eq. solution

13.

Sopaantyadvayamantyam

The ultimate and twice the  penultimate

Factorization

14.

Urdhva-Tiryakbhyam.

Vertically and crosswise

Multiplication, argument division

15.

Vyashtisamanstih

Part and Whole.

Biquadratic equations

16.

Yaavadunam

Whatever the extent of its deficiency.

Cubing

CHAPTER- 4

OBJECTIVES OF PhD WORK 

Objectives of my Ph.D. research work can be divided into five broad sections: Understanding of Vedic Approach:

Ancient Indian mathematics is called as Vedic Mathematics [7]. Vedic mathematics from Vedas was first proposed by Sri Bharati Krisna Tirthaji, after his survey on Vedas. Vedic mathematics reduces the complexity in calculations that exist in conventional mathematics. Generally there are sixteen sutras available in Vedic mathematics. Applications of these Sutra are given in Table 3.1.

Implementation of Vedic Multiplier:

Among 16 Sutra of Vedic Mathematics only two sutras are applicable for multiplication operation. They are Urdhva Triyakbhyam sutra (literally means vertically and cross wise) and  Nikhilam Sutra (literally means All from 9 and last from 10). Developing the 16 X 16 Bit Vedic Multiplier using UT sutra is designed & verified. A novel design is developed which is designed on Tanner EDA tool

in 16nm Technology using CMOS logic family. Delay

(27.14865 ns) is lesser than Booth and recently developed Multiplier using Vedic approach. Power dissipation (0.1692638 mW) is also much lesser than these multiplier.

Implementation of Convolution using Vedic Approach:

 Next task is to develop the very basic functional operation of an LTI system i. e. Convolution using Vedic approach. In this Adder, Shifter and Multiplier blocks will be used. So for all these three Vedic Algorithms will be used to develop. We will try to develop finite length circular convolution for discrete time signals.

ALU Design using Vedic Algorithms

Arithmetic & Logical Unit (ALU) Design will be the next task. All logical operation can be  performed using Vedic Algorithm. So we can design all building blocks of ALU using Vedic approach. DSP processor design using Vedic Algorithms

After designing the ALU we can design FFT algorithms using Vedic Approach. We can also design a complete Digital Signal Processor on the Vedic Apprach. This will surely be the fastest and less power consumed processor.

Since my Ph.D. research is at an early stage, the preliminary parts of my research which have  been covered till now are presented here. So, here the primary focus will be the followings: (1) Stateof-the-art review of Vedic algorithms. (2) Comparison of performance of existing Non-Vedic and Vedic Algorithm for Multipliers. (3) Development of a Novel Design of the 16X16 bit Multiplier using Vedic Algorithm

13

CHAPTER -5

RESEARCH PLAN The Main challenge was to develop a new design of a Multiplier using Vedic Algorithm which can be fastest among the available Multiplier algorithms. After developing this design now we can go to design the other algorithms of DSP.

5.1 Research Problem

The following problems are of interest in the development of DSP Processor using Vedic Algorithm: 

First, what will be the circuitry to design a Multiplier, Adder using Vedic Algorithms?



Second, how we can implement the convolution using Vedic Algorithm?



Third, how we can design an ALU using Vedic Algorithms?



Fourth, how we can design FFT using Vedic Algorithm?



Fifth, How we can design a DSP processor using Vedic Algorithm?

The division of the research problem into the five problems above defines the following 5.2 Four research hypotheses: 

RH1: To obtain a distinctively high speed and power efficient Multiplier and Adder using Vedic Algorithm, we have to design new circuits.



RH2: To implement convolution we have to take circular convolution because of finite length sequence it will handled.



RH3: To design an ALU we use remaining sutra of the Vedic Mathematics.



RH4: For DIT FFT and DIF FFT algorithm implementation we can use matrix multiplication approaches of Vedic Mathematics.

5.3 Research assumptions

The general research assumption is that the Vedic algorithms provide a good performance circuitry to DSP related problems.

5.4RESEARCH STRATEGY For the achievement of the above objective, the research method involves the following: Phase 1:

This phase will comprise of Literature survey. Phase 2:

a) Analysis of the different Vedic algorithms for the Multi plication.  b) Selection of appropriate algorithms that could improves the performance of system. Selected algorithms are simulated using Tanner Tool Phase 3:

Convolution using Vedic Algorithm is to be designed in this phase. Its performance should be optimized in this phase.

Phase 4:

ALU design using Vedic Algorithm is to be take place in this phase. Its optimizations issue should be  proper handled.

Phase 5:

FFT and Filter Design using Vedic Algorithm as well as Digital Signal Processor Design will take place in this Phase.

Phase 6: Results will be concluded with the help of the data, which may be obtained throughout these Phases of research work and will be compiled in thesis. Work Plan:

The work plan (activity schedule) and the time by which these are to be achieved are indicated in the form of horizontal bar chart. There are six phases in the methodology; work plan (bar chart) will be as shown in figure 4.2.

Fig 5.1 -Work plan

CHAPTER- 6 PUBLICATION JOURNAL NAME: International Journal of Computer Application, USA. PUBLICATION YEAR: December18, 2012.

Low Power high speed 16x16 bit multiplier using Vedic Mathematics R.K. Bathija,

R.S. Meena,

S. Sarkar 

GITS, Udaipur, [email protected]

UCE, RTU,KOTA [email protected]

Jadhavpur University, Kolkatta [email protected]

ABSTRACT High-speed parallel multipliers are one of the keys in RISCs (Reduced Instruction Set

Computers), DSPs (Digital Signal Processors), and graphics accelerators and so on. Array multiplier, Booth Multiplier and Wallace Tree multipliers are some of the standard approaches used in implementation of binary multiplier which are suitable for VLSI implementation. A simple digital multiplier (henceforth referred to as Vedic Multiplier in short VM) architecture  based on the Urdhva Tiryakbhyam (Vertically and Cross wise) Sutra of Vedic Mathematics is  presented. An improved technique for low power and high speed multiplier of two binary numbers (16 bit each) is developed. An algorithm is proposed and implemented on 16nm CMOS technology. The designed 16x16 bit multiplier dissipates a power of 0.17 mW. The propagation delay time of  the proposed architecture

is 27.15ns. These results are many improvements over power 

dissipations and delays reported in literature for Vedic and Booth Multiplier. Keywords Vedic Multiplier, Urdhva Tiryakbhyam, CMOS Technology, Power Dissipation, Propagation

Delay.

1. INTRODUCTION The ancient system of Vedic Mathematics was rediscovered from the Indian Sanskrit texts

known as the Vedas, between 1911 and 1918 by Sri Bharati Krisna Tirthaji (1884-1960) from the Atharva Vedas. According to his research all of mathematics is based on sixteen Sutras, or wordformulas [1]. These formulae describe the way the mind naturally works and are therefore a great help in directing the student to the appropriate method of solution. In the Vedic system difficult  problems or huge sums can often be solved immediately by the Vedic method. These striking and beautiful methods are just a part of a complete system of mathematics which is far more

systematic than the modern system. Vedic Mathematics manifests the coherent and unified structure of mathematics and the methods are complementary, direct and easy. It’s a unique technique of calculations based on simple principles and rules , with which any mathematical  problem - be it arithmetic, algebra, geometry trigonometry, or even calculus can be solved mentally[2]. In this paper a simple 16 bit digital multiplier is proposed which is

based on Urdhva

Tiryakbhyam (Vertically Crosswise) Sutra of the Vedic Maths. Two binary numbers (16-bit each) are multiplied with this Sutra. The potential of this method is that the power dissipation of  this circuit is 0.17 mW. & propagation delay of the proposed architecture is 27.15ns. These results are improvements over power dissipations and delays reported in literature for Vedic and Booth Multiplier. Array multiplier, Booth Multiplier and Wallace Tree multipliers are some of  the standard approaches used in implementation of binary multiplier which are suitable for VLSI implementation. Table (1): Comparison of Different Conventional Multipliers Parameter

Array

Wallace

Booth’s

Multiplier

Tree

Multipli

Operation

Less

Multiplier High

Highest

Speed Time Delay Area

More Maximum

Medium Medium

Less Minimu

area

area

 because

 because it

 because

adder/su

uses

Wallace

is small

a

large

Tree used

number of 

to reduce

Complexity

Adders Less

Operands More

Most co

Power 

complex Most

complex More

Less

Consumption FPGA

Less

 Not

Most ef 

implementation

efficient

efficient

In the section 2 introduction of the method will be discuss, with the description of the Sutra, steps of multiplication. In section 3 design of the 16x16 bit multiplier with the basic building  blocks like 2x2 bit Multiplication, 4x4 bit multiplication, 8x8 bit multiplication. In section 4 we state the comparison of different multiplier. In section 5 we conclude.

2.

2.1

Introduction to Proposed Technique Design Factors of Multiplication: Latency, throughput, area, and design complexity are the important factors to choose a

suitable design for the requirement. Latency is a measure of how long the inputs to a device are stable until the final result available on outputs. Throughput is the measure of how many multiplications can be performed in a given period of time .

2.2

Urdhva Tiryakbhyam Sutra[2]

The basic Sutras and Urdhva Tiryakbhyam Sutra in the Vedic Mathematics helps to do almost all the numeric computations in easy and fast manner [3]. The Sutra which we employ in this  project is Urdhva Tiryakbhyam (Multiplication)

2.3

Description of Sutra[2]

This is the general formula applicable to all cases of multiplication [3]. Urdhva Tiryakbhyam means “Vertically and Crosswise”, which is the method of multiplication followed. Illustration:

Figure (1): Multiplication of two decimal numbers by Urdhava Tiryakbhyam Sutra [1]

Figure (2): Line diagram for multiplication of two 4 – bit numbers [1]. 3.

Design of the 16x16 Multiplier

3.1

The Fundamental Block (2×2 block)

In the design of the proposed Vedic multiplier a 2×2 block is a fundamental block (Basic block) is shown in fig 3. Also symbol of this fundamental block is shown to be used in 4 x 4 bit Multiplier. We know that in binary multiplication basically we AND each two bits in 2-input AND gate[4]. First off all vertical bits (LSBs) are ANDed this will result in the LSB of the result. Than we and crosswise bits and then result is added using a half adder. The sum output of the half adder is the next bit of the result right to the LSB. The carry output is also added in half  adder with the AND output of the MSBs. The carry of this adder is the MSB of the result. The waveforms of input and output of 2-bit multiplier using Urdhva Tiryakbhyam Sutra [5] of Vedic mathematics is shown in figure 4. Power dissipation of this multiplier is 23.2 µW and  propagation delay is 1.51 nsec. 62 transistors are used in this design.

Figure (3): 2-Bit multiplier using Urdhva Tiryakbhyam Sutra & its symbol

Figure (4): Input Output waveforms of 2x2 Bit multiplier 

3.2

Design of 4×4 block 

The design of 4×4 block shown in fig (5) is a simple arrangement of 2×2 blocks in an optimized manner. The first step in the design of 4×4 block will be grouping the 2 bit of each 4 bit input. These pair terms will form vertical and crosswise product terms. Each input bit-pair is handled  by a separate 2×2 Vedic the schematic of a 4×4 block designed using 2×2 blocks. The partial  products represent the Urdhva vertical and cross product terms. Then using or and half adder  assembly to find the final product. Power dissipation of this multiplier is 0.18 mW and  propagation delay is 1.71 nsec. 618 transistors are used in this design

Figure (5): 4-Bit multiplier using Urdhva Tiryakbhyam Sutra & its symbol

3.3

Design of 8×8 block 

The design of 8×8 block is a similar arrangement of 4×4 blocks in an optimized manner as in figure 3. The first step in the design of 8×8 block will be grouping the 4 bit (nibble) of each 8 bit input. These quadruple terms will form vertical and crosswise product terms. Each input bitquadruple is handled by a separate 4×4 Vedic multiplier to produce eight partial product rows. These partial products rows are then added in an 8-bit carry look ahead adder optimally to generate final product bits. The figure (6) shows the schematic of an 8×8 block designed using 4×4 blocks. The partial  products represent the Urdhva vertical and cross product terms. Then using or and half adder  assembly to find the final product. Power dissipation of this multiplier is 0.035mW and  propagation delay is 1.72 nsec. 3222 transistors are used in this design.

Figure (6): 8-Bit multiplier using Urdhva Tiryakbhyam Sutra & its symbol

Figure (7): 16-Bit multiplier using Urdhva Tiryakbhyam Sutra & its symbol

3.4

Design of a 16×16 Multiplier

The design of 16×16 block is a similar arrangement of 8×8 blocks in an optimized manner as in figure (7). The first step in the design of 16×16 block will be grouping the 8 bit (byte) of each 16

 bit input. These lower and upper bytes pairs of two inputs will form vertical and crosswise  product terms. Each input byte is handled by a separate 8×8 Vedic multiplier to produce sixteen  partial product rows. These partial products rows are then added in a 16-bit carry look ahead adder optimally to generate final product bits. The figure 5 shows the schematic of a 16×16  block designed using 8×8 blocks. The partial products represent the Urdhva vertical [6] and cross  product terms. Then using or and half adder assembly to find the final product. Power dissipation [7] of this multiplier is 0.18 mW and propagation delay is 1.71 nsec. 618 transistors are used in this design.

4.

CONCLUSION

The proposed Vedic multiplier (discussed in section 3) is simulated using Tanner Tool v14.1. The Comparison between proposed multiplier and Booth radix-4 multiplier and the multiplier in [3] is shown in table (2). As from the table this multiplier helps in future to make fast processors. Schematic from S Edit is shown in figure (8). Table (2): Table of design comparison of Multipliers S.No.

Parameters Comparison

of   Paper design

[3] Booth algorithm

Proposed design

1

Delay ( n sec)

37.668

46.740

27.14865

2

Power Dissipation (m Watts)

29.34

151.34

0.1692638

3

No. of Transistors used

4299

7296

14382

Figure (8): Schematic diagram of 16 bit Multiplier using Urdhva Tiryakbhyam Sutra 5.

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[1]

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 power efficient multiplier and square architecture based on ancient Indian Vedic mathematics, www.vedicmathsindia.org. [8]

Vishal Verma and Himanshu Thapliyal , “High Speed Efficient N X N Bit Multiplier 

Based On Ancient Indian Vedic Mathematics”, Proceedings International Conference On VLSI, Las Vegas, June 2003

CHAPETR- 7 FUTURE PLANNING

The development of different circuitry design will take place in following order: S. Nature of Work No.

1. 2. 3. 4. 5.

Multiplier using (UT Sutra) Multiplier using (Nikhilam Sutra) Convolution ALU design DSP design

Duration

4 Month 2 Month

Completed (C)/ Under Process (UP) / To be developed (TD) C UP

2Month 3 Month 4 Month

TD TD TD

CHAPTER 8 REFRENCES [1]

Mr. Abhishek Gupta, Mr. Amit Jain, Mr. Anand Var dhan Bhalla, Mr. Utsav Malviya “ Design Of High

Speed FFT Processor Using Vedic Multiplication Technique “ International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012,  pp.1501-1504

[2]

Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, Vedic Mathematics: Sixteen Simple

[3]

 Mathematical Formulae from the Veda. Delhi (1965).

[4]

Williams, K., Discover Vedic Mathematics. Skelmersdale: Inspiration Books (1984).

[5]

Jagadeshwar Rao M, Sanjay Dubey , “A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits”IOSR Journal of Electronics and Communication Engineering  (IOSRJECE) ISSN: 2278-2834, ISBN No: 2278-8735 Volume 3, Issue 1 (Sep-Oct 2012), PP 07-11 www.iosrjournals.org 

[6]

Anuja George, “A Novel Design of Low Power, High Speed SAMM and its FPGA Implementation”  International Journal of Computer Applications (0975 – 8887) Volume 43– No.4, April 2012.

[7]

K. Neelima, M. Bharathi, “ An Algorithm for FPGA based Implementation of Variable Precision MAC unit for High Performance Digital FIR Filters”, International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 6, November- December 2012,  pp.670-673.

[8]

Jai Skand Tripathi, Priya Keerti Tripathi,Deepti Shakti Tripathi, “An Efficient Design of Vedic Multiplier using New Encoding Scheme”  International Journal of Computer Applications (0975 –  8887) Volume 53– No.11, September 2012

[9]

R.Bhaskar, Ganapathi Hegde, P.R.Vaya, “An efficient hardware model for RSA Encryption system using Vedic mathematics”, International Conference on Communication Technology and System Design 2011

[10]

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Rutuparna Panda, “An Improved Squaring Circuit for Binary (IJACSA) International Journal of Advanced Computer Science and

 Applications, Vol. 3, No.2, 2012 [11]

Abhishek Gupta, “Arithmetic Unit Implementation Using Delay Optimized Vedic Multiplier with BIST Capability” International Journal of Engineering and Innovative  Technology (IJEIT) Volume 1, Issue 5, May 2012

[12]

More T.V. and Panat A.R., “Comparative Study of Pipelined Reconfigurable FFT

Processor”,

International Journal of Knowledge Engineering ISSN: 0976-5816 & E-ISSN: 0976-5824, Volume 3, Issue 1, 2012, pp.-107-110 [13]

Aniruddha Kanhe, Shishir Kumar Das and Ankit Kumar Singh, “DESIGN AND IMPLEMENTATION OF LOW POWER MULTIPLIER USING VEDIC MULTIPLICATION TECHNIQUE”, International Journal of Computer Science and Communication Vol. 3, No. 1, January-June 2012, pp. 131-132

[14]

Pushpalata Verma, “ Design of 4x4 bit Vedic Multiplier using EDA Tool”,  International Journal of  Computer Applications (0975 – 888) Volume 48– No.20, June 2012

[15]

Mr. Abhishek Gupta, Mr. Amit Jain, Mr. Anand Vardhan Bhalla, Mr. Utsav Malviya , “Design Of High Speed FFT Processor Using Vedic Multiplication Technique” International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, SeptemberOctober 2012, pp.1501-1504.

[16]

G.Ganesh Kumar, V.Charishma, “Design of High Speed Vedic Multiplier using Vedic Mathematic Techniques”, International Journal of Scientific and Research Publications, Volume 2, Issue 3, March 2012 1 ISSN 2250-3153.

[17]

Shylashree.N, D. Venkata Narayana Reddy, V. Sridhar, “Efficient Implementation of Scalar  Multiplication for Elliptic Curve Cryptography using Ancient Indian Vedic Mathematics over  GF ( p)”,  International Journal of Computer Applications (0975 – 8887) Volume 49– No.7, July 2012.

[18]

Mr. Abhishek Gupta, Mr. Utsav Malviya, Prof. Vinod Kapse, “A Novel Approach to Design High Speed Arithmetic Logic Unit Based On Ancient Vedic Multiplication Technique” International Journal of  Modern Engineering Research (IJMER) www.ijmer.com Vol.2, Issue.4, July-Aug 2012 pp-2695-2698 ISSN: 2249-6645

[19]  L. Sriraman, T.N. Prabakar, “FPGA implementation of high performance Multiplier using squarer ”,

 International Journal of Advanced Computer Engineering & Architecture Vol. 2 No. 2 (June-December, 2012). [20]

D.Kishore Kumar, A.Rajakumari, “Modified Architecture of Vedic Multiplier for High Speed Applications”, International Journal of Engineering Research & Technology (IJERT) Vol. 1 Issue 6, August – 2012 ISSN: 2278-0181

[21]

Rana Mukherji, Amit Kumar Chatterjee, Manishita Das, “Implementation of an efficient multiplier  architecture based on ancient Indian Vedic mathematics using SystemC” KIST Journal of Science and TechnologyVolume 1 Number 1 2011 pp. 47-57 ISSN 2225 -8639.

[22]

Sree Nivas A, Kayalvizhi N, “Implementation of Power Efficient Vedic Multiplier”  International   Journal of Computer Applications (0975 – 8887) Volume 43– No.16, April 2012.

[23]

Piyush S. Kasat et al. “Multiplication Algorithms for VLSI – A Review”, International Journal on Computer Science and Engineering (IJCSE) ISSN : 0975-3397 Vol. 4 No. 11 Nov 2012 pp 1761-1765.

[24]  Neelima Koppala, Rohit Sreerama, Paidi Satish, “Performance Comparison of Fast Multipliers

Implemented on Variable Precision Floating Point Multiplication Algorithm”,  International Journal of  Computer Applications in Engineering Sciences [VOL II, ISSUE II, JUNE 2012, ISSN: 2231-4946 [25]

Varsharani V. Haibatpure, Prabha S. Kasliwal,, B.P. Patil, “Performance Evaluation of Proposed Vedic Multiplier in Microwind”, International Journal of Communication Engineering Applications-IJCEA http://technicaljournals.org ISSN: 2230-8520; e-ISSN: 2230-8539 Vol 03, Issue 03; July 2012 pp 498502

[26]

Sudhanshu Mishra, Manoranjan Pradhan, “ Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier”  International Journal of  Computer Applications (0975 – 8887) Volume 41– No.9, March 2012

[27]

Soma BhanuTej, “Vedic Algorithms to develop green chips for future”, International Journal of Systems , Algorithms & Applications, Volume 2, Issue ICAEM12, February 2012, ISSN Online: 2277-2677