4706－DS00－R BCM4706 Advance Data Sheet NDA Clear

Advance Data Sheet

BCM4706 Communications Processor with Network Acceleration Hardware GENERAL DESCRIPTION

FEATURES

The Broadcom® BCM4706 processor is a communications device targeted for wireless access points and routers.

• Advanc Advanced ed MIPS32 MIPS32 74K 74K Core Core - 32 KB KB I-ca I-cach che, e, 32 32 KB D-ca D-cach che e - BCM47 BCM4706 06 CPU runs runs at 600 MHz/ MHz/120 1200 0 DMIPs DMIPs • On-chip On-chip SoC – RAM™ provide providess low latency latency read/ read/ write access to improve system performance • Advanc Advanced ed Gigab Gigabit it Ether Ethernet net MAC MAC • MII/RGM MII/RGMII/ II/SGM SGMII II interf interface ace • Supports Supports extern external al GbE GbE switch switch (such as BCM53115/BCM53125) • Supports Supports externa externall 10/100 10/100 switch switch (such (such as BCM5325E) • One One USB USB 2.0 2.0 hos hostt port port • 16-bit/ 16-bit/32-bi 32-bitt DDR2 300 300 MHz memory interface interface • Suppor Supports ts seria seriall or parall parallel el Flash Flash • Dual PCI PCI Express Express interf interface ace complia compliant nt with with PCI Express base specification revision 1.1 • UART/MDIO UART/MDIO/SPI/J /SPI/JT TAG interfac interface, e, up to 16 GPIOs GPIOs 8 • I S audio/TDM voice interfaces • BCM47 BCM4706 06 pack package age:: 23 23 mm × 23 mm, 484-pin PBGA

At the center of the device is a high-performance 600 MHz MIPS32® 74K™ core with a 32 KB four-way four-way set associative instruction cache, a 32 KB four-way set associative data cache, and a 64-entry translation lookaside buffer (TLB). Enhanced CPU memory subsystem subsystem architecture provides increased system performance. The device uses state-of-the-art, state-of-the-art, low power, and low leakage 65 nm LP technology. The BCM4706 integrates several peripheral interfaces including Gigabit Ethernet MACs, USB 2.0, PCI Express®, serial and parallel Flash, DDR memory memor y, and audio/voice TDM subsystem. subsystem. Various common I/ O controllers are also integrated. These I/O controllers include JTAG, UART, MDIO, GPIO, and SPI.

RGMII or MII 2.5 Gbps

MIPS32 Core (600 MHz)

DDR2 Memory Controller

2.5 Gbps

480 Mbps SerDes

EJTAG I-Cache 32 KB

D-Cache 32 KB

SGMII/ SerDes

SerDes

SerDes

USB Phy

PCle 1x1

PCle 1x1

USB 2.0 Host

GMAC

GMAC

Parser/FP

Parser/FP

DMA

DMA

CPU Local Bus SoC-RAM (512 KB)

System Bus

System Bus TDM Peripheral Peripheral Interface

GPIO

Serial Flash

Parallel Flash 8b/16b

SPI

I2C

UART /I2C

UART I8S/TDM 2 VOIP Channels or 8 Audio Channels

Figure 1: Functional Block Diagram 4706-DS00-R 5300 Calif alifo ornia Avenue • Irvi rvine, CA 92617 617 • Phone: 949-9 9-926-50 -5000 • Fax: 949-926 -926--5203 203 4/12/2011 DXKOG

Jun June 02, 2010 010

Revision History Revision

Date

Change Description

4706-DS00-R

06/02/10

Initial release

Broadcom Corporation 5300 California Avenue Irvine, CA 92617 © 2010 by Broadcom Corporation All rights reserved Printed in the U.S.A. Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/ or the EU. Any other trademarks or trade names mentioned are the property of t heir respective owners. This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, management, or other high risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-IS", WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. 4/12/2011 DXKOG

BCM4706 Advance Data Sheet

Table of Contents

Table of Contents Section 1: Functional Description ........................... ....................................... .......................... ......................... ......................... ...................... ........ 9 Overview.........................................................................................................................................................9 Overview .........................................................................................................................................................9 MIPS Core .......................................................................................................................................................9 Reset ...............................................................................................................................................................9 Crystal Oscillator and Clock Generator ..........................................................................................................9 DDR2 SDRAM Interface ................................................................................................................................10 USB 2.0 Host Controllers ..............................................................................................................................10 PCI Express Interface ....................................................................................................................................10 Transaction Layer Interface .................... .............................. ................... ................... ..................... .................... ................... .................... ......................... ........................ ...........11 ..11 Data Link Layer...................... Layer............................... ................... .................... .................. .................. .................... ................... .................. ................... .......................... .......................... ............11 ..11 Physical Layer...................... Layer................................ .................... .................... .................. .................. .................... ................... ................... .................... .......................... .......................... ............12 ..12 Logical Subblock.................. Subblock............................ .................... .................... ................... ................... .................... ................... ................... .................... ........................... ...........................12 ..........12 Scrambler/Descrambler............................ Scrambler/Descrambler.................. .................... ................... ................... .................... .................... ................... ................... ......................... .........................12 ..........12 8B/10B Encoder/Decoder ................... ............................ .................. ................... ................... ................... .................... .................. .................. .................... ........................12 ..............12 Elastic FIFO........ FIFO .................. ..................... ................... .................. ..................... ................... .................. ..................... ................... .................. .......................... .......................... ................... ..........1 .12 2 Electrical Subblock ................... ............................ .................... ..................... .................... ................... ................... .................... ................... ................... .......................... ......................13 ......13 Configuration Space.......................... Space.................................... .................... .................... ................... ................... .................... ................... ................... .......................... .......................13 .......13 10/100/1000 Ethernet MAC Controller .......................................................................................................13 Flash Interface ..............................................................................................................................................13 SPI/UART/GPIO Interface.............................................................................................................................14 Interface .............................................................................................................................14 I8S/TDM Interface ........................................................................................................................................14

Section 2: Hardware Signal Descriptions................................... Descriptions................................................. ............................ ......................... ........... 15 BCM4706 Pin Tables .....................................................................................................................................21 BCM4706 Ballmap ........................................................................................................................................27

Section 3: Electrical Characteristics............ Characteristics......................... ........................... ............................ ............................. ............................ ............... 28 Absolute Maximum Ratings .........................................................................................................................28 Recommended Operating Conditions and DC Characteristics ....................................................................29 Core and I/O Power Sequencing Requirements ..........................................................................................30 DDR2 SDRAM Memory Interface DC Characteristics ..................................................................................31 USB Host Interface DC Characteristics .........................................................................................................31 PCIe DC Characteristics.................................................................................................................................33 Characteristics .................................................................................................................................33 1G SGMII/SerDes Port Signals......................................................................................................................33 Signals ......................................................................................................................33 Standard 3.3V Signals ...................................................................................................................................34 Standard 2.5V Signals ...................................................................................................................................34

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Table of Contents

XTAL Oscillator Interface ..............................................................................................................................34

Section 4: Timing Characteristics ..................................................................................... 35 Reset and Clock Timing ................................................................................................................................35 Parallel Flash Timing.....................................................................................................................................36 Parallel Flash READ Timing.....................................................................................................................36 Parallel Flash WRITE Timing...................................................................................................................37 Serial Flash Timing (ST Micro-compatible Device) ......................................................................................38 DDR2 SDRAM AC Timing Characteristics .....................................................................................................39 USB Host Interface AC Timing Characteristics .............................................................................................40 PCIe Interface Timing ...................................................................................................................................41 PCIe_REFCLKP/N Timing ........................................................................................................................41 MII Interface Timing .....................................................................................................................................43 MII Input Timing.....................................................................................................................................43 MII Output Timing..................................................................................................................................44 RGMII Interface Timing ................................................................................................................................45 RGMII Output Timing (Normal Mode) ...................................................................................................45 RGMII Output Timing (Delayed Mode) ..................................................................................................46 RGMII Input Timing (Normal Mode) ......................................................................................................47 RGMII Input Timing (Delayed Mode) .....................................................................................................48 SGMII/SerDes Serial Interface......................................................................................................................49 Serial Interface Output Timing...............................................................................................................49 Serial Interface Input Timing..................................................................................................................50 I8S/TDM Audio/Video AC Specification ......................................................................................................51 JTAG Interface ..............................................................................................................................................52 MDC/MDIO Master Interface ......................................................................................................................53 SPI Master Interface .....................................................................................................................................54 Timing Parameters for CPHA=0 .............................................................................................................54 Timing Parameters for CPHA=1 .............................................................................................................55

Section 5: Thermal Specifications .................................................................................... 56 BCM4706.......................................................................................................................................................56 BCM4706 Thermal Specifications Without External Heatsink at 70°C ..................................................56 BCM4706 Thermal Specifications with External Heatsink at 70°C.........................................................57 BCM4706 Thermal Specifications Without External Heatsink at 85°C ..................................................58 BCM4706 Thermal Specifications with External Heatsink at 85°C.........................................................59

Section 6: Mechanical Information .................................................................................. 60 BCM4706.......................................................................................................................................................60

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Table of Contents

Section 7: Ordering Information ...................................................................................... 61

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List of Figures

List of Figures Figure 1: Functional Block Diagram....................................................................................................................1 Figure 2: PCI Express Layer Model ...................................................................................................................11 Figure 3: BCM4706 Ballmap—Top View...........................................................................................................27 Figure 4: Power Supply Sequencing .................................................................................................................30 Figure 5: Reset and Clock Timing......................................................................................................................35 Figure 6: Parallel Flash READ Timing Diagram..................................................................................................36 Figure 7: Parallel Flash WRITE Timing Diagram................................................................................................37 Figure 8: Serial Flash Timing Diagram ..............................................................................................................38 Figure 9: PCIe_REFCLKP/N Timing....................................................................................................................41 Figure 10: PCIe[1:0]_RDP/N Timing..................................................................................................................41 Figure 11: PCIe[1:0]_TDP/N Timing..................................................................................................................42 Figure 12: MII Input Timing..............................................................................................................................43 Figure 13: MII Output Timing ...........................................................................................................................44 Figure 14: RGMII Output Timing (Normal Mode).............................................................................................45 Figure 15: RGMII Output Timing (Delayed Mode)............................................................................................46 Figure 16: RGMII Input Timing (Normal Mode)................................................................................................47 Figure 17: RGMII Input Timing (Delayed Mode)...............................................................................................48 Figure 18: Serial Interface Output Timing ........................................................................................................49 Figure 19: Serial Interface Input Timing...........................................................................................................50 Figure 20: IXS Transmitter Timing....................................................................................................................51 Figure 21: IXS Receiver Timing .........................................................................................................................51 Figure 22: JTAG Interface .................................................................................................................................52 Figure 23: MDC/MDIO Master Interface..........................................................................................................53 Figure 24: SPI Master Interface: Timing Parameters for CPHA=0....................................................................54 Figure 25: SPI Master Interface: Timing Parameters for CPHA=1....................................................................55 Figure 26: BCM4706 Mechanical Information .................................................................................................60

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List of Tables

List of Tables Table 1: Hardware Signals ................................................................................................................................ 15 Table 2: BCM4706 Sorted by Pin Location ....................................................................................................... 21 Table 3: BCM4706 Sorted by Signal Name....................................................................................................... 24 Table 4: Absolute Maximum Ratings................................................................................................................ 28 Table 5: Recommended Operating Conditions ................................................................................................ 29 Table 6: Total Power and Supply Current......................................................................................................... 29 Table 7: DC Characteristics for DDR2 SDRAM Interface................................................................................... 31 Table 8: USB Host Interface DC Characteristics................................................................................................ 31 Table 9: USB 1.1 Electrical and Timing Parameters.......................................................................................... 32 Table 10: PCIe DC Characteristics..................................................................................................................... 33 Table 11: 1G SGMII/SerDes Port Signals .......................................................................................................... 33 Table 12: Standard 3.3V Signals ....................................................................................................................... 34 Table 13: Standard 2.5V Signals ....................................................................................................................... 34 Table 14: XTAL Oscillator Interface .................................................................................................................. 34 Table 15: Reset and Clock Timing ..................................................................................................................... 35 Table 16: Parallel Flash READ Timing ............................................................................................................... 36 Table 17: Parallel Flash WRITE Timing.............................................................................................................. 37 Table 18: Serial Flash Timing ............................................................................................................................ 38 Table 19: AC Characteristics for DDR SDRAM Interface ................................................................................... 39 Table 20: USB 2.0 Host Interfaces Timing Parameters ..................................................................................... 40 Table 21: USB 1.1 Timing Parameters .............................................................................................................. 40 Table 22: PCIe_REFCLKP/N Timing ................................................................................................................... 41 Table 23: PCIe[1:0]_RDP/N Timing................................................................................................................... 42 Table 24: PCIe[1:0]_TDP/N Timing ................................................................................................................... 42 Table 25: MII Input Timing ............................................................................................................................... 43 Table 26: MII Output Timing ............................................................................................................................ 44 Table 27: RGMII Output Timing (Normal Mode) .............................................................................................. 45 Table 28: RGMII Output Timing (Delayed Mode) ............................................................................................. 46 Table 29: RGMII Input Timing (Normal Mode)................................................................................................. 47 Table 30: RGMII Input Timing (Delayed Mode)................................................................................................ 48 Table 31: Serial Interface Output Timing ......................................................................................................... 49 Table 32: Serial Interface Input Timing ............................................................................................................ 50 Table 33: IXS Receiver Timing.................................................................................................. ......................... 51 Table 34: JTAG Interface................................................................................................................................... 52 Table 35: MDC/MDIO Master Interface ........................................................................................................... 53

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List of Tables

Table 36: SPI Master Interface ......................................................................................................................... 54 Table 37: Timing Parameters for CPHA=1 ........................................................................................................ 55 Table 38: Package for 2s2p Board, TA = 70°C, P = 2.7W from Simulation.............................................................................................. 56 Table 39: BCM4706 Thermal Specifications Without External Heatsink at 70°C ............................................. 56 Table 40: Package with 30x30x25 mm External Heat Sink on 2s2p Board, TA = 70°C, P = 2.7W from Simulation.............................................................................................. 57 Table 41: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 70°C............................ 57 Table 42: Package for 2s2p Board, TA = 85° C, P = 2.7 W from Simulation ............................................................................................ 58 Table 43: BCM4706 Thermal Specifications Without External Heatsink at 85°C ............................................. 58 Table 44: Package with 30x30x25 mm External Heat Sink on 2s2p Board, TA = 85°C, P = 2.7W from Simulation.............................................................................................. 59 Table 45: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 85°C............................ 59 Table 46: Ordering Information ....................................................................................................................... 61

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Functional Description

Section 1: Functional Description Overview The Broadcom® BCM4706 is a family of processors optimized for power and cost without compromising performance. Integrating a high-performance 600 MHz MIPS32® 74KTM core with a 32 KB four-way set associative instruction cache, a 32 KB four-way set associative data cache, and a 6 4-entry TLB, the BCM4706 offers significant performance improvements in both transfer rates and CPU utilization. Flexible support for a variety of system bus interfaces is provided including Gigabit Ethernet MACs, an audio/ voice TDM unit, a USB 2.0 host port, PCI Express® (X1 lane), 16-bit/32-bit DDR2 300 MHz memory control, serial Flash port, and 16-bit parallel Flash port. There are 16 GPIOs on the BCM4706 processor. All inputs can be used to generate processor interrupts.

MIPS Core The chip integrates an advanced 600 MHz MIPS32 74K core with a 32 KB four-way set associative I-cache and a 32 KB four-way set associative D-Cache. The MIPS32 74K core has an integrated 32 × 32-bit single-cycle multiply/accumulate block running at CPU core speed, providing additional signal or media processing capabilities. The integrated MMU with a 64-entry TLB block is included, allowing support for common multithreaded real-time operating systems (RTOS) such as the standard Linux® distribution.

Reset A power-on or hard reset is initiated by an active low reset pulse on the RESET_N Schmitt-triggered input pin. The reset signal has a minimum required low pulse duration to guarantee that a sufficiently long reset is applied to all internal circuits, including integrated PHYs (see Table 15: “Reset and Clock Timing,” on page 35). The initialization process loads all pin configurable modes, resets all internal processes, and puts the device in the idle state. During initialization, the clock source input signal must be active, and the 3.3V power supply to the device must be stable.

Crystal Oscillator and Clock Generator A typical BCM4706-based platform requires only a single crystal to clock the entire device. Several internal PLLs are driven by the oscillator and generate the various clocks, including the clock for the 10/100/1000 MAC core and the MIPS32 74K, DDR2 SDRAM, PCIe, UART, and USB 2.0 host controllers.

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DDR2 SDRAM Interface

DDR2 SDRAM Interface The integrated DDR2 controller has on-chip serial termination resistors on the address, data and control signals, except DDR clocks. The differential clock pair needs external serial termination resistors. Additionally, VREF pin must be set to half of the DDR_OVDD_1P8 voltage. This can be accomplished by using two equal value resistors to divide the DDR_OVDD_1P8 voltage.

USB 2.0 Host Controllers The BCM4706 integrates a USB 2.0 host controller that supports high-speed USB 2.0 ports. It is also backward compatible with full-speed and low-speed USB 1 .1 devices. Each host port has a dedicated overcurrent input to notify the OS or driver to take appropriate action. Individual port power control is also available.

PCI Express Interface The PCI Express (PCIe) core on the BCM4706 is a high performance serial I/O interconnect that is protocol compliant and electrically compatible with the PCI Express Base Specification v1.1. This core contains all the necessary blocks, including logical and electrical functional subblocks, to perform PCIe functionality and maintain high-speed links using existing PCI system configuration software implementations without modification. The PCIe core is organized in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as shown in Figure 2. A configuration or link management block is provided for enumerating the PCIe configuration space and supporting generation and reception of System Management Messages by communicating with PCIe layers. Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host and BCM4706 device. The transmit side processes outbound packets while the receive side processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to indicate the packet type and any other optional fields.

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PCI Express Interface

HW/SW Interface

HW/SW Interface

Transaction Layer

Transaction Layer

Data Link Layer

Data Link Layer

Physical Layer

Physical Layer

Logical Subblock

Logical Subblock

Electrical Subblock

Electrical Subblock

TX

TX

RX

RX

Figure 2: PCI Express Layer Model

Transaction Layer Interface The PCIe core employs a packet-based protocol to transfer data between the host and BCM4706 device, delivering new levels of performance and features. The upper layer of the PCIe is the Transaction Layer, which is primarily responsible for assembly and disassembly of transaction layer packets (TLPs). TLP structure contains header, data payload, and end-to-end CRC (ECRC) fields, which are used to communicate transactions, such as read and write requests and other events. A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication between devices with credit-based flow control of TLP, which eliminates wasted link bandwidth due to retries.

Data Link Layer The data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its primary responsibility is to provide a reliable, efficient mechanism for the exchange of TLPs between two directly connected components on the link. Services provided by the data link layer include data exchange, initialization, error detection and correction, and retry services. Data link layer packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the mechanism used to transfer link management information between data link layers of the two directly connected components on the link, including TLP acknowledgement, power management, and flow control.

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PCI Express Interface

Physical Layer The physical layer of the PCIe provides a handshake mechanism between the data link layer and the high-speed signaling used for Link data interchange. This layer is divided into the logical and electrical functional subblocks. Both subblocks have dedicated transmit and receive units that allow for point-to-point communication between the host and PCIe device. The transmit section prepares outgoing information passed from the data link layer for transmission, and the receiver section identifies and prepares received information before passing it to the data link layer. This process involves link initialization, configuration, scrambler, and data conversion into a specific format.

Logical Subblock The logical subblock’s primary functions are to prepare outgoing data from the data link layer for transmission and identify received data before passing it to the data link layer.

Scrambler/Descrambler This PCIe PHY component generates a pseudo-random sequence for scrambling of data bytes and the idle sequence. On the transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the receive side, descrambling is applied to characters after 8b/10b decoding. Scrambling may be disabled in polling and recovery for testing and debugging purposes.

8B/10B Encoder/Decoder The PCIe core on the BCM4706 uses an 8b/10b encoder/decoder scheme to provide DC balancing, clock synchronization and data recovery, and error detection. The transmission code is specified in ANSI X3.2301994, clause 11 and in IEEE 802.3z, 36.2.4. Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a 6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when to encode one of the twelve Special Symbols included in the 8b/10b transmission code. These code groups are concatenated to form a 10-bit Symbol, which is then transmitted serially. Special Symbols are used for link management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and easily distinguished.

Elastic FIFO An elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit clock domain and the receive clock domain, with worst case clock frequency specified at 600 ppm tolerance. As a result, the transmit and receive clocks can shift one clock every 1666 c locks. In addition, the FIFO adaptively adjusts the elastic level based on the relative frequency difference of the write and read clock. This technique reduces the elastic FIFO size and the average receiver latency by half.

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10/100/1000 Ethernet MAC Controller

Electrical Subblock The high-speed signals utilize the common mode logic (CML) signaling interface with on-chip termination and deemphasis for best in class signal integrity. A deemphasis technique is employed to reduce the effects of intersymbol interference (ISI) due to the interconnect by optimizing voltage and timing margins for worst case channel loss. This results in a maximally open “eye” at the detection point, thereby allowing the receiver to receive data with an acceptable bit-error rate (BER). To further minimize ISI, multiple bits of the same polarity that are output in succession are dee mphasized. Subsequent same bits are reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for maximum interoperability while minimizing the complexity of controlling the deemphasis values. The highspeed interface requires AC coupling on the transmit side to eliminate the DC common mode voltage from the receiver. The range of AC capacitance allowed is 75 nF to 200 nF.

Configuration Space The PCIe function in the BCM4706 implements the configuration space as defined in the PCI Express Base Specification v1.1.

10/100/1000 Ethernet MAC Controller The BCM4706 integrates a high performance yet flexible Ethernet MAC controller. GMAC port 0 of the BCM4706 supports the following interfaces through strap pin settings: • RGMII: 10/100/1000 Mbps mode • MII: 10/100 Mbps mode The BCM4706 supports a second GMAC with SGMII interface in 10/100/1000 Mbps mode. These interfaces can work with a wide variety of Ethernet PHYs and switches. In RGMII mode, the bus signals operate at 2.5V, with the exception that the MDIO and MDC pins operate at 3.3V. All the Ethernet MAC controller output pins have built-in series termination so external termination resistors are not required.

Flash Interface An on-chip, 16-bit external bus interface (EBI) provides the following connectivity options: • 16-bit NOR or NAND flash memory. BCM4706 supports up to 256 MB. • Serial Flash (ST-compatible four-pin SPI interface) The BCM4706 has two Flash chip select pins so it can support up to two Flash devices in any of the combinations in the following list: • One parallel Flash • One serial Flash

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SPI/UART/GPIO Interface

• Two parallel Flash • Two serial Flash • One serial Flash + one parallel Flash (either the serial Flash or parallel Flash can be the boot device) • One serial Flash + NAND Flash (serial Flash must be the boot device to set up the on-chip NAND Flash controller before it is accessed) The BCM4706 has 16-bit parallel Flash data pins and supports either an 8-bit or 16-bit parallel Flash through strap-pin settings when the parallel Flash is the boot device. However, byte-mode configuration should not be used when 16-bit parallel Flash is used. When the BCM4706 is used in a configuration with two parallel Flash devices, mixing of 8-bit and 1 6-bit parallel Flash memory is not supported.

SPI/UART/GPIO Interface The BCM4706 supports one dedicated two-wire UART interface (UART_TX and UART_RX pins). It can support one additional UART interface by sharing GPIO pins. The BCM4706 also supports one SPI master. The pin sharing is enabled by software with the following configuration: • GPIO[3:0] and GPIO[9:8] can be configured as the SPI master interface. • GPIO[7:6] can be configured as the UART interface. There are 16 3.3V GPIO pins on the BCM4706. These pins can be used to connect to various external devices. Upon power-up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register.

I8S/TDM Interface The BCM4706 integrates a Voice/Audio TDM subsystem core that provides support for up to two full-duplex voice channel conversations or up to eight audio channels for stereo or multichannel music/sound acquisition or playback applications. The BCM4706 supports various flavors of TDM interface operations to work with external A/D or D/A devices. The following list contains the possible channel combinations: • Audio/voice output only: one three-wire I8S/TDM interface • Audio/voice input only: one three-wire I8S/TDM interface • Full-duplex audio/voice: two three-wire I8S/TDM interfaces or one four-wire TDM interface

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Hardware Signal Descriptions

Section 2: Hardware Signal Descriptions The section describes the BCM4706 hardware signals and uses the following conventions: • I = Input signal • O = Output signal • I/O = Bidirectional signal • IPD = Input Signal with internal pull-down • IPU = Input Signal with internal pull-up Table 1: Hardware Signals Pin Names

I/O

V

Pin Description

DDR_SDRAM_ADDR[14:0] O

1.8V

DDR2 address bus

DDR_SDRAM_BA[2:0]

O

1.8V

DDR2 bank address

DDR_SDRAM_CAS

O

1.8V

DDR2 column address select

DDR_SDRAM_CKE

O

1.8V

DDR2 clock enable

DDR_SDRAM_CS_N

O

1.8V

DDR2 chip select

DDR_SDRAM_ODT

O

1.8V

DDR2 on-die termination

DDR_SDRAM_RAS

O

1.8V

DDR2 row address select

DDR_SDRAM_REF

I

0.9V

0.9V (DDR_OVDD_1P8 divided by two) DDR2 reference voltage

DDR_SDRAM_WE

O

1.8V

DDR2 write enable

DDR_SDRAM_ZQ

I/O

–

Output impedance calibration. This pin should be attached to a 240Ω resister to VSS for impedance calibration.

DDR_SDRAM_CK0P/N

O

1.8V

DDR2 differential clock pair for byte lane 1 and 0

DDR_SDRAM_CK2P/N

O

1.8V

DDR2 differential clock pair for byte lane 3 and 2

DDR_SDRAM_DM[3:0]

O

1.8V

DDR2 data mask

DDR_SDRAM_DQSP[3:0]

I/O

1.8V

DDR2 differential pair data strobe for byte lane 3 to 0

DDR_SDRAM_DQSN[3:0] I/O

1.8V

DDR2 differential pair data strobe for byte lane 3 to 0

DDR_SDRAM_DQ[31:0]

1.8V

DDR2 data bus

DDR SDRAM Interface

I/O

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Table 1: Hardware Signals (Cont.) Pin Names

I/O

V

Pin Description

Parallel Flash Interface/Strap Pins Note: Strap pin values are latched during reset, after reset the pin behaves as a Flash address pin. FLASH_ADDR[26:0]

IPD/O

3.3V

When connecting to NAND Flash: • FLASH_ADDR0: NAND Flash CLE (command latch enable) output. • FLASH_ADDR1: NAND Flash ALE (address latch enable) output. • FLASH_ADDR2: NAND Flash WP# (write protect) output (active low). • FLASH_ADDR21: NAND Flash R/B# (ready/not busy) input with internal pullup. • FLASH_ADDR[4:20], [22:25]: Unused.

FLASH_ADDR6/ MIPS_EJTAG_MODE

IPD/O

3.3V

MIPS EJTAG mode enable: • 0: General JTAG interface • 1: MIPS EJTAG interface (connect to ICE)

FLASH_ADDR8/ GMAC_VSEL

IPD/O

3.3V

Ethernet interface voltage level select: • Set this pin low to configure port 0 GMAC interface to operate in 2.5V RGMII. • Set this pin high for 3.3V MII.

FLASH_ADDR12/PCIe_DIS IPD/O

3.3V

PCIe port 1 disable: • 0: PCIe port 1 is enabled. • 1: PCIe port 1 is disabled for power saving.

FLASH_ADDR16/ PCIe_REFCLKSEL

IPD/O

3.3V

PCIe SerDes reference clock select: • 0: Use internal PLL to generate 100 MHz clock. • 1: Use the external 100 MHz differential clock source, through PCIe_REFCLKP/N pins.

FLASH_ADDR17/ BOOT_FLASH_TYPE

IPD/O 3.3V

Boot Flash type, depending on SFLASH_BOOT setting, this pin specifies the parallel Flash or serial Flash boot device type: If (SFLASH_BOOT == 0): • 0: 8-bit parallel Flash • 1: 16-bit parallel Flash If (SFLASH_BOOT == 1): • 0: ST-compatible serial Flash • 1: Atmel® serial Flash

FLASH_ADDR18/ SFLASH_BOOT

IPD/O 3.3V

Specifies using parallel Flash or serial Flash as the boot device: • 0: Boot device is a parallel Flash • 1: Boot device is a serial Flash

FLASH_ADDR19/ MIPS_ENDIAN

IPD/O

MIPS endian setting: • 0: Little endian • 1: Big endian

3.3V

BROADCOM ®

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I/O

V

Pin Description

FLASH_ADDR22/ TX_DELAY_MODE

IPD/O

3.3V

GMAC port 0 transmit interface 2 ns delay mode: • 0: No delay • 1: Enable 2 ns delay

FLASH_ADDR23/ RX_DELAY_MODE

IPD/O

3.3V

GMAC port 0 receive interface 2 ns delay mode: • 0: No delay • 1: Enable 2 ns delay

FLASH_ADDR[25:24]/ GMAC_MODE

IPD/O

3.3V

GMAC port 0 interface mode: • 2'b01: MII mode • 2'b1x: RGMII mode

FLASH_CS0_N

O

3.3V

Chip select for the boot Flash (active low). Can be connected to serial or parallel Flash

FLASH_CS1_N

O

3.3V

Chip select for second Flash (active low). Can be connected to serial, parallel, or NAND Flash

FLASH_DATA[15:0]

I/O

3.3V

Parallel/NAND Flash data bus. External pull downs are required when unused.

FLASH_OE_N

O

3.3V

Output enable (active low). NAND Flash RE# (read enable) output (active low)

FLASH_WE_N

O

3.3V

Write enable (active low). NAND Flash WE# (write enable) output (active low)

Ethernet Interface (RGMII/MII) Port 0 Note: RGMII—10/100/1000 Mbps; MII—10/100 Mbps only GMAC_COL

IPD

2.5V/3.3V

Collision detect

GMAC_CRS

IPD

2.5V/3.3V

Carrier sense

GMAC_RXCLK

IPD/O

2.5V/3.3V

Receive clock

GMAC_RXD[3:0]

IPD

2.5V/3.3V

Receive data

GMAC_RXDV

IPD

2.5V/3.3V

Receive data valid

GMAC_RXER

IPD

2.5V/3.3V

Receive error

GMAC_TXCLK

IPD/O

2.5V/3.3V

Transmit clock

GMAC_TXD[3:0]

O

2.5V/3.3V

Transmit data

GMAC_TXEN

O

2.5V/3.3V

Transmit enable

GMAC_TXER

O

2.5V/3.3V

Transmit error

Port 1 Note: SGMII—10/100/1000 Mbps SGMII_TXDP

O

1.2V

SGMII SerDes transmit data

SGMII_TXDN

O

1.2V

SGMII SerDes transmit data

SGMII_RXDP

I

1.2V

SGMII SerDes receive data

SGMII_RXDN

I

1.2V

SGMII SerDes receive data

BROADCOM ®

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I/O

V

Pin Description

GPIO/SPI/UART Interfaces (internal PU/PD of GPIOs is user-configurable through register setting) GPIO0/SPI_SCLK

I/O

3.3V

GPIO bit 0 or SPI master clock output

GPIO1/SPI_SS0

I/O

3.3V

GPIO bit 1 or first SPI master select output

GPIO2/SPI_MOSI

I/O

3.3V

GPIO bit 2 or SPI master data output

GPIO3/SPI_MISO

I/O

3.3V

GPIO bit 3 or SPI master data input

GPIO4

I/O

3.3V

GPIO bit 4

GPIO5/

I/O

3.3V

GPIO bit 5

GPIO6/UART_RX2

I/O

3.3V

GPIO bit 6 or 2nd UART receive data input

GPIO7/UART_TX2

I/O

3.3V

GPIO bit 7 or 2nd UART transmit data output

GPIO8/SPI_SS1

I/O

3.3V

GPIO bit 8 or second SPI select

GPIO9/SPI_SS2

I/O

3.3V

GPIO bit 9 or third SPI select

GPIO10/FLASH_CS2_N

I/O

3.3V

GPIO bit 10 or additional chip select

GPIO11/FLASH_CS3_N

I/O

3.3V

GPIO bit 11 or additional chip select

GPIO[12:15]

I/O

3.3V

GPIO bits 12 to 15

JTCK

IPU

3.3V

JTAG clock

JTDI

IPU

3.3V

JTAG data input

JTDO

O

3.3V

JTAG data output

JTMS

IPU

3.3V

JTAG mode select

JTRST

IPU

3.3V

JTAG reset (active low)

MDC

O

3.3V

Management clock

MDIO

IPD/O

3.3V

Management data

PCIe0_RDN

I

1.2V

Negative leg of the differential pair receive serial data on PCIe port 0

PCIe0_RDP

I

1.2V

Positive leg of the differential pair receive serial data on PCIe port 0

PCIe0_TDN

O

1.2V

Negative leg of the differential pair transmit serial data on PCIe port 0

PCIe0_TDP

O

1.2V

Positive leg of the differential pair transmit serial data on PCIe port 0

PCIe0_RST_N

O

1.2V

PCIe port 0 reset (active low)

PCIe1_RDN

I

1.2V

Negative leg of the differential pair receive serial data on PCIe port 1

PCIe1_RDP

I

1.2V

Positive leg of the differential pair receive serial data on PCIe port 1

PCIe1_TDN

O

1.2V

Negative leg of the differential pair transmit serial data on PCIe port 1

JTAG Interface

MIIM Interface

PCIe Interface

BROADCOM ®

June 02, 2010 • 4706-DS00-R

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I/O

V

Pin Description

PCIe1_TDP

O

1.2V

Positive leg of the differential pair transmit serial data on PCIe port 1

PCIe1_RST_N

O

1.2V

PCIe port 1 reset (active low)

PCIe_REFCLKOUTP/N

O

1.2V

100 MHz reference clock output differential pair

PCIe_REFCLKP/N

I

1.2V

100 MHz reference clock input differential pair This is used when FLASH_ADDR16/PCIe_REFCLKSEL pin is enabled.

SFlash_CLK

O

3.3V

Clock output for serial Flash

SFlash_SO

O

3.3V

Data output signal driving serial Flash

SFlash_SI

IPU

3.3V

Data input from serial Flash

TDM0_BITCLK

IPU/O

3.3V

TDM channel 0 bit clock

TDM0_SDIO

IPU/O

3.3V

TDM channel 0 serial data input/output

TDM0_WS

IPU/O

3.3V

TDM channel 0 word select

TDM1_BITCLK

IPU/O

3.3V

TDM channel 1 bit clock

TDM1_SDIO

IPU/O

3.3V

TDM channel 1 serial data input/output

TDM1_WS

IPU/O

3.3V

TDM channel 1 word select

UART_RX

IPU

3.3V

UART receive data

UART_TX

O

3.3V

UART transmit data

USB_DATA_N/P

I/O

1.2V

USB differential pair data

USB_RREF

I/O

1.2V

USB resistance reference. This pin should be connected to an external 4.02 kΩ resistor in parallel with a 100 pF capacitor to ground.

USB_OCD

IPU

3.3V

USB over-current-detect input pin

RESET_N

IPU

3.3V

Chip reset, active low, Schmitt-triggered

XTALI

I

3.3V

25 MHz crystal/oscillator input

XTALO

O

3.3V

Crystal output

OSC_XTAL_SEL

IPD

3.3V

25 MHz oscillator/crystal input clock select, 0V: selects crystal, 3.3V: selects oscillator

NC

–

–

No connect

Serial Flash Interface

I8S/TDM Interface

UART Interface

USB Interface

Miscellaneous Interface

BROADCOM ®

June 02, 2010 • 4706-DS00-R

Page 19 4/12/2011 DXKOG




I/O

V

Pin Description

CORE_DVDD_1P2

–

1.2V

1.2V digital core power

CORE_PLLAVDD_1P2

–

1.2V

1.2V core PLL analog power

MISC1_PLLAVDD_1P2

–

1.2V

1.2V miscellaneous PLL analog power

MISC2_PLLAVDD_1P2

–

1.2V

1.2V miscellaneous PLL analog power

DDR_OVDD_1P8

–

1.8V

1.8V DDR2 and 1.8V I/O power

INT_OVDD_33

–

3.3V

3.3V interface I/O power, including Flash, I8S/TDM, GPIO, MDC, UART, JTAG interfaces, and global clock/reset pins

GMAC_OVDD_25_33

–

2.5V/3.3V

GMAC port 0 power supply, tied to 2.5V for RGMII, 3.3V for MII

PCIe_PLLVDD_1P2

–

1.2V

1.2V PCIe SerDes PLL analog power

PCIe_SDVDD_1P2

–

1.2V

1.2V PCIe SerDes TX/RX analog power

SGMII_PLLAVDD_1P2

–

1.2V

1.2V SGMII SerDes PLL power

SGMII_VDD_1P2

–

1.2V

1.2V SGMII SerDes TX/RX analog power

USB_DVDD_1P2

–

1.2V

1.2V USB PHY PLL digital power

USB_PLLAVDD_1P2

–

1.2V

1.2V USB PHY PLL analog power

USB_AVDD_2P5

–

2.5V

2.5V USB PHY analog power

USB_AVDD_3P3

–

3.3V

3.3V USB PHY analog power

XTAL_PLLAVDD_3P3

–

3.3V

3.3V analog power for XTALI/O

DVSS

–

0V

Ground

PCIe_PLLVSS

–

0V

PCIe SerDes PLL analog ground

PCIe_SDVSS

–

0V

PCIe SerDes analog TX/RX ground

CORE_PLLAVSS

–

0V

Core PLL analog ground

MISC1_PLLAVSS

–

0V

Miscellaneous PLL analog ground

MISC2_PLLAVSS

–

0V

Miscellaneous PLL analog ground

SGMII_PLLAVSS

–

0V

SGMII SerDes PLL ground

SGMII_VSS

–

0V

SGMII SerDes TX/RX ground

USB_AVSS

–

0V

USB PHY ground

Power

Ground

BROADCOM ®

June 02, 2010 • 4706-DS00-R

Page 20 4/12/2011 DXKOG


BCM4706 Pin Tables

BCM4706 Pin Tables Table 2: BCM4706 Sorted by Pin Location Ball Signal

Ball Signal

Ball Signal

Ball Signal

A1

DDR_OVDD_1P8

B16

FLASH_ADDR5

D10

FLASH_DATA1

F1

DDR_SDRAM_DQ24

A2

DDR_SDRAM_DQ30

B17

DVSS

D11

F2

DDR_SDRAM_DQ25

A3

DDR_SDRAM_DQ31

B18

FLASH_WE_N


F3

DDR_SDRAM_DM3

A4

JTRST

B19

UART_TX

D12

FLASH_ADDR20

F4

DVSS

A5

JTMS

B20

MDIO

D13

FLASH_ADDR15

F5

INT_OVDD_33

A6

SFlash_SO

B21

GPIO13

D14

F6

DVSS

A7

FLASH_DATA15

B22

GPIO12

FLASH_ADDR12/ PCIe_DIS

INT_OVDD_33

A8

FLASH_DATA11

DDR_SDRAM_DQSP3

FLASH_ADDR7

F7

C1

D15

DVSS

A9

FLASH_DATA7

DDR_SDRAM_DQSN3

FLASH_ADDR4

F8

C2

D16

INT_OVDD_33

A10

FLASH_DATA3

DDR_OVDD_1P8

NC

F9

C3

D17

DVSS

A11

FLASH_ADDR26

DVSS

INT_OVDD_33

F10

C4

D18

INT_OVDD_33

A12


JTCK

RESET_N

F11

C5

D19

DVSS

DVSS

USB_OCD

F12

C6

D20

INT_OVDD_33


C7

FLASH_DATA14

GPIO9/SPI_SS2

F13

A13

D21

DVSS

A14

FLASH_ADDR14

DVSS

INT_OVDD_33

F14

C8

D22

INT_OVDD_33

A15

FLASH_ADDR10

FLASH_DATA6

DDR_SDRAM_DQ22

F15

C9

E1

DVSS

A16


DVSS

DDR_SDRAM_DQ23

F16

C10

E2

INT_OVDD_33

FLASH_ADDR25/ GMAC_MODE

DDR_SDRAM_DQ27

F17

C11

E3 E4

NC

F18

DVSS

JTDI

GPIO5

DVSS

E5

F19

C12

SFlash_SI

GPIO8/SPI_SS1


E6

F20

C13

E7

FLASH_DATA13

F21

GPIO7/UART_TX2

F22

GPIO2/SPI_MOSI

G1

DDR_OVDD_1P8

G2

DVSS

G3

DDR_OVDD_1P8

G4

DVSS

A17

FLASH_ADDR2

A18

FLASH_OE_N

A19

UART_RX

A20

MDC

C14

DVSS

E8

FLASH_DATA8

A21

GPIO15

C15

FLASH_ADDR9

E9

FLASH_DATA5

A22

GPIO14

C16

DVSS

E10

FLASH_DATA0

B1

DDR_SDRAM_DQ26

C17

FLASH_ADDR1

E11

B2

DVSS

C18

FLASH_CS0_N


B3

DVSS

C19

INT_OVDD_33

E12

G5

DVSS

B4

DVSS

C20

DVSS


G6

DVSS

B5

DVSS

C21

GPIO11/FLASH_CS3_N

E13


G7

DVSS

B6

FLASH_CS1_N

C22

GPIO10/FLASH_CS2_N

E14

FLASH_ADDR11

G8

DVSS

B7

DVSS

D1

DDR_SDRAM_DQ28

E15

G9

CORE_DVDD_1P2

B8

FLASH_DATA10

D2

DVSS


G10

DVSS

B9

DVSS

D3

DDR_SDRAM_DQ29

E16

FLASH_ADDR3

G11

CORE_DVDD_1P2

B10

FLASH_DATA2

D4

DVSS

E17

FLASH_ADDR0

G12

DVSS

B11

DVSS

D5

JTDO

E18

DVSS

G13

CORE_DVDD_1P2

B12

FLASH_ADDR21

D6

SFlash_CLK

E19

INT_OVDD_33

G14

DVSS

B13

DVSS

D7

FLASH_DATA12

E20

OSC_XTAL_SEL

G15

DVSS

B14

FLASH_ADDR13

D8

FLASH_DATA9

E21

DVSS

G16

DVSS

B15

DVSS

D9

FLASH_DATA4

E22

GPIO6/UART_RX2

G17

DVSS

BROADCOM ®

June 02, 2010 • 4706-DS00-R

Page 21 4/12/2011 DXKOG


BCM4706 Pin Tables

Bal Ball Sign ignal

Bal Ball Sign ignal

Ball Ball Sig Signa nal l

Bal Ball Signal

G18

INT_ INT_O OVDD_3 DD_33 3

J17

DVSS

L1 6

DVSS

N15

DVSS

G19

GPIO4

J18

DVSS

L17

DVSS

N16

DVSS

G20 G20

GPIO GPIO3/ 3/SP SPI_ I_MI MISO SO

J19

NC

L1 8

PCIe_RE e_REF FCLKN

N17 N17

PCIe_SDVSS

G21 G21

GPIO GPIO1/ 1/SP SPI_ I_SS SS0 0

J20

TDM1_SDIO

L1 9

PCIe0_RDP

N18 N18

PCIe_SDVSS

G22 G22

GPIO GPIO0/ 0/SP SPI_ I_SC SCLK LK

J21

TDM0_SDIO

L20

PCIe0_RDN

N19 N19

PCIe0_TDP

H1

DDR_SDRAM_DQSP2

J22

TDM0_BITCLK

L21 L21

PCI PCIe_SD e_SDVD VDD_ D_1 1P2

N20 N20

PCIe0_TDN

H2

DDR_SDRAM_DQSN2

K1

DDR_SDRAM_DQ20

L2 2

PCIe1_ e1_RST_N

N21 N21

PCI PCIe_RE e_REFC FCLK LKOU OUTN TN

H3

DVSS

K2

DDR_SDRAM_DQ16

M1

DDR_SDRAM_DQ14

N22 N22

PCI PCIe_RE e_REFC FCLK LKOU OUTP TP

H4

DDR_SDRAM_DQ21

K3

DVSS

M2

DDR_SDRAM_DQ15

P1

DDR_SDRAM_DQ12

H5

DVSS

K4

DDR_SDRAM_DQ17

M3

DDR_OVDD_1P8

P2

DDR_SDRAM_DQ9

H6

DVSS

K5

DVSS

M4

DVSS

P3

DDR_OVDD_1P8

H7

DVSS

K6

DVSS

M5

DVSS

P4

DDR_SDRAM_DQ8

H8

DDR_OVDD_1P8

K7

DVSS

M6

DVSS

P5

DVSS

H9

DVSS

K8

DVSS

M7

DVSS

P6

DVSS

H10 H10

CORE_ ORE_DV DVDD DD_1 _1P2 P2

K9

DVSS

M8

DDR_OVDD_1P8

P7

DVSS

H11

DVSS

K10

DVSS

M9

DVSS

P8

DVSS

H12 H12


K11

DVSS

M10 DVSS

P9

DVSS

H13

DVSS

K12

DVSS

M11 DVSS

P10

DVSS

H14 H14


K13

DVSS

M12 DVSS

P11

DVSS

H15

DVSS

K14

CORE_ ORE_D DVDD_ VDD_1 1P2

M13 DVSS

P12

DVSS

H16

DVSS

K15

DVSS

M14 M14 CORE CORE_D _DVD VDD_ D_1P 1P2 2

P13

DVSS

H17

DVSS

K16

PCIe_S e_SDVSS

M15 DVSS

P14 P14

CORE ORE_DVD _DVDD D_1P _1P2

H18

NC

K17

DVSS

M16 DVSS

P15

DVSS

H19

NC

K18

PCIe PCIe_P _PLLLVSS

M17 M17 PCIe PCIe_S _SDV DVDD DD_1 _1P2 P2

P16

DVSS

H20

NC

K19

PCIe_S Ie_SD DVDD VDD_1P _1P2

M18 M18 PCIe PCIe_R _REF EFCL CLKP KP

P17

DVSS

H21

TDM1_WS

K20

PCIe_S e_SDVSS

M19 M19 PCIe PCIe_S _SDV DVDD DD_1 _1P2 P2

P18

DVSS

H22

TDM0_WS

K21

PCIe0_ e0_RST_N

M20 M20 PCIe PCIe_S _SDV DVSS SS

P19 P19

PCIe_S e_SDVD DVDD_1P D_1P2 2

J1

DDR_SDRAM_CK2P

K22

TDM1_BI _BITCLK

M21 M21 PCI PCIe1_R e1_RDP DP

P20 P20

PCIe PCIe_P _PLL LLVD VDD_ D_1P 1P2 2

J2

DDR_SDRAM_CK2N

L1

DDR_SDRAM_DQ19

M22 M22 PCI PCIe1_R e1_RDN DN

P21

PCIe1_TDP

J3

DDR_OVDD_1P8

L2

DDR_SDRAM_DQ18

N1

DDR_SDRAM RAM_DQ _DQSP1

P22

PCIe1_TDN

J4

DVSS

L3

DVSS

N2

DDR_SDRAM RAM_DQ _DQSN1

R1

DDR_SDRAM_DQ11

J5

DVSS

L4

DDR_SDRAM_DM2

N3

DVSS

R2

DDR_SDRAM_DQ10

J6

DVSS

L5

DVSS

N4

DDR_SDRAM_DQ13

R3

DVSS

J7

CORE_DVDD_1P2

L6

DVSS

N5

DVSS

R4

DDR_SDRAM_DM1

J8

DVSS

L7

CORE_DVDD_1P2

N6

DVSS

R5

DVSS

J9

DVSS

L8

DVSS

N7

DVSS

R6

DVSS

J10

DVSS

L9

CORE_DVDD_1P2

N8

CORE_DVDD_1P2

R7

DVSS

J11

DVSS

L1 0

DVSS

N9

DVSS

R8

CORE_DVDD_1P2

J12

DVSS

L1 1

DVSS

N1 0

DVSS

R9

DVSS

J13

DVSS

L1 2

DVSS

N1 1

DVSS

R10 R10

DDR_O DR_OVD VDD_ D_1P 1P8 8

J14

DVSS

L1 3

DVSS

N1 2

DVSS

R11 R11

CORE ORE_DVD _DVDD D_1P _1P2

J15

DVSS

L1 4

DVSS

N1 3

DVSS

R12

DVSS

J16

DVSS

L1 5

DVSS

N1 4

DVSS

R13

DVSS

BROADCOM ®

June 02, 20 10 • 4706-DS00-R

Page 22 4/12/2011 DXKOG


BCM4706 Pin Tables

Bal Ball Sign ignal

Bal Ball Sign ignal

Ball Ball Sig Signa nal l

Bal Ball Signal

R14

DVSS

U13 U13

SGMI SGMII_P I_PLL LLA AVDD_ VDD_1P 1P2 2

W12 SGMII SGMII_PL _PLLA LAVDD VDD_1P _1P2 2

AA11 XTAL_P XTAL_PLLA LLAVDD_3 VDD_3P3 P3

R15

DVSS

U14 U14

SGMI SGMII_ I_VD VDD_ D_1P 1P2 2

W13 W13 SGMI SGMII_V I_VDD DD_1 _1P2 P2

AA AA12 12 XTAL XTALO O

R16

DVSS

U15

DVSS


AA13 AA13 SGMII SGMII_VD _VDD_1 D_1P2 P2

R17

DVSS

U16

DVSS


AA14 AA14 SGMII_ SGMII_TX TXDN DN

R18

DVSS

U17 U17

GMAC GM AC_O _OVD VDD_ D_25 25_3 _33 3

W16 W16 GM GMAC AC_T _TXD XD1 1

AA15 AA15 SGMII SGMII_VD _VDD_1 D_1P2 P2

R19

DVSS

U18

DVSS

W17 W17 GM GMAC AC_T _TX XCLK CLK

AA AA16 16 SGMI SGMII_ I_RX RXDP DP

R20 R20

USB_ SB_AVDD_ VDD_2 2P5

U19

USB_ USB_A AVDD VDD_3P _3P3

W18 GM GMA AC_COL _COL

AA17 AA17 SGMII_ SGMII_VDD VDD_1P _1P2 2

R21 R21

PCIe PCIe_S _SDV DVDD DD_1 _1P2 P2

U20

USB_AVSS

W19 W19 GM GMAC AC_R _RXD XDV V

AA AA18 18 GM GMAC AC_T _TXE XER R

R22

PCIe_SDVSS

U21

NC

W20 W20 MISC MISC1_ 1_PL PLLA LAVS VSS S

AA AA19 19 GM GMAC AC_R _RXD XD3 3

T1

DVSS

U22

USB_D SB_DA ATA_N A_N

W21 MISC2_ MISC2_PLL PLLA AVDD_1P VDD_1P2 2

AA AA20 20 GM GMAC AC_R _RXD XD2 2

T2

DVSS

V1

DDR_OVDD_1P8

W22 NC

AA21 CORE_PLLA CORE_PLLAVDD_1 VDD_1P2 P2

T3

DVSS

V2

DVSS

Y1

DDR_SDRAM_DQ7

AA22 NC

T4

DVSS

V3

DVSS

Y2

DDR_SDRAM_DQ3

AB1 AB1

DDR_ DDR_SD SDRA RAM_ M_CK CK0P 0P

T5

DVSS

V4

DDR_SDRAM_CKE

Y3

DDR_SDRAM_DQ0

AB2 AB2

DDR_ DDR_SD SDRA RAM_ M_CK CK0N 0N

T6

DVSS

V5

DDR_SDRAM_RAS

Y4

DDR_OVDD_1P8

AB3 AB3

DDR_S DR_SDR DRA AM_OD M_ODT T

T7

DVSS

V6

DDR_OVDD_1P8

Y5

DVSS

AB4 AB4

DDR_S DR_SDR DRA AM_W M_WE

T8

DVSS

V7

DVSS

Y6

DDR_SDRAM_BA1

AB5 AB5

DDR_S DR_SDR DRA AM_BA M_BA0 0

T9

CORE_DVDD_1P2

V8

DVSS

Y7

DDR_SDRAM_ADDR0

AB6 AB6

DDR_ DDR_SD SDRA RAM_ M_AD ADDR DR2 2

T10

DVSS

V9

DVSS

Y8

DDR_SDRAM_ADDR4

AB7 AB7


T11

DVSS

V10 V10

DDR_ DDR_OV OVDD DD_1 _1P8 P8

Y9

DDR_SDRAM_ADDR6

AB8 AB8


T12

DVSS

V11

NC

Y10 Y10


AB9 AB9


T13

DVSS

V12

DVSS

Y11

NC

AB10 AB10 DDR_SD DDR_SDRAM RAM_AD _ADDR1 DR13 3

T14

CORE_ ORE_D DVDD VDD_1P _1P2

V13

NC

Y12 Y12

SGM GMIII_P I_PLLA LLAVSS VSS

AB11 AB11 SGMII_ SGMII_PLL PLLAV AVSS SS

T15

DVSS

V1 4

SGMII_VSS

Y13

SGMII_VSS

AB12 AB12 XTAL XTALII

T16

DVSS

V15

DVSS

Y14

SGMII_VSS

AB13 AB13 SGMI SGMII_ I_VS VSS S

T17

DVSS

V16

DVSS

Y15

SGMII_VSS

AB14 AB14 SGMI SGMII_ I_TX TXDP DP

T18

DVSS

V17 V17

GMAC GM AC_O _OVD VDD_ D_25 25_3 _33 3

Y16

SGMII_VSS


T19

USB_D B_DVDD VDD_1P _1P2

V18

DVSS

Y17

GMAC_TXEN

AB16 AB16 SGMI SGMII_ I_RX RXDN DN

T20

NC

V19

GMAC_CRS

Y18

GMAC_TXD3


T21

USB_AVSS

V20 V20

MISC MISC2_ 2_PL PLLA LAVS VSS S

Y19

GMAC_RXER

AB18 AB18 GM GMAC AC_T _TXD XD0 0

T22

USB_RREF

V21 V21

USB_ USB_PL PLLA LAVD VDD_ D_1P 1P2 2

Y20 Y20

CORE_ ORE_P PLLA LLAVSS VSS

AB19 AB19 GM GMAC AC_T _TXD XD2 2

U1

DDR_SDRAM_DQSN0

V22 V22

USB_ USB_D DATA_P A_P

Y21 Y21

MISC MISC1_ 1_PL PLLA LAVD VDD_ D_1P 1P2 2

AB20 AB20 GM GMAC AC_R _RXC XCLK LK

U2

DDR_SDRAM_DQSP0

W1

DDR_S R_SDRAM_DQ _DQ6

Y22

NC

AB21 AB21 GM GMAC AC_R _RXD XD1 1

U3

DVSS

W2


AA1 AA 1

DDR_ DDR_SD SDRA RAM_ M_DQ DQ2 2

AB22 AB22 GM GMAC AC_R _RXD XD0 0

U4

DVSS

W3


AA2 AA 2

DDR_ DDR_SD SDRA RAM_ M_DQ DQ1 1

U5

DVSS

W4

DVSS

AA3 AA 3

DDR_ DDR_SD SDRA RAM_ M_DM DM0 0

U6

DVSS

W5

DDR_S R_SDRAM_CA _CAS

AA4 AA 4

DDR_ DDR_SD SDRA RAM_ M_RE REF F

U7

DVSS

W6

DDR_S R_SDRAM_CS _CS_N

AA5 AA 5

DDR_ DDR_SD SDRA RAM_ M_BA BA2 2

U8

DVSS

W7

DDR_ DDR_S SDRAM RAM_ADD _ADDR3 R3

AA6

DVSS

U9

DVSS

W8

DDR_O R_OVDD_1P _1P8

AA7 AA 7


U10

DVSS

W9

DDR_ DDR_S SDRAM RAM_ADD _ADDR9 R9

AA8

DVSS

U11

DVSS

W10 W10 DDR_S DDR_SDR DRAM AM_A _ADD DDR1 R12 2

AA9 AA 9


U12

DVSS

W11 W11 DDR_ DDR_SD SDRA RAM_ M_ZQ ZQ

AA10 AA10 DDR_SD DDR_SDRAM RAM_AD _ADDR1 DR14 4

BROADCOM ®

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BCM4706 Pin Tables

Table 3: BCM4706 Sorted by Signal Name Signal

Ball Signal

Ball Signal

Ball Signal

Ball

CORE_DVDD_1P2

G9

DDR_ DDR_SD SDR RAM_A AM_AD DDR2 DR2

AB6

DDR_SDRAM_DQ27

E3

DVSS

C20

CORE_DVDD_1P2

G11

DDR_S DR_SDR DRAM AM_ _ADDR ADDR3 3

W7

DDR_SDRAM_DQ28

D1

DVSS

D2

CORE_DVDD_1P2

G13


Y8

DDR_SDRAM_DQ29

D3

DVSS

D4

CORE_DVDD_1P2

H10


AB7

DDR_SDRAM_DQ3

Y2

DVSS

E18

CORE_DVDD_1P2

H12


Y9

DDR_SDRAM_DQ30

A2

DVSS

E21

CORE_DVDD_1P2

H14

DDR_S DR_SDR DRAM AM_ _ADD ADDR7

AA9 AA9

DDR_SDRAM_DQ31

A3

DVSS

F4

CORE_DVDD_1P2

J7


AB8

DDR_SDRAM_DQ4

W3

DVSS

F6

CORE_DVDD_1P2

K14


W9

DDR_SDRAM_DQ5

W2

DVSS

F8

CORE_DVDD_1P2

L7

DDR_SDRAM_BA0

AB5

DDR_SDRAM_DQ6

W1

DVSS

F10

CORE_DVDD_1P2

L9

DDR_SDRAM_BA1

Y6

DDR_SDRAM_DQ7

Y1

DVSS

F12

CORE_DVDD_1P2

M14

DDR_SDRAM_BA2

AA5

DDR_SDRAM_DQ8

P4

DVSS

F14

CORE_DVDD_1P2

N8

DDR_SDRAM_CAS

W5

DDR_SDRAM_DQ9

P2

DVSS

F16

CORE_DVDD_1P2

P14

DDR_SDRAM_CK0N

AB2

DDR_ DDR_SD SDR RAM_D AM_DQS QSN0 N0

U1

DVSS

F18

CORE_DVDD_1P2

R8

DDR_SDRAM_CK0P

AB1

DDR_ DDR_SD SDR RAM_ AM_DQS DQSN1

N2

DVSS

G2

CORE_DVDD_1P2

R11

DDR_SDRAM_CK2N

J2


H2

DVSS

G4

CORE_DVDD_1P2

T9

DDR_SDRAM_CK2P

J1


C2

DVSS

G5

CORE_DVDD_1P2

T14

DDR_SDRAM_CKE

V4

DDR_S R_SDRAM_DQ SP SP0

U2

DVSS

G6

CORE ORE_PLL _PLLA AVDD_ VDD_1 1P2

AA21 AA21

DDR_SDRAM_CS_N

W6

DDR_S R_SDRAM_DQSP1

N1

DVSS

G7

CORE_PLLAVSS

Y20

DDR_SDRAM_DM0

AA3

DDR_ DDR_SD SDR RAM_D AM_DQS QSP2 P2

H1

DVSS

G8

DDR_OVDD_1P8

A1

DDR_SDRAM_DM1

R4

DDR_ DDR_SD SDR RAM_D AM_DQS QSP3 P3

C1

DVSS

G10

DDR_OVDD_1P8

C3

DDR_SDRAM_DM2

L4

DDR_SDRAM_ODT

AB3

DVSS

G12

DDR_OVDD_1P8

G1

DDR_SDRAM_DM3

F3

DDR_SDRAM_RAS

V5

DVSS

G14

DDR_OVDD_1P8

G3

DDR_SDRAM_DQ0

Y3

DDR_SDRAM_REF

AA4

DVSS

G15

DDR_OVDD_1P8

H8

DDR_SDRAM_DQ1

AA2

DDR_SDRAM_WE

AB4

DVSS

G16

DDR_OVDD_1P8

J3

DDR_SDRAM_DQ10

R2

DDR_SDRAM_ZQ

W11

DVSS

G17

DDR_OVDD_1P8

M3

DDR_SDRAM_DQ11

R1

DVSS

B2

DVSS

H3

DDR_OVDD_1P8

M8

DDR_SDRAM_DQ12

P1

DVSS

B3

DVSS

H5

DDR_OVDD_1P8

P3

DDR_SDRAM_DQ13

N4

DVSS

B4

DVSS

H6

DDR_OVDD_1P8

R10

DDR_SDRAM_DQ14

M1

DVSS

B5

DVSS

H7

DDR_OVDD_1P8

V1

DDR_SDRAM_DQ15

M2

DVSS

B7

DVSS

H9

DDR_OVDD_1P8

V6

DDR_SDRAM_DQ16

K2

DVSS

B9

DVSS

H11

DDR_OVDD_1P8

V10

DDR_SDRAM_DQ17

K4

DVSS

B11

DVSS

H13

DDR_OVDD_1P8

W8

DDR_SDRAM_DQ18

L2

DVSS

B13

DVSS

H15

DDR_OVDD_1P8

Y4

DDR_SDRAM_DQ19

L1

DVSS

B15

DVSS

H16

DDR_S DR_SD DRAM RAM_ADD _ADDR0 R0

Y7

DDR_SDRAM_DQ2

AA1

DVSS

B17

DVSS

H17

DDR_S DR_SD DRAM RAM_ADD _ADDR1 R1

AA7 AA7

DDR_SDRAM_DQ20

K1

DVSS

C4

DVSS

J4

DDR_ DDR_SD SDRA RAM_ M_AD ADDR DR10 10 Y10 Y10

DDR_SDRAM_DQ21

H4

DVSS

C6

DVSS

J5

DDR_ DDR_SD SDRA RAM_ M_AD ADDR DR11 11 AB9 AB9

DDR_SDRAM_DQ22

E1

DVSS

C8

DVSS

J6

DDR_ DDR_SD SDRA RAM_ M_AD ADDR DR12 12 W10 W10

DDR_SDRAM_DQ23

E2

DVSS

C10

DVSS

J8

DDR_ DDR_SD SDRA RAM_ M_AD ADDR DR13 13 AB10 AB10

DDR_SDRAM_DQ24

F1

DVSS

C12

DVSS

J9

DDR_ DDR_SD SDRA RAM_ M_AD ADDR DR14 14 AA AA10 10

DDR_SDRAM_DQ25

F2

DVSS

C14

DVSS

J10

DDR_SDRAM_DQ26

B1

DVSS

C16

DVSS

J11

BROADCOM ®

June 02, 20 10 • 4706-DS00-R

Page 24 4/12/2011 DXKOG


BCM4706 Pin Tables

Signal

Ball Signal

Ball Signal

Ball Signal

Ball

DVSS

J12

DVSS

N5

DVSS

T7

FLASH_ADDR14

A14

DVSS

J13

DVSS

N6

DVSS

T8

FLASH_ADDR15

D13

DVSS

J14

DVSS

N7

DVSS

T10

E13

DVSS

J15

DVSS

N9

DVSS

T11


DVSS

J16

DVSS

N10

DVSS

T12

C13

DVSS

J17

DVSS

N11

DVSS

T13


DVSS

J18

DVSS

N12

DVSS

T15


A13

DVSS

K3

DVSS

N13

DVSS

T16

E12

DVSS

K5

DVSS

N14

DVSS

T17


DVSS

K6

DVSS

N15

DVSS

T18

FLASH_ADDR2

A17

DVSS

K7

DVSS

N16

DVSS

U3

FLASH_ADDR20

D12

DVSS

K8

DVSS

P5

DVSS

U4

FLASH_ADDR21

B12

DVSS

K9

DVSS

P6

DVSS

U5

A12

DVSS

K10

DVSS

P7

DVSS

U6


DVSS

K11

DVSS

P8

DVSS

U7


D11

DVSS

K12

DVSS

P9

DVSS

U8

K13

DVSS

P10

DVSS

U9


E11

DVSS DVSS

K15

DVSS

P11

DVSS

U10

C11

DVSS

K17

DVSS

P12

DVSS

U11


DVSS

L3

DVSS

P13

DVSS

U12

FLASH_ADDR26

A11

DVSS

L5

DVSS

P15

DVSS

U15

FLASH_ADDR3

E16

DVSS

L6

DVSS

P16

DVSS

U16

FLASH_ADDR4

D16

DVSS

L8

DVSS

P17

DVSS

U18

FLASH_ADDR5

B16

DVSS

L10

DVSS

P18

DVSS

V2

A16

DVSS

L11

DVSS

R3

DVSS

V3


DVSS

L12

DVSS

R5

DVSS

V7

FLASH_ADDR7

D15

DVSS

L13

DVSS

R6

DVSS

V8


E15

DVSS

L14

DVSS

R7

DVSS

V9

FLASH_ADDR9

C15

DVSS

L15

DVSS

R9

DVSS

V12

FLASH_CS0_N

C18

DVSS

L16

DVSS

R12

DVSS

V15

FLASH_CS1_N

B6

DVSS

L17

DVSS

R13

DVSS

V16

FLASH_DATA0

E10

DVSS

M4

DVSS

R14

DVSS

V18

FLASH_DATA1

D10

DVSS

M5

DVSS

R15

DVSS

W4

FLASH_DATA10

B8

DVSS

M6

DVSS

R16

DVSS

Y5

FLASH_DATA11

A8

DVSS

M7

DVSS

R17

DVSS

AA6

FLASH_DATA12

D7

DVSS

M9

DVSS

R18

DVSS

AA8

FLASH_DATA13

E7

DVSS

M10

DVSS

R19

FLASH_ADDR0

E17

FLASH_DATA14

C7

DVSS

M11

DVSS

T1

FLASH_ADDR1

C17

FLASH_DATA15

A7

DVSS

M12

DVSS

T2

FLASH_ADDR10

A15

FLASH_DATA2

B10

DVSS

M13

DVSS

T3

FLASH_ADDR11

E14

FLASH_DATA3

A10

DVSS

M15

DVSS

T4

D14

FLASH_DATA4

D9

DVSS

M16

DVSS

T5

FLASH_ADDR12/ PCIe_DIS FLASH_ADDR13

B14

FLASH_DATA5

E9

DVSS

N3

DVSS

T6

BROADCOM ®

June 02, 2010 • 4706-DS00-R

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BCM4706 Pin Tables

Signal

Ball Signal

Ball Signal

Ball Signal

Ball

FLASH_DATA6

C9

INT_OVDD_33

E19

PCIe_SDVDD_1P2

M17

SGMII_VSS

Y16

FLASH_DATA7

A9

INT_OVDD_33

F5

PCIe_SDVDD_1P2

M19

SGMII_VSS

AB13

FLASH_DATA8

E8

INT_OVDD_33

F7

PCIe_SDVDD_1P2

P19

SGMII_VSS

AB15

FLASH_DATA9

D8

INT_OVDD_33

F9

PCIe_SDVDD_1P2

R21

SGMII_VSS

AB17

FLASH_OE_N

A18

INT_OVDD_33

F11

PCIe_SDVSS

K16

TDM0_BITCLK

J22

FLASH_WE_N

B18

INT_OVDD_33

F13

PCIe_SDVSS

K20

TDM0_SDIO

J21

GMAC_COL

W18

INT_OVDD_33

F15

PCIe_SDVSS

M20

TDM0_WS

H22

GMAC_CRS

V19

INT_OVDD_33

F17

PCIe_SDVSS

N17

TDM1_BITCLK

K22

GMAC_OVDD_25_33

U17

INT_OVDD_33

G18

PCIe_SDVSS

N18

TDM1_SDIO

J20

GMAC_OVDD_25_33

V17

JTCK

C5

PCIe_SDVSS

R22

TDM1_WS

H21

GMAC_RXCLK

AB20

JTDI

E5

PCIe0_RDN

L20

UART_RX

A19

GMAC_RXD0

AB22

JTDO

D5

PCIe0_RDP

L19

UART_TX

B19

GMAC_RXD1

AB21

JTMS

A5

PCIe0_RST_N

K21

USB_AVDD_2P5

R20

GMAC_RXD2

AA20

JTRST

A4

PCIe0_TDN

N20

USB_AVDD_3P3

U19

GMAC_RXD3

AA19

MDC

A20

PCIe0_TDP

N19

USB_AVSS

T21

GMAC_RXDV

W19

MDIO

B20

PCIe1_RDN

M22

USB_AVSS

U20

GMAC_RXER

Y19

MISC1_PLLAVDD_1P2

Y21

PCIe1_RDP

M21

USB_DATA_N

U22

GMAC_TXCLK

W17

MISC1_PLLAVSS

W20

PCIe1_RST_N

L22

USB_DATA_P

V22

GMAC_TXD0

AB18

MISC2_PLLAVDD_1P2

W21

PCIe1_TDN

P22

USB_DVDD_1P2

T19

GMAC_TXD1

W16

MISC2_PLLAVSS

V20

PCIe1_TDP

P21

USB_OCD

D20

GMAC_TXD2

AB19

NC

D17

RESET_N

D19

USB_PLLAVDD_1P2

V21

GMAC_TXD3

Y18

NC

E4

SFlash_CLK

D6

USB_RREF

T22

GMAC_TXEN

Y17

NC

H18

SFlash_SI

E6

XTAL_PLLAVDD_3P3

AA11

GMAC_TXER

AA18

NC

H19

SFlash_SO

A6

XTALI

AB12

GPIO0/SPI_SCLK

G22

NC

H20

SGMII_PLLAVDD_1P2

U13

XTALO

AA12

GPIO1/SPI_SS0

G21

NC

J19

SGMII_PLLAVDD_1P2

W12

GPIO10/FLASH_CS2_N C22

NC

T20

SGMII_PLLAVSS

Y12

GPIO11/FLASH_CS3_N C21

NC

U21

SGMII_PLLAVSS

AB11

GPIO12

B22

NC

V11

SGMII_RXDN

AB16

GPIO13

B21

NC

V13

SGMII_RXDP

AA16

GPIO14

A22

NC

W22

SGMII_TXDN

AA14

GPIO15

A21

NC

Y11

SGMII_TXDP

AB14

GPIO2/SPI_MOSI

F22

NC

Y22

SGMII_VDD_1P2

U14

GPIO3/SPI_MISO

G20

NC

AA22

SGMII_VDD_1P2

W13

GPIO4

G19

OSC_XTAL_SEL

E20

SGMII_VDD_1P2

W14

GPIO5

F19

PCIe_PLLVDD_1P2

P20

SGMII_VDD_1P2

W15

GPIO6/UART_RX2

E22

PCIe_PLLVSS

K18

SGMII_VDD_1P2

AA13

GPIO7/UART_TX2

F21

PCIe_REFCLKN

L18

SGMII_VDD_1P2

AA15

GPIO8/SPI_SS1

F20

PCIe_REFCLKOUTN

N21

SGMII_VDD_1P2

AA17

GPIO9/SPI_SS2

D21

PCIe_REFCLKOUTP

N22

SGMII_VSS

V14

INT_OVDD_33

C19

PCIe_REFCLKP

M18

SGMII_VSS

Y13

INT_OVDD_33

D18

PCIe_SDVDD_1P2

K19

SGMII_VSS

Y14

INT_OVDD_33

D22

PCIe_SDVDD_1P2

L21

SGMII_VSS

Y15

BROADCOM ®

June 02, 2010 • 4706-DS00-R

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Electrical Characteristics

Section 3: Electrical Characteristics Absolute Maximum Ratings Table 4: Absolute Maximum Ratingsa Parameter

Symbol

Min

Max

Units

3.3V Supply Voltage

INT_OVDD_33, GMAC_OVDD_25_33, USB_AVDD_3P3, XTAL_PLLAVDD_3P3

–0.5

+3.63

V

2.5V Supply Voltage

GMAC_OVDD_25_33, USB_AVDD_2P5

–0.5

+2.75

V

1.2V Supply Voltage

CORE_DVDD_1P2, CORE_PLLAVDD_1P2, MISC1_PLLAVDD_1P2, MISC2_PLLAVDD_1P2, PCIe_PLLVDD_1P2, PCIe_SDVDD_1P2, SGMII_PLLAVDD_1P2, SGMII_VDD_1P2, USB_DVDD_1P2, USB_PLLAVDD_1P2

–0.5

+1.32

V

1.8V Supply Voltage

DDR_OVDD_1P8

–0.5

+1.98

V

Maximum Junction Temperature

TJ_MAX

–

+125

o

Commercial Ambient Temperature (Operating)

TA

0

+70

o

Industrial Ambient Temperature (Operating)

TA

–40

+85

o

Operating Humidity

–

–

+85

%

Storage Temperature

TSTG

–40

+125

o

Storage Humidity

–

–

60

%

C C C

C

a. These specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions. Operation at maximum conditions for extended periods may adversely affect long-term reliability of the device.

BROADCOM ®

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Recommended Operating Conditions and DC Characteristics

Recommended Operating Conditions and DC Characteristics Table 5: Recommended Operating Conditions Symbol

Nominal

Limits

Units

CORE_DVDD_1P2

1.2V

±5%

V

CORE_PLLAVDD_1P2

1.2V

±5%

V

MISC1_PLLAVDD_1P2

1.2V

±5%

V

MISC2_PLLAVDD_1P2

1.2V

±5%

V

DDR_OVDD_1P8

1.8V

±0.1

V

INT_OVDD_33

3.3V

±5%

V

GMAC_OVDD_25_33

2.5V/3.3V

±5%

V

PCIe_PLLVDD_1P2

1.2V

±5%

V

PCIe_SDVDD_1P2

1.2V

±5%

V

SGMII_PLLAVDD_1P2

1.2V

±5%

V

SGMII_VDD_1P2

1.2V

±5%

V

USB_DVDD_1P2

1.2V

±5%

V

USB_PLLAVDD_1P2

1.2V

±5%

V

USB_AVDD_2P5

2.5V

±5%

V

USB_AVDD_3P3

3.3V

±5%

V

XTAL_PLLAVDD_3P3

3.3V

±5%

V

Note: See the BCM4706 Hardware Design Guide on docSAFE for more information on power supplies decoupling.

Table 6: Total Power and Supply Current Supply Voltage

BCM4706 Typical Value

Units

3.3V

75

mW

2.5V

105

mW

1.8V

840

mW

1.2V

1670

mW

Note: These power consumption numbers were derived under nominal conditions. For example, typical corner silicon, nominal temperature (25°C), and nominal voltages.

BROADCOM ®

June 02, 2010 • 4706-DS00-R

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Core and I/O Power Sequencing Requirements

Core and I/O Power Sequencing Requirements The BCM4706 device requires specific power sequencing between the core and I/O supplies. • The BCM4706 device power sequence requires I/O power (3.3V; 2.5V; 1.8V) to come up first, followed by the core power (1.2V). The requirement is that the core power (1.2V) should not be on until the I/O power (3.3V, 2.5V, 1.8V) reaches at least 1.0V. • When core power reaches nominal core voltage (1.2V ±5%), the I/O power should be stable at nominal I/O voltage (3.3V ±5%, 2.5V ±5%, or 1.8V ±5%) • The maximum ramp-up time for core power 1.2V (from 0V to nominal voltage ±5%) is 2 ms as shown in figure below. In addition, for successful power-up, Broadcom recommends that the external hardware reset be asserted for at least 50 ms after both I/O and core power are stable as shown in Figure 4.

Figure 4: Power Supply Sequencing

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DDR2 SDRAM Memory Interface DC Characteristics

DDR2 SDRAM Memory Interface DC Characteristics Table 7: DC Characteristics for DDR2 SDRAM Interface Parameter

Symbol Min

Max

Units

Conditions

SSTL Reference Voltage

VREF

DDR_OVDD_1P8 × 0.49

DDR_OVDD_1P8 × 0.51

V

Typically derived from DDR_OVDD_1P8 ÷ 2

DC Input High Voltage

VIHDC

VREF + 0.125

DDR_OVDD_1P8 + 0.3

V

–

DC Input Low Voltage

VILDC

–0.3

VREF – 0.125

V

–

AC Input High Voltage

VIHAC

VREF + 0.2

–

V

–

AC Input Low Voltage

VILAC

–

VREF – 0.2

V

–

DC Output High Voltage

VOH

DDR_OVDD_1P8 0.35

–

V

–

DC Output Low Voltage

VOL

–

0.35

V

–

DC Output Source Current IOH

9

–

mA

–

DC Output Sink Current

IOL

9

–

mA

–

Output Impedance

ZOUT

36

44

Ω

–

Termination Impedance

ZTERM

54 108

66 132

Ω

Strong termination

Ω

Weak termination

USB Host Interface DC Characteristics Table 8: USB Host Interface DC Characteristics Parameter

Symbol

Min

Typ

Max

Units

Conditions

Input Common Mode Voltage Range

VHSCM

-50

–

500

mV

–

Differential Input Voltage Sensitivity

VHSDI

300

–

–

mV

Static | VIDP – VIDN |

Squelch Detection Threshold (differential)

VHSSQ

–

–

100

mV

Squelch detected

150

–

–

mV

No Squelch detected

Disconnect Detection Threshold (differential)

VHSDSC

625

–

–

mV

Disconnect detected

–

–

525

mV

Disconnect undetected

Receiver – HS mode

Transmitter–HS mode Output High Voltage

VHSOH

360

400

440

mV

Static condition

Output Low Voltage

VHSOL

–10

0

10

mV

Static condition

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USB Host Interface DC Characteristics

Table 8: USB Host Interface DC Characteristics (Cont.) Parameter

Symbol

Min

Typ

Max

Units

Conditions

Output Impedance

RO

40.5

45

49.5

ohm

Single-ended

Chirp-J Output Voltage (differential)

VCHIRPJ

700

1100

mV

HS Termination disabled RPU connected

Chirp-K Output Voltage (differential)

VCHIRPK

-900

-500

mV

HS Termination disabled RPU connected

Note: See Section 7 of the USB 2.0 specification (www.usb.org) for more info on the Receiver Eye Diagram Template.

Table 9: USB 1.1 Electrical and Timing Parameters Value Parameter

Symbol

Condition

Differential Input Sensitivity (min)

VDI

Differential Common Mode Range (max)

Minimum

Typical

Maximum

Units

Static |VIDP – VIDN 200 |

–

–

mV

VCM

–

0.8

–

2.5

V

Output High Voltage

VFSOH

Static condition

2.8

–

3.6

V

Output Low Voltage

VFSOL

Static condition

0.0

–

0.3

V

Output Signal Crossover Voltage

VCRS

–

1.3

–

2.0

V

Output Impedance

RO

Single-ended

28

36

44

Ω

Bus Pull-down Resistor on Host Port

RPD

–

14.25

–

15.75

kΩ

Input Impedance

ZIN

–

300

–

Receiver — FS

Transmitter — FS

Terminations

kΩ

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PCIe DC Characteristics

PCIe DC Characteristics Table 10 shows PCIe DC characteristics. Table 10: PCIe DC Characteristics Parameter

Description

Min

Typ

Max

Units

ZOUT

Transmitter Output Impedance (differential)

–

100

–

Ω

VOD

Transmitter Output Voltage (differential peak – to – peak)

–

–

1200

mVP-P

ZIN

Receiver Input Impedance (differential)

-

100

–

Ω

VID

Receiver Input Voltage (differential peak – to – peak)

175

–

2000

mVP-P

Transmitter

Receiver

1G SGMII/SerDes Port Signals Table 11 shows the 1G SGMII/SerDes port signals. These signals are AC coupled. Table 11: 1G SGMII/SerDes Port Signals Parameter

Description

Min

Typ

Max

Units

VID

Receiver Input Voltage, differential peak to peak, AC coupled

100

–

2000

mV

RIN

Receiver Input Impedance, differential, integrated on-chip

80

100

120

Ω

VOD

Transmitter Output Voltage, differential peak-to-peak, programmable

–

700

1100

mV

RO

Transmitter Output Impedance (differential)

80

100

120

Ω

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Standard 3.3V Signals

Standard 3.3V Signals These specifications apply to all 3.3V signals, such as Flash, Serial Flash, MII, I8S/TDM, GPIO, MDC/MDIO, UART, JTAG interfaces, and global clock/reset pins. Table 12: Standard 3.3V Signals Parameter

Description

Min

Typ

Max

Units

VIN

Input voltage

– 0.3

–

3.6

V

VIL

Input low voltage

–

–

0.8

V

VIH

Input high voltage

2.0

–

–

V

VOL

Output low voltage

–

–

0.4

V

VOH

Output high voltage

2.4

–

–

V

CI

I/O pin capacitance

–

–

10

pF

Standard 2.5V Signals These specifications apply to the RGMII interface. Table 13: Standard 2.5V Signals Parameter

Description

Min

Typ

Max

Units

VIN

Input voltage

– 0.3

–

2.75

V

VIL

Input low voltage

–

–

0.8

V

VIH

Input high voltage

1.7

–

–

V

VOL

Output low voltage

–

–

0.4

V

VOH

Output high voltage

2.0

–

–

V

CI

I/O pin capacitance

–

–

10

pF

XTAL Oscillator Interface Table 14: XTAL Oscillator Interface Parameter

Symbol

Min

Max

Units

Input Low Voltage

XTALIL

–0.3

+0.8

V

Input High Voltage

XTALIH

2.0

XTAL_PLLAVDD_3P3 + 0.5

V

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Timing Characteristics

Section 4: T iming Characteristics Reset and Clock Timing t210 Voltage Rails

t204 t201

t203

XTAL_IN (25 MHz) t202

t207

t208

RESET_N

t209 Configuration Strap Signals

Valid

Figure 5: Reset and Clock Timing

Table 15: Reset and Clock Timing Parameter Description

Minimum

Typical

Maximum

Units

t201

XTALI frequency

–

25.0000

–

MHz

t202

XTALI high time

–

20

–

ns

t203

XTALI low time

–

20

–

ns

t204

RESET_N low pulse duration

50

–

–

ms

t207

Configuration valid setup to RESET_N rising

0

–

–

µs

t208

Configuration valid hold from RESET_N rising

8.5

–

10

µs

t209

RESET_N deassertion to normal operation

–

110

–

µs

t210

Reset low hold time after power supplies stabilize

50

–

–

ms

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Parallel Flash Timing

Parallel Flash Timing Parallel Flash READ Timing FLASH_ADDR[26:0]

Address Valid t3

t2

t1

FLASH_CS[1:0]_N

FLASH_OE_N

t0

FLASH_DATA[15:0]

Data Valid

Figure 6: Parallel Flash READ Timing Diagram

Table 16: Parallel Flash READ Timing Parameter Descriptions

Min

Typ

Max

Units

Comments

t0

Output Enable Assertion Time

1

–

32

Internal reference clock

WaitCount0+ 1

t1

Chip Select Inactive Time

1

–

32


WaitCount1+ 1

t2

Chip Select Low to Output Enable Low 1

–

32


WaitCount2+ 1

t3

Output Enable High to Chip Select High

–

32


WaitCount3+ 1

1

Note: Each timing parameter can be programmed individually through the corresponding WaitCount field on the FlashWaitCnt register.

Note: The internal reference clock runs at 150 MHz.

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Parallel Flash Timing

Parallel Flash WRITE Timing FLASH_ADDR[26:0]

Address Valid t3

t2

t1

FLASH_CS[1:0]_N

FLASH_WE_N

t0

FLASH_DATA[15:0]

Data Valid

Figure 7: Parallel Flash WRITE Timing Diagram

Table 17: Parallel Flash WRITE Timing Parameter

Descriptions

Min

Typ

Max

Units

Comments

t0

Output Enable Assertion Time

1

–

32

Internal reference clock WaitCount0 + 1

t1

Chip Select Inactive Time

1

–

32


t2

Chip Select Low to Write Enable 1 Low

–

32


t3

Write Enable High to Chip Select 1 High

–

32


Note: Each timing parameter can be programmed individually through the corresponding WaitCount field on the FlashWaitCnt register.

Note: The internal reference clock runs at 150 MHz.

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Serial Flash Timing (ST Micro-compatible Device)

Serial Flash Timing (ST Micro-compatible Device) tp SFlash_CLK t1 Flash_CSx_N t2

t3

SFlash_SI t4 SFlash_SO Figure 8: Serial Flash Timing Diagram Table 18: Serial Flash Timing Parameter

Descriptions

Min

Typ

Max

Units

f FREQ

SFlash_CLK frequency

–

–

37.5

MHz

tP

Cycle time: SFlash_CLK period

26.67/40

–

–

ns

t1

Delay time: Flash_CSx_N low to SFlash_CLK rising 20 edge

–

–

ns

t2

Setup time: SFlash_SI valid to SFlash_CLK falling edge

10

–

–

ns

t3

Hold time: SFlash_CLK falling edge to SFlash_SI invalid

0

–

–

ns

t4

Output valid time: SFlash_SO valid to SFlash_CLK 5.5 rising edge

–

–

ns

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DDR2 SDRAM AC Timing Characteristics

DDR2 SDRAM AC Timing Characteristics Table 19 shows the AC characteristics for the DDR SDRAM interface. Table 19: AC Characteristics for DDR SDRAM Interface Parameter Description

Min

Typ

Max

Units

tCK(avg)

Average clock period (programmable) 3.33

–

–

ns

tCH(avg)

Average clock HIGH pulse width

0.48

0.5

0.52

tCK(avg)

tCL(avg)

Average clock LOW pulse width

0.48

0.5

0.52

tCK(avg)

tJIT(per)

Clock period jitter

–125

–

125

ps

tJIT(cc)

Cycle to cycle clock period jitter

–250

–

250

ps

tJIT(duty)

Duty cycle jitter

–125

–

125

ps

tDQSS

DQS latching rising transitions to –250 associated clock edges (for write, also related to tDSS, tDSH)

0

250

ps

tDQSH

DQS HIGH pulse width (for write)

0.35

0.5

–

tCK(avg)

tDQSL

DQS LOW pulse width (for write)

0.35

0.5

–

tCK(avg)

tWPRE

Write preamble, DQS driver turn-on to 0.35 the first DQS edge

–

–

tCK(avg)

tWPST

Write postamble, DQS time to high-Z after the last falling DQS edge

–

–

tCK(avg)

tCK2AC

Delay from clock to address and control – signals, VDL adjustable (related to tIS, tIH at DDR2 SDRAM)

0.25

–

tCK(avg)

tIPW

Control and address output pulse width 0.6

–

–

tCK(avg)

0.4

tWDQ2DQS Delay from DQ or DM to DQS, VDL adjustable (for write, related to tDS, tDH at DDR2 SDRAM)

–

0.25

–

tCK(avg)

tDIPW

DQ and DM output pulse width (for write)

0.35

–

–

tCK(avg)

tDQSCK

DQS delay from clock (for read)

–400

–

400

ns

tRDQDQSS DQ to DQS setup time (for read)

0.2-tCK(avg)/4

–

–

ns

tRDQDQSH DQ hold time after DQS (for read)

tCK(avg)/4+0.2

–

–

ns

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USB Host Interface AC Timing Characteristics

USB Host Interface AC Timing Characteristics Table 20: USB 2.0 Host Interfaces Timing Parameters Parameter

Symbol

Min

Typ

Max

Units

Conditions

Baud Rate

BPS

–

480

–

Mbps

–

Units Interval

UI

–

2083

–

ps

–

∆ THSRX

–0.15

–

0.15

UI

–

Output Rise Time

THSR

500

–

–

ps

10% to 90%

Output Fall Time

THSF

500

–

–

ps

90% to 10%

TX Output Jitter

∆ THSTX

–0.05

–

0.05

UI

–

Receiver – HS mode Receiver Jitter Tolerance Transmitter–HS mode

Table 21: USB 1.1 Timing Parameters Value Parameter

Symbol

Condition Min

Typ

Max

Units

Baud Rate

BPS

–

–

12

–

Mbps

Units Interval

UI

–

–

83.33

–

ns

RX Jitter Tolerance

TJR1

To next –18.5 transition

–

18.5

ns

RX Jitter Tolerance

TJR2

For paired –9 transitions

–

9

ns

Output Rise Time

TFSR

10 to 90% 4

–

20

ns

Output Fall Time

TFSF

10 to 90% 4

–

20

ns

Note: For details, see the USB 1.1 Specification, Section 7.3.2, Tables 7-5 and 7-6.

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PCIe Interface Timing

PCIe Interface Timing PCIe_REFCLKP/N Timing Figure 9 shows PCIe_REFCLKP/N timing.

PCIe_REFCLKP/N

TF

TJ

TR

T CYCLE

Figure 9: PCIe_REFCLKP/N Timing

Table 22: PCIe_REFCLKP/N Timing Parameter

Descriptions

Min

Typ

Max

Units

FREQ

Frequency (1/TCYCLE)

–

100

–

MHz

TOL

Tolerance

–50

–

+50

ppm

VID

Differential peak-to-peak amplitude

1.32

–

1.70

VP-P

tR/tF

Rise/Fall time

–

–

1.0

ns

tJ

Max RMS (10 kHz to 50 MHz)

–

–

4.7

ps

PCIe[1:0]_RDP/N Timing Figure 10 shows PCIe[1:0]_RDP/N timing.

TJITTER

PCIe[1:0]_RDP/N

Figure 10: PCIe[1:0]_RDP/N Timing

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PCIe Interface Timing

Table 23: PCIe[1:0]_RDP/N Timing Parameter

Descriptions

Min

Typ

Max

Units

FREQ

Baud rate

–

2.5

–

GBaud

ZIN

Input impedance (differential)

–

100

–

Ω

VID

Differential peak-to-peak input voltage

175

–

2000

mVP-P

tJ

Jitter tolerance (minimum RX EYE width)

0.4

–

–

UI

PCIe[1:0]_TDP/N T iming Figure 11 shows PCIe[1:0]_TDP/N timing.

TJITTER

PCIe[1:0]_TDP/N

TR

TF

Figure 11: PCIe[1:0]_TDP/N Timing

Table 24: PCIe[1:0]_TDP/N Timing Parameter

Descriptions

Min

Typ

Max

Units

FREQ

Baud rate

–

2.5

–

GBaud

ZOUT

Output impedance (differential)

–

100

–

Ω

VOD

Differential peak-to-peak output voltage

–

–

1200

mVP-P

TR/TF

Output rise/fall time (20% to 80%)

0.125

–

–

UI

tJ

Output jitter (minimum TX EYE width)

0.7

–

–

UI

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MII Interface Timing

MII Interface Timing This section shows timing information for the MII Interface pins.

MII Input Timing

t402 t401

t403

t404

GMAC_RXCLK

GMAC_RXDV GMAC_RXD[3:0]

Figure 12: MII Input Timing

Table 25: MII Input Timing Parameter Description

Min

Typ

Max

Units

t401

GMAC_RXDV, GMAC_RXD[3:0] to GMAC_RXC rising setup time

10

–

–

ns

t402

GMAC_RXC clock period (10BASE-T mode)

–

400

–

ns

GMAC_RXC clock period (100BASE-TX mode)

–

40

–

ns

GMAC_RXC high/low time (10BASE-T mode)

160

–

240

ns

GMAC_RXC high/low time (100BASE-TX mode)

16

–

24

ns

t404

GMAC_RXDV, GMAC_RXD[3:0] to GMAC_RXC rising hold time 10

–

–

ns

–

Duty cycle

50

60

%

t403

40

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MII Interface Timing

MII Output Timing

GMAC_TXCLK

GMAC_TXEN GMAC_TXD[3:0]

Figure 13: MII Output Timing

Table 26: MII Output Timing Parameter Description

Min

Typ

Max

Units

t405

GMAC_TXC high to GMAC_TXEN, GMAC_TXD[3:0] valid

0

–

25

ns

t406

GMAC_TXC high to GMAC_TXEN, GMAC_TXD[3:0] invalid (hold)

0

–

–

ns

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RGMII Interface Timing

RGMII Interface Timing The following specifies timing information for the GMAC interface pins when configured in RGMII mode.

RGMII Output Timing (Normal Mode) RGMII output timing defaults to the normal mode when the FLASH_ADDR22/TX_DELAY_MODE pin is pulled low at power-on reset.

GMAC_TXCLK

GMAC_TXD[3:0]

Figure 14: RGMII Output Timing (Normal Mode)

Table 27: RGMII Output Timing (Normal Mode) Parameter Description

Min

Typ

Max

Units

–

GMAC_TXCLK clock period (1000M mode)

7.2

8.0

8.8

ns

–


36

40

44

ns

–


360

400

440

ns

t201

Tskew: Data to clock output skew

–500 (1000M) –

+500 (1000M) ps

–

Duty cycle for 1000M (GE)

45

50

55

%

–

Duty cycle for 10/100M (FE)

40

50

60

%

Note: The output timing in 10/100M operation is always as specified in the delayed mode.

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RGMII Output Timing (Delayed Mode) RGMII output timing is set to the delayed mode when the FLASH_ADDR22/TX_DELAY_MODE pin is pulled high at power-on reset.

GMAC_TXCLK (internal) Delayed GMAC_TXCLK (actual output at source)

GMAC_TXD[3:0]

Figure 15: RGMII Output Timing (Delayed Mode)

Table 28: RGMII Output Timing (Delayed Mode) Parameter Description

Min

Typ

Max Units

–


7.2

8.0

8.8

ns

–


36

40

44

ns

–


360

400

440

ns

t201D

Tsetup, data valid to clock transition: Available setup time at the output source (delayed mode)

1.2 (all speeds) 2.0

–

ns

t202D

Thold, clock transition to data valid: Available hold time at the output source (delayed mode)

1.2

2.0

–

ns

–


45

50

55

%

–


40

50

60

%

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RGMII Input Timing (Normal Mode) RGMII Input T iming defaults to the delayed mode when the FLASH_ADDR23/RX_DELAY_MODE pin is pulled low at power-on reset. The receive clock will not be delayed with 2 ns internally.

GMAC_RXCLK (internal)

GMAC_RXCLK (actual)

GMAC_RXD[3:0]

Figure 16: RGMII Input Timing (Normal Mode)

Table 29: RGMII Input Timing (Normal Mode) Parameter Description

Min Typ

Max Units

–

GMAC_RXCLK clock period (1000M mode)

7.2

8.0

8.8

ns

–


36

40

44

ns

–


360

400

440

ns

t301

Tsetup, input setup time: valid data to clock

1.0

2.0

–

ns

t302

Thold, input hold time: clock to valid data

1.0

2.0

–

ns

–


45

50

55

%

–


40

50

60

%

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RGMII Input Timing (Delayed Mode) RGMII Input T iming is set to the delayed mode when the FLASH_ADDR23/RX_DELAY_MODE pin is pulled high at power-on reset. The receive clock will be delayed with 2 ns internally.

GMAC_RXCLK (internal) Delayed GMAC_RXCLK (actual output at destination)

GMAC_RXD[3:0]

Figure 17: RGMII Input Timing (Delayed Mode)

Table 30: RGMII Input Timing (Delayed Mode) Parameter Description

Min

Typ

Max

Units

t301D

Tsetup, input setup time (delayed mode)

-1.0 (10/100/1000M)

–

–

ns

t302D

Thold, input hold time (delayed mode)

3.0 (1000M)

–

–

ns

9.0 (10/100M)

–

–

ns

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SGMII/SerDes Serial Interface

SGMII/SerDes Serial Interface This subsection specifies timing information for the serial interface.

Serial Interface Output Timing SGMII_TXDP

SGMII_TXDN

t802

t803

t805

Figure 18: Serial Interface Output Timing

Table 31: Serial Interface Output Timing Parameter Description

Min

Typ

Max

Units

t801

Transmit Data Signaling Speed

–

1.25

–

GBaud

t802

Transmit Data Rise Time (20%-80%)

100

–

200

ps

t803

Transmit Data Fall Time (20%- 80%)

100

–

200

ps

t804

Transmit Data Output Differential Skew

–

0

–

ps

t805

Transmit Data Total Jitter

–

–

0.24

UI

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SGMII/SerDes Serial Interface

Serial Interface Input Timing SGMII_RXDP

SGMII_RXDN

t808

Figure 19: Serial Interface Input Timing

Table 32: Serial Interface Input Timing Parameter Description

Min

Typ

Max

Units

t806

Receive Data Signaling Speed

–

1.25

–

GBaud

t808

Receive Data Jitter (peak-to-peak)

–

–

0.6

UI

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I8S/TDM Audio/Video AC Specification

I8S/TDM Audio/Video AC Specification Tperiod

TDM[1:0]_BITCLK Thigh

Tlow

TDM[1:0]_WS or TDM[1:0]_SDIO T pd

Figure 20: IXS Transmitter Timing

Tperiod

TDM[1:0]_BITCLK Thigh

Tlow

TDM[1:0]_WS or TDM[1:0]_SDIO T hold

Tsetup

Figure 21: IXS Receiver Timing I

Table 33: IXS Receiver Timing Parameter

Description

Min

Max Units Conditions

Tcyc

TDM[1:0]_BITCLK frequency

DC

75

Tperiod

TDM[1:0]_BITCLK period

13.33 –

ns

–

Thigh

TDM[1:0]_BITCLK high

5.33

8

ns

–

Tlow

TDM[1:0]_BITCLK low

5.33

8

ns

–

Tduty_cyc

TDM[1:0]_BITCLK duty cycle

40

60

%

–

Tpd

TDM[1:0]_BITCLK to TDM[1:0]_WS or TDM[1:0]_SDIO delay

–

3

ns

Output mode

Tsetup

TDM[1:0]_WS or TDM[1:0]_SDIO setup time

2

–

ns

Input mode

Thold

TDM[1:0]_WS or TDM[1:0]_SDIO hold time

2

–

ns

Input mode

MHz Programmable

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JTAG Interface

JTAG Interface JTAG timing is synchronous to the JTCK clock.

Figure 22: JTAG Interface Table 34: JTAG Interface Parameter

Description

Min

Typ

Max

Units

TCYCLE

JTAG Cycle Time

50

–

–

ns

TSU

Input Setup Time

10

–

–

ns

TH

Input Hold Time

10

–

–

ns

TOD

Output Delay T ime Measured from Falling Edge of JTCK

–

–

22

ns

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MDC/MDIO Master Interface

MDC/MDIO Master Interface MDIO timing is synchronous to the MDC clock. The BCM4706 is an MDC/MDIO master device that drives the MDC clock.

t1 MDC t2 MDIO (out) t3

t4

MDIO (in) Figure 23: MDC/MDIO Master Interface Table 35: MDC/MDIO Master Interface Parameter

Description

Min

Typ

Max

Units

t1

MDC cycle time, software programmable

40/60a

–

–

ns

t2

MDIO output delay from MDC falling

–

–

15

ns

t3

MDIO input setup time to MDC rising

20

–

–

ns

t4

MDIO input hold time to MDC rising

0

–

–

ns

a. Six internal reference clock cycles, which is 40 ns.

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SPI Master Interface

SPI Master Interface BCM4706 GPIO pins can be configured as SPI master interfaces to connect up to three SPI slaves. This supports all four combinations of clock phase and polarity.

Timing Parameters for CPHA=0 tp CPHA=0

SCLK (GPIO0)

CPOL=0

CPOL=0

CPOL=1

CPOL=1

SS0/1/2 (GPIO1/8/9)

t2

t1 t3

MOSI (GPIO2) t4

t5

MISO (GPIO3) Figure 24: SPI Master Interface: Timing Parameters for CPHA=0

Table 36: SPI Master Interface Parameter

Description

Min

Typ

Max

Units

tp

SCLK period, software programmable

80

–

–

ns

t1

Minimum leading time before the first SCLK edge

–

1.5

–

tp

t2

Minimum trailing time after the last SCLK edge

–

0.5

–

tp

t3

MOSI output delay from SCLK clock falling/rising (CPOL=0/ – 1)

–

10

ns

t4

MISO input setup time to SCLK clock rising/falling (CPOL=0/ 10 1)

–

–

ns

t5

MISO input hold time to SCLK clock rising/falling (CPOL=0/1) 10

–

–

ns

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SPI Master Interface

Timing Parameters for CPHA=1 tp CPHA=1

SCLK (GPIO0)

CPOL=0

CPOL=0

CPOL=1

CPOL=1

SS0/1/2 (GPIO1/8/9)

t2

t1 t3

MOSI (GPIO2) t4

t5

MISO (GPIO3) Figure 25: SPI Master Interface: Timing Parameters for CPHA=1

Table 37: Timing Parameters for CPHA=1 Parameter

Description

Min

Typ

Max

Units

tp

SCLK period, software programmable

80

–

–

ns

t1

Minimum leading time before the first SCLK edge

–

1

–

tp

t2

Minimum trailing time after the last SCLK edge

–

1

–

tp

t3

MOSI output delay from SCLK clock rising/falling (CPOL=0/1)

–

–

10

ns

t4

MISO input setup time to SCLK clock falling/rising (CPOL=0/1)

10

–

–

ns

t5

MISO input hold time to SCLK clock falling/rising (CPOL=0/1)

10

–

–

ns

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Thermal Specifications

Section 5: Thermal Specifications This section describes the device thermal specifications. The maximum ThetaJA is a function of the maximum ambient air temperature of the system.

BCM4706 This subsection describes BCM4706 device ther mal specifications.

BCM4706 Thermal Specifications Without External Heatsink at 70°C Table 38 and Table 39 show the simulation and thermal performance data on the 2s2p board, without external heatsink. The maximum ThetaJA is a function of the maximum ambient air temperature of the system. Table 38: Package for 2s2p Board, T A = 70°C, P = 2.7W from Simulation Parameter

Value

Device power dissipation, P(W)

2.70

Ambient air temperature TA (°C)

70

θJA in still air (°C/W)

21.43

θJB (°C/W)

9.80

θJC (°C/W)

8.81

Table 39: BCM4706 Thermal Specifications Without External Heatsink at 70°C Air Velocity m/s

ft/min

T J_max (°C)

T T_ (°C)

θ JA (°C/W)

Ψ JT (°C/W)

Ψ JB (°C/W)

0

0

127.86

109.20

21.43

6.91

12.25

0.508

100

122.36

103.65

19.39

6.93

12.16

1.016

200

119.63

100.86

18.38

6.95

12.05

2.032

400

116.60

97.73

17.26

6.99

11.89

3.048

600

114.87

95.93

16.62

7.02

11.78

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BCM4706

BCM4706 Thermal Specifications with External Heatsink at 70°C Table 40 and Table 41 show the simulation and thermal performance data with the 30x30x25 mm external heatsink for the 2s2p board. The maximum ThetaJA is a function of the maximum ambient air temperature of the system. Table 40: Package with 30x30x25 mm External Heat Sink on 2s2p Board, T A = 70°C, P = 2.7W from Simulation Parameter

Value


2.70


70


15.33

θJB (°C/W)

9.80

θJC (°C/W)

8.81

Table 41: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 70°C Air Velocity m/s

ft/min

T J_max (°C)

T T_ (°C)

θ JA (°C/W)

Ψ JT (°C/W)

Ψ JB (°C/W)

0

0

111.39

90.63

15.33

7.69

9.77

0.508

100

101.31

79.98

11.59

7.90

9.08

1.016

200

99.42

77.98

10.90

7.94

8.94

2.032

400

98.31

76.83

10.48

7.96

8.87

3.048

600

97.81

76.32

10.30

7.96

8.85

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BCM4706

BCM4706 Thermal Specifications Without External Heatsink at 85°C Table 42 and Table 43 show the simulation and thermal performance data on the 2s2p board, without external heatsink. The maximum ThetaJA is a function of the maximum ambient air temperature of the system. Table 42: Package for 2s2p Board, T A = 85° C, P = 2.7 W from Simulation Parameter

Value


2.70


85


21.43

θJB (°C/W)

9.80

θJC (°C/W)

8.81

Table 43: BCM4706 Thermal Specifications Without External Heatsink at 85°C Air Velocity m/s

ft/min

T J_max (°C)

T T_ (°C)

θ JA (°C/W)

Ψ JT (°C/W)

Ψ JB (°C/W)

0

0

142.86

124.20

21.43

6.91

12.25

0.508

100

137.36

118.65

19.39

6.93

12.16

1.016

200

134.63

115.86

18.38

6.95

12.05

2.032

400

131.60

112.73

17.26

6.99

11.89

3.048

600

129.87

110.93

16.62

7.02

11.78

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BCM4706

BCM4706 Thermal Specifications with External Heatsink at 85°C Table 44 and Table 45 show the simulation and thermal performance data with the 30x30x25 mm external heatsink for the 2s2p board. The maximum ThetaJA is a function of the maximum ambient air temperature of the system. Table 44: Package with 30x30x25 mm External Heat Sink on 2s2p Board, T A = 85°C, P = 2.7W from Simulation Parameter

Value


2.70


85


15.33

θJB (°C/W)

9.80

θJC (°C/W)

8.81

Table 45: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 85°C Air Velocity m/s

ft/min

T J_max (°C)

T T_ (°C)

θ JA (°C/W)

Ψ JT (°C/W)

Ψ JB (°C/W)

0

0

126.39

105.63

15.33

7.69

9.77

0.508

100

116.31

94.98

11.59

7.90

9.08

1.016

200

114.42

92.98

10.90

7.94

8.94

2.032

400

113.31

91.83

10.48

7.96

8.87

3.048

600

112.81

91.32

10.30

7.96

8.85

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Mechanical Information

Section 6: Mechanical Information BCM4706

Figure 26: BCM4706 Mechanical Information

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Ordering Information

Section 7: Ordering Information Table 46: Ordering Information Part Number

Package

Ambient Temperature

BCM4706KPBG

23 mm x 23 mm 484-pin PBGA (Lead-free)

0° to 70°C

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4706－DS00－R BCM4706 Advance Data Sheet NDA Clear

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