Experiment #3 Encoders, Decoders, Multiplexers, Multiplexers, and DeMux’s Digital Laboratory Section: Saturday 11:00am!:00pm "nstructor: Dr $dnan %e&ya Student 'ame: (ait&am Da’ana Student "D: 11!1331
Date: 11)10)!01* 1 | +age
$bstract "n t&is experiment e ill discuss and inspect t&e main -unctions pertaining to t&e Encoders)Decoders and Mux’s and deMux’s and try to understand &o t&ey operate and &o to implement .arious -unctions using t&em
Apparatus/Equipment Used: 1 /L!!001 asic Electricity ircuit Lab ! /L!*00! ombinational Logic ircuit Experiment Module 2! 3 /L!*003 ombinational Logic ircuit Experiment Module 23 4 /L!*004 ombinational Logic ircuit Experiment Module 24
5&eory 1. Multiplexers Multiplexers are combinational logic circuit t&at can direct one and only one input and route it to t&e output "t basically selects one input o- !6' number o- inputs 2' determines t&e si7e o- t&e Mux and number o- input bits and selection bits to be t&e output, using a selectors8
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2. DeMultiplexers ontrary to Multiplexers, DeMultiplexers recei.es 9n number oinput signals and directs one o- t&em to a !6n number o- output lines8
;ig 3 loc< Diagram o- DeMux
;ig 4 DeMux’s 5rut& 5able
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3. Encoders =nliui.alent binary code at its output $n 9nbit binary encoder &as ! n input lines and nbit output lines it& common types t&at include 4to!, ?to3 and 1*to4 line con@gurations 5&e output lines o- a digital encoder generate t&e binary e>ui.alent ot&e input line &ose .alue is e>ual to 91 and are a.ailable to encode eit&er a decimal or &exadecimal input pattern to typically a binary or 9D 2binary coded decimal output code
;ig A Encoder loc< Diagram and "ts 5rut& 5able
!. Decoders Binar Decoders are anot&er type o- digital logic de.ice t&at &as inputs o- !bit, 3bit or 4bit codes depending upon t&e number o- data input lines, so a decoder t&at &as a set o- to or more bits ill be de@ned as &a.ing an nbit code, and t&ere-ore it ill be possible to represent !n possible .alues 5&us, a decoder generally decodes a binary .alue into a nonbinary one by setting exactly one o- its n outputs to logic 91
;ig * Decoder loc< Diagram and 5rut& 5able
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+rocedure 1. A. "onstructing !#to#2#$ine Encoder %it& Basic 'ates /L!*003 Module as set on /L!*001 ircuit Lab, bloc< a as located a-terards $ ABdc Boltage as applied on t&e Module, "nputs $D ere connected to Sitc&es 0 to 3 respecti.ely, ;? and ;C outputs ere connected to logic "ndicators L0 and L1, "nput se>uence as -olloed as re>uested utputs o- t&e se>uences ere recorded
2. "onstructing 1(#to#!#$ine Encoder %it& ))$ *" /L!*004 Module as set on /L!!001, loc< a as located, module as poered on, inputs $1 to $? ere connected to $C to D respecti.ely, outputs $ to D ere connected to logic "ndicators L1 to L4, results and outputs ere recorded according to t&e gi.en table
3. "onstructing 2#to!#$ine Decoder %it& Basic 'ates /L!*003 Module as set on /L!!001, loc< c as located, module as poered on, inputs $ and ere connected to Sitc& 1 and 0 to D respecti.ely, outputs ;rom ;1 to ;4 ere connected to logic indicators L1L4 respecti.ely, results and outputs ere recorded according to t&e gi.en table and gi.en se>uences
!. "onstructing !#to#1(#$ine Decoder %it& ))$ *" /L!*00! Module as set on /L!!001, loc< c as located, module as poered on, inputs $1,1,1,D1 ere connected to Sitc& 1 to 3 respecti.ely, outputs -rom 0 to C ere connected to logic indicators L1 LC respecti.ely, results and outputs ere recorded according to t&e gi.en table and gi.en se>uences
+. "onstructing 2#to#1#$ine Multiplexer %it& ,asic 'ates /L!*004 Module as set on /L!!001, loc< e as located, module as poered on, inputs $, and ere connected to Sitc& 0 and 1, selector to Sitc& ! respecti.ely, output ;3 ere connected to logic
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indicator L3, results and outputs ere recorded according to t&e gi.en table and gi.en se>uences
-. "onstructing #to#1#$ine Multiplexer %it& *" /L!*004 Module as set on /L!!001, loc< - as located, module as poered on, inputs D0 to D ere connected to D"+ Sitc&es D0FD, inputs , , $ Data sitc&es ere to be connected to SG!, SG1, SG0, S5HE as connnected to data SG3, and set to 0, % and ; outputs ere connected to logic indicators L0 and L1, results and outputs ere recorded according to t&e gi.en table and gi.en se>uences
. Using Multiplexer to implement $ogic 0unctions: /L!*004 Module as set on /L!!001, loc< - as located, module as poered on, inputs D, , , $ ere connected SG0FSG4 respecti.ely, % output as connected to Logic "ndicator L0, results and outputs ere recorded according to t&e gi.en table and gi.en se>uences
. "onstructing 1#to#2#$ine Demultiplexer %it& Basic $ogic 'ates /L!*004 Module as set on /L!!001, loc< e as located, module as poered on, $ as connected to Data Sitc& 0, to SG3, ;1 and ;! to L1, L! Hespicte.ly, as set to 0 and t&en to 1 c&anges ere obser.ed and recorded
. "onstructing 1#to##$ine Demultiplexer %it& "M *" /L!*004 Module as set on /L!!001, loc< b as located, module as poered on,E and D ere connected to D0 and D1 respecti.ely, $, , to SG0, SG1, and SG! respecti.ely utputs %0F% ere connected to L0FL D as set to 0 and t&en to 1 c&anges ere obser.ed and recorded, results and outputs ere recorded according to t&e gi.en table and gi.en se>uences
Hesult Discussion 1. A. "onstructing !#to#2#$ine Encoder %it& Basic 'ates D $ 000 0 000 1 001 0 001 1 010
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;C
;?
0
0
0
0
0
1
0
0
1
0
0 010 1 011 0 011 1 100 0 100 1 101 0 101 1 110 0 110 1 111 0 111 1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
)&is circuit %or4s as !#to#2 line in coder and it %or4s onl %&en a one is in input 2. A. "onstructing 1( to#!#$ine Encoder %it& ))$ *" A A A A- A+ A! D " B A A3 A2 A1 (11111111 ( 1 1 ( ((1111111 ( 1 1 ( 11111111( 1 1 1 ( 1111111(( 1 1 ( 1 111111(11 1 1 ( ( 11111(((( 1 ( 1 1 1111(1111 1 ( 1 ( 1111(((11 1 ( 1 ( 111(111(( 1 1 ( 1 11(11(11( 1 ( ( ( 11(((1111 1 ( ( ( 1(((((111 ( 1 1 1 )&is circuit %or4s as a priorit acti5e lo% ,cd priorit encoder
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3. "onstructing 2#to!#$ine Decoder %it& Basic 'ates
Hesults are sel- decoder
!. "onstructing Decoder %it&
B A ( ( ( 1 1 ( 1 1
0 1 1
0 2 (
0 3 (
0 ! (
(
1
(
(
(
(
1
(
(
(
(
1
explanatory, !4
!#to#1(#$ine ))$ *"
D
D 01!34A*? $ C 0 0 0 0 011111111 0 1 1 0 0 0 101111111 1 1 ! 0 0 1 110111111 0 1 3 0 0 1 111011111 0 1 4 0 1 0 111101111 0 1 A 0 1 0 111110111 1 1 * 0 1 1 111111011 0 1 0 1 1 111111101 1 1 ? 1 0 0 111111110 0 1 C 1 0 0 111111111 1 0 $ D Decoder t&at &as &ig&ly acti.e input, acti.e lo output
+. "onstructing 2#to#1#$ine Multiplexer %it& ,asic 'ates
$ 0 0 0 1
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;3
0
0
0
0
0 0 0 1 1 0 1 1 1 0 1 1
1
1
1
1
0
0
0
1
1
0
1
1
6&en "7( 03 is determined , B8equal to B9 %&en "71 03 is determined , A8equal to A9 -. "onstructing #to#1#$ine Multiplexer %it& *" " B ; 0 A ( ( ( ( ( ( ( ( ( 1 ( 1 ( ( ( ( 1 1 ( 1 1 ( ( ( ( 1 ( 1 ( 1 1 1 ( ( ( 1 1 ( ( 1 %itc&es D(#D %ere randoml s%itc&ed and output %as recorded . "onstructing 0unction using Mux D A ( ( | +age
"
B ;
(
(
1
( 1 ( ( ( 1 ( ( ( 1 ( ( ( 1 1 ( 1 1 1 ( 1 1 1 ( 1 1 1 ( 1 1
(
(
(
(
1
1
(
1
(
1
(
1
1
(
1
1
1
(
1
1
1
(
(
1
(
(
(
(
1
1
(
1
1
1
(
(
1
(
(
1
1
(
1
1
1
Ge consider D as selection lines and $ as t&e input line, t&e combination o- t&e table inputs t&at connection it& output is t&is se>uence: $I, $I, 1, $, $I, 1, 0, $
. "onstructing 1#to#2#$ine Demultiplexer %it& Basic $ogic 'ates G&en ;! c&anges, ;1 remains @xed 2;1J1 and ;! c&anges at t&e output too G&en ;1 c&anges, ;! remains @xed 2;!J1 and ;! c&anges accordingly it& t&e input
. "onstructing 1#to##$ine Demultiplexer %it& "M *" D
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%0 %1 %! %3 %4 %A
$ 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1
%* 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
% 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
onclusion In this experiment we learned how to use Mux's and DeMux's. Encoders and Decoders, implement functions using them and so on. Our results came as expected, True and verified the theoretical one, One of the main disadvantages of standard digital encoders is that they can generate the wrong output code when there is more than one i nput present at logic level !". #or example, if we ma$e inputs D! and D% &I& at logic !" (oth at the same time, the resulting output is neither at )!" or at !)" (ut will (e at !!" which is an output (inary num(er that is different to the actual input present. *lso, an output code of all logic )"s can (e generated when all of its inputs are at )" O+ when input D) is eual to one.
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