2.3. CONTROL UNIT IMPLEMENTATION A wide variety of techniques have been used for control unit implementation. Most of these fall into one of two categories: 1. Hardw Hardwir ired ed imp implem lement entati ation on 2. Micro programmed implementation
2.3.1 HARDWIRED IMPLEMENTATION
In a hardwired implementation, the control unit is essentially a state machine circuit. Its input logic signals are transformed into a set of output logic signals, which are the control signals. Control Unit Inputs
he !ey inputs are the instruction register, the cloc!, flags, and control bus signals. "irst consider the instruction register. he control unit ma!es use of the opcode and will perform different actions #issue a different combination of control signals$ for different instructions. o simplify the control unit logic, there should be a unique logic input for each opcode. his function can be performed by a decoder, which decoder, which ta!es an encoded input and produces a single output. A decoder will have n binary inputs and %n binary outputs. able able %.&.% is an e'ample for n ( % he cloc! portion of the control unit issues a repetitive sequence of pulses. his is useful for measuring the duration of micro)operations. he control unit emits different control signals at different time units within a single instruction cycle. A counter as input to the control unit, with a different control signal being used for 1, %, and so forth. At the end of an instruction cycle, the control unit must feed bac! to the counter to reinitiali*e it at 1 Tabl 2.3.1 A +ecoder with wo Inputs and "our utputs
I1
I%
1
%
&
-
1
1
1
1
1
1
1
1
/ith these two refinements,#decoder,$ the control unit can be depicted as in "igure %.&.0.
Figure 2.3.6 Control Unit with Decoded with Decoded Inputs
Control Unit Lo!i"
o define the hardwired implementation of a control unit, all that remains is to discuss the internal logic of the control unit that produces output control signals as a function of its input signals. "or each control signal, to derive a oolean e'pression of that signal as a function of the inputs. his is best e'plained by e'plained by e'am ple. 2et 2et us consider consider again again our simple simple e'ample e'ample illustrated in "igure %.&.3
Figure 2.3.5 Data Paths and Control Signals
/e see in able %.&.& the micro)operation sequences and control signals needed to control three of the four phases of the instruction cycle.
Tabl 2.3.2
Micro)operations and 4ontrol 5ignals
2et us consider a single control signal, 43. his signal causes data to be read from the e'ternal data bus into the M6. /e can see that it is used twice in able1 able1
2et us u s define two new control signals, 7 and 8, that have the following interpretation: 78 ( "etch 4ycle Indirect 4ycle 78 ( 1 78 (1 9'ecute 4ycle 78 ( 11 Interrupt 4ycle hen the following oolean e'pression defines 43:
43 ( 7 : 8 : % ; 7 : 8 : % hat is, the control signal 43 will be asserted during the second time unit of both the fetch and indirect cycles. his e'pression is not complete. 43 is also needed during the e'ecute cycle. "or our simple e'ample, let us assume assume that there are only three instructions that read from memory: 2+A, A++, and A<+.
2. MICROPRO#RAMMED IMPLEMENTATION
In addition to the use of control signals, each micro)operation is described in symbolic notation. his nota notati tion on loo! loo!ss susp suspic icio ious usly ly li!e li!e a progr program ammi ming ng langu languag age. e. In fact fact it is a lang langua uage, ge, !nown !nown as a $i"ropro!ra$$in! lan!ua! . 9ach line describes a set of micro)operations occurring at one time and is !nown as a $i"roinstru"tion . A sequence of instructions is !nown as a $i"ropro!ra$, or firmware. or firmware. his term reflects that a microprogram is midway between hardware and software. It is easier to design in firmware than hardware, but it is more difficult to write a firmware program than a software program. 4onsider that for each micro)operation, all that the control unit is allowed to do is generate a set of control signals. hus, for any micro)operation, each control line emanating from the control unit is either on or off. his condition can, of course, be represented by a binary digit for each control line. 5o we could construct a control word in which each bit represents one control line. hen each micro)operation would be represented by a different pattern of 1s and s in the control word. 5uppose we string string together together a sequence sequence of control words to represent the sequence sequence of micro)operation micro)operationss performed by the control unit.
Mi"ropro!ra$$' Control Unit
he control memory of "igure %.1 contains a program that describes the behavior o f the control unit. It follows that we could implement the control unit b y simply e'ecuting that program. "igure %.% shows the !ey elements of such an implementation. he set of microinstructions is stored in the control memory. he control address register contains the address of the ne't microinstruction to be read./hen a microinstruction is read from the control memory, memory, it is transferred to a control buffer register. he left)hand portion of that connects to the control lines emanating from the control unit. hus, reading a microinstruction from the control memory is the same as executing that microinstruction.he third element shown in the figure is a sequencing unit that loads the control address register and issues a read command.
(i!ur 2.1 rgani*ation of 4ontrol Memory
(i!ur 2.2 4ontrol >nit Microarchitecture
(i!ur 2.3 "unctioning of Microprogrammed 4ontrol >nit
he two basic tas!s performed by a microprogrammed control unit are as follows: 1. Mi"roinstru"tion s)un"in!* ?et the ne't microinstruction from the control memory. e 'ecute the microinstruction. 2. Mi"roinstru"tion +"ution* ?enerate the control signals needed to e'ecute
1. ,)un"in! T"%ni)us
ased on the current microinstruction, condition flags, and the contents of the instruction register, a control memory address must be generated for the n e't microinstruction. /e can group them into three general categories, as illustrated in "igures %.- to %.0. hese categories are based on the format of the address information in the microinstruction: microinstruction: a. wo address fields b. 5ingle address field c. @ariable format a. T-o a''rss il's
he simplest approach is to provide two address fields in each microinstruction. "igure %.- suggests how this information is to be used. A multiple'er is provided that serves as a destination for both address fields plus the instruction register. ased on an address)selection input, the multiple'er transmits either the opcode or one of the two addresses to the control address register #4A6$.he 4A6 is subsequently decoded to produce the ne't microinst microinstructi ruction on address. address. he address)se address)selecti lection on signals signals are provided by a branch logic module whose input consists of control unit flags plus bits from the control portion of the microinstruction.
Address "ields (i!ur 2./ ranch 4ontrol 2ogic: wo Address
b. ,in!l a''rss il'
(i!ur 2.0 ranch 4ontrol 2ogic: 5ingle Address "ield
". ariabl ariabl or$at
Another approach is to provide for two entirely different microinstruction formats #"igure %.0$. ne bit designates which format is being used. In one format, the remaining bits are used to activate control signals. In the other format, some bits drive the branch logic module, and the remaining bits provide the address.
(i!ur 2. ranch 4ontrol 2ogic: @ariable @ariable "ormat
2. Mi"roinstru"tion Mi"roinstru"ti on E+"ution
he microinstruction cycle is the basic event on a microprogrammed processor. 9ach cycle is made up of two parts: fetch and e'ecute. he control logic module #"igure %.$ generates control signals as a function of some of the bits in the microinstruction. It should be clear that the format and con tent of the microinstruction will determine the comple'ity of the control logic module.
(i!ur 2. Micro)operation e'ecutions
