Schematic Diagrams
Ap A p p end en d i x B : Sch Sc h emat em atii c Diag Di agrr ams am s This appendix has circuit diagrams of the C5505/C5505Q/C5505C/C5505Q-C C5505/C5505Q/C5505C/C5505Q-C notebook’s notebook’s PCB’s. The following table indicates where to find the appropriate schematic diagram. Di ag r am - Pag e
Di ag r am - Pag e
Di ag r am - Pag e
System Block Diagram - Page B - 2
SB700-1 - Page B - 15
VCORE_Core - Page B - 28
Clock Generator - Page B - 3
SB700-2 - Page B - 16
0.9V, 1.8V, 1.8VS, 1.5VS - Page B - 29
CPU-1 - Page B - 4
SB700-3 - Page B - 17
1.1VS, 1.2V, 1.2VS - Page B - 30
CPU-2 - Page B - 5
SB700-4 - Page B - 18
VDD3, VDD5 - Page B - 31
CPU-3 - Page B - 6
New Card, Mini PCIE - Page B - 19
Charger, DC In - Page B - 32
CPU-4 - Page B - 7
CCD, 3G, SATA ODD - Page B - 20
Click Board - Page B - 33
DDRII SO-DIMM_0 - Page B - 8
USB, Fan, TP, Multi-Con - Page B - 21
Audio Board/USB - Page B - 34
DDRII SO-DIMM_1 - Page B - 9
Card Reader/LAN JMC261 JMC261 - Page B - 22
Power Switch Board Board - Page B - 35
RS780M-1 - Page B - 10
SATA HDD, LED, LED, MDC, BT - Page B - 23
External ODD Board - Page B - 36
RS780M-2 - Page B - 11
Audio Codec ALC272 ALC272 - Page B - 24
RS780M-3 - Page B - 12
KBC ITE IT8502E IT8502E - Page B - 25
LVDS, Inverter - Page Page B - 13
System PWR, 2.5V 2.5V - Page B - 26
HDMI, CRT - Page B - 14
PWRGD, RST - Page Page B - 27
Table B - 1
Schematic Diagrams
B . S c h e m a t i c D i a g r a m s
Version Note The schematic diagrams in this chapter are based upon version 6-7P-C5505-002. If your mainboard (or other boards) are a later version, please check with the Service Center for for updated diagrams (if required).
B - 1
Schematic Diagrams
System Block Diagram CLEVO C5500Q EXTERNAL CLOCK GENERATOR
AMD S1G2 CPU CLICKBOARD
ICS9LPRS480 64 PIN
Channel A
U N B U F FE R E D D D R 2 SODIMM 0
Channel B
U N B U F FE R E D D D R 2
CPU Temperature sensor
638-Pin uFCPGA 638
6-71-E51Q2-D01
SODIMM 1
DDR II AUDIO BOARD
HD T
USB X 1 6-71-C4508-D02A T U O
POWER SWITCH BOARD Power switch + Hotkey X 3
s m a r g a i D c i t a m e h c S . B
6-71-E51QS-D01
LVDS CON
H y p e r T r a n s p o rt L I N K 0 C PU I / F
HDMI CON
INTEGRATED GRAPHICS LVDS/CRT 1 X 8 P CI E I / F
6-71-E51QN- D01 CRT CON
6-7P-C5505-002 PCB 5? 1 ? ? : 6-71-C5500-D02 6-71-E51Q2-D01A 6-71-C4508-D02A 6-71-E51QS-D01A 6-71-E51QN-D01
HyperTransport (HT)
RS780M(C)
EXTERNAL ODD BOARD
Sheet 1 of 35 System Block Diagram
N I
1 X4 PCIE I/F WITH SB 4 X 1 P CI E I / F 465PIN FCBGA
Int Speaker
GPP PCIE INTERFACE 100 MHz PCIE3
MINIPCIE-3G USB4
PCIE0
Card Reader\Lan JMC261
INT MIC
PCIE2
NEW CARD
MD C
PCIE X4
MINIPCIE-WL
USB7
USB5
ALC 272 CODEC/
SB700
HD AUDIO I/F 24 MHz
USB2.0 (10)
USB 2.0 480 Mbps USB#2 P o rt 2
SYSTEM PWR,2.5V 1.8VS,3.3VS,5VS,3.3V,1.2VS
USB#1
USB#0
P o rt 1
Port 0
Headphone Jack
SATA II (4PORTS) AZAL IA H D AUDI O AC 97 2 .3
MIC In Jack
USB8
Int Speaker
SPI I/F
Bluetooth
C CD USB9 or USB6
PWRGD,RST
LPC I/F AC PI 1. 1
SATA
INT RTC
I/F
HDD SATA#1
549PIN FCBGA SATA ODD SATA#4 VCORE_VDD _CORE CPU_VDD0,CPU_ VDDD1
NEW CARD ONLY C4500
32.768 KHz
LPC 33 MHz
0.9V,1.8V , 1.8VS,1.5VS
32.768 KHz
1.1VS,1.2V,1.2VS,1.2V_HT
KBC IT8502E
128pins LQFP
VCORE_VDD _NB
CPU FAN
14*14*1.6mm DEBUG PORT VDD3 , VDD5 BATTERY CHAGER CHARGER,DC IN
B - 2 System Block Diagram
INT KEYBOARD
PS 2 TOUCH PAD
AUDIO BOARD
TPA6017 AMP
ATA 66/ 100/13 3 AUDIO BOARD
L
SPI ROM
R
Schematic Diagrams
Clock Generator 3 .3 VS
CL K _ VDD
1.2 VS L 32
L 54
H C B 1 6 08 K F - 12 1T 2 5- 0 6
.1 U _ 16 V_ 0 4
.1 U_ 1 6 V_ 0 4
C L K_ VDD IO H C B 1 6 08 K F- 1 2 1T 25 -0 6
.1U _ 1 6V_ 0 4
C321 C5 2 7
C 2 39
C 24 0
C2 9 3
.1 U _ 16 V_ 0 4
.1 U_ 1 6 V_ 0 4
.1 U _1 6 V_ 0 4
C2 3 7
C2 5 8
C2 8 9
C306 1 U _ 16 V_ 0 6
C2 6 0
C2 7 0
C2 9 1
C2 9 2
C241
C 2 38
1 0 U _6 .3 V_ 0 8
1 0U _ 6.3 V_ 0 8 .1U _ 16 V_ 0 4
.1 U_ 1 6V _0 4
.1 U_ 1 6 V_ 0 4
. 1U _ 16 V_ 0 4
Place very close toU1 CL K_ V D D
L 31
U4
C 2 90 .1 U _1 6 V_ 0 4 L 25
Z0201
4 7
Z0202 56 60
H C B 1 6 08 K F- 1 2 1 T2 5- 0 6 C 2 59
63 26 48 55 35 16 40
.1 U _1 6 V_ 0 4
C L K_ VDD
25 47 34 11 17
CL K_ VD DIO
Layout note: PLACE CRYSTAL WITHIN 500 MILS OF ICS9LPRS480
1 24 46 52 43 33 10 18
X2 2
1
R1 7 5 *1 M_ 0 4
C281
1 4 .31 8 MH z
C3 2 0
Z0203 61 Z0204 62 * 0 _0 4 0 2 _5 m i l_s h o rt Z0209 23 45 Z0210 44 Z0211 39 W L AN_ C LKR EQ # 38
Z 02 0 5 2 7 P_ 5 0 V_0 4
27 P_ 5 0 V_ 04
.1 U _1 6 V_ 0 4
P l a c e w i th i n 0 . 5 " o f CLKGEN
H C B 1 6 08 K F- 1 2 1 T2 5- 0 6
CL K_ V D D
.1 U_ 1 6 V_0 4
Placen ext to VDD48
R1 7 9
PCIE_ EXPC ARD _ CL K R EQ#
CL K_ VDD
R 1 33
C PUK G0 T _L PR S C PU KG0 C _L PR S
VD DR EF G ND REF VD VD VD VD VD VD VD
D4 8 DAT IG DC PU DH TT DSB_ SR C DSR C DSAT A
VD VD VD VD VD
DAT IG _I O DC PU_ IO DSB_ SR C_ IO DSR C_ IO 1 DSR C_ IO 2
G G G G G G G G
ND 48 ND ATI G1 ND CPU ND HT T ND SAT A ND SB_ SRC ND SRC 1 ND SRC 2
X1 X2 C C C C C
A TI G0 T _L PR S AT IG0 C _L PR S A TI G1 T _L PR S AT IG1 C _L PR S SRC 7 T_ L PR S/2 7M Hz _ SS SRC 7 C_ L PRS/ 27 M Hz _N S
SB_ SR C0 T _L PR S SB_ SR C0 C _L PR S SB_ SR C1 T _L PR S SB_ SR C1 C _L PR S S R C0 T _L PR S SR C0 C _L PR S S R C1 T _L PR S SR C1 C _L PR S S R C2 T _L PR S SR C2 C _L PR S S R C3 T _L PR S SR C3 C _L PR S S R C4 T _L PR S SR C4 C _L PR S SRC 6 T /SAT AT _L PR S SR C6 C /SAT AC _L PR S
LKR LKR LKR LKR LKR
EQ EQ EQ EQ EQ
0# 1# 2# 3# 4#
HT T 0 T/ 66 M _L PR S H TT 0 C/ 66 M _L PR S 4 8 MH z_ 0
Z0206 51
8 . 2K _ 04 C2 4 9
PD # * 1U _ 1 6V_ 0 6 2 3
7 ,8 ,1 5 S C L K 0 7 ,8 ,1 5 SDA TA0
VD DA_ 2 7 G ND A_2 7
2008/03/18
G G G G
ND ND ND ND
1 2 3 4
SM BCL K SM BDAT T h erm a l_ GN D1 T h erm a l_ GN D2 T h erm a l_ GN D3 T h erm a l_ GN D4
REF 0/S EL _H T T6 6 R EF 1 /SEL _ SAT A RE F 2/ SEL _2 7 T h er ma l _ GN D5 T h er ma l _ GN D6 T h er ma l _ GN D7 T h er ma l _ GN D8 T h er ma l _ GN D9
50 49
CPU _ CL KP_ R CPU _ CL KN _R
R N 30 1 2
4 * 0_ 4P 2 R _0 4_ 4 mil _ sh o rt 3
30 29 28 27
NBG F X_ CL KP_ R NBG F X_ CL KN _R GF X_ CL KP _R GF X_ CL KN _ R
R N 34 1 2
4 * 0_ 4P 2 R _0 4_ 4 mil _ sh o rt 3
6 5
Z 0 20 7
37 36 32 31
NBS LIN K_ CL KP_ R NBS LIN K_ CL KN _ R SBSR C_ CL KP _R SBSR C_ CL KN _ R
22 21 20 19 15 14 13 12 9 8
R N 31 1 2 R N 33 1 2
NBG PP_ CL KP _R NBG PP_ CL KN _ R P C I E _ E X P C A R D _ C L K P _ RR N 3 5 1 2 PC IE_ EXPCA RD _C L KN_ R PCIE _P E1_ C L KP_ R PCIE _P E1_ C L KN_ R PCIE _P E2_ C L KP_ R R N 37 1 PCIE _P E2_ C L KN_ R 2 PCIE _P E3_ C L KP_ R R N 36 1 PCIE _P E3_ C L KN_ R 2
CPU_CLKP5 CPU_CLKN 5
NBGFX_CLKP 10 NBGFX_CLKN 10
4 * 0_ 4P 2 R _0 4_ 4 mil _ sh o rt 3 4 * 0_ 4P 2 R _0 4_ 4 mil _ sh o rt 3
SBLINK_CLKP 10 SBLINK_CLKN 10 SBSRC_CLKP 14 SBSRC_CLKN 14
4 * 0_ 4P 2 R _0 4_ 4 mil _ sh o rt 3
PCIE_EXPCARD_CLKP 18 PCIE_EXPCARD_CLKN 18
4 * 0_ 4P 2 R _0 4_ 4 mil _ sh o rt 3 4 * 0_ 4P 2 R _0 4_ 4 mil _ sh o rt 3
Clock chip has internal serial terminations
Sheet 2 of 35 Clock Generator
fordifferencial pairs, external resist ors are reservedfor debugpurpose.
PCIE_CR_CLKP 21 PCIE_CR_CLKN 21 PCIE_WLAN_CLKP 18 PCIE_WLAN_CLKN 18
42 41 54 53
NBH T REF _ C L KP_ R NBH T REF _ C L KN_ R
64
Z 0 20 8
59 58 57
SEL _ HT 6 6 SEL _ SAT A SEL _ 27 M Hz
G G G G G
ND ND ND ND ND
R N 32 1 2 R 17 6
R 1 58
4 * 0_ 4P 2 R _0 4_ 4 mil _ sh o rt 3
NBHT_CLKP 10 NBHT_CLKN 10
3 3 _ 1 % _0 4
CLK_48M_USB 15
1 58 _1 % _ 06
NB_OSC 10 RS780 1.1V
5 6 7 8 9
R1 5 1 9 0.9 _ 1 % _ 06
IC S9 LP RS4 8 0
R 44 6 *0 _ 0 4 02 _ 5 m i l_ s ho rt
SB_14.318M_OSC 14
0514-J addfor SB710
CL K _ VD D
C L K_ VDD * d e fa u lt
R 14 2 R1 3 4 * 8.2 K_ 0 4 15 ,1 8 P C I E _ E X P C A R D _ C L K R E Q # 1 8 W L AN _ CL KRE Q#
R1 3 5 *8 .2 K_ 04 PC IE_ EXPCA RD _C L KREQ # W L AN _ CL KR EQ#
SE L_ H T6 6 * 8 .2 K_0 4 SE L_ SAT A SE L _ 2 7 MH z
R1 6 0
* 8 .2K _0 4
R1 4 3
8 .2K _0 4
1
6 6 MH z 3 .3 V s i ngl e en d e d HT T c ol c k
0*
1 0 0M Hz d fi fe re n tial H TT c lo ck
SEL _ HT T 6 6
SEL _ SA T A
1
1 0 0 MH zn o n -s pre a d ing d i ff ere n ti a lS ATA clo c k
0 * 1 0 0 MH z s p re a din g d fi fe re n tia l SR C c l oc k 1 * 2 7 M Hz sin g el d c loc k SEL _ 2 7M Hz
R 15 0 8 .2 K_ 0 4
R1 5 9
R1 5 2
* 8 .2K _0 4
* 8. 2K_ 0 4
0
1 0 0 MH z s p re a din g d fi fe re n tia l SR C c l oc k
Clock Generator B - 3
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
CPU-1 U15A
1.2VS D1 D2 D3 D4
1.5A 60MIL
s m a r g a i D c i t a m e h c S . B
Sheet 3 of 35 CPU-1
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
HT_NB_CPU_CAD_H0 HT_NB_CPU_CAD_L0 HT_NB_CPU_CAD_H1 HT_NB_CPU_CAD_L1 HT_NB_CPU_CAD_H2 HT_NB_CPU_CAD_L2 HT_NB_CPU_CAD_H3 HT_NB_CPU_CAD_L3 HT_NB_CPU_CAD_H4 HT_NB_CPU_CAD_L4 HT_NB_CPU_CAD_H5 HT_NB_CPU_CAD_L5 HT_NB_CPU_CAD_H6 HT_NB_CPU_CAD_L6 HT_NB_CPU_CAD_H7 HT_NB_CPU_CAD_L7 HT_NB_CPU_CAD_H8 HT_NB_CPU_CAD_L8 HT_NB_CPU_CAD_H9 HT_NB_CPU_CAD_L9 HT_NB_CPU_CAD_H10 HT_NB_CPU_CAD_L10 HT_NB_CPU_CAD_H11 HT_NB_CPU_CAD_L11 HT_NB_CPU_CAD_H12 HT_NB_CPU_CAD_L12 HT_NB_CPU_CAD_H13 HT_NB_CPU_CAD_L13 HT_NB_CPU_CAD_H14 HT_NB_CPU_CAD_L14 HT_NB_CPU_CAD_H15 HT_NB_CPU_CAD_L15
9 9 9 9
HT_NB_CPU_CLK_H0 HT_NB_CPU_CLK_L0 HT_NB_CPU_CLK_H1 HT_NB_CPU_CLK_L1
E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5 J3 J2 J5 K5 N1 P1 P3 P4
9 HT_NB_CPU_CT L_H0 9 HT_NB_CPU_CT L_L0 9 HT_NB_CPU_CT L_H1 9 HT_NB_CPU_CT L_L1
VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3
1.2VS HTLI NK
L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15
VLDT _B0 VLDT _B1 VLDT _B2 VLDT _B3
L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15
L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1
L0_CLKOUT_H0 L0_CLKO UT_L0 L0_CLKOUT_H1 L0_CLKO UT_L1
L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1
L0_CTLOUT_ H0 L0_CTLOUT_ L0 L0_CTLOUT_ H1 L0_CTLOUT_ L1
AE2 AE3 AE4 AE5
1.5A 60MIL
AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W 2 W 3 V 1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W 5 V 4 V 3 V 5 U5 T4 T3
HT_CPU_NB_C AD_H0 9 HT_CPU_NB_C AD_L0 9 HT_CPU_NB_C AD_H1 9 HT_CPU_NB_C AD_L1 9 HT_CPU_NB_C AD_H2 9 HT_CPU_NB_C AD_L2 9 HT_CPU_NB_C AD_H3 9 HT_CPU_NB_C AD_L3 9 HT_CPU_NB_C AD_H4 9 HT_CPU_NB_C AD_L4 9 HT_CPU_NB_C AD_H5 9 HT_CPU_NB_C AD_L5 9 HT_CPU_NB_C AD_H6 9 HT_CPU_NB_C AD_L6 9 HT_CPU_NB_C AD_H7 9 HT_CPU_NB_C AD_L7 9 HT_CPU_NB_C AD_H8 9 HT_CPU_NB_C AD_L8 9 HT_CPU_NB_C AD_H9 9 HT_CPU_NB_C AD_L9 9 HT_CPU_NB_C AD_H10 9 HT_CPU_NB_C AD_L10 9 HT_CPU_NB_C AD_H11 9 HT_CPU_NB_C AD_L11 9 HT_CPU_NB_C AD_H12 9 HT_CPU_NB_C AD_L12 9 HT_CPU_NB_C AD_H13 9 HT_CPU_NB_C AD_L13 9 HT_CPU_NB_C AD_H14 9 HT_CPU_NB_C AD_L14 9 HT_CPU_NB_C AD_H15 9 HT_CPU_NB_C AD_L15 9
Y1 W 1 Y4 Y3
HT_CPU_NB_C LK_H0 HT_CPU_NB_C LK_L0 HT_CPU_NB_C LK_H1 HT_CPU_NB_C LK_L1
R2 R3 T5 R5
HT_CPU_NB_C TL_H0 9 HT_CPU_NB_C TL_L0 9 HT_CPU_NB_C TL_H1 9 HT_CPU_NB_C TL_L1 9
SOCKET_638_P IN
* I f VL D T i s c o n n e c t e d o n l y o n o n e s i d e , o n e 4. 7u F c ap s h o u l d b e a d d e d t o the island side 1.2VS
4.7U_6. 3V_06 C440
4. 7U _6.3V_06 C443
4.7U_6.3V_06
C447
.22U_10V_04 C452
.22 U_10V_04
Place close to socket
B - 4 CPU-1
C451
9 9 9 9
C442
180P_NPO_50V_04
C441 180P_NPO_50V _04
Schematic Diagrams
CPU-2 VTT 750mA
Processor Memory Interface
VTT 7 5 0m A
U1 5C 8 M EM_ M B_D AT A[0 ..63 ]
0 .9 V
0 .9 V
U 15 B D10 C10 B1 0 AD 1 0
PLACETHEM CLOSETO CPUWITHIN1" R3 0 1 R2 9 3
1.8 V
3 9. 2 _ 1% _ 04 3 9. 2 _ 1% _ 04
VTT 1 VTT 2 VTT 3 VTT 4
AF 1 0 AE1 0
M_ZP M_ZN
MEM Z P MEM Z N
MEM _ MA_ RE SET # H 1 6 7 M EM_ M A0 _O DT 0 7 M EM_ M A0 _O DT 1
MEM _ MA1 _ OD T0 MEM _ MA1 _ OD T1
7 M EM_ M A0 _C S# 0 7 M EM_ M A0 _C S# 1
Z 0 4 01 Z 0 4 02
Z 0 4 03 Z 0 4 04 7 7 7 7
ME M_ MA_ C ME M_ MA_ C ME M_ MA_ C ME M_ MA_ C
T19 V2 2 U21 V1 9 T20 U19 U20 V2 0
LK1 _ P LK1 _ N LK7 _ P LK7 _ N
7 M EM_ MA_ AD D[0 ..1 5 ]
Z 0 4 05 Z 0 4 06 MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM
_ MA_ AD D0 _ MA_ AD D1 _ MA_ AD D2 _ MA_ AD D3 _ MA_ AD D4 _ MA_ AD D5 _ MA_ AD D6 _ MA_ AD D7 _ MA_ AD D8 _ MA_ AD D9 _ MA_ AD D1 0 _ MA_ AD D1 1 _ MA_ AD D1 2 _ MA_ AD D1 3 _ MA_ AD D1 4 _ MA_ AD D1 5
R SVD_ M2
MA_ MA_ MA_ MA_ MA_ MA_ MA_ MA_ MA_ MA_ MA_ MA_ MA_ MA_ MA_ MA_
R20 R23 J21 R19 T22 T24
7 ME M_ MA_ R AS# 7 ME M_ MA_ C AS# 7 ME M_ MA_ W E#
M EMV REF
MB0 _ OD T0 MB0 _ OD T1 MB1 _ OD T0 M B0 _C S_ L0 M B0 _C S_ L1 M B1 _C S_ L0 M B_ CKE0 M B_ CKE1
MA_ CL K_ H5 MA_ CL K_ L 5 MA_ CL K_ H1 MA_ CL K_ L 1 MA_ CL K_ H7 MA_ CL K_ L 7 MA_ CL K_ H4 MA_ CL K_ L 4
N21 M20 N22 M19 M22 L20 M24 L21 L19 K2 2 R21 L22 K2 0 V2 4 K2 4 K1 9
7 ME M_ MA_ BAN K0 7 ME M_ MA_ BAN K1 7 ME M_ MA_ BAN K2
VT T _SE NSE
MA0 _ OD T0 MA0 _ OD T1 MA1 _ OD T0 MA1 _ OD T1
MA_ CKE 0 MA_ CKE 1
N19 N20 E1 6 F16 Y16 AA1 6 P1 9 P2 0
VT T5 VT T6 VT T7 VT T8 VT T9
RSVD _M 1
MA0 _ CS_ L 0 MA0 _ CS_ L 1 MA1 _ CS_ L 0 MA1 _ CS_ L 1
J22 J20
7 M EM_ M A_ CKE0 7 M EM_ M A_ CKE1
MEM :CM D/C T RL /CL K
MB_ CL K_ H5 M B_ CL K_ L5 MB_ CL K_ H1 M B_ CL K_ L1 MB_ CL K_ H7 M B_ CL K_ L7 MB_ CL K_ H4 M B_ CL K_ L4
ADD 0 ADD 1 ADD 2 ADD 3 ADD 4 ADD 5 ADD 6 ADD 7 ADD 8 ADD 9 ADD 1 0 ADD 1 1 ADD 1 2 ADD 1 3 ADD 1 4 ADD 1 5
M B_A DD0 M B_A DD1 M B_A DD2 M B_A DD3 M B_A DD4 M B_A DD5 M B_A DD6 M B_A DD7 M B_A DD8 M B_A DD9 M B_ ADD 10 M B_ ADD 11 M B_ ADD 12 M B_ ADD 13 M B_ ADD 14 M B_ ADD 15
MA_ BAN K0 MA_ BAN K1 MA_ BAN K2
M B_ BANK0 M B_ BANK1 M B_ BANK2
MA_ RAS _L MA_ CAS _L MA_ W E_ L
MB_ R AS_L MB_ C AS_L M B_W E_L
W 10 A C1 0 A B10 A A10 A 10 Y10
Z0407
CPU _M _ VREF _ SU S
W 17 B 18
M EM_ MB _R ESET #
W 26 W 23 Y 2 6 M EM_ MB 1_ O DT 0
MEM _ MB0 _ OD T0 8 MEM _ MB0 _ OD T1 8
V 26 W 25 U22 Z0408
MEM _ MB0 _ CS# 0 8 MEM _ MB0 _ CS# 1 8
J25 H26
MEM _ MB_ CKE 0 8 MEM _ MB_ CKE 1 8
P 22 R22 A 17 A 18 A F 18 A F 17 R26 R25
Z0409 Z0410
P 24 N24 P 26 N23 N26 L23 N25 L24 M26 K 26 T26 L26 L25 W 24 J23 J24
MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM
MEM MEM MEM MEM
Z0411 Z0412
_ MB_ CL K1 _P _ MB_ CL K1 _ N _ MB_ CL K7 _P _ MB_ CL K7 _ N
8 8 8 8
M E M _ M B _ A D D [ 0 . . 1 5]
_M B_ ADD 0 _M B_ ADD 1 _M B_ ADD 2 _M B_ ADD 3 _M B_ ADD 4 _M B_ ADD 5 _M B_ ADD 6 _M B_ ADD 7 _M B_ ADD 8 _M B_ ADD 9 _M B_ ADD 1 0 _M B_ ADD 1 1 _M B_ ADD 1 2 _M B_ ADD 1 3 _M B_ ADD 1 4 _M B_ ADD 1 5
R24 U26 J26
M E M _ M B _B A N K 0 M E M _ M B _B A N K 1 M E M _ M B _B A N K 2
U25 U24 U23
0 M M I D - t e O S k c o o T s
8
8 8 8
MEM _ MB_ RAS # 8 MEM _ MB_ CAS # 8 M E M _ M B _W E # 8
SO CK E T_ 6 3 8_ PIN 8 MEM _M B_ DM [0. .7] 1.8 V
R 97 1K_ 0 4 _1 %
W i d t h 2 0 m i l , l e n g t h < 6 i n ch CPU _ M_ VREF _SU S
C 11 5
C 10 5
R9 6 1K_ 0 4 _1 %
.1U _ X7 R _1 0 V_ 04
0 .9 V
C 13 8 1 0U _1 0 V_ 0 8
1 0 00 P_ X7 R_ 5 0V_ 0 4
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM
_M _M _M _M _M _M _M _M _M _M _M _M _M _M _M _M
B_ B_ B_ B_ B_ B_ B_ B_ B_ B_ B_ B_ B_ B_ B_ B_
DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ
S0 S0 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S7 S7
_P _N _P _N _P _N _P _N _P _N _P _N _P _N _P _N
M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM _ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM _ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM _ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM _ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D M EM_ MB_ D
AT A0 AT A1 AT A2 AT A3 AT A4 AT A5 AT A6 AT A7 AT A8 AT A9 AT A10 AT A11 AT A12 AT A13 AT A14 AT A15 AT A16 AT A 17 AT A18 AT A19 AT A20 AT A 21 AT A22 AT A23 AT A24 AT A25 AT A26 AT A27 AT A28 AT A29 AT A30 AT A31 AT A32 AT A33 AT A34 AT A35 AT A36 AT A37 AT A38 AT A39 AT A40 AT A41 AT A42 AT A43 AT A44 AT A45 AT A46 AT A47 AT A48 AT A49 AT A 50 AT A51 AT A52 AT A53 AT A 54 AT A55 AT A56 AT A57 AT A58 AT A59 AT A60 AT A61 AT A62 AT A63
C1 1 A1 1 A1 4 B1 4 G1 1 E1 1 D1 2 A1 3 A1 5 A1 6 A1 9 A2 0 C1 4 D1 4 C1 8 D1 8 D2 0 A2 1 D2 4 C2 5 B2 0 C2 0 B2 4 C2 4 E2 3 E2 4 G2 5 G2 6 C2 6 D2 6 G2 3 G2 4 AA2 4 AA2 3 AD2 4 AE2 4 AA2 6 AA2 5 AD2 6 AE2 5 AC2 2 AD2 2 AE2 0 AF 2 0 AF 2 4 AF 2 3 AC2 0 AD2 0 AD1 8 AE1 8 AC1 4 AD1 4 AF 1 9 AC1 8 AF 1 6 AF 1 5 AF 1 3 AC1 2 AB1 1 Y1 1 AE1 4 AF 1 4 AF 1 1 AD1 1
M M M M M M M M
M0 M1 M2 M3 M4 M5 M6 M7
A1 2 B1 6 A2 2 E2 5 AB2 6 AE2 2 AC1 6 AD1 2
EM_ EM_ EM_ EM_ EM_ EM_ EM_ EM_
MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_
D D D D D D D D
C1 2 B1 2 D1 6 C1 6 A2 4 A2 3 F26 E2 6 AC2 5 AC2 6 AF 2 1 AF 2 2 AE1 6 AD1 6 AF 1 2 AE1 2
MEM :DAT A MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_
D ATA 0 D ATA 1 D ATA 2 D ATA 3 D ATA 4 D ATA 5 D ATA 6 D ATA 7 D ATA 8 D ATA 9 D ATA 10 D ATA 11 D ATA 12 D ATA 13 D ATA 14 D ATA 15 D ATA 16 D ATA 17 D ATA 18 D ATA 19 D ATA 20 D ATA 21 D ATA 22 D ATA 23 D ATA 24 D ATA 25 D ATA 26 D ATA 27 D ATA 28 D ATA 29 D ATA 30 D ATA 31 D ATA 32 D ATA 33 D ATA 34 D ATA 35 D ATA 36 D ATA 37 D ATA 38 D ATA 39 D ATA 40 D ATA 41 D ATA 42 D ATA 43 D ATA 44 D ATA 45 D ATA 46 D ATA 47 D ATA 48 D ATA 49 D ATA 50 D ATA 51 D ATA 52 D ATA 53 D ATA 54 D ATA 55 D ATA 56 D ATA 57 D ATA 58 D ATA 59 D ATA 60 D ATA 61 D ATA 62 D ATA 63
MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_
D D D D D D D D
MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_ MB_
D QS_ H0 D QS_ L 0 D QS_ H1 D QS_ L 1 D QS_ H2 D QS_ L 2 D QS_ H3 D QS_ L 3 D QS_ H4 D QS_ L 4 D QS_ H5 D QS_ L 5 D QS_ H6 D QS_ L 6 D QS_ H7 D QS_ L 7
M0 M1 M2 M3 M4 M5 M6 M7
MA _D AT A0 MA _D AT A1 MA _D AT A2 MA _D AT A3 MA _D AT A4 MA _D AT A5 MA _D AT A6 MA _D AT A7 MA _D AT A8 MA _D AT A9 M A_ DAT A1 0 M A_ DAT A1 1 M A_ DAT A1 2 M A_ DAT A1 3 M A_ DAT A1 4 M A_ DAT A1 5 M A_ DAT A1 6 M A_ DAT A1 7 M A_ DAT A1 8 M A_ DAT A1 9 M A_ DAT A2 0 M A_ DAT A2 1 M A_ DAT A2 2 M A_ DAT A2 3 M A_ DAT A2 4 M A_ DAT A2 5 M A_ DAT A2 6 M A_ DAT A2 7 M A_ DAT A2 8 M A_ DAT A2 9 M A_ DAT A3 0 M A_ DAT A3 1 M A_ DAT A3 2 M A_ DAT A3 3 M A_ DAT A3 4 M A_ DAT A3 5 M A_ DAT A3 6 M A_ DAT A3 7 M A_ DAT A3 8 M A_ DAT A3 9 M A_ DAT A4 0 M A_ DAT A4 1 M A_ DAT A4 2 M A_ DAT A4 3 M A_ DAT A4 4 M A_ DAT A4 5 M A_ DAT A4 6 M A_ DAT A4 7 M A_ DAT A4 8 M A_ DAT A4 9 M A_ DAT A5 0 M A_ DAT A5 1 M A_ DAT A5 2 M A_ DAT A5 3 M A_ DAT A5 4 M A_ DAT A5 5 M A_ DAT A5 6 M A_ DAT A5 7 M A_ DAT A5 8 M A_ DAT A5 9 M A_ DAT A6 0 M A_ DAT A6 1 M A_ DAT A6 2 M A_ DAT A6 3 M M M M M M M M
A_ A_ A_ A_ A_ A_ A_ A_
DM DM DM DM DM DM DM DM
0 1 2 3 4 5 6 7
M A_D QS _H MA_ D QS_ L M A_D QS _H MA_ D QS_ L M A_D QS _H MA_ D QS_ L M A_D QS _H MA_ D QS_ L M A_D QS _H MA_ D QS_ L M A_D QS _H MA_ D QS_ L M A_D QS _H MA_ D QS_ L M A_D QS _H MA_ D QS_ L
0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
G1 2 F12 H1 4 G1 4 H1 1 H1 2 C1 3 E1 3 H1 5 E1 5 E1 7 H1 7 E1 4 F14 C1 7 G1 7 G1 8 C1 9 D2 2 E2 0 E1 8 F18 B2 2 C2 3 F20 F22 H2 4 J1 9 E2 1 E2 2 H2 0 H2 2 Y2 4 AB2 4 AB2 2 AA2 1 W22 W21 Y2 2 AA2 2 Y2 0 AA2 0 AA1 8 AB1 8 AB2 1 AD2 1 AD1 9 Y1 8 AD1 7 W16 W14 Y1 4 Y1 7 AB1 7 AB1 5 AD1 5 AB1 3 AD1 3 Y1 2 W11 AB1 4 AA1 4 AB1 2 AA1 2 E1 2 C1 5 E1 9 F24 AC2 4 Y1 9 AB1 6 Y1 3 G1 3 H1 3 G1 6 G1 5 C2 2 C2 1 G2 2 G2 1 AD2 3 AC2 3 AB1 9 AB2 0 Y1 5 W15 W12 W13
ME M_ MA_ D ATA0 ME M_ MA_ D ATA1 ME M_ MA_ D ATA2 ME M_ MA_ D ATA3 ME M_ MA_ D ATA4 ME M_ MA_ D ATA5 ME M_ MA_ D ATA6 ME M_ MA_ D ATA7 ME M_ MA_ D ATA8 ME M_ MA_ D ATA9 MEM _M A_ DAT A1 0 MEM _M A_ DAT A1 1 MEM _M A_ DAT A1 2 ME M_ MA_ D ATA1 3 ME M_ MA_ D ATA1 4 ME M_ MA_ D ATA1 5 ME M_ MA_ D ATA1 6 ME M_ MA_ D ATA1 7 ME M_ MA_ D ATA1 8 ME M_ MA_ D ATA1 9 ME M_ MA_ D ATA2 0 ME M_ MA_ D ATA2 1 ME M_ MA_ D ATA2 2 ME M_ MA_ D ATA2 3 ME M_ MA_ D ATA2 4 ME M_ MA_ D ATA2 5 ME M_ MA_ D ATA2 6 ME M_ MA_ D ATA2 7 ME M_ MA_ D ATA2 8 ME M_ MA_ D ATA2 9 ME M_ MA_ D ATA3 0 ME M_ MA_ D ATA3 1 ME M_ MA_ D ATA3 2 ME M_ MA_ D ATA3 3 ME M_ MA_ D ATA3 4 ME M_ MA_ D ATA3 5 ME M_ MA_ D ATA3 6 ME M_ MA_ D ATA3 7 ME M_ MA_ D ATA3 8 ME M_ MA_ D ATA3 9 ME M_ MA_ D ATA4 0 ME M_ MA_ D ATA4 1 ME M_ MA_ D ATA4 2 ME M_ MA_ D ATA4 3 ME M_ MA_ D ATA4 4 ME M_ MA_ D ATA4 5 ME M_ MA_ D ATA4 6 ME M_ MA_ D ATA4 7 ME M_ MA_ D ATA4 8 ME M_ MA_ D ATA4 9 ME M_ MA_ D ATA5 0 ME M_ MA_ D ATA5 1 ME M_ MA_ D ATA5 2 ME M_ MA_ D ATA5 3 ME M_ MA_ D ATA5 4 ME M_ MA_ D ATA5 5 ME M_ MA_ D ATA5 6 ME M_ MA_ D ATA5 7 ME M_ MA_ D ATA5 8 ME M_ MA_ D ATA5 9 ME M_ MA_ D ATA6 0 ME M_ MA_ D ATA6 1 ME M_ MA_ D ATA6 2 ME M_ MA_ D ATA6 3 M M M M M M M M
EM EM EM EM EM EM EM EM
_M _M _M _M _M _M _M _M
A_ A_ A_ A_ A_ A_ A_ A_
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
M EM_ MA_ D AT A[0.. 63 ] 7
Sheet 4 of 35 CPU-2
1 M M I D - t O e S k c o o T s
M EM_ MA_ D M[0 ..7 ] 7
MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM
_M _M _M _M _M _M _M _M _M _M _M _M _M _M _M _M
A_ DQ S0_ A_ DQ S0_ A_ DQ S1_ A_ DQ S1_ A_ DQ S2_ A_ DQ S2_ A_ DQ S3_ A_ DQ S3_ A_ DQ S4_ A_ DQ S4_ A_ DQ S5_ A_ DQ S5_ A_ DQ S6_ A_ DQ S6_ A_ DQ S7_ A_ DQ S7_
P N P N P N P N P N P N P N P N
7 7
7 7
7 7 7 7 7
7 7 7
7 7 7 7
Place close to socket SO CKET _ 6 38 _ PIN 4 .7 U_ 6 .3V _0 6 C4 9 1
*4 .7U _ 6.3 V_ 0 6
C 49 9
4 .7 U_ 6 .3 V_0 6 C4 9 3
4.7 U _6 .3 V_ 0 6
C 50 0
.2 2 U_ 1 0 V_0 4 C4 9 2
* .22 U _1 0 V_ 0 4
C 4 85
.2 2 U_ 1 0 V _ 04 C4 7 7
*.2 2 U_ 1 0 V_0 4
1 0 0 0P _X7 R_ 5 0 V_0 4
C 4 89
C8 5
C4 95
* 1 00 0 P_ X7 R _5 0 V_ 0 4
10 0 0 P_X7 R_ 5 0 V_ 04 C 47 8
C4 8 3
*1 00 0 P_ X7R _ 50 V_ 0 4
18 0 P_ NPO _ 50 V_ 0 4 C 48 4
C8 6
18 0 P_ NPO _ 50 V_ 0 4
1 8 0 P_N PO_ 5 0 V_ 04 C 49 0
C4 8 8
*1 8 0P_ N PO_ 5 0 V_0 4
CPU-2 B - 5
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
CPU-4 U 15 F U1 5 E
CPU _VD D0
VDD0CORE 0.375-1.500V 18A
G4 H2
VD D0 _1 VD D0 _2
VD D1 _ 1 VD D1 _ 2
VD D0 _3 VD D0 _4 VD D0 _5 VD D0 _6
VD D1 _ 3 VD D1 _ 4 VD D1 _ 5 VD D1 _ 6
VD D0 _7 VD D0 _8 VD D0 _9 VD D0 _1 0 VD D0 _1 1 VD D0 _1 2
VD D1 _ 7 VD D1 _ 8 VD D1 _ 9 VDD 1_ 1 0 VDD 1_ 1 1 VDD 1_ 1 2
VD D0 _1 3 VD D0 _1 4 VD D0 _1 5 VD D0 _1 6
VDD 1_ 1 3 VDD 1_ 1 4 VDD 1_ 1 5 VDD 1_ 1 6
VD D0 _1 7 VD D0 _1 8 VD D0 _1 9 VD D0 _2 0
VDD 1_ 1 7 VDD 1_ 1 8 VDD 1_ 1 9 VDD 1_ 2 0
VD D0 _2 1 VD D0 _2 2 VD D0 _2 3
K1 6 M1 6 P1 6
VDD 1_ 2 1 VDD 1_ 2 2 VDD 1_ 2 3 VDD 1_ 2 4
VD DNB _1 VD DNB _2
VDD 1_ 2 5 VDD 1_ 2 6
T16 V1 6
VD DNB _3 VD DNB _4
VDD IO2 7
J9 J11 J13 J15 K6 K1 0 K1 2 K1 4 L4 L7 L9 L11 L13 L15
CPU_VDDNB 3A C PU_ VDD NB
1 .8 V
M2 M6 M8 M1 0 N7 N9 N1 1
VD DNB _5 VD DIO1 VD DIO2 VD DIO3 VD DIO4 VD DIO5 VD DIO6 VD DIO7
VDD IO2 6 VDD IO2 5 VDD IO2 4 VDD IO2 3 VDD IO2 2 VDD IO2 1 VDD IO2 0 VDD IO1 9 VDD IO1 8
VD DIO8 VD DIO9 VD DIO1 0 VD DIO1 1
VDD IO1 7 VDD IO1 6 VDD IO1 5 VDD IO1 4
VD DIO1 2
VDD IO1 3
H2 5 J17 K1 8
VDDIO 2A
CPU _ VDD 1
K2 1 K2 3 K2 5 L17 M1 8 M2 1 M2 3 M2 5 N1 7
AA4 A A11
P8 P1 0
VDD1CORE 1.375-1.500V 18A
R4 R7 R9 R1 1
A A13 A A15 A A17 A A19 AB2 AB7
T2 T6 T8 T 10
AB9 A B23 A B25 AC 11
T 12 T 14
AC 13 AC 15
U7 U9
AC 17 AC 19
U1 1 U1 3
AC 21 AD6
U1 5 V6 V8
AD8 AD 25 A E11
V1 0 V1 2
A E13 A E15
V1 4 W4
A E17 A E19
Y2 AC4 AD2
A E21 A E23 B4 B6
1 .8V
Y2 5 V2 5 V2 3 V2 1 V1 8 U1 7 T 25 T 23
VDDIO 2A
SS1 SS2 SS3 SS4
VSS VSS VSS VSS
66 67 68 69
V V V V
SS5 SS6 SS7 SS8
VSS VSS VSS VSS
70 71 72 73
V SS9 V SS10 V SS11 V SS12 V SS13 V SS14
VSS VSS VSS VSS VSS VSS
74 75 76 77 78 79
V SS15 V SS16 V SS17 V SS18
VSS VSS VSS VSS
80 81 82 83
V SS19 V SS20 V SS21 V SS22
VSS VSS VSS VSS
84 85 86 87
V SS23 V SS24 V SS25 V SS26
VSS VSS VSS VSS
88 89 90 91
J6 J8 J10 J12 J14 J16
L6 L8 L10 L12
N 18 P2
B11 B13
V SS31 V SS32 V SS33 V SS34 V SS35 V SS36 V SS37 V SS38 V SS39
VSS 96 VSS 97 VSS 98 VSS 99 V SS1 00 V SS1 01 V SS1 02 V SS1 03 V SS1 04
P7 P9
V SS40 V SS41 V SS42 V SS43
V SS1 05 V SS1 06 V SS1 07 V SS1 08
V SS44 V SS45 V SS46 V SS47
V SS1 09 V SS1 10 V SS1 11 V SS1 12
V SS48 V SS49
V SS1 13 V SS1 14
E4 V SS50 F 2 V SS51 F 11 V SS52 F 13 V SS53 F 15 V SS54 F 17 V SS55 F 19 V SS56 F 21 V SS57
V SS1 15 V SS1 16
U 14 U 16
V SS1 17 V SS1 18 V SS1 19 V SS1 20 V SS1 21 V SS1 22
U 18 V2
F 23 V SS58 F 25 V SS59 H7 V SS60 H9 V SS61
V SS1 23 V SS1 24
V1 5 V1 7
V SS1 25 V SS1 26
W6 Y 21
V SS62 V SS63 V SS64 V SS65
V SS1 27 V SS1 28 V SS1 29
Y 23 N6
D6 D8 D9 D 11
P1 8
D 13 D 15
D 21 D 23 D 25
H 21 H 23 J4
SOC K ET _6 3 8 _P I N
C 35
C 98
1 80 P_ NP O_ 50 V_ 0 4 C 5 94 C7 7
.0 1 U_ 1 6V _0 4
* 1 0U _6 .3 V_ 0 6
C9 1
1 0U _ 6.3 V_ 0 6 1 0U _ 6. 3V_ 0 6 CP U_ VDD 1
C5 95
10 U _6 .3 V_ 06
* 1 0U _ 6.3 V_ 0 6
1 0 U_ 6 .3V _0 6
.22 U _1 0 V_ 0 4
AC 6 M 17
VSS 94 VSS 95
R1 7 P2 5 P2 3 P2 1
C 99
M7 M9
VSS 92 VSS 93
B23 B25
C 97
L14 L16 L18
V SS29 V SS30
B19 B21
.22 U _1 0 V_ 0 4 C3 4
K1 5 K1 7
V SS27 V SS28
T 21 T 18
CP U_ VDD 0
K7 K9 K1 1 K1 3
B8 B9
B15 B17
BOTTOM SIDE DECOUPLING
J18 K2
N4 N8 N 10 N 16
D 17 D 19 SO CK ET _ 6 38 _ PIN
V V V V
C9 2
C 10 0
C 93
C 79
C9 4
1 0 U_ 6 .3 V_ 061 0 U_ 6. 3V_ 0 6 1 0 U_ 6 .3V_ 0 6 1 0 U_ 6 .3V _0 6
CP U_ V DD NB
1 8 0 P_N PO_ 5 0 V_ 04 C6 5
C 78
.0 1 U_ 1 6V _0 4
C 5 96
C5 97
Sheet 6 of 35 CPU-4
*1 0 U_ 6 .3 V_0 6 * 1 0U _ 6.3 V_ 0 6
1.8 V
P1 1 P1 7 R8 R 10
.2 2 U_ 1 0 V_0 4
R 16 R 18 T7 T9 T11 T13
C1 02
1 0 U_ 6 .3 V_ 06
C103
C 13 2
C 13 3
C1 1 8
C 1 04
1 0 U_ 6 .3V_ 0 6 1 0 U_ 6 .3V_ 0 6 1 0 U_ 6 .3V _0 6 .2 2 U_ 1 0V _0 4
C 1 12
1 8 0 P_ X7 R_ 5 0 V_ 04 C1 1 3
1 8 0 P_X7 R_ 5 0 V_ 04
T15 T17 U4 U6 U8 U 10 U 12
V7 V9 V1 1 V1 3
DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE 1 .8 V
4.7 U _6 .3 V_ 06 C 1 25
C1 2 0
4 .7U _ 6.3 V_ 0 6 * 4 .7U _ 6.3 V_ 0 6
.2 2 U_ 1 0V _0 4 C1 2 8
4 .7 U_ 6 .3V _0 6
C 12 9
C1 1 7
*.2 2 U_ 1 0V _0 4 C 11 6
.2 2 U_ 1 0V _0 4
C1 2 4
.0 1 U_ 1 6 V_0 4 C 1 11
* .22 U _1 0 V_ 0 4
C1 1 4
1 80 P_ N PO_ 5 0V_ 0 4 C 1 21
C1 1 0
.0 1U _ 16 V_ 0 4
CPU-4 B - 7
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
DDRII SO-DIMM_0 SO-DIMM 0 4 ME M_MA _ ADD[0 ..1 5]
MEM_ MA _A DD0 MEM_ MA _A DD1 MEM_ MA _A DD2 MEM_ MA _A DD3 MEM_ MA _A DD4 MEM_ MA _A DD5 MEM_ MA _A DD6 MEM_ MA _A DD7 MEM_ MA _A DD8 MEM_ MA _A DD9 MEM_ MA _A DD10 MEM_ MA _A DD11 MEM_ MA _A DD12 MEM_ MA _A DD13 MEM_ MA _A DD14 MEM_ MA _A DD15 MEM_ MA _B A NK2
4 ME M_MA _B A NK [ 0 ..2]
s m a r g a i D c i t a m e h c S . B
4 4 4 4 4 4
Sheet 7 of 35 DDRII SO-DIMM_0
MEM_ MA _B A NK0 MEM_ MA _B A N K1 MEM_ MA 0_C S# 0 MEM_ MA 0_C S# 1 MEM _MA _CL K1 _P MEM _MA _CL K1 _N MEM _MA _CL K7 _P MEM _MA _CL K7 _N MEM _MA _CK E 0 MEM _MA _CK E 1 MEM_ MA _CA S # MEM_ MA _RA S # MEM_ MA _W E# SA 0 _DIM0_ 1 SA 1 _DIM0_ 1 SCL K 0 SDA T A0
ME M_MA 0 _CS #0 ME M_MA 0 _CS #1 ME M_MA _ CLK 1_ P ME M_MA _ CLK 1_ N ME M_MA _ CLK 7_ P ME M_MA _ CLK 7_ N 4 ME M_MA _C KE 0 4 ME M_MA _C KE 1 4 MEM_ MA_ CA S# 4 MEM_ MA_ RA S# 4 MEM_ MA _W E#
R123
2 ,8,1 5 SCL K 0 R12 6 2 ,8,1 5 SDA T A0
10K _ 04
10 K _04
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195
MEM_ MA 0_O DT0 114 MEM_ MA 0_O DT1 119
4 ME M_MA 0_ ODT0 4 ME M_MA 0_ ODT1 4 MEM_ MA _DM[0..7 ]
MEM_ MA_ DM0 10 MEM_ MA_ DM1 26 MEM_ MA_ DM2 52 MEM_ MA_ DM3 67 MEM _ MA_ DM4 130 MEM_ MA_ DM5 147 MEM_ MA_ DM6 170 MEM_ MA_ DM7 185
4 4 4 4 4 4 4 4
MEM_ MA _DQS 0_ P MEM_ MA _DQS 1_ P MEM_ MA _DQS 2_ P MEM_ MA _DQS 3_ P MEM_ MA _DQS 4_ P MEM_ MA _DQS 5_ P MEM_ MA _DQS 6_ P MEM_ MA _DQS 7_ P
MEM _MA _DQS 0_ P 13 MEM _MA _DQS 1_ P 31 MEM _MA _DQS 2_ P 51 MEM _MA _DQS 3_ P 70 MEM _MA _DQS 4_ P 131 MEM _MA _DQS 5_ P 148 MEM _MA _DQS 6_ P 169 MEM _MA _DQS 7_ P 188
4 4 4 4 4 4 4 4
MEM_ MA _DQS 0_ N MEM_ MA _DQS 1_ N MEM_ MA _DQS 2_ N MEM_ MA _DQS 3_ N MEM_ MA _DQS 4_ N MEM_ MA _DQS 5_ N MEM_ MA _DQS 6_ N MEM_ MA _DQS 7_ N
MEM _MA _DQS 0_ N 11 MEM _MA _DQS 1_ N 29 MEM _MA _DQS 2_ N 49 MEM _MA _DQS 3_ N 68 MEM _MA _DQS 4_ N 129 MEM _MA _DQS 5_ N 146 MEM _MA _DQS 6_ N 167 MEM _MA _DQS 7_ N 186 1 .8V 112 111 117 96 95 118 81 82 87 103 88 104
3 .3V S
C18 9 2.2U _6.3 V_ 06
C1 90
199 .1U_X 7R_ 10 V_ 04
5 ,8 CP U_ME MHOT# MV REF _ DIM
Z 07 01 R12 5 *0_ 04 02_ 5m l i_s ho r t
83 120 50 69 163
MVRE F _DIM C159 2.2U_ 6.3V _ 06
C1 58
1
DIMM0 _GND0 201 DIMM0 _GND1 202
.1 U_X 7R_ 10 V_ 04
47 133 183 77 12 48 184 78 71 72 121 122 196 193 8
J_ DIMM_1 A A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 1 0/A P A11 A12 A13 A14 A15 A 1 6_B A 2 BA0 BA1 S0# S1# CK 0 CK 0 # CK 1 CK 1 # CK E 0 CK E 1 CA S # RA S # WE# SA0 SA1 S CL S DA ODT 0 ODT 1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS 0 DQS 1 DQS 2 DQS 3 DQS 4 DQS 5 DQS 6 DQS 7 DQS 0 # DQS 1 # DQS 2 # DQS 3 # DQS 4 # DQS 5 # DQS 6 # DQS 7 # 1-7 34 074 -1 J_ DIMM_1 B V DD1 V DD2 V DD3 V DD4 V DD5 V DD6 V DD7 V DD8 V DD9 V DD1 0 V DD1 1 V DD1 2 V DDS P D NC1 NC2 NC3 NC4 NCT E ST V RE F GND0 GND1
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 V S S 10 V S S 11 V S S 12 V S S 13 V S S 14 V S S 15 1-7 34 074 -1 1.8 V
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 12 3 12 5 13 5 13 7 12 4 12 6 13 4 13 6 14 1 14 3 15 1 15 3 14 0 14 2 15 2 15 4 15 7 15 9 17 3 17 5 15 8 16 0 17 4 17 6 17 9 18 1 18 9 19 1 18 0 18 2 19 2 19 4
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ1 0 DQ1 1 DQ1 2 DQ1 3 DQ1 4 DQ1 5 DQ1 6 DQ1 7 DQ1 8 DQ1 9 DQ2 0 DQ2 1 DQ2 2 DQ2 3 DQ2 4 DQ2 5 DQ2 6 DQ2 7 DQ2 8 DQ2 9 DQ3 0 DQ3 1 DQ3 2 DQ3 3 DQ3 4 DQ3 5 DQ3 6 DQ3 7 DQ3 8 DQ3 9 DQ4 0 DQ4 1 DQ4 2 DQ4 3 DQ4 4 DQ4 5 DQ4 6 DQ4 7 DQ4 8 DQ4 9 DQ5 0 DQ5 1 DQ5 2 DQ5 3 DQ5 4 DQ5 5 DQ5 6 DQ5 7 DQ5 8 DQ5 9 DQ6 0 DQ6 1 DQ6 2 DQ6 3
ME M_MA _DA T A0 ME M_MA _DA T A1 ME M_MA _DA T A2 ME M_MA _DA T A3 ME M_MA _DA T A4 ME M_MA _DA T A5 ME M_MA _DA T A6 ME M_MA _DA T A7 ME M_MA _DA T A8 ME M_MA _DA T A9 ME M_MA _DA T A1 0 ME M_MA _DA T A1 1 ME M_MA _DA T A1 2 ME M_MA _DA T A1 3 ME M_MA _DA T A1 4 ME M_MA _DA T A1 5 ME M_MA _DA T A2 0 ME M_MA _DA T A1 7 ME M_MA _DA T A1 8 ME M_MA _DA T A2 1 ME M_MA _DA T A2 3 ME M_MA _DA T A2 2 ME M_MA _DA T A1 9 ME M_MA _DA T A1 6 ME M_MA _DA T A2 4 ME M_MA _DA T A2 5 ME M_MA _DA T A2 7 ME M_MA _DA T A2 6 ME M_MA _DA T A2 8 ME M_MA _DA T A2 9 ME M_MA _DA T A3 0 ME M_MA _DA T A3 1 ME M_MA _DA T A3 2 ME M_MA _DA T A3 8 ME M_MA _DA T A3 3 ME M_MA _DA T A3 4 ME M_MA _DA T A3 6 ME M_MA _DA T A3 7 ME M_MA _DA T A3 5 ME M_MA _DA T A3 9 ME M_MA _DA T A4 0 ME M_MA _DA T A4 1 ME M_MA _DA T A4 2 ME M_MA _DA T A4 3 ME M_MA _DA T A4 4 ME M_MA _DA T A4 5 ME M_MA _DA T A4 6 ME M_MA _DA T A4 7 ME M_MA _DA T A4 8 ME M_MA _DA T A4 9 ME M_MA _DA T A5 0 ME M_MA _DA T A5 1 ME M_MA _DA T A5 2 ME M_MA _DA T A5 3 ME M_MA _DA T A5 4 ME M_MA _DA T A5 5 ME M_MA _DA T A5 6 ME M_MA _DA T A5 7 ME M_MA _DA T A6 2 ME M_MA _DA T A5 8 ME M_MA _DA T A6 0 ME M_MA _DA T A6 1 ME M_MA _DA T A6 3 ME M_MA _DA T A5 9
0.9 V
M EM_ MA_ DA TA[0.. 63 ] 4
4 ME M_MA _ CKE 0
4 ME M_MA _ WE #
MEM_ MA _B A NK2
4 3
1 RN2 2 4 P2 RX4 7_ 04
MEM_ MA _A DD9 MEM_ MA _A DD12
4 3
1 RN3 2 4 P2 RX4 7_ 04
MEM _ MA _A DD8 MEM_ MA _A DD1
4 3
1 RN4 2 4 P2 RX4 7_ 04
MEM_ MA _A DD5 MEM_ MA _A DD3
4 3
1 RN5 2 4 P2 RX4 7_ 04
MEM_ MA _A DD10
4 3
1 RN6 2 4 P2 RX4 7_ 04
MEM_ MA _B A NK0
4 3
1 RN7 2 4 P2 RX4 7_ 04
4 3
1 RN8 2 4 P2 RX4 7_ 04
1 2
4 RN9 3 4 P2 RX4 7_ 04
4 ME M_MA _ CAS # 4 ME M_MA 0 _CS #1 4 ME M_MA 0 _ODT1 4 ME M_MA _ CKE 1
MEM_ MA _A DD15 MEM_ MA _A DD14 MEM_ MA _A DD7
1 2
4 RN1 0 3 4 P2 RX4 7_ 04
MEM_ MA _A DD11 MEM_ MA _A DD6
1 2
4 RN1 1 3 4 P2 RX4 7_ 04
MEM_ MA _A DD4 MEM _ MA _A DD2
1 2
4 RN1 2 3 4 P2 RX4 7_ 04
MEM_ MA _A DD0 MEM_ MA _B A NK1
1 2
4 RN1 3 3 4 P2 RX4 7_ 04
1 2
4 RN1 4 3 4 P2 RX4 7_ 04
1 2
4 RN1 5 3 4 P2 RX4 7_ 04
4 ME M_MA _ RAS # 4 ME M_MA 0 _CS #0 4 ME M_MA 0 _ODT0
MEM_ MA _A DD13
CLOSE
C1 64
*.1U_ X7R_1 0V_0 4 1 .8 V .1U_ X7R_10 V_04
C1 88 C1 73
*.1U_ X7R_1 0V_0 4 1 .8 V .1U_ X7R_10 V_04
C1 78
TO
*.1U_ X7R_1 0V_0 4 1 .8 V .1U_ X7R_10 V_04
C1 84 C1 81
*.1U_ X7R_1 0V_0 4 1 .8 V .1U_ X7R_10 V_04
C1 75 C1 83
*.1U_ X7R_1 0V_0 4 1 .8 V .1U_ X7R_10 V_04
C1 72 C1 87
*.1U_ X7R_1 0V_0 4 1 .8 V .01 U_1 6V_0 4
C1 86
SO-DIMM _0
.1 U_X 7R_ 10 V_ 04
C1 22
C10 9
.0 1U_ 16 V_ 04
C1 23
C127
* .1 U_X 7R_ 10 V_ 04
C13 0
C1 26
.1U_ X7 R _10 V _04 *.1U_ X7 R_1 0V _0 4 .1U_ X7 R_1 0V _0 4
4 ME M_MA _ CLK 7_ P
1.5P _ X7R_ 50 V _04
4 ME M_MA _ CLK 1_ P C1 01
tolerance 10% 1113
4 ME M_MA _ CLK 1_ N
1.5 P_ X7 R_50 V _0 4
0.9V
C1 65
1 0U_ 10 V_ 08
1 .8V
C1 79
C1 71
1 0U_ 10 V_ 08
.1U_ X7 R _10 V _04
C1 74
C1 77
.1U_ X7 R _10 V _04
0 _0 4
C15 7
C1 34 *.1 UF_ 16 V _04 5
+
6
U3 B *L M35 8 7 Z 0 703
MV RE F_ DIM *1 0_ 04 _1% R1 04
Width 20mil ,length <6inch MV RE F _DIM
-
4
C1 40 1 00 0P F _50 V _0 4 Z 0 70 4
R11 3 *1 0K _0 4 R1 08 R 11 0
* 0 _0 4
* 0 _ 04
C16 1 .1U_ X7 R_1 0V _0 4
C16 0 10 00 P_ X7 R_5 0V _0 4
C1 56
.1U_ X7R _10 V _04
C1 51
*.1U_ X7 R_1 0V _0 4
.01 U_16 V _0 4
C1 54 .1U_ X7R_ 10 V _04
1 .8 V
C1 48
1 00U_ 6.3 V_ B 2 1 0U_ 10 V_ 08
*.1U_ X7 R_1 0V _0 4
C1 55
.1U_ X7 R _10 V _04
1.8V
3 .3 V
Z 070 2
PLACE CLOSETO PROCESSOR WIT HIN 1 . 5 I N C H
C1 06
tolerance 10% 1113
4 ME M_MA _ CLK 7_ N
8
B - 8 DDRII SO-DIMM_0
*.1U_ X7R_1 0V_0 4 1 .8 V .1U_ X7R_10 V_04
C1 68
PLACE CLOSE TO SOCKET( PER EMI/EMC)
1K _1 %_ 04
1 K _1 %_0 4
C1 76
1 .8V
18 24 41 53 42 54 59 65 60 66 12 7 13 9 12 8 14 5 16 5 17 1 17 2 17 7 18 7 17 8 19 0 9 21 33 15 5 34 13 2 14 4 15 6 16 8 2 3 15 27 39 14 9 16 1 28 40 13 8 15 0 16 2
V S S1 6 V S S1 7 V S S1 8 V S S1 9 V S S2 0 V S S2 1 V S S2 2 V S S2 3 V S S2 4 V S S2 5 V S S2 6 V S S2 7 V S S2 8 V S S2 9 V S S3 0 V S S3 1 V S S3 2 V S S3 3 V S S3 4 V S S3 5 V S S3 6 V S S3 7 V S S3 8 V S S3 9 V S S4 0 V S S4 1 V S S4 2 V S S4 3 V S S4 4 V S S4 5 V S S4 6 V S S4 7 V S S4 8 V S S4 9 V S S5 0 V S S5 1 V S S5 2 V S S5 3 V S S5 4 V S S5 5 V S S5 6 V S S5 7
R 11 1
R1 12
*.1U_ X7R_1 0V_0 4 1 .8 V .1U_ X7R_10 V_04
C1 69
C1 85
+ C1 67
R1 09
C1 63
C146
C19 1
C15 3
C1 70
10U_ 10 V_ 08
*10 U_1 0V _0 8
4.7 U_6 3. V _0 6 *4 .7U_ 6.3V _0 6
C18 2
C1 50
C1 62
C147
C149
*1 U_6.3 V_ 04
1 U_6 3. V _04
1 U_6 .3V _0 4
.2 2U_ X7 R_0 6
*.22U _X7 R_0 6
C1 52 .1U_X 7R_ 10 V_ 04
Schematic Diagrams
DDRII SO-DIMM_1 SO-DIMM 1 4 MEM_ MB _A DD[0..1 5]
ME M_ MB _A DD0 10 2 ME M_ MB _A DD1 10 1 ME M_ MB _A DD2 10 0 ME M_ MB _A DD3 9 9 ME M_ MB _A DD4 9 8 ME M_ MB _A DD5 9 7 ME M_ MB _A DD6 9 4 ME M_ MB _A DD7 9 2 ME M_ MB _A DD8 9 3 ME M_ MB _A DD9 9 1 ME M_ MB _A DD1 0 10 5 ME M_ MB _A DD1 1 9 0 ME M_ MB _A DD1 2 8 9 ME M_ MB _A DD1 3 11 6 ME M_ MB _A DD1 4 8 6 ME M_ MB _A DD1 5 8 4 ME M_ MB _B ANK 2 8 5
4 ME M_ MB_ BAN K[0 ..2]
4 4 4 4 4 4
3.3 V S
R1 30 4.7 K _0 4
ME M_ MB _B ANK 0 10 7 ME M_ MB _B ANK 1 10 6 ME M_ MB 0_ CS #0 11 0 ME M_ MB 0_ CS #1 11 5 ME M_ MB _CL K 1_ P 3 0 ME M_ MB _CL K 1_ N 3 2 ME M_ MB _CL K 7_ P 16 4 ME M_ MB _CL K 7_ N 16 6 79 ME M_ MB _CKE 0 80 ME M_ MB _CKE 1 ME M_ MB _CAS # 11 3 ME M_ MB _RAS # 10 8 ME M_ MB _W E # 10 9 19 8 SA 0_ DIM1_ 1 20 0 SA 1_ DIM1_ 1 19 7 SCL K0 19 5 SDA TA 0
M EM_ MB 0_ CS#0 M EM_ MB 0_ CS#1 M EM_ MB _CL K1_ P M EM_ MB _CL K1_ N M EM_ MB _CL K7_ P M EM_ MB _CL K7_ N 4 M EM_ MB _CK E0 4 M EM_ MB _CK E1 4 ME M_MB _ CA S# 4 ME M_MB _ RA S# 4 ME M_M B_ W E# 2,7 1, 5 SCL K0 2,7 1, 5 SDA TA 0
R1 32
4 M EM_ MB 0_ ODT0 4 M EM_ MB 0_ ODT1 4 ME M_M B_ DM[0..7 ]
0_ 04
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
ME M_ MB 0_ ODT0 11 4 ME M_ MB 0_ ODT1 11 9 ME M_ MB _DM0 ME M_ MB _DM1 ME M_ MB _DM2 ME M_ MB _DM3 ME M_ MB _DM4 ME M_ MB _DM5 ME M_ MB _DM6 ME M_ MB _DM7
10 26 52 67 13 0 14 7 17 0 18 5
ME M_ MB _DQS 0 _P 1 3 ME M_ MB _DQS 1 _P 3 1 ME M_ MB _DQS 2 _P 5 1 ME M_ MB _DQS 3 _P 7 0 ME M_ MB _DQS 4 _P 13 1 ME M_ MB _DQS 5 _P 14 8 ME M_ MB _DQS 6 _P 16 9 ME M_ MB _DQS 7 _P 18 8
ME M_MB _ DQS0_ P ME M_MB _ DQS1_ P ME M_MB _ DQS2_ P ME M_MB _ DQS3_ P ME M_MB _ DQS4_ P ME M_MB _ DQS5_ P ME M_MB _ DQS6_ P ME M_MB _ DQS7_ P
ME M_ MB _DQS 0 _N 1 1 ME M_ MB _DQS 1 _N 2 9 ME M_ MB _DQS 2 _N 4 9 ME M_ MB _DQS 3 _N 6 8 ME M_ MB _DQS 4 _N 12 9 ME M_ MB _DQS 5 _N 14 6 ME M_ MB _DQS 6 _N 16 7 ME M_ MB _DQS 7 _N 18 6
ME M_MB _ DQS0_ N ME M_MB _ DQS1_ N ME M_MB _ DQS2_ N ME M_MB _ DQS3_ N ME M_MB _ DQS4_ N ME M_MB _ DQS5_ N ME M_MB _ DQS6_ N ME M_MB _ DQS7_ N
11 2 11 1 11 7 96 95 11 8 81 82 87 10 3 88 10 4
C20 0 2.2 U_6 .3V_0 6
5,7 C PU_ MEMHOT # MV RE F_ DIM
C2 01 .1U_ X7 R_1 0V_ 04
19 9
R13 1 Z 0 80 1 *0_ 04 02 _5 mil _ sh ort MV REF _DIM
C19 8 2.2 U_6 .3V_0 6
C1 97
83 12 0 50 69 16 3 1
DIMM1 _G ND0 20 1 DIMM1 _G ND1 20 2
.1U_ X7 R_1 0V_ 04
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 /AP A11 A12 A13 A14 A15 A16 _BA 2 BA 0 BA 1 S0# S1# CK 0 CK 0# CK 1 CK 1# CK E 0 CK E 1 CA S # RA S # W E# SA 0 SA 1 SCL SDA ODT 0 ODT 1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS 0 DQS 1 DQS 2 DQS 3 DQS 4 DQS 5 DQS 6 DQS 7 DQS 0 # DQS 1 # DQS 2 # DQS 3 # DQS 4 # DQS 5 # DQS 6 # DQS 7 #
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 12 3 12 5 13 5 13 7 12 4 12 6 13 4 13 6 14 1 14 3 15 1 15 3 14 0 14 2 15 2 15 4 15 7 15 9 17 3 17 5 15 8 16 0 17 4 17 6 17 9 18 1 18 9 19 1 18 0 18 2 19 2 19 4
MEM_M B_ DATA0 ME M_M B_ DATA1 MEM_M B_ DATA2 MEM_M B_ DATA3 MEM_M B_ DATA4 MEM_M B_ DATA5 MEM_M B_ DATA6 MEM_M B_ DATA7 MEM_M B_ DATA8 MEM_M B_ DATA9 MEM_M B_ DATA1 0 MEM_M B_ DATA1 1 MEM_M B_ DATA1 2 MEM_M B_ DATA1 3 MEM_M B_ DATA1 4 MEM_M B_ DATA1 5 MEM_M B_ DATA2 2 MEM_M B_ DATA1 7 ME M_M B_ DATA1 8 MEM_M B_ DATA1 6 MEM_M B_ DATA2 0 MEM_M B_ DATA2 1 MEM_M B_ DATA2 3 ME M_M B_ DATA1 9 MEM_M B_ DATA2 4 MEM_M B_ DATA2 5 MEM_M B_ DATA2 6 MEM_M B_ DATA2 7 MEM_M B_ DATA2 8 MEM_M B_ DATA2 9 MEM_M B_ DATA3 0 MEM_M B_ DATA3 1 MEM_M B_ DATA3 2 MEM_M B_ DATA3 3 MEM_M B_ DATA3 4 ME M_M B_ DATA3 5 ME M_M B_ DATA3 6 MEM_M B_ DATA3 7 MEM_M B_ DATA3 8 MEM_M B_ DATA3 9 MEM_M B_ DATA4 0 MEM_M B_ DATA4 1 MEM_M B_ DATA4 2 MEM_M B_ DATA4 3 MEM_M B_ DATA4 4 MEM_M B_ DATA4 5 MEM_M B_ DATA4 6 MEM_M B_ DATA4 7 MEM_M B_ DATA4 8 MEM_M B_ DATA4 9 MEM_M B_ DATA5 0 MEM_M B_ DATA5 1 MEM_M B_ DATA5 2 MEM_M B_ DATA5 3 MEM_M B_ DATA5 4 MEM_M B_ DATA5 5 MEM_M B_ DATA5 6 MEM_M B_ DATA5 7 MEM_M B_ DATA5 8 MEM_M B_ DATA5 9 MEM_M B_ DATA6 0 MEM_M B_ DATA6 1 MEM_M B_ DATA6 3 MEM_M B_ DATA6 2
0.9 V
ME M_MB _ DA TA[63 :0] 4
4 MEM _MB_C KE0
M EM_ MB _B ANK 2
4 3
1 RN16 2 4P2R X4 7_ 04
M EM_ MB _A DD1 2 M EM_ MB _A DD9
4 3
1 RN17 2 4P2R X4 7_ 04
M EM_ MB _A DD8 M EM_ MB _A DD5
4 3
1 RN18 2 4P2R X4 7_ 04
M EM_ MB _A DD3 M EM_ MB _A DD1
4 3
1 RN19 2 4P2R X4 7_ 04
M EM_ MB _A DD1 0 M EM_ MB _B ANK 0
4 3
1 RN20 2 4P2R X4 7_ 04
4 3
1 RN21 2 4P2R X4 7_ 04
4 3
1 RN22 2 4P2R X4 7_ 04
M EM_ MB _A DD1 4
1 2
4 RN23 3 4P2R X4 7_ 04
M EM_ MB _A DD1 5 M EM_ MB _A DD7
1 2
4 RN24 3 4P2R X4 7_ 04
M EM_ MB _A DD1 1 M EM_ MB _A DD6
1 2
4 RN25 3 4P2R X4 7_ 04
M EM_ MB _A DD4 M EM_ MB _A DD2
1 2
4 RN26 3 4P2R X4 7_ 04
M EM_ MB _A DD0 M EM_ MB _B ANK 1
1 2
4 RN27 3 4P2R X4 7_ 04
4 MEM _MB_W E # 4 MEM _MB_C AS# 4 MEM _MB0_ CS#1 4 MEM _MB0_ ODT 1 4 MEM _MB_C KE1
C22 5 C 22 4 C21 6 C 22 6 C21 2 C 22 8 C20 9 C 20 7 C20 5
4 MEM _MB_R AS# 4 MEM _MB0_ CS#0 4 MEM _MB0_ ODT 0
M EM_ MB _A DD1 3
1 2
4 RN28 3 4P2R X4 7_ 04
1 2
4 RN29 3 4P2R X4 7_ 04
C 22 2 C22 3 C 21 1 C22 1 C 21 4 C22 7 C 21 8
*.1U_ X7R_1 0V_ 04 1 .8V .1 U_ X7 R_1 0V_0 4 *.1U_ X7R_1 0V_ 04 1 .8V .1 U_ X7 R_1 0V_0 4 *.1U_ X7R_1 0V_ 04 1 .8V .1 U_ X7 R_1 0V_0 4 *.1U_ X7R_1 0V_ 04 1 .8V .1 U_ X7 R_1 0V_0 4 *.1U_ X7R_1 0V_ 04 1 .8V .0 1U _1 6V _0 4 *.1U_ X7R_1 0V_ 04 1 .8V .1 U_ X7 R_1 0V_0 4
Sheet 8 of 35 DDRII SO-DIMM_1
*.1U_ X7R_1 0V_ 04 1 .8V .1 U_ X7 R_1 0V_0 4 *.1U_ X7R_1 0V_ 04 1 .8V .1 U_ X7 R_1 0V_0 4
1.8 V .1U_ X7 R_1 0V_ 04
C2 19
C2 04
.1U_ X7 R_1 0V _ 04
C2 15
.1U_ X7 R_1 0V_ 04 .1U_ X7 R_1 0V _ 04
C2 08
.1U_ X7 R_1 0V _0 4
C2 13
C2 17
.1U_ X7 R_1 0V _ 04
P L A C E C L O S E T O S O C K ET ( P E R E M I / E M C )
2-17 34 07 2-2
1 .8 V
3 .3V S
J_ DIMM_2 A
47 13 3 18 3 77 12 48 18 4 78 71 72 12 1 12 2 19 6 19 3 8
J_ DIMM_2 B VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD1 0 VDD1 1 VDD1 2 VDDSP D NC1 NC2 NC3 NC4 NCT EST VRE F GND0 GND1 VS S1 VS S2 VS S3 VS S4 VS S5 VS S6 VS S7 VS S8 VS S9 VS S1 0 VS S1 1 VS S1 2 VS S1 3 VS S1 4 VS S1 5 2-17 34 07 2-2
VS S16 VS S17 VS S18 VS S19 VS S20 VS S21 VS S22 VS S23 VS S24 VS S25 VS S26 VS S27 VS S28 VS S29 VS S30 VS S31 VS S32 VS S33 VS S34 VS S35 VS S36 VS S37 VS S38 VS S39 VS S40 VS S41 VS S42 VS S43 VS S44 VS S45 VS S46 VS S47 VS S48 VS S49 VS S50 VS S51 VS S52 VS S53 VS S54 VS S55 VS S56 VS S57
18 24 41 53 42 54 59 65 60 66 12 7 13 9 12 8 14 5 16 5 17 1 17 2 17 7 18 7 17 8 19 0 9 21 33 15 5 34 13 2 14 4 15 6 16 8 2 3 15 27 39 14 9 16 1 28 40 13 8 15 0 16 2
4 ME M_MB_ CLK 7_ P P L A C E C L O S E T O P R O C E S SO R W I T H I N 1 5. I N C H
C1 07
tolerance 10% 1113
4 ME M_MB_ CLK 7_ N
1.5 P _X 7R_ 50 V_ 04
4 ME M_MB_ CLK 1_ P C1 08
tolerance 10% 1113
4 ME M_MB_ CLK 1_ N
1.5 P _X 7R_ 50 V_ 04
0 .9V 1 .8 V
C2 44
C2 43
C20 3
C23 0
C23 1
1 U_6 .3V _0 4
1U _6 .3 V _0 4
1U_ 6.3 V_0 4
.22 U_X 7R_ 06
.22 U_X7R_ 06
+ C51 5 *22 0U_ 4V _ D
C19 3
C 19 2
10U _1 0V_0 8
1 0U _10 V _0 8
1 .8V
+ C2 20 1 00 U_6 .3 V _B 2
C2 29
C24 2
C24 5
C23 4
10 U_ 10 V_ 08
*1 0U_ 10 V_ 08
10 U_1 0V_ 08
*4.7 U_6 .3V _ 06 4.7 U_6 .3V_0 6
C19 9 C5 17
C5 18
C20 6
C21 0
C51 9
C51 6
.1 U_ X7 R_1 0V_0 4 .1 U_X 7R _1 0V _0 4 * .1 U_ X7 R_1 0V _0 4 * .1 U_X 7R _1 0V _0 4 .1 U_X 7R_ 10 V_0 4 .0 1U_ 16 V_ 04
C52 0
C 52 1
.1U _X7R_ 10 V_ 04 .1U_ X7 R _ 10V _ 04
DDRII SO-DIMM_1 B - 9
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
RS780M-1
s m a r g a i D c i t a m e h c S . B
Sheet 9 of 35 RS780M-1
Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
HT_CPU_NB_CAD_H0 HT_CPU_NB_CAD_L0 HT_CPU_NB_CAD_H1 HT_CPU_NB_CAD_L1 HT_CPU_NB_CAD_H2 HT_CPU_NB_CAD_L2 HT_CPU_NB_CAD_H3 HT_CPU_NB_CAD_L3 HT_CPU_NB_CAD_H4 HT_CPU_NB_CAD_L4 HT_CPU_NB_CAD_H5 HT_CPU_NB_CAD_L5 HT_CPU_NB_CAD_H6 HT_CPU_NB_CAD_L6 HT_CPU_NB_CAD_H7 HT_CPU_NB_CAD_L7
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
HT_CPU_NB_CAD_H8 HT_CPU_NB_CAD_L8 HT_CPU_NB_CAD_H9 HT_CPU_NB_CAD_L9 HT_CPU_NB_CAD_H10 HT_CPU_NB_CAD_L10 HT_CPU_NB_CAD_H11 HT_CPU_NB_CAD_L1 1 HT_CPU_NB_CAD_H12 HT_CPU_NB_CAD_L12 HT_CPU_NB_CAD_H13 HT_CPU_NB_CAD_L13 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H15 HT_CPU_NB_CAD_L15
3 3 3 3
HT_CPU_NB_CLK_H0 HT_CPU_NB_CLK_L0 HT_CPU_NB_CLK_H1 HT_CPU_NB_CLK_L1
3 3 3 3
HT_CPU_NB_CTL_H0 HT_CPU_NB_CTL_L0 HT_CPU_NB_CTL_H1 HT_CPU_NB_CTL_L1
AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W21 W20 V21 V20 U20 U21 U19 U18 T22 T23 AB23 AA22 M22 M23 R21 R20
R 3 03
3 0 1_ 1 %_0 4 H T _ R X C A L P HT_RXCALN
C23 A24
D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6 J6 J5 J7 J8 L5 L6 M8 L8 P7 M7 P5 M5 R8 P8 R6 R5 P4 P3 T4 T3 18 PCIE_NB_MINICARD_RXP 18 PCIE_NB_MINICARD_RXN 21 21
PCIE_NB_CARDREADER_RXP PCIE_NB_CARDREADER_RXN 18 PCIE_NB_EXPCARD_R XP 18 PCIE_NB_EXPCARD_R XN
14 14 14 14 14 14 14 14
PCIE_SB_NB_RX0P PCIE_SB_NB_RX0N PCIE_SB_NB_RX1P PCIE_SB_NB_RX1N PCIE_SB_NB_RX2P PCIE_SB_NB_RX2N PCIE_SB_NB_RX3P PCIE_SB_NB_RX3N
AE3 AD4 AE2 AD3 AD1 AD2 V5 W6 U5 U6 U8 U7 AA8 Y8 AA7 Y7 AA5 AA6 W5 Y5
U10A HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
PART 1 OF 6
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
F / I U P C T R O P S N A R T R E P Y H
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N
HT_RXCALP HT_RXCALN RS780(RX780)
HT_TXCALP HT_TXCALN
U10B GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N
PART 2 OF 6
X F G F / I E I C P
PCIE I/F GP P
PCIE I/F SB
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GF X_TX10P GFX_TX10N GF X_TX11P GFX_TX11N GF X_TX12P GFX_TX12N GF X_TX13P GFX_TX13N GF X_TX14P GFX_TX14N GF X_TX15P GFX_TX15N GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN) RS780(RX780)
B - 10 RS780M-1
D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22
H T _ N B _C P U _ C A D _ H 0 H T _ N B _C P U _ C A D _ L 0 H T _ N B _C P U _ C A D _ H 1 H T _ N B _C P U _ C A D _ L 1 H T _ N B _C P U _ C A D _ H 2 H T _ N B _C P U _ C A D _ L 2 H T _ N B _C P U _ C A D _ H 3 H T _ N B _C P U _ C A D _ L 3 H T _ N B _C P U _ C A D _ H 4 H T _ N B _C P U _ C A D _ L 4 H T _ N B _C P U _ C A D _ H 5 H T _ N B _C P U _ C A D _ L 5 H T _ N B _C P U _ C A D _ H 6 H T _ N B _C P U _ C A D _ L 6 H T _ N B _C P U _ C A D _ H 7 H T _ N B _C P U _ C A D _ L 7
F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18
H T _ N B _C P U _ C A D _ H 8 3 H T _ N B _C P U _ C A D _ L 8 3 H T _ N B _C P U _ C A D _ H 9 3 H T _ N B _C P U _ C A D _ L 9 3 H T _ N B _C P U _ C A D _ H 1 0 3 HT_NB_CPU_CAD_ L10 3 H T _ N B _C P U _ C A D _ H 1 1 3 HT_NB_CPU_CAD_ L11 3 H T _ N B _C P U _ C A D _ H 1 2 3 HT_NB_CPU_CAD_ L12 3 H T _ N B _C P U _ C A D _ H 1 3 3 HT_NB_CPU_CAD_ L13 3 H T _ N B _C P U _ C A D _ H 1 4 3 HT_NB_CPU_CAD_ L14 3 H T _ N B _C P U _ C A D _ H 1 5 3 HT_NB_CPU_CAD_ L15 3
H24 H25 L21 L20
H T _ N B _C P U _ C L K _H 0 3 H T _ N B _C P U _ C L K _L 0 3 H T _ N B _C P U _ C L K _H 1 3 H T _ N B _C P U _ C L K _L 1 3
M24 M25 P19 R18 B24 B25
A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
HT_NB_CPU_CTL_H0 3 HT_NB_CPU_CTL_L0 3 HT_NB_CPU_CTL_H1 3 HT_NB_CPU_CTL_L1 3 HT_TXCALP H T_TXCALN
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N
R 30 2
3 01 _ 1% _ 04
C466 C467 C460 C461 C453 C454 C449 C448
0 . 1 u_ 1 0V _X 7 R_ 04 0 . 1 u_ 1 0V _X 7 R_ 04 0 . 1 u_ 1 0V _X 7 R_ 04 0 . 1 u_ 1 0V _X 7 R_ 04 0 . 1 u_ 1 0V _X 7 R_ 04 0 . 1 u_ 1 0V _X 7 R_ 04 0 . 1 u_ 1 0V _X 7 R_ 04 0 . 1 u_ 1 0V _X 7 R_ 04
HDMI_DATA0P HDMI_DATA0N HDMI_DATA1P HDMI_DATA1N HDMI_DATA2P HDMI_DATA2N HDMI_CLKP HDMI_CLKN
HDMI_DATA0P 13 H D M I _ D AT A 0N 1 3 HDMI_DATA1P 13 H D M I _ D AT A 1N 1 3 HDMI_DATA2P 13 H D M I _ D AT A 2N 1 3 HDMI_CLKP 13 HDMI_CLKN 13
AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2
GPP_TX0P_C GPP_TX0N_C
C434
.1U_X7R_16V_04 C435 . 1U_X7R_16V_04
GPP_TX2P_C GPP_TX2N_C GPP_TX3P_C GPP_TX3N_C
C438
.1U_X7R_16V_04 C436 . 1U_X7R_16V_04 .1U_X7R_16V_04 C444 . 1U_X7R_16V_04
PCIE_NB_CARD READER_TXP 21 PCIE_NB_CARD READER_TXN 21 PCIE_NB_EXPCARD_TXP 18 PCIE_NB_EXPCARD_TXN 18
AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5
A_TX0P_C A_TX0N_C A_TX1P_C A_TX1N_C A_TX2P_C A_TX2N_C A_TX3P_C A_TX3N_C
C9
. 1 U _ X7 R _ 1 6 V _0 4 C12 . 1 U _ X7 R _ 1 6 V _0 4 C11 . 1 U _ X7 R _ 1 6 V _0 4 C16 .1U_X7R_16V_04 C425
PCIE_NB_SB_TX0P PCIE_NB_SB_TX0N PCIE_NB_SB_TX1P PCIE_NB_SB_TX1N PCIE_NB_SB_TX2P PCIE_NB_SB_TX2N PCIE_NB_SB_TX3P PCIE_NB_SB_TX3N
AC8 AB8
Z0901 R 2 6 9 Z0902 R 23
C439
C8 C10 C431 1 . 2 7K _1 % _ 04 2 K_ 1%_ 04
VDD_PCIE
. 1 U _ X7 R _ 1 6V _ 04 . 1 U _ X7 R _ 1 6V _ 04 . 1 U _ X7 R _ 1 6V _ 04 . 1U_X7R_16V_04
PCIE_NB_MINICAR D_TXP 18 PCIE_NB_MINICAR D_TXN 18
14 14 14 14 14 14 14 14
Schematic Diagrams
RS780M-3 1 .1 VS
1. 2V( RS740)
1 .1 VS
VD D_ P C IE
1. 1V( RX780; RS780)
1. 2V( RS740)
1. 1V(RX780;RS780)
U1 0 E L 10
Z1101
H C B 1 60 8K F - 12 1T 25
C4 6 4 .7 U_ 6 .3 V_ 0 6
L 51
C4 5 .1 U_ 1 6 V_ 0 4
C 60 .1 U_ 1 6 V_ 0 4
C4 7 9
C 82
C 74
.1 U_ 1 6 V_ 0 4
.1 U_ 1 6 V_ 0 4
.1 U _1 6 V_ 0 4
H C B 1 60 8K F - 12 1T 25
4 .7 U_ 6 .3 V_ 0 6
C4 8 6
J17 K1 6 L16 M1 6 P1 6 R1 6 T16
C 59 .1 U _1 6 V_ 0 4
H1 8 G1 9 F20 E2 1 D2 2 B2 3 A2 3
VD DH T RX
1 .2 VS L7
VD DH T TX
H C B 16 08 K F - 1 2 1T 2 5
AE2 5 A D2 4 A C2 3 AB2 2 AA2 1 Y2 0 W19 V1 8 U1 7 T17 R1 7 P1 7 M1 7
C 32 4 .7 U _ 6. 3V _0 6
C3 3
C2 6
C25
C2 7 .1 U _1 6 V_ 0 4
.1 U_ 1 6 V_ 0 4.1 U _ 16 V _0 4
s m a r g a i D c i t a m e h c S . B
.1 U_ 1 6 V_ 0 4
1 .8 VS L6
Sheet 11 of 35 RS780M-3
H C B 16 0 8 K F - 1 2 1 T 2 5
.1 U_ 1 6 V_ 0 4
C4 0
C18
C 22
C2 3
4 .7 U _ 6. 3V _0 6 4 .7 U _6 .3 V_ 0 6
J10 P1 0 K1 0 M1 0 L10 W9 H9 T10 R1 0 Y9 AA9 AB9 AD 9 AE9 U1 0
VD DA 18 P CIE
.1 U_ 1 6 V_ 0 4
C17
C 41 .1 U _1 6 V_ 0 4
.1 U_ 1 6 V_ 0 4
1 .8 VS
1U _ 1 0V _0 6
C5 5
1 .8 VS R272
F9 G9 Z 1 1 0 3 AE1 1 A D1 1
* 0_ 0 60 3 _3 2 m i l_s h ort * 1U _ 1 0 V_ 06
U 1 0F
V V V V V V V
DD DD DD DD DD DD DD
HT HT HT HT HT HT HT
_ _ _ _ _ _ _
1 2 3 4 5 6 7
V V V V V V V
DD DD DD DD DD DD DD
HT HT HT HT HT HT HT
R R R R R R R
X X X X X X X
_1 _2 _3 _4 _5 _6 _7
V V V V V V V V V V V V V
DD DD DD DD DD DD DD DD DD DD DD DD DD
HT HT HT HT HT HT HT HT HT HT HT HT HT
T T T T T T T T T T T T T
X_ X_ X_ X_ X_ X_ X_ X_ X_ X_ X_ X_ X_
1 2 3 4 5 6 7 8 9 10 11 12 13
V V V V V V V V V V V V V V V
DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1
8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE 8 PCIE
PART 5/6
_1 _2 _3 _4 _5 _6 _7 _8 _9 _ 10 _ 11 _ 12 _ 13 _ 14 _ 15
V DD 1 8_ 1 V DD 1 8_ 2 V DD 1 8_ M EM 1( NC ) V DD 1 8_ M EM 2( NC )
C4 3 0
V DD P C IE_ 1 V DD P C IE_ 2 V DD P C IE_ 3 V DD P C IE_ 4 V DD P C IE_ 5 V DD P C IE_ 6 V DD P C IE_ 7 V DD P C IE_ 8 V DD P C IE_ 9 VDD PC IE _ 1 0 VDD PC IE _ 1 1 VDD PC IE _ 1 2 VDD PC IE _ 1 3 VDD PC IE _ 1 4 VDD PC IE _ 1 5 VDD PC IE _ 1 6 VDD PC IE _ 1 7
R E W O P
VD VD VD VD VD VD
D_ D_ D_ D_ D_ D_
VD DC _ 1 VD DC _ 2 VD DC _ 3 VD DC _ 4 VD DC _ 5 VD DC _ 6 VD DC _ 7 VD DC _ 8 VD DC _ 9 VD DC _ 1 0 VD DC _ 1 1 VD DC _ 1 2 VD DC _ 1 3 VD DC _ 1 4 VD DC _ 1 5 VD DC _ 1 6 VD DC _ 1 7 VD DC _ 1 8 VD DC _ 1 9 VD DC _ 2 0 VD DC _ 2 1 VD DC _ 2 2 M M M M M M
EM1 EM2 EM3 EM4 EM5 EM6
(N (N (N (N (N (N
C) C) C) C) C) C)
V DD 3 3_ 1 (N C) V DD 3 3_ 2 (N C)
A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
VD D_ P CIE
L8 HC B1 6 0 8K F -1 2 1T 2 5 C5 4 .1 U_ 1 6 V_ 0 4
C3 0 .1 U_ 1 6 V _ 0 4
C4 6 5 1 U_ 1 0 V_ 0 6
C 39 1 U_ 1 0 V_ 0 6
C 31 4 .7 U_ 6 .3 V_ 0 6
1 .1 VS K1 2 J14 U1 6 J11 K1 5 M1 2 L14 L11 M1 3 M1 5 N1 2 N1 4 P1 1 P1 3 P1 4 R1 2 R1 5 T11 T15 U1 2 T14 J16
. 1U _ 1 6V _ 04
.1 U _ 16 V_ 0 4
.1 U _1 6 V_ 0 4
1 0 U_ 6 .3 V_ 0 6 C15
C2 4
C13
. 1U _ 1 6V _ 04
C43
C4 4
.1 U_ 1 6 V _ 0 4
C 20
.1 U_ 1 6 V_ 0 4
C14
C21
C1 9
.1 U _ 1 6V _0 4
1 0 U_ 6 .3 V_ 0 6
AE1 0 AA1 1 Y1 1 AD 1 0 AB1 0 AC 1 0 3 .3 VS H1 1 H1 2
RS7 8 0 (RX7 8 0 )
Z1102
R5 9 *0 _ 0 60 3 _ 3 2 m i l_ s h or t C42 . 1U _ 1 6V _ 04
C5 6 .1U _ 1 6 V_ 04
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA 4 AB 5 AB 1 AB 7 AC 3 AC 4 AE 1 AE 4 AB 2
AE1 4 D1 1 G8 E1 4 E1 5 J1 5 J1 2 K1 4 M1 1 L1 5
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS
APC IE1 APC IE2 APC IE3 APC IE4 APC IE5 APC IE6 APC IE7 APC IE8 APC IE9 APC IE1 0 APC IE1 1 APC IE1 2 APC IE1 3 APC IE1 4 APC IE1 5 APC IE1 6 APC IE1 7 APC IE1 8 APC IE1 9 APC IE2 0 APC IE2 1 APC IE2 2 APC IE2 3 APC IE2 4 APC IE2 5 APC IE2 6 APC IE2 7 APC IE2 8 APC IE2 9 APC IE3 0 APC IE3 1 APC IE3 2 APC IE3 3 APC IE3 4 APC IE3 5 APC IE3 6 APC IE3 7 APC IE3 8 APC IE3 9 APC IE4 0
V V V V V V V V V V
SS 1 SS 2 SS 3 SS 4 SS 5 SS 6 SS 7 SS 8 SS 9 SS 1 0
PART 6/6
RS7 8 0 (R X7 8 0 )
RS740/RX780/RS780POW ER DIFFERENCE TA BLE PIN N AME
RS740
RX780
RS780
PIN NA ME
VD D HT
NC
+ 1 .1 V
+ 1.1 V
I OP LL V D D
+1 . 2V
NC
+ 1 .1 V
VD D HT RX
NC
+ 1 .1 V
+ 1.1 V
AVD D
+3 .3 V
NC
+ 3 .3 V
VD D HT T X
+ 1 .2 V
+ 1 .2 V
+ 1.2 V
AVD DD I
+1 .8 V
NC
+ 1 .8 V
VD D A 1 8P CIE
NC
+ 1 .8 V
+ 1.8 V
AVD DQ
+1 . 8 V
NC
+ 1 .8 V
VD D G1 8
+ 1 .8 V
+ 1 .8 V
+ 1.8 V
PL L VDD
+1 .2 V
NC
+ 1 .1 V
VD D 18 _ M EM
NC
NC
+ 1.8 V
PL L VDD 1 8
+1 .8 V
NC
+ 1 .8 V
VD D P CIE
+ 1 .2 V
+ 1 .1 V
+ 1.1 V
VD DA1 8 PC IEPL L
+1 .2 V
+ 1 .8 V
+ 1 .8 V
+ 1 .2 V
+ 1 .1 V
+ 1.1 V
VD D C
RX780
RS780
VD DA 1 8 H TP LL
+1 .8 V
+ 1 .8 V
+ 1 .8 V
+1 .8 V/1 .5 V
NC
+ 1 .8 V/1 .5 V
VD DL T P1 8
+1 .8 V
NC
+ 1 .8 V
VD D G3 3
+ 3 .3 V
NC
+ 3.3 V
VD DL T 1 8
+1 .8 V
NC
+ 1 .8 V
IO PL L VDD 1 8
+ 1 .8 V
N C
+ 1.8 V
VD DL T 3 3
+3 .3 V
NC
NC
VD D _M EM
B - 12 RS780M-3
RS740
D N U O R G
VSSA HT VSSA HT VSSA HT VSSA HT VSSA HT VSSA HT VSSA HT VSSA HT VSSA HT VSS A HT 1 VSS A HT 1 VSS A HT 1 VSS A HT 1 VSS A HT 1 VSS A HT 1 VSS A HT 1 VSS A HT 1 VSS A HT 1 VSS A HT 1 VSS A HT 2 VSS A HT 2 VSS A HT 2 VSS A HT 2 VSS A HT 2 VSS A HT 2 VSS A HT 2 VSS A HT 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
V V V V V V V V V V V V V V V V V V V V V V V V
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
SS1 SS1 SS1 SS1 SS1 SS1 SS1 SS1 SS1 SS2 SS2 SS2 SS2 SS2 SS2 SS2 SS2 SS2 SS2 SS3 SS3 SS3 SS3 SS3
A 25 D23 E 22 G22 G24 G25 H19 J22 L17 L22 L24 L25 M20 N22 P 20 R19 R22 R24 R25 H20 U22 V 19 W 22 W 24 W 25 Y2 1 A D2 5 L12 M14 N13 P 12 P 15 R11 R14 T12 U14 U11 U15 V 12 W 11 W 15 A C1 2 A A1 4 Y1 8 A B1 1 A B1 5 A B1 7 A B1 9 A E2 0 A B2 1 K 11
Schematic Diagrams
LVDS, Invert er PANEL CONNECTOR COSTDOW N VIN
L3 HCB 16 08 KF -12 1T 25
C4 0 .1u _50 V_ Y5V_0 6
80mil s
C42 2
C4 23
0 .1 u_ 50V_ Y5 V_06
0 .1u_ 50 V_ Y5V_0 6 10 NB_ LVDS_ TX_CLKLN 10 NB_ LVDS_ TX_CLKLP 10 NB_ LVDS_ TX_L1 N 10 NB_ LVDS_ TX_L1 P 10 NB_ LVDS_ TX_L0 N 10 NB_ LVDS_ TX_L0 P
1 3 5 7 9 11 13 NB_ LVDS_ TX_CL KL N 1 5 NB_ LVDS_ TX_CL KL P 1 7 19 NB_ LVDS_ TX_L 1N 21 23 NB_ LVDS_ TX_L 1P 25 NB_ LVDS_ TX_L 0N 27 NB_ LVDS_ TX_L 0P 29
CLOSE TO LVDS CONN. PIN
J_ LCD1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 87 12 6-30 06
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
3 .3V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
NB_L CD_DDC _ DAT A NB_L CD_DDC_ CLK
NB_LCD_ DDC_DATA 10 NB_LCD_ DDC_CL K 10
BRIGHTNESS INV_BLON
AC
C A
C36 7 *.1U _ 10 V_ X7R_04
*BAV99
NB_L V DS_ TX_ L2 N NB_L V DS_ TX_ L2 P
NB_LVDS _T X_L 2N 10 NB_LVDS _T X_L 2P 10 3.3 VS
C412
2A
PL VDD
D20 BRIGHTNESS
BRIGHT NESS 24
0.1u _1 6V_Y5V_ 04
C4 11
C40 9
4 .7u_ 25 V_ X5 R_08 0.1 u_ 16V_Y5 V_ 04
AMD CHECK CLOSE TO J_LCD1
10 NB_ LVDS_ TX_U1N 10 NB_ LVDS_ TX_U1P 10 NB_ LVDS_ TX_CLKUP 10 NB_ LVDS_ TX_CLKUN
NB_ LVDS_ TX_U1 N NB_ LVDS_ TX_U1 P
NB_L VDS_T X_ U2 N NB _L VDS_T X_ U2 P
NB_ LVDS_ TX_CL KUP NB_ LVDS_ TX_CL KUN
NB_L VDS_T X_ U0 N NB _L VDS_T X_ U0 P
NB_ LVDS_ TX_U2N 1 0 NB_ LVDS_ TX_U2P 10
Sheet 12 of 35 LVDS, Inverter
NB_ LVDS_ TX_U0N 1 0 NB_ LVDS_ TX_U0P 10
INVERTER CONNECTOR 0624J CHG "*" 24
BKL _EN
R 24 4
1 K0 _ 04
3.3 VS
R24 5
C392
10 0K_04
*0.47 u_ 10V_ Y5V_04
10 NB_L CD_ BKL _EN
NB_LCD_ BKL _EN
1
4.7K_0 4 R 1 97
3.3V 4 1
R196 BLON
0 _0 4
3 . 3V U8 A 7 4LVC0 8PW 3
2
4 1
4
3. 3V U8B 74 LVC08 PW
C3 78
6
*0 .1u _16 V_ Y5V_0 4
5 7
R198
7 4 1
*2.7K_0 4 16
SB_ BL ON R24 6
4 1
12
15 ,20,2 4 LID_SW #
9
3 .3V
10 0K_04
U8C 74 LVC08 PW 8
10 U8D 74 LVC08 PW
INV_ BLON
7
11
R24 7
C40 2
1M_ 04
0.1 u_1 6V_Y5 V_ 04
13
1 5,26 SB_PWRGD
7
PANEL POWER 3.3VS SY S1 5V
SYS1 5V
R14
R1 2
1M_0 4
1 M_0 4
+
C4 21 *1 00 u_6 .3V_B_C
Q2 9 P2 703 BAG 6 5 2 4 1 0.1u _1 6V_Y5V_ 04
PL VDD
C419
3
R261
R2 62
200 _1 %_0 4
2 00 _1% _0 4 0 .1u_ 16 V_ Y5V_0 4 10 0K_04 10 u_ 6.3V_X5R_ 06
D
Q7 G S
C4 10
C41 3
R26 0
C5
MT N70 02Z HS3 0 1. u_ 16V_ Y5V_04 D
Q6
G D
G
10 NB_L CD_PWR_ EN
S
R 13
S
MTN70 02 ZHS3
Q5 MTN70 02 ZHS3
* 2 .7K _0 4
LVDS, Inverter B - 13
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
SB700-4 1 .2 V S
PLACE ALL THEDECOUPLING CAPSON THISSHEETCLOSET O SB AS POSSIBLE. 3 .3 V S 22 U _6 .3 V _ 0 8
C2 8 5
.1 U_ 1 6 V _ 04
s m a r g a i D c i t a m e h c S . B
C2 6 9
.1U _ 1 6V _ 0 4
C3 0 9
1 U_ 1 0 V _ 0 6
C 2 48
.1 U _1 6 V _ 0 4
C 2 74
1U _ 10 V _ 0 6
C 2 57
C 2 56
C 2 86
* 1U _ 10 V _ 0 6 * 1U _ 10 V _ 0 6
C 2 99
1 U_ 1 0V _0 6
L9 M9 T15 U9 U16 U17 V8 W7 Y6 AA4 AB5 AB21
C 3 29
1 U _1 0 V _ 0 6
C2 6 4
SB700 V D DQ _1 V D DQ _2 V D DQ _3 V D DQ _4 V D DQ _5 V D DQ _6 V D DQ _7 V D DQ _8 V D DQ _9 V D DQ _1 0 V D DQ _1 1 V D DQ _1 2
Part 3of 5
V D D3 3 _ 18 _ 1 V D D3 3 _ 18 _ 2 V D D3 3 _ 18 _ 3 V D D3 3 _ 18 _ 4
O / I H S L F / E D I
Y20 AA21 AA22 AE25
C2 7 9
C3 0 3 C 2 68 22 U _6 .3 V _ 0 8 .1 U_ 1 6 V _ 04 .1U _ 1 6V _ 0 4 .1 U _ 16 V _ 0 4
L27
R3 4 6 *0 _ 08 0 5 _ 50 m i l_ s h o rt
2A
P18 P19 P20 P21 R22 R24 R25
HC B 1 6 0 8K F - 1 21 T 2 5 _0 6 C3 1 9
C3 1 8
2 2 U_ 6 . 3 V _ 08 1 U_ 1 0V _0 6
C3 1 5
1 U _1 0 V _ 0 6
C3 1 6
1 U_ 1 0 V _ 06
C3 1 7
C3 1 3
C3 1 4
1U _ 10 V _ 0 6 .1U _ 1 6V _ 0 4
.1 U_ 1 6 V _0 4
P C IE _ V DD R_ 1 P C IE _ V DD R_ 2 P C IE _ V DD R_ 3 P C IE _ V DD R_ 4 P C IE _ V DD R_ 5 P C IE _ V DD R_ 6 P C IE _ V DD R_ 7
1 .2 V S
2A
L24
AA14 AB18 AA15 AA17 AC18 AD17 AE17
A V D D_ S A T A
HC B 1 6 0 8K F - 1 21 T 2 5 _0 6 C2 5 5
L1 5 M1 2 M1 4 N1 3 P12 P14 R1 1 R1 5 T1 6
Z2102
O / I N E G K L C
C K V D D_ 1 . 2 V _ 1 C K V D D_ 1 . 2 V _ 2 C K V D D_ 1 . 2 V _ 3 C K V D D_ 1 . 2 V _ 4
L2 1 L2 2 L2 4 L2 5
Z2101
U1 8 E
2.5A C3 0 0
C3 1 1
C 31 0
C5 3 5
C 30 1
C3 1 2
SB700
C 30 2 .1U _ 1 6V _ 0 4
1 U_ 1 0V _0 6 1 U_ 1 0V _0 6
1 U _1 0 V _ 0 6 1 U _1 0 V _ 0 6
.1 U _ 16 V _ 0 4 2 2 U_ 6 .3 V _ 0 8
L55 H C B 1 6 0 8 K F -1 2 1T 2 5 _ 06
T10 U10 U11 U12 V11 V14 W9 Y9 Y1 1 Y1 4 Y1 7 AA9 AB9 AB11 AB13 AB15 AB17 AC8 AD8 AE8
POWER
P CIE _V DD R
1 .2 V S
0 S E R O C
O / I O I P G / I C P
V DD _ 1 V DD _ 2 V DD _ 3 V DD _ 4 V DD _ 5 V DD _ 6 V DD _ 7 V DD _ 8 V DD _ 9
1.2 V _ C K V D D
1.8V=>FLASH M EMORY MODE(DEFAULT) 3.3V=>IDE MODE
3 .3V S
Sheet 17 of 35 SB700-4
SB700 (A11) 1.2V SB700 (A12) 1.2VS
U 18 C
C2 7 7
C2 5 4
2 2 U_ 6 .3 V _ 0 8 1 U_ 1 0 V _ 06 1 U_ 1 0 V _ 06
C2 7 8
C2 6 7
.1U _ 1 6V _ 0 4
.1 U_ 1 6 V _0 4
A V D D_ A V D D_ A V D D_ A V D D_ A V D D_ A V D D_ A V D D_
3 .3 V
O / I K N I L - O A / I 5 S _ V 3 . 3
SATA_1 SATA_4 SATA_2 SATA_3 SATA_5 SATA_6 SATA_7
S 5 _ 3 .3 V _ 1 S 5 _ 3 .3 V _ 2 S 5 _ 3 .3 V _ 3 S 5 _ 3 .3 V _ 4 S 5 _ 3 .3 V _ 5 S 5 _ 3 .3 V _ 6 S 5 _ 3 .3 V _ 7
A17 A24 B17 J4 J5 L1 L2
C 3 08
C3 5 5
.1 U_ 1 6 V _0 4
C 3 25
.1 U _ 16 V _ 0 4
2 2U _ 6. 3V _ 0 8
1.2 V
O / 5 I A S T E A S R O C
S 5 _ 1 .2 V _ 1 S 5 _ 1 .2 V _ 2
G2 G4 C3 2 7
U S B _ P H Y _ 1 .2 V _ 1 U S B _ P H Y _ 1 .2 V _ 2
A10 B10
C3 2 6
C3 3 6
.1 U_ 1 6 V _0 4 1 U_ 1 0 V _ 0 6
.1 U_ 1 6 V _ 04
C3 3 5 1 U_ 1 0V _0 6
1 .2 V _ US B _ P H Y _ R
A15 B15 C14 D8 D9 D11 D13 D14 D15 E15 F12 F14 G9 H9 H17 J9 J11 J12 J14 J15 K10 K12 K14 K15
A V S S _S A TA _1 A V S S _S A TA _2 A V S S _S A TA _3 A V S S _S A TA _4 A V S S _S A TA _5 A V S S _S A TA _6 A V S S _S A TA _7 A V S S _S A TA _8 A V S S _S A TA _9 A V S S _S A TA _1 0 A V S S _S A TA _1 1 A V S S _S A TA _1 2 A V S S _S A TA _1 3 A V S S _S A TA _1 4 A V S S _S A TA _1 5 A V S S _S A TA _1 6 A V S S _S A TA _1 7 A V S S _S A TA _1 8 A V S S _S A TA _1 9 A V S S _S A TA _2 0
A V S S _U S B _ 1 A V S S _U S B _ 2 A V S S _U S B _ 3 A V S S _U S B _ 4 A V S S _U S B _ 5 A V S S _U S B _ 6 A V S S _U S B _ 7 A V S S _U S B _ 8 A V S S _U S B _ 9 A V S S _U S B _ 1 0 A V S S _U S B _ 1 1 A V S S _U S B _ 1 2 A V S S _U S B _ 1 3 A V S S _U S B _ 1 4 A V S S _U S B _ 1 5 A V S S _U S B _ 1 6 A V S S _U S B _ 1 7 A V S S _U S B _ 1 8 A V S S _U S B _ 1 9 A V S S _U S B _ 2 0 A V S S _U S B _ 2 1 A V S S _U S B _ 2 2 A V S S _U S B _ 2 3 A V S S _U S B _ 2 4
3 .3 V
2A
L36
A V DD _ US B
1 0 U_ 1 0V _0 8
H C B 1 6 0 8 K F -1 2 1T 2 5 _ 06 C3 5 4 1U _ 10 V _ 0 6
C 34 1
C3 4 7
* 1U _ 10 V _ 0 6 .1 U _1 6 V _ 0 4
C3 4 3 .1 U _ 16 V _ 0 4
C3 4 0
C3 4 8
.1 U_ 1 6 V _ 04
C3 3 0
C3 5 8
*.1 U_ 1 6 V _ 0 4 .1 U _1 6 V _ 0 4
C3 5 9 1 0U _ 10 V _ 0 8
A V D DC K _ 3 .3 V
A16 B16 C16 D16 D17 E17 F15 F17 F18 G15 G17 G18
3.3 V S
200mA
L30 H CB 10 0 5 K F -1 2 1 T2 0 _ 0 4
AE7 A V D DT X _ 0 A V D DT X _ 1 A V D DT X _ 2 A V D DT X _ 3 A V D DT X _ 4 A V D DT X _ 5 A V D DR X _0 A V D DR X _1 A V D DR X _2 A V D DR X _3 A V D DR X _4 A V D DR X _5
V 5 _V R E F A V DD C K _3 .3 V
L L P O / I B
A V DD C K _1 .2 V
J1 6
A V DD CK _ 3 .3 V
K17
A V DD CK _ 1 .2 V
E9
5VS 3 .3 V S
D 16 C
A
3 .3 V _ A V D DC
A V DD C
S U
F M 5 82 2 C2 5 2 1 U_ 1 0V _0 6
? ? ? ? M540SE? ? ? ?
1 .2 V
2A
1 .2 V _ CK V D D
L34 H C B 1 6 0 8 K F -1 2 1T 2 5 _ 06 C 33 1
C3 4 9 C3 3 2
C 3 44 C 3 33
.1U _ 1 6V _ 0 4 1 U _1 0 V _ 0 6 .1 U_ 1 6 V _0 4 *1 U _1 0 V _ 0 6 1 0U _ 10 V _ 0 8
A V DD CK _ 1 .2 V
200mA
L29 HC B 1 0 0 5K F - 1 21 T 2 0 _0 4
C3 0 5 2 .2 U_ 6 .3 V _ 06
H18 J17 J22 K25 M16 M17 M21 P16 F9
P C IE _ C P C IE _ C P C IE _ C P C IE _ C P C IE _ C P C IE _ C P C IE _ C P C IE _ C AVSSC SB700
1 .2V _U S B _ P H Y _ R R39 7
B - 18 SB700-4
R 1 47 1K_04
SB700
C3 4 2 2 .2U _ 6 .3V _0 6
1.2 V S
V 5 _ V RE F
* _0 0 6 0 3 _3 2 m l i_ s ho rt C5 5 9 C5 6 8 C5 6 7 .1 U _1 6 V _ 0 4.1 U _1 6 V _ 0 4 2 2 U_ 6 .3 V _ 08
3 .3 V _ AV D DC
3 .3 V
200mA
L3 5 HC B 1 00 5 K F -1 2 1 T 20 _ 0 4 C3 3 8 C3 3 9 .1U _ 1 6V _ 0 4 2.2 U _ 6.3 V _ 0 6
K _ V S S _1 K _ V S S _2 K _ V S S _3 K _ V S S _4 K _ V S S _5 K _ V S S _6 K _ V S S _7 K _ V S S _8
D N U O R G
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50
P C IE _ CK _V S S _ 9 P CI E _ C K _ V S S _ 1 0 P CI E _ C K _ V S S _ 1 1 P CI E _ C K _ V S S _ 1 2 P CI E _ C K _ V S S _ 1 3 P CI E _ C K _ V S S _ 1 4 P CI E _ C K _ V S S _ 1 5 P CI E _ C K _ V S S _ 1 6 P CI E _ C K _ V S S _ 1 7 P CI E _ C K _ V S S _ 1 8 P CI E _ C K _ V S S _ 1 9 P CI E _ C K _ V S S _ 2 0 P CI E _ C K _ V S S _ 2 1
Part 5of 5
A V S S CK
A2 A25 B1 D7 F20 G1 9 H8 K9 K11 K16 L4 L7 L 10 L 11 L 12 L 14 L 16 M6 M1 0 M1 1 M1 3 M1 5 N4 N1 2 N1 4 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R1 0 R1 2 R1 4 T 11 T 12 T 14 U4 U1 4 V6 Y21 AB1 AB19 AB25 AE1 AE24
P23 R1 6 R1 9 T 17 U1 8 U2 0 V18 V20 V21 W19 W22 W24 W25 L 17
Schematic Diagrams
New Card, Mini PCIE NEW CARD(Port 8)
NEW CARD ONLY C4500 SUPPORT
3 .3 V C 5 88
3 .3 V
* 0 . 1u _ 61 V _ Y 5V _ 0 4
5
BU F _P LT _ RST # 3 .3V S
1 .5VS
1
U 22 4 * MC7 4 VHC 1 G0 8 DF T 1 G
3 .3 V 2 1 . 5V S
C5 8 2
C 59 3
3 . 3V S
U2 3 17
*0 .1 u_ 1 6 V_ Y 5 V_ 04 *0 .1u _ 1 6V _Y 5V _0 4 * 0.1 u _ 16 V_ Y5 V_ 0 4
A UXIN
AUXO UT
3 .3 VIN
3.3 VO UT
1 .5 VIN
1.5 VO UT
2
12
6 20 1
2 1 ,2 4,2 6 BUF _PL T _ RST # SUSB #
S YSRS T# S HDN # S TBY #
19
15 U SB_ OCP6 _ 7 #
3 .3 V
15
NC _3 .3 VAUX
3
NC _3 .3 V
36mils 48mils
11
NC _1 .5 V
48mils
8
NC _R ST #
10 9
NC _C PPE# NC _C PUSB#
PERST # C PPE# CPU SB#
O C# R 4 27 R 4 22
R 42 4
*1 0 0K_ 0 4
*1 0 0 K_ 04
C 5 45
C5 5 0
C 55 1
* 0 .1u _ 1 6V_ Y 5V_ 0 4 * 0.1 u _ 16 V_ Y5 V_ 0 4 *0 .1 u _1 6 V_ Y5 V_ 04 J _ NEW 1 12 + 3.3 VAU X 14 + 3.3 V 15 + 3.3 V 10 + 1.5 V 9 + 1.5 V NC _ PERST # 13 PER ST# 17 4 CPP E# CPU SB# 11 1 5 ,2 1 P C I E _ W A K E # 16 W AKE# 2 ,15 PC IE_ EXP CARD _ CL KREQ # CL KR EQ# R 36 9 1 0 K_04 3 .3 VS 19 2 PC IE_E XPC ARD _ CL KP REF CL K+ 18 2 PC IE_E XPC ARD _ CL KN REF CL K-
3
C5 80
15 ,2 4 ,2 5,2 6
R4 2 3
3 .3 V
18 RCL KEN
* 10 K _04 1 0K _ 0 4
4 5 13 14
NC NC NC NC *W 8 3 L3 5 1 YG
G ND EG ND
7 21
R4 2 1
16
Sheet 18 of 35 New Card, Mini PCIE
*1 0 K_ 04
NC 9 9 9 9
3 .3V
ENEP2231 NFE2 pin1,8,9,10,20 has
PC PC PC PC
IE_ NB_ EXPCA R IE_ NB_ EXPCA R IE_N B_ EXP CAR IE_N B_ EXP CAR
internally pulled high(110~330K Ohm)
15 15
15 15 R 37 6 R 37 7
15 PC IE_ EXPC ARD _ PW REN #
* 01 m _li s h ort_ 0 4 * 01 m _li s h ort_ 0 4
D_ D_ D_ D_
R XP R XN TXP TXN
U SBP7 U SBN7
SD AT A2 SC L K2
NC _C PPE# NC _C PUSB #
22 21 25 24 3 2
8 7
PET p 0 PET n 0 PER p0 PER n0
R ESER VED R ESER VED
USB _D + USB _D -
SMB _D AT A SMB _C LK
GN D GN D GN D GN D
5 6
1 20 23 26
* 13 5 8 01 5 1- 5
MINI CARD (WLAN,Port 5) Layout Show "WLAN(Wimax, 802.11N)" Note
20mils 3.3 V C 5 31
J _M INI1 3 .3 V
R 34 7
1 0 K _0 4
PCIE_ W AKE#
1 3 5 7 11 13 9 15
2 W LAN _ CL KREQ # 2 P CIE_ W L AN_ CL KN 2 P CIE_ W L AN_ CL KP
W AKE# COE X1 COE X2
3 .3 VAU X_ 0 1. 5V_ 0 UIM_ PW R UIM _D AT A UIM _ CL K UIM _R ESET UIM _ VPP
CL KREQ # REF C LKREF C LK+ GND 0 GND 1
2 6 8 10 12 14 16
24 W LA N_ DET # 9 PCIE_ NB _M INIC ARD _R XN 9 PCIE_ NB _M INIC ARD _R XP 9 PCIE _N B_ MINI CAR D _ TXN 9 PCIE_ NB _M INIC ARD _T XP 24 24 22 ,2 4
8 0 DET # 3 IN 1 BT _EN
R 43 9 R 44 0
R 36 3 R 36 2
* 1 0 m l_i s ho rt * 1 0 m l_i s ho rt
* 0_ 0 4 0 _ 04 3.3 V
R4 4 1
*1 5m il_s h ort_0 6
0511-J CL _ CL K1 CL _ DAT A1 CL _ RST # 1
change
VD D3 BT_ EN
R 44 2
* 0_ 0 4
R 44 3
* 0_ 0 4
35 23 25 31 33 17 19 37 39 41 43 45 47 49 51
C 52 9
20mils 1 .5 VS
UIM _PW R_ 1 UIM _D AT A_1 UIM _C L K_1 UIM _R ST _1 UIM _VP P_1
C 5 79
C5 8 1
* 0. 1u _ 16 V_ Y5 V_ 0 4 *1 0 u_ 6 .3 V_X5 R_ 0 6
4 GN D5
KEY 21 27 29
C5 3 0
0 .1 u _1 6 V_ Y5 V_ 04 1 0 u_ 6 .3 V_X5 R_ 0 6 0.1 u _ 16 V_ Y5 V_ 0 4
GND 2 GND 3 GND 4
GN D6 GN D7 GN D8 GN D9 GN D1 0
GND 1 1 PETn 0 PETp 0 PERn 0 PERp 0 Re se rv e d 0 Re se rv e d 1 GND 1 2 3.3 VAU X_ 3 3.3 VAU X_ 4 GND 1 3 Re se rv e d 2 Re se rv e d 3 Re se rv e d 4 Re se rv e d 5
W _ DISABL E# PERSET # SM B_ CL K SM B_D AT A US B_D U SB_ D+ 3 .3 VAU X_ 1 1. 5V_ 1 1. 5V_ 2 3 .3 VAU X_ 2 L ED _WW A N# LE D_ W L AN# L ED _W P AN#
R 41 8
18 26 34 40 50 20 22 30 32 36 38 24 28 48 52 42 44 46
1 0 K _0 4
0514-J add BT_DET#
3. 3VS
W LAN _ EN 2 2,2 4
BUF _ PL T _R ST # MIN I_SC L K1
R 44 8
0_04
R 44 9
* 0 _0 4
R 36 0 R 36 1
* 0 _0 4 * 0 _0 4
L4 1 3 R 4 10
* 1 5 m _il s h ort_ 0 6
3 .3 V 1 .5V S 3 .3V
2
B T_ DE T# 2 2 ,24 W DT _ EN 2 4
S C LK 1 S D A TA 1
15 1 5
4 U S BN 5
15
U SBP5
15
1
*W CM2 0 1 2F 2S-1 6 1 T0 3 -s ho rt
W LAN _ LED # 22 ,24 C 5 83
C5 8 4
8 89 0 8 -52 0 4 M-0 1 0 .1u _ 1 6V _Y 5V _0 4
0511-J change
1 0u _ 6 .3V_ X5 R _ 0 6 24
8 0C LK
New Card, Mini PCIE B - 19
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
CCD, 3G, SATA ODD MINI CARD 3G(Port 6)
3G POWER R 13 7
Layout Sho w "3.5G(HSDPA)" Note
3.3 V 1 3 5 7 11 13 9 15
J _ 3G 1 W AK E# CO EX1 CO EX2
3.3 VAU X_ 0 1. 5V_ 0 UIM_ PW R UIM _D AT A UIM _ CL K UIM _R ESET UIM _ VPP
CL KR EQ# REF CL KREF CL K+ GN D0 GN D1
GN D5
2 6 8 10 12 14 16
* 0_ 0 8 Q2 2 AO 3 41 5 S D
3A 120mils
60mils U IM_ PW R U IM_ DAT A U IM_ CL K U IM_ RST U IM _ VPP
G
C2 62
C2 5 0
+C2 5 1
C 2 32
0.1 u _ 16 V_ Y5 V_ 04 22 0 u _4 V_ V_ B 0.1 u _ 16 V_ Y5 V_ 04
C2 3
1 u_ 6. 3 V _Y 5 V _0 4
1 0 u _1 0 V_ Y 5 V_0 8
s m a r g a i D c i t a m e h c S . B
24
Sheet 19 of 35 CCD, 3G, SATA ODD
35 23 25 31 33
3 G_ D ET#
C 5 58
C 5 56
0 .1 u _1 6 V_ Y5 V_0 4 1 0 u _6 .3 V_ X5 R_ 0 6
17 19 37 39 41 43 45 47 49 51
GN D1 1 PET n 0 PET p 0 PER n0 PER p0 Re s e rv ed 0 Re s e rv ed 1 GN D1 2 3 .3V AUX_3 3 .3V AUX_4 GN D1 3 Re s e rv ed 2 Re s e rv ed 3 Re s e rv ed 4 Re s e rv ed 5 8 8 91 0 -5 20 4 M-0 1
W _ DISABL E# PERSET # SM B_ CL K SM B_D AT A US B_D U SB_ D+ 3.3 VAU X_ 1 1. 5V_ 1 1. 5V_ 2 3.3 VAU X_ 2 L ED _W W AN# L ED_ W L AN# L ED _W P AN#
C 26 3
1 0 0K _0 4
0 .1 u_ 1 6V _Y 5V_ 0 4
1 0 0 K_ 0 4 D
GN D6 GN D7 GN D8 GN D9 GN D1 0
R 15 4
2 0 K_1 % _ 04 R136
GN D2 GN D3 GN D4
3 G_ 3 .3 V
R 14 6
4
KEY 21 27 29
3A 120mils
3G _ 3.3 V
18 26 34 40 50
G
24 3 G_ PW R
Q2 3 MT N7 0 02 Z H S3
S
From SB GPIO Pin default HI
20 22 30 32 36 38
3 G_EN
24
2
1
R 1 82 24 28 48 52 42 44 46
Power Plane: Suspend S3: Defined
L33 *W C M2 0 12 F 2 S-1 61 T 0 3-s h o rt 4
3
U S B N4
15
U SBP4
15
3 G_ 3 .3V *1 5m i _ l s h ort_ 0 6
SIM CONN
60mils 3 G_ 3 .3 V +C 28 3
R 26
4 . 7K _ 0 4
C3 6 5 *0 .1 u _1 6 V_Y 5 V_0 4
2 2 0u _ 4 V_V_ B J_ SIM 1 R 39 0 * 10 m il_ s ho rt_ 0 4 U IM_ CL K
C3 C2 C1
U I M_ RS T U IM_ PW R C 56 6
LOCK (TOP VIEW) U IM_ CL K U IM_ RST U IM_ PW R
U IM_ DAT A U IM_ VPP U IM_ GN D
R3 3 6 *1 0 m il_ sh o rt_ 04 C7 C6 C5
OPEN
2 2 p_ 5 0 V_N PO_ 0 4
U IM_ DAT A U I M _V P P C 5 26
C1 77 0 6 61 -1 SIML OC K
C 3 61
C5 28
2 2 p _5 0 V_N PO_ 0 4 22 p _5 0V_ NP O _0 4 2 2 p _5 0 V_ NPO_ 0 4
CCD
SATA ODD 5V L 43
Q28 MT P3 4 03 N 3 S D
H C B 1 00 5K F - 12 1T 20
C 40 5 C1
G
5V_ CC D
48 mil MJ_CCD1
R2 59
C 40 7
C 40 6
C 40 8
10 0 K_0 4
1 u _6 .3 V_ Y5 V_ 04
0 .1 u_ 1 0V _X7 R_ 0 4
1 u _6 .3 V_ Y5 V _0 4
1
0 . u1 _1 0V _ X 7R _ 40
1 u _6 .3 V_ Y5 V_0 4 J _ OD D1 S1 S2 S3 S4 S5 S6 S7
SAT A_ T X4+ _C 1 6 SAT A_ T X4 -_ C 1 6
1 00 K_ 0 4 J _C CD 1 R6
SAT A_ RX4 -_C 1 6 SAT A_ RX4 +_C 16
3 3 0K _ 0 4 D
CC D_ EN 24 P1 P2 P3 P4 P5 P6 C1 8 5 53 -1 01 PIN G ND 1 ~ 2 = G ND
B - 20 CCD, 3G, SATA ODD
5
R4
Q3 MT N7 0 0 2Z H S3
G
CC D_ EN
15 15 24
US BN9 US BP9 CC D_ DET #
15 15 24
US BN6 US BP6 CC D_ DET #
USBN 9 USBP9 CCD _ DET #
S
5 VS
8 52 0 5 -05 0 01 _ R J _C CD 2
From H8 default HI C5 05
C5 07
C5 0 6
C5 0 3
C5 0 4
C5 0 2
+C5 0 1
*0 .1u _ 1 6V_ Y5 V_ 0 4 0.1 u _ 16 V_ Y5 V_ 04 1 u_ 6 .3V _Y 5V_ 0 4 1 00 u _ 6.3 V_ B _ A 0.1 u _ 16 V_ Y5 V_ 04 *0 .1 u_ 1 6V _Y 5V_ 0 4 1 0u _ 6 .3V_ X5R _ 06
1 2 3 4 5
USBN 6 USBP6 CCD _ DET #
1 2 3 4 5 *8 5 20 5 -0 50 0 1 _R
Schematic Diagrams
USB, Fan, TP, Multi-Con USB PORT*2(Port 0,Port1) 3 .3 V
5 V S_ F A N
FAN CONTROL
F ON #
24 US BVCC 01
5V
U SB_O CP0 _ 1 #
5
U14
2
C8 1
3
1u _ 6. 3V_ Y5 V_ 0 4
4
V I N 1 V OUT 2 V I N 2 V OUT 3
60mils
CPU _F AN
7
C8 9
8
10 u _6 .3 V_ X5 R _0 6 0 .1 u_ 1 6V _Y 5V_ 0 4
C 80
5 VS
J _ F AN1
* 0_ 0 4
0 .1 u _1 6 V_ Y5 V_0 4
R 66 1 5 K_1 % _ 04
1 0u _ 6.3 V_ X5R _ 06
C 11 9
2 2u _ 6 .3V_ X5 R _ 08 1 0 0u _ 6 .3V_ B _ A 0 .1 u_ 1 6V _Y 5V_ 0 4
R 42 9
U SBP0
* 0_ 0 4
1
3
2
4
85 2 0 5-0 3 7 01
Port 0 V+
1 2 L59 W C M2 0 12 F 2 S-1 61 T 0 3
R 43 0
3 4
* 0_ 0 4
5V
DAT A_ H
C1 0 77 0 -1 04 A3
USBVC C0 1
A * C H 35 5 P T
3
5 VS_ T P 5 VS
4 1 2 3 D D D D N N N N G G G G
GN D
C D 15
1
CLICK CONN
J _ USB1
4. 7K _0 4 JFAN
0515-J Add"*"
DAT A_ L
0520 -J EMI CHG
R 1 24
3 .3 VS C1 3 1
C 48 2
+
15
C5 1 1
24 CPU _ F ANSEN
1 5 USB_ OC P0 _1 #
U SBN0
1 2 3
C 50 8
80 mil
15
5 VS_ F AN
R 32 6
GND
U SBVCC 01 R 65 1 0 K_0 4
8 7 6 5
GN D GN D GN D GN D
F ON #
6-02-097 15-920
DD_ O N#
FON VIN VO UT VSET G 9 90 P1 1U
R T 97 1 5BG S 25 ,2 6 ,28 ,2 9
U17
* 0_ 0 4
1 EN #
1 2 3 4
R 32 8
6
F L G# V OUT 1
60mils
5 VS
5V S
R71 * 1 0K_ 0 4
R 1 18 R 11 9
* 1 5m i l _ sh or t _ 06 * 0_ 0 6
C1 43
J _T P1
FOR CLICK BOARD
1 2 3 4
1 2 3 4 D D D N N D N N G G G G
R1 1 6
R1 1 7
10 K_ 0 4
1 0K_ 0 4
C1 4 2
C1 4 5
T P_D ATA T P _C L K
8 52 0 1 -04 0 5 1
Sheet 20 of 35 USB, Fan, TP, Multi-Con
C1 4 4
*1 0u _ 6 .3V_ X5R _ 06
1 u_ 6 .3 V_Y 5 V_0 4 24 24
47 p _ 50 V_ NPO _0 4 4 7p _ 50 V_ NPO _ 04
80 mil +C 19 5
C1 8 0
1 0 0u _ 6 .3V_ B _ A
POWER SWITCH CONN.
0 .1u _ 1 6V_ Y5 V_ 0 4
Port 1 R 4 31
* 0 _ 04
15
USBN 1
15
USBP 1
1
0520-J EMI CHG
3
2
2 L6 0 W CM 20 1 2F 2S-1 6 1 T0 3
R 43 2
3 4
* 0_ 04
J_ SW 3
DAT A_ L DAT A_ H GN D
4 1 2 3 D D D D N N N N G G G G 1 2 3 4 D D D D N N N N G G G G
0526-J l ay ou t ? ? ? ?
J _SW 1
5V 15
U SBN2
15
U SBP2
R 21 0
* 1 0 m il_ sh o rt_ 04
U SBN2 _ R
R 21 1
* 1 0 m il_ sh o rt_ 04
U SBP2 _R
2 3 MIC 1-R 2 3 MIC 1-L 2 3 H EADPH ON E-R 2 3 H EADPH ON E-L 2 3 MIC _SE NSE 2 3 HP_ SEN SE
2 3 SPKOU T R+ 2 3 SPKOU T R-
1.1A 60mils C 2 98
R 178 MIC 1-R MIC1-L HEAD PHO NE-R HEAD PHO NE-L MIC _SEN SE SPK_ HP# HP_ SEN SE USBN 2_ R USBP2 _ R SPKOU T R+ SP KOUT R -
0 .0 1u _ 50V_ X7R_ 04 0_ 0 6
J_ AUD IO1 1 2 3 4 5 6 7 8 9 10 11 12 13 14
R4 3 4 1 0 0K_ 0 4 M PW R_ BT N# W EB _W W W # W EB _EM AIL # L ID_ SW #
M _ BN T # W EB_ W W W # 2 4 W EB_ EMAIL# 2 4 L ID_ SW # 1 2 ,1 5,2 4
AP_ KEY #
25
AP_ KEY# 2 4
1 2 3 4 5 6 7 8 9 10
PC5 2
PC 40
CLOSE TO J_SW1
0 .1u _ 5 0V_ X7R _ 04
20mil
AP_KEY#
0520-J EMI CHG 0.01uF?0.1u F
MPW R _BT N # W EB_ W W W # W EB_ EMAIL # LID _ SW #
* 0 .01 u_5 0 V_X7R _0 4
VD D3
3 .3 V
0 .1 u _5 0 V_ X7 R_ 0 4
FOR AUDIO/B
20mil
FOR POWER SWITCH BOARD PC 41
CONN.(Port 2)
C5500Q Click/B LED Use
0526-J Add *0 .1u_ 5 0 V_X7 R_0 4
88 2 9 6-0 8 L
3 .3 VS
Audio/B
1 2 3 4 5 6 7 8
V+
C1 0 77 0 - 1 04 A3
3 3. V
PC2 42
J _ USB2 1
4
3 . 3V S
W EB_ W W W # 2 4 W EB_ EM AIL# 2 4 L ID_ SW # 12 ,1 5,24
J _T P2 AP_ KEY# 2 4
D
Q1 4
G
20mil
1 2 3 4 5 6
L ED_ PW R # 2 2 ,2 4 L ED_ ACIN # 22 ,24 L ED_ BAT _ F UL L# 2 2 ,24 L ED_ BAT _ CHG # 22 ,2 4
85 2 01 -0 6 05 1
*MT N 70 0 2Z H S3 S
0512-J change p in
AP_O N
l a yo u t?? ??
VI N
*5 0 50 0 -0 10 4 1 -00 1 L
AP_ O N
R3 0 *4 7 K_ 04
A P _O N
25
0512-J change
87 2 13 -1 4 R
USB, Fan, TP, Multi-Con B - 21
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
SATA HDD, LED, MDC, BT
SATA HDD J _ HDD 1
MJ_ M DC1 S1 S2 S3 S4 S5 S6 S7
S AT A _T X0 +_ C S AT A _T X0 -_C
12
SA T A_ T X0 + C _ 16 SA T A_ T X0 -_ C 1 6
S AT A _R X 0-_ C S AT A _R X 0+ _ C
3.3 V
1
SA T A_RX0 -_C 1 6 SA T A_ RX0 +_C 16 3.3 VS
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
11
2
C 54 1
15 ,2 3 A Z _S DOU T 1 5,2 3 15 1 5,2 3
C5 46
0 .0 1 u_ 5 0V _X 7 R_ 0 4 10 u _6 .3 V _ X5 R _0 6
A Z _ S YN C A Z _ S DIN 1 A Z _ RST #
R 3 86
* 33_ 0 4
MA Z _S D OU T_ R
R 3 87 R 3 88 R 3 89
* 33_ 0 4 * 22_ 0 4 * 33_ 0 4
MA Z _S Y NC _R MA Z _S D IN1 _ R MA Z _R S T #_ R
1 3 5 7 9 11
J_ M DC1 GN D A za li a _S DO GN D A za li a _S YNC A za li a _S DI A za li a _R ST # *8 8 01 8 -1 20 G
2 4 6 8 10 12
R E S ERV ED R E S ERV ED 3.3 V M ai n /au x GND GND A za ila _ BCL K
R3 5 6
*0 _ 0 40 2 _1 0 m il_ s ho rt
3.3 V
10mil MAZ _ BIT CL K_ R R 35 0
5 VS
* 0 _0 4
C 54 7
C 54 2
*. 1U _1 0 V_ X7 R _0 4
* 22 p _5 0 V _ NP O _0 4
A Z _ B IT CL K
HD D_ NC 0 C 53 6
HD D _ NC 1 HD D_ NC 2 HD D_ NC 3
C5 3 4
C5 3 3
C 5 32
C 53 7
+C5 2 4
0 .1 u _1 6 V _ Y 5 V _0 4 0. 1u _ 16 V _ Y5 V _ 0 4 2 2 u_ 6 .3 V _X 5 R_ 0 8 0 .1 u_ 1 6V _Y 5V_ 0 4 1 u _ 6.3 V_ Y 5 V _ 0 4 *1 0 0u _ 6 .3V _ B _ A
Sheet 22 of 35 SATA HDD, LED, MDC, BT
ACE S-9 1 9 07 -0 22 0 A-H0 1 P IN G ND 1 ~ 2 = G ND
LED 3 . 3 VS 3 .3VS
3.3 V S
3 .3V S
R8 R2
R3
R5
12 0 _0 4
2 2 0_ 0 4
2 2 0 _0 4
2 2 0_ 0 4
A
A
HDD/ D2 4 3 G Y 2 7 1 P S Y R
LED C
A
NUM D3
CD-ROM
4 3 G Y 2 7 1 P S Y R
S A T A _ LE D # 16
LED C
4 3 G Y 2 7 1 P S Y R
LED C
LE D _ NUM # 24
L E D _C A P # 24
BT LED SCROLL
D5
LOCK
R7
2 2 0 _0 4
A
CAPS D4
LOCK
Bluetooth(Port8)
3 . 3V S
3.3 V S
R1
C
4 3 G Y 2 7 1 P S Y R
1
1
3
2
4
LOCK
2 2 0_ 0 4
WLAN
3
LED
D1 Y
2
G S
0514-J
RY -SP 15 5 HY YG 4
LED
R 4 44
V DD 3
HC B 1 00 5 K F - 1 2T 2 0C5 10 W L A N_ LED#
B
LE D _ S CR O L L# 2 4
E
FOR C4500
V DD 3
E
W L A N _EN
1 8,2 4
Q1 * DT C1 1 4 EUA
0.1 u _ 16 V_ Y 5 V _ 04 10 u _ 6.3 V_ X 5R _0 6
15 15 18 ,2 4 B T_ EN
R2 5 1
R2 5 3
*2 2 0 _0 4 *2 2 0_ 0 4
1 8,2 4
2 2
1
1 0 K _ 04 D
B T _E N
8 7 2 12 -0 6L Q4 0 MT N7 0 02 Z H S 3
G S
3
D 30
D 31
G S
R 32 7
Q2 DT C1 1 4E U A
1 2 3 4 5 6
B T _E N #
BAT LED
LED
3
Y
J _B T 1
*2 2 0_ 0 4 *2 20 _ 0 4
POWER ON 1 1
U S BN8 U S BP 8 B T _D E T # 3 .3 V
From EC default HI
R2 5 4
C5 0 9
1 8,2 4
18 ,2 4 R2 5 2
3V _ BT 1
50m il
L 53
* 1 0 m li _ sh o rt_ 04
C
B VDD 3
3.3 V
Add
4
C
V D D3
A Z _ B IT CL K 1 5 , 23
Y
* RY-S P15 5 HY YG4
4
2
L ED_ PW R# 2 0 ,24 L E D_ AC IN#
2 0,2 4
G S
*R Y -S P 15 5 HY Y G4
4
LE D_ B A T _F U LL # 2 0,2 4 L ED_ BA T _CHG #
20 ,2 4
SATA HDD, LED, MDC, BT B - 23
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
Au dio Co dec AL C272 CODEC ( ALC272-GR )
0517-J ? ?
P I N 25 , P IN 3 8 ? 1 ? 1 0 uF / . 1u F R 45 0
1 .5 V S
PC BEEP 24
15
K B C_ B E E P
ICH _S P K R
3. 3V S
C 3 68
1u _6 .3V_ Y 5V _04
C 3 62
1u _6 .3V_ Y 5V _04
BEEP
R4 5 1
L42 3 .3 V S _A UD HC B 1 00 5 K F -1 2 1T 2 0
D 2 5 C
* S C S 55 1V - 30 A
L37
H CB 1 00 5K F-1 21T 2 0
5V
5VS_AUD
* 0_ 0 6
* 1 5 m li _ s ho rt_ 0 6
C 5 65
C5 6 4
0 .1 u _1 0 V _ X 7R _ 04
1 0 u_ 1 0 V _Y 5 V _ 08
C3 6 4 *0 .1 u_ 1 0 V _ X7 R _0 4
C4 0 3
C 5 92
C 57 7
C5 8 7
0 .1u _ 1 0V _X 7 R_ 0 4
1 0 u _ 10 V _ Y 5 V _ 0 8
0 .1 u_ 1 0 V _ X7 R _0 4
0 .1u _ 1 0V _X 7 R_ 0 4
A UD G
C 4 04
R4 3 5 *1 0 m il _ sh o rt C3 5 7 C3 5 6
C3 9 6
0 .1 u _1 0 V _ X 7R _ 04
5VS
C3 5 3 1u _ 6 .3V _Y 5 V _0 4
0 .1 u _5 0 V _Y 5 V_ 0 6 0 .1 u _5 0 V _Y 5 V_ 0 6
1 0 u_ 1 0 V _Y 5 V _ 08 A U DG
MI C2 _ L MI C2 _ R
s m a r g a i D c i t a m e h c S . B
MI C1 _ L MI C1 _ R
C3 6 9 C3 7 0
*0 .1 u _ 61 V _ Y5 V _ 04 *0 .1 u _ 61 V _ Y5 V _ 04
C3 7 1 C3 7 2
*0 .1 u _ 61 V _ Y5 V _ 04 *0 .1 u _ 61 V _ Y5 V _ 04
A UD G U21
Sheet 23 of 35 Aud io Codec ALC272
1 5 ,2 2 A Z _ S DO UT 1 5 ,2 2 A Z _ B ITC L K 15 A Z _ S DI N0 15 ,2 2 AZ_SYNC 15 ,2 2 A Z _ RS T#
Ver y cl ose t o Au dio Codec
2 3
A L C _ GP I O0 A L C_ GP I O1
2 2_ 0 4 A Z _ S DIN 0 _R
R40 5
5 6 8 10 11
E A P D_ MO DE
47
S P DIF O
48 45 46 44
C 5 73 BEEP
R 235 R 39 6 C 574
10 K _ 0 4 1 0K _ 1 % 0_ 4 0 . 1u _1 0V _X 7R _ 04
20 20
*0 .1 u _10 V _X 7R _ 04
43 12
A UD G 1 u _6.3 V_ Y5 V _0 4
C5 7 2
A UD G
R 22 7 R41 2
M IC_ S E N S E HP _ S E N S E
2 0K _ 1 % _ 04 5 . 1K _ 1 % _ 04
13 34 14 15
R396 VIA1812? 5.1K ALC272 ? 1K
INT _ MIC R 24 9
C3 9 4 C 39 5
1K_04
4 .7 u _6.3 V_ X5 R_ 0 6 4 . 7 u _ 6 .3 V _ X 5 R _ 0 6
MIC 2 _L MIC 2 _R
16 17 18 19 20
M IC2 -V R E F O
20 20
R 22 9 R 22 8
M IC1 -L M IC1 -R
7 5 _ 1 %_ 0 4 7 5 _ 1% _ 0 4
C3 7 3 C3 6 3
4 .7 u _6.3 V_ X5 R_ 0 6 4 .7 u _6.3 V_ X5 R_ 0 6
MIC 1 _L MIC 1 _R
21 22
5 8 2 3
1 9
1 2 S S S S V V D D
C 5 86 * 2 2p _ 5 0V _ N P O_ 0 4
A U DG
Layout Note:
4 7
D O I D V D D D V D
C5 7 1
Ver y cl ose t o Au dio Codec
1 0 _u 1 0V _ Y5 V_ 08 A UD G
G P IO0 /DM IC-D A T A 1 /2 G P IO1 /DM IC-D A T A 3 /4 S D A TA -OU T B IT -CL K S D A TA -IN S Y NC RESET#
Layout Note:
A L C_ V R E F
1 2 D D D D V V A A
VREF MIC 1 -V RE F O
M ON O-O UT
DIGITAL
27 28
MI C1 -V RE F O
D27 A
C
CH3 5 5 P T
MIC 1 -V RE F O -R
D28 A
C
CH3 5 5 P T
MIC 1 -V RE F O -L
37
EAPD S P D IF O1 S P D IF O2
CPVEE CB N CBP
D MIC- CL K 1 /2 D MIC- CL K 3 /4 NC P C B E E P -IN
L OU T1 -L L OU T 1- R
S e n se A (J D 1) S e n se B (J D 2)
L OU T2 -L L OU T 2- R
ANALOG
L INE 2 -L L INE 2 -R
HP O UT -L H P OU T- R
M IC2 -L M IC2 -R
L INE 1 -L L IN E 1- R
L INE 1 -V R E F O M IC2 -V RE F O L INE 2 -V R E F O
J DR E F
31 30 29
C5 7 6 C5 7 5
Layout Note:
R2 5 0
R2 3 0
4 .7K _ 0 4
4 .7 K _0 4
MIC 1 -L
M IC1 -R
A U DG
35 36
F R ON T-L F R ON T-R
C 38 1
C3 8 0
*6 8 0p _ 5 0 V _X 7 R_ 0 4
39 41 33 32
A U DG
HE A DP H ON E -L HE A DP H ON E -R
*6 8 0 p_ 5 0 V _ X7 R _0 4
AUD G
H E ADP HON E -L 2 0 H E ADP HON E -R 20
23 24 MIC 2-V R E F O
NEAR CODEC 40
J DR E F
R 257
2 0 K _ 1% _ 0 4
R 1 15 2 .2 K _ 0 4
1 2 S S S S V V A A
M IC1 -L M IC1 -R
2 .2 u _6.3 V_ X5R _04 2 .2 u _6.3 V_ X5R _04
A UD G
R257 VIA181 2 ? 5. 1K ALC272 ? 20K
A L C2 7 2
6 2 2 4
Cod ec pin 1 ~ pin 11 and pin 44 ~ pin 48 are Dig ital sign als.
J _ INT MIC 1
IN T _M IC
3 3 0 p _5 0 V _ X7 R _0 4
T h e o t he r s a r e A n a l og s i g n a ls .
AMP (TPA6017)
A U DG 5V S
S P K OU TL +
5VS_REAR
J_INTMI C1 2 1
1 2
C 1 41
8 8 26 6 -0 20 0 1 P C B F o ot pri n t = 8 82 6 6 -2L
PCB FOO TPRIN T 2L 6-20-63120-102
L40 1
2
F C M 10 05 K F - 1 2 1 T 03
L58
HC B 10 0 5 K F -1 21 T 2 0
S P K OU T LC5 6 9 *1 0 u_ 1 0 V _ Y 5 V _ 08
C 57 0 1 0 u _1 0 V _ Y 5 V _ 0 8
C4 0 0 * 10 u _ 6.3 V _ X 5 R _ 06
L 39 F C M1 0 0 5K F - 12 1 T 03 1 2
C 39 9 0 .1 u _1 6 V _ Y 5 V _ 0 4
C3 8 7
3.3 V S 3 .3 V S
Low mute!
C 3 93
A U DG
*0 .1 u_ 1 6V _Y 5 V _04
3 .3 V S _ A UD
R2 3 6
16
S B _M UT E # E A P D _ MO DE
2 4 K B C_ M UT E #
D 44 C R248
S C S3 5 5 V A * 0_ 0 4
C3 8 3 C3 9 7
A U DG *1 u _6 .3 V _ X 5R _ 06 C 3 82 C 3 75 A U DG C 3 98 C 3 74 A U DG *1 u _6 .3 V _ X 5R _ 06
F R ON T -L
C 3 79
10 0 K _ 0 4
* 0 . 1u _ 1 0V _ X 7 R_ 0 4 5
1
R2 58 A U DG *1 00 K _ 0 4
F R ON T -R C5 9 1
4
2
A UDG 3
U9 MC 74 V H C1 G0 8 DF T1 G
5VS A UDG
Gain Settings GAIN0 GAIN1 AV(i nv) 0 0 6dB 0 1 10 dB 1 1
B - 24 Audio Codec ALC272
0 1
15.6 dB 21.6 dB
I NPUT I MPED ANCE 90k 70k 45k 25k
R23 1 R2 2 1 R22 2 R2 3 2
S P K O UT L + *1 u _ 6. 3V _ X 5 R _ 0 6
1 u_ 6 .3 V_ X5 R _0 4 1 u_ 6 .3 V_ X5 R _0 4
L IN L IN +
1 u_ 6 .3 V_ X5 R _0 4 R INR IN+ 1 u_ 6 .3 V_ X5 R _0 4 S P K O UT L * 1 u _6 . 3 V_ X5 R_ 0 S P K _E N 1 00 K_ 0 4 * 1 0 K0 _ 04 G A IN0 G A IN1 1 00 K_ 0 4 * 1 0 K0 _ 04
C 366
5 9 17 7 6 19 2 3 1 11 13 20 21
1 8 0 p_ 5 0 V _ NP O _0 4 R 2 39 * 1 0m il _s h o rt
U1 9 L IN L IN + R INR IN+ SD # G A IN 0 G A IN 1
C 38 5 1 00 0 p _5 0 V _ X 7R _ 04
P V DD P V DD V DD
d a P
L O UT + L OU T -
l a mR O U T + r e R O U T h T
G ND G ND G ND BYPASS G ND E XP O S E D P A D NC
6 15 16 4
S P K O UT L +
8
S P K O UT L -
18
S P K O UT R +
14
S P K O UT R-
10
AMP_BYPAS S
S P KO UT R+
20
S P KO UT R- 2 0
12
C3 7 6
TP A 60 1 7 A 2 P W P R
2.2 u _ 10 V _ Y 5V _ 0 4
A UD G A U DG
TO AUDIO BOARD CONN.
S P K O UT L +_ R S P K O UT L -_R C3 8 6
J _ S P K L 1 J_SPK1 2 1 1 2
8 52 0 4 -02 0 0 1 P C B F o o tpr ni t = 8 52 0 4 -02 R 1 8 0p _ 5 0V _N P O_ 0 4
Schematic Diagrams
KBC ITE IT8502E KB C_ A VD D
V D D3 L 28
VD D3 C3 2 2
C3 5 0
C 3 52
C 35 1 C2 9 6
1 0u _ 6 .3V _X5 R _ 0 6 0 .1 u _ 16 V _ Y5 V _ 0 4 0.1 u _ 16 V _ Y 5V _0 4 0 .1 u _1 6 V _ Y5 V _ 0 4
C2 9 5HC B 1 00 5 KF -1 2 T 20
C 29 4
0 .1u _ 1 6 V_Y 5 V_ 04 0.1 u _ 1 6V_ Y 5V _0 4
* 0.1 u _ 16 V_ Y 5V _0 4
V DD 3
3 .3 VS C3 2 4
KBC _ AGN D
0.1 u _ 16 V _ Y 5V _0 4 U5 14 L AD0 14 L AD1 14 L AD2 14 L AD3 14 LP C_ CL K1 14 LF RAM E # 14 S ERIR Q 1 8,2 1 ,2 6 B UF _ P L T _ RS T #
L PC_ C LK 2
K BC _ W RES E T#
0517-J CHGPin76 to 80 for EC8518
E C 85 1 8 _T 2 E C 85 1 8 _T 3
19 3 G_ PW R 1 8,2 2 W L AN_ EN 20 CPU _ F AN 23 KB C_ MU T E#
R 1 67 * 1 0K _0 4 KB_ BD_ ID
R 1 69 19 19
* 1 0K _0 4
3G _ DET # C CD _D E T #
31 S M C_ BAT 31 S M D_ BAT 5 SM C_ CPU _ TH E R M 5 SM D_ CPU _ TH E R M
23 KBC _BE E P 2 2 L ED_ S C RO L L# 22 L E D _N UM # 22 L E D _ CAP# 2 0 ,2 2 LE D _ BA T _C HG # 20 ,2 2 L E D_ BA T _ F UL L # 20 ,2 2 L E D_ PW R #
18 18 18 15 20 20
B AT _ DET B AT _ V OL T _ R CU R_ S EN S E_ R T OT AL _ CU R_ R K B_ BD _ID 3 G_ D E T# CC D _ D E T # MO DE L_ ID
26 T H ERM _R S T #
76 77 78 79 80 81
66 67 68 69 70 71 72 73
110 S M C_ B AT S M D_ B AT 111 S M C_ CPU _ TH ER M 1 1 5 S M D_ CPU _ TH ER M 1 1 6 S M C_ V GA _T H ERM 1 1 7 S M D_ V GA _T H ERM 1 1 8
L CD _ B RIG HT NE SS 2 4 25 K BC _ B EEP 28 29 30 31 32 34
80 C LK 3IN 1 8 0D E T # P ME# T P_ CL K T P_ DA T A
TP_ C LK TP_ D AT A
T HER M_ R S T#
85 86 87 88 89 90
125 18 21
25 P W R_ S W # 1 2 ,1 5 ,20 L ID _S W #
33
2 0 W EB _ W W W #
L AD0 L AD1 L AD2 L AD3 L PCC L K L F RA ME# LPC S ER IRQ L PCR S T # /W UI4 /G PD2 ( PU )
KSI 0/ST B# KSI1 /AF D# KSI2 /IN IT# KSI3 /SL IN# KSI4 KSI5 MATRIX KSI6 KSI7 KSO 0 /PD0 KSO 1 /PD1 KSO 2 /PD2 KSO 3 /PD3 KSO 4 /PD4 KSO 5 /PD5 KSO 6 /PD6 KSO 7 /PD7 K SO 8 /ACK# K SO9 /BU SY KSO1 0 /PE KS O 11 /ER R# K SO1 2 /SL CT K SO 13 K SO 14 K SO 15
G A20 /G PB5 K BR ST #/ GP B6 ( P U ) P W U REQ # /GPC 7 ( PU ) L 8 0L L A T /GP E 7( P U ) E C SCI# /G P D3 ( P U ) E C SMI# /G P D4 ( P U )
DAC D D D D D D
AC0 AC1 AC2 AC3 AC4 AC5
/GP /GP /GP /GP /GP /GP
J0 J1 J2 J3 J4 J5
IT8502E-J
D D D D D D D D
C0 C1 C2 C3 C4 C5 C6 C7
FLASH
/GP /GP /GP /GP /GP /GP /GP /GP
I0 I1 I2 I3 I4 I5 I6 I7
F L F R A ME# /G PG2 F L AD 0 /SCE# F L A D1 /S I F L AD 2/ SO F L AD3 /G PG6 F L CL K /S CK ( P D )F L R ST #/W UI7 /T M/G PG0
GPIO
SMBUS
( P D )KS O 16 /G PC3 ( P D )KS O 17 /G PC5
S M CL K 0 /GP B 3 S M DAT 0 /GP B 4 S M CL K 1 /GP C 1 S M DAT 1 /GP C 2 S M CL K 2 /GP F 6( P U ) S M DAT 2 /GP F 7( P U )
( ( ( ( ( ( (
PWM P P P P P P P P
W W W W W W W W
M0 M1 M2 M3 M4 M5 M6 M7
/GPA0 /GPA1 /GPA2 /GPA3 /GPA4 /GPA5 /GPA6 /GPA7
( ( ( ( ( ( ( (
PU PU PU PU PU PU PU PU
) ) ) ) ) ) ) )
S2 S2 S2 S2 S2 S2
C D C D C D
PD PD PD PD PD PD PD
)ID0 )ID1 )ID2 )ID3 )ID4 )ID5 )ID6
/G /G /G /G /G /G /G
PH0 PH1 PH2 PH3 PH4 PH5 PH6
( PD )ID7 /G PG1
EXT GPIO ( PD )E GAD /GPE1 ( P D )EGC S# /GPE2 ( P D )EGC LK /GPE3
PS/2 P P P P P P
58 59 60 61 62 63 64 65
KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S
I0 I1 I2 I3 I4 I5 I6 I7
36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55
KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S KB-S
O O O O O O O O O O O O O O O O
0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1
0 1 2 3 4 5
4 5 6 8 11 12 14 15
KB-SI0 KB-SI1 KB-SI2 KB-SI3 KB-SI4 KB-SI5 KB-SI6 KB-SI7
1 2 3 7 9 10 13 16 17 18 19 20 21 22 23 24
KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO KB-SO
WAKE UP
LK0 /G PF 0 ( PU A T0 /G PF 1 ( PU LK1 /G PF 2 ( PU A T1 /G PF 3 ( PU LK2 /G PF 4 ( PU A T2 /G PF 5 ( PU
)
( PD )W U I5 /GPE5 ( P D )L PC PD# /W U I6 /GPE6
) ) )
PWM/COUNTER
)
( P D )TA CH0 /G PD6 ( P D )TA CH1 /G PD7
)
WAKE UP
( P D )T MR I0 /W UI2 /G PC4 ( P D )T MR I1 /W UI3 /G PC6
P W R S W /G P E4 ( PU )
CIR
R I1# /W U I0 /GPD 0 ( PU ) R I2# /W U I1 /GPD 1 ( PU )
( PD ) CRX/G PC0 ( PD )CT X/GPB2
GP INTERRUPT
LPC/WAKE UP
G INT /GP D5 ( PU )
( P D )L 8 0H L AT /GPE0
100 101 102 103 104 105 106
108 109
BT _ EN BKL _E N
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1u _ 6 .3 V_Y 5 V_ 04
1 2 3 7 9 10 13 16 17 18 19 20 21 22 23 24
VD D3 J _ 80 D E BUG 1 1 2 3 4 5
3IN 1 80 C LK 80 D ET #
VCH G-S E L 31
KBC _ SPI_ SCL K
56 57 93 94 95 96 97 98 99
S S S S S S S S S S S S S S S S V V V V V V V V A 1 2 7 9 1 3 2 1 2 4 9 1 2 1 1
CLOCK CK 3 2 KE CK3 2 K
C C D _E N
1 9
SUS B# SUSC#
1 5,1 8, 2 5, 2 6 15
MODE L MODE L_ID HI/ LOW
SM D_ BAT
W L A N_ L E D# 1 8 ,2 2 W D T_ E N 1 8 W L A N_ D E T# 1 8 BT _D ET # 1 8,2 2 DD _ ON 25
BT _D ET #
107
3 G_EN
82 83 84
B AT _ DET
31
BA T _VO L T
31
CU R_ SEN SE
31
35 17
BA T_ VO LT
19
S MI # 15 S CI # 15 PW R _BT N # 15
C UR _S E NSE
T O TAL _ CU R
T OT AL _ CU R
RSM RST # 1 5 KBC _R ST # 15
47 48
CPU _ F ANSE N 2 0 DD _ ON_ LAT CH 2 5
120 124
5 7
X3 4 3
C3 9 1
VDD 3 N C3 2
CEL L _ CO NT RO L 3 1
C K3 2K E C K3 2K R 1 92
R 20 7
4 .7K_ 04
S WI #
15
C H G _E N
3 1
0623-J PW R Add
*
HI
LOW VDD 3
M OD EL _ ID
S YS_ P W R GD _ R
R 16 8
10 K _ 0 4
R 17 0
* 10 K _0 4
R 20 9
A P_K E Y#
0517-J CHG f or EC8518
L ED_ CT R L
19
2 128
4 .7K_ 04
0 _ 04
C 2 82
* 10 _0 4
S Y S _ P WR G D
26
0 . 1u _1 6V _ Y 5V _ 04
L P C_ CL K2
R 1 81
C 3 07
* 1 p0 _5 0V _ N P O _0 4
BA T _ VOL T
R 1 53
1 0 0_ 0 4
BAT _ VOL T _ R
C 2 61
1 u _6 . 3V _Y 5 V _ 04
CU R_ SE N SE R 1 62
* 10 0 _ 04
CU R_ SEN SE_ R
C 2 72
* 1 _u 6. 3 V _Y 5 V _ 0 4
T OT AL _C UR R 1 61
* 10 0 _ 04
T OT A L _ CU R _ R
C 2 71
* 1 _u 6. 3 V _Y 5 V _ 0 4
VCO RE_ O N 2 7
SYS _PW RG D_ R
119 123
1 0 K_ 04
R 20 8
B AV 9 9R E C TIF I ER C AC D19 A B AV 9 9R E C TIF I ER C AC A D17 B AV 9 9R E C TIF I ER C AC A D18 * BAV 9 9 REC T IF IER C AC A D21 * BAV 9 9 REC T IF IER
BA T_ D ET 31
R 14 4
C45 00
C AC A D23 B AV 9 9R E C TIF I ER C AC A D24
SM C_ BAT
0511-J P i n 95 t o WL AN L E D
CL K R UN # L AN_ DS P _E C#
Sheet 24 of 35 KBC ITE IT8502E
8 5 20 5 -0 5 00 1
0511-J Add pin104 VCHG-SEL
( PD )RI NG #/P W RF AIL # /L PCR ST # /GPB7
UART R XD /GPB 0( P U ) T XD/G PB1 ( PU ) IT 8 5 02 E -J
WEB0--->AP KEY WEB1--->EMAILKEY WEB2--->WWW K EY
4 5 6 8 11 12 14 15
KBC _SP I_C E# KBC _SP I_S I KBC _SP I_S O
112 1 8,2 2 12
KB C_ W R E SET #
J _ KB 2 * 8 52 0 1 -2 40 5 1
VD D3
ADC A A A A A A A A
10 0 K_ 0 4
FOR C4500
C2 9 7
T C A C B V V A
K/B
J_KB1
J _K B1 8 5 2 01 -2 4 0 51
W R ST #
23 15
20 AP_ K EY# 2 0 W E B _ EMA IL #
3
Y Y Y Y Y B Y B B T B T B T B T T S T S S S S S V V V V V V
C C V
R1 7 7
24
FOR C5500Q
4 7
14 126 4 16 20
15 G A2 0 31 AC _IN # 2 0 ,2 2 LE D_ ACIN # 5 ,1 5 TH ERM _ AL E RT #
V D D3
10 9 8 7 13 6 5 22
4 1 7 6 0 2 1 2 2 2 5 9 1 1 1
1 1
1
PCL K_ K BC _R
KBC_SPI_*_R = 0.1"~0.5"
0 .1 u_ 16 V_ Y5 V_ 04 U2 0
1
SPI_ VD D 8
VD D
SI SO CE # SC K
N C_ 0 4 R2 3 3 1 K_ 0 4
W P#
3
5 2 1 6
K B C_ SPI_ S I_ R K B C_ SPI_ S O_ R K B C_ SPI_ CE # _ R K B C_ SPI_ S CL K_ R
W P# R2 4 3 4 .7 K_ 0 4 HO LD # 7
* 1 0 M_ 0 4
H OL D #
VS S
4
R R R R
406 24 2 25 6 234
KB C_ SP I_ SI KB C_ SP I_ SO KB C_ SP I_ C E # KB C_ SP I_ SC L K
4 7 _ 04 1 5 _ 1% _ 0 4 1 5 _ 1% _ 0 4 4 7 _ 04 C 5 78 C 3 90 C 4 01 C 3 7
KBC_ KBC_ KBC_ KBC_
SPI SPI SPI SPI
_SI _SO _C E# _SC L K
* 3 3p _5 0V _ N P O _0 4 * 3 3p _5 0V _ N P O _0 4 * 3 3p _5 0V _ N P O _0 4 * 3 3p _5 0V _ N P O _0 4
SST 25 VF 0 8 0 B
CM 2 00 S3 2 7 68 1 2 20 _ 3 2. 76 8 KHz 1 2 J SPI1
4 3
C 32 3 R 17 1 *1 0 m il _ s h ort_ 0 4
0 .1 u_ 1 6 V_ Y 5 V _ 04
X7
LC D_ BR IGH TN ESS
1 2 BR IGH T NESS
C3 4 5 N C1 2
C 2 73
N C _0 4 1
* 0.1u _1 6V _ Y 5V _0 4
1 8 p _5 0 V_ NPO _ 04
1 2
0514-J addcol ayout X3
*M C-1 4 6 3_ 2 .7 68 KH z C 33 4 1 8 p_ 5 0 V_ NPO _ 04
KBC _ S P I_ CE# _ R
1
KBC _ SP I_ SO_ R
2
WP#
3
CE# SO
4
W P# VSS
V DD
8
SPI_ VD D
7
H OL D#
6
KBC _ SPI_ SCL K_ R
5
KBC _ SPI_ SI_ R
HO L D# SCK SI
*A C A-S PI -0 0 4 -T 03 KBC _AG ND
CO-LA YOUTWITHSPI ROM
KBC ITE IT8502E B - 25
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
System PWR, 2.5V SY S5 V
SYS 5V
VA R2 3 7
R 33 5
10 K_ 0 4
1 0 K_ 04 DD _O N#
DD _O N#
2 0 ,2 6, 28 ,2 9
SUSBL
D
24
D D_ ON
DD_ O N
2 6, 2 8, 2 9
VIN
PC2 3 9
PC2 4 0
*0 .1 u_ 5 0 V_Y 5 V_0 6
*0 .1 u _5 0 V_ Y5 V_ 06
*0 .1 u _5 0 V_ Y5 V_ 06
D
Q2 4 1 MT N7 0 02 Z H S3
G
C 38 4
PJ 3
S
1 5 ,18 ,2 4 ,26
SUSB#
SU SB#
2
ON
Q 21 1 M TN 7 00 2 Z HS3
G
PJ 12
S
0 .1 u _1 6 V_ X7 R_ 0 4
R2 5 5
O PEN- 1m m
R 1 45
1 00 K_ 0 4
O PEN-1 m m
2
0517-J
C5 2 5 3 0p _ 5 0V_ N PO _ 0 4
1
VA
1 0 0 K_ 04
20 20
PU 11 VA
VIN1
VIN
D D_ ON _ LAT C H
M_ BT N#
4
AP_ ON
8 7
3
M_ BT N#
PW R_ SW #
INST AN T-O N
GN D
Sheet 25 of 35 System PWR, 2.5V
5A
0_ 04
D D_ ON _LAT CH 2 4
6
PW R_ SW # 2 4
5
PR 22 4 1 0 K_ 1% _ 0 4
NM O S SY S1 5V
VDD 3
R1 2 7
N MOS
Q2 0 AO4 4 6 8 8 7 3 6 2 5 1
SY S15 V
3 .3 VS
C2 0 2
Q 19 M TN 70 0 2 Z HS3
D
C1 9 4
G
2 2 00 p _5 0 V_ X7 R _0 4
C5 8 9
Q4 6 MT N7 0 0 2Z H S3
D
C5 8 5
G
22 0 0 p_ 5 0 V_X7 R_ 0 4
S
C5 9 0
0.1 u _ 16 V_ Y5 V_ 0 4 1 0u _ 1 0V_ Y 5V_ 0 8
M7 XJ TI MMING SYS1 5 V
SU SBL
1 .8V
R 3 11
S
2 0 0 K_1 % _ 04
Q 37 AO 44 6 8 8 7 3 6 2 5 1
SY S1 5V
VD D 3
R3 3 4
Q 42 AO 4 46 8 8 7 3 6 2 5 1
5A
3 .3 V
5A
D
C5 1 4 2 2 00 p _5 0 V_ X7 R _0 4
Q4 3 MT N7 0 02 Z H S3
D
C1 6 6 22 0 0 p_ 5 0 V_X7 R_ 0 4
S
* 10 0K _ 0 4
P R 17 2
1 0 0K _0 4
2 .5V_ PG
D
8 1 PQ 4 1
G
PC 20 6 .0 2 2U _ 16 V_ X7R _0 4
26 ,2 8 ,29 S U S B L S
PU6 VIN VIN POK
VC NT L VO UT VO UT
6
VF B
2 .5 V _ CP U
1A
4 3 PR1 2 1
EN GND
2
Ra
1 0K_ 1 % _0 4
PC1 3 8 0.0 1 u _5 0 V_ X7 R_ 0 4
PC 1 46 1 0 u _6 .3 V_ X5 R _0 6
AX66 1 0
M TN 7 00 2 Z HS3
PR1 2 3
Rb 0514-J pow er change OZ 8033 to AX6 610
B - 26 System PWR, 2.5V
2 6, 2 8, 2 9
PC 20 2
0 .01u _ 50V_ X7R _ 04
PC 20 0
*0 .0 1 u_ 5 0 V_X7 R_ 0 4
PC 19 8
0 .01u _ 50V_ X7R _ 04
PC 42
1 u_ 1 0V _0 6 5 9 7
5VS SU SBL
S
3.3 V DD _O N#
PC1 4 8
3. 3VS 5V
Q 16 M TN 7 00 2 Z HS3
5 VS
PC 14 7
1 0u _ 6. 3V_ X5 R _ 06 0 .1 u_ 1 6 V_Y 5 V_0 4
Q35 M T N7 0 02 Z H S3 G
5A
10 u _6 .3 V_ X5R _0 6
0 .01u _ 50 V_ X7R _ 04
S
3.3 VS PC1 5 0
5A
C4 96
0 .1u _ 16 V_ Y5 V_ 0 4
Power Plane
G
DD _ ON#
P R 17 1
2A
C4 9 7
4
5 V_ EN
G
5V
1M _ 04
4
3. 3V_ EN
Q4 4 AO4 4 6 8 8 7 3 6 2 5 1
R1 2 0
Power Plane
1 M_ 0 4
VDD 5
SY S15 V
2 2 0 0p _ 5 0V_ 0 4
1 .8V S
5A
4
D
NMOS
0512-J change
NMOS
C 4 94
NM OS
6
5 VS
4
5 VS_ EN
SU SBL
2 4 5
3A
10 0 K_ 1% _ 0 4 0 .1u _ 1 6V _Y 5V _ 0 4 1 0 u_ 1 0 V_Y 5 V _0 8
4
1 3
DEBUG USE
Q47 A O4 46 8 8 7 3 6 2 5 1
R4 1 1
C 19 6
6 8 0K_ 1 % _0 4 3. 3VS_ EN
V DD5
5A
V DD3
SW1 * T JG -5 33 -S-T /R M _ BTN #
4 .7K_ 1 % _0 4
Vout = 0 .8V ( 1 + Ra / Rb )
PC1 4 5 10 u _ 6.3 V_ X5R _ 06
From H8
VIN1 R 44 5
P2 8 08 A1
5A
DD_ON"L" T O "H" FROM EC
CHG
2
VIN
s m a r g a i D c i t a m e h c S . B
VIN 1
PC2 3 8
PC 87
0 .01u _ 50 V_ X7R _ 04
PC 17 6
0 .01u _ 50V_ X7R _ 04
PC 18 0
*0 .0 1 u_ 5 0 V_X7 R_ 0 4
Schematic Diagrams
PWRGD, RST 5V 5V S
3.3 VS
1. 8 VS
1.5 VS
3.3 V
2.5 V_ CPU R 1 14
R4 04
R1 21
R1 22
R 4 25
R 3 09
10 0 _1 % _ 06
10 0 _1 % _ 06
10 0 _1 % _ 06
1 0 0 _1 % _ 06
1 0 0 _1 % _ 06
R 2 38
1 0 0 _1 % _ 06 D D
G S
2 5 ,28 ,2 9
PWRGD
G MT N7 0 02 Z HS 3
S
D
Q1 7 G MT N7 0 02 Z HS 3
S
D
Q1 8 G MT N7 0 02 Z HS3
S
D
Q48 G M T N7 00 2 Z HS3
S
Q34
S
M T N7 00 2 Z HS3
M T N7 00 2 Z HS3
S
M T N7 00 2 Z HS3
DD _O N#
20 ,2 5,2 8 ,2 9 D D_ ON #
3 .3 VS R 17
1 .2V_ PG
1 .1V_ N B_PG
29
1 .2V_ SB_ PG
15
SYS_ R ST#
* 10 K _0 4
R 18
1 0K _0 4
R 22 5
2 2_ 0 4
R1 5
2 2_ 0 4
2 .5V_ C PU SB_ PW R GD 12 ,15 3 .3VS
* 2.2 u _6 .3 V_ Y5 V_ 06 R1 6
R4 2 8 10 0 K_ 04
2 2_ 0 4 1 .8 VS
D 26 C
* R B 7 5 1V A
1 5 ,18 ,2 4 ,25
U 16
5
CPU_VCORE & VDD_NB
2 4
1 3
SU SB#
C P U _ V D D _E N 2 7
Sheet 26 of 35 PWRGD, RST
7 4 AHC1 G 08 GW R 43 3
27 PW R GD _VC OR E
15
Q27
G
C7 29
1 0 0 _1 % _0 6 D
Q15
G
SU SBL
S USBL
3 .3 V
29
D
Q4 5
2 2_ 0 4
R1 9 3 00 _ 0 4
R2 0
W D_ PW R GD
3 .3 V
0_ 0 4
NB_ PW RG D_IN
10
R2 2 0 2 0K_ 0 4
D22 VD D5
3 .3 V
24
C
T HER M_ RST #
A
3.3 VS
SYS_ RST #
SYS_ RST # 15
C3 6 0 *CH 7 51 H-4 0 PT
R 241
10 K _ 0 4
R2 4 0
5VS
1 0K _0 4 C D32
28
C
1 .8 V_PG
R4 1 7
D33
.1 U_ 5 0V_ 0 6
1 0K _0 4
A
A R B 7 51 V
3 .3 V
SYS_ PW RG D 2 4 D
RB7 5 1V G
S
D
Q2 6 G MT N 70 0 2Z HS3
S
Q2 5
R 42 0
MT N 70 0 2Z H S3
5
*4 .7u _ 6 .3V_ X5 R_ 06
1
1 0,1 4 ,16 A_ RS T# 14
R 38 5
PC IRST #
16
H11 C 2 76 D1 8 6
H 15 C 27 6 D1 8 6
H19 H2 1 C 2 76 D1 4 6 _1 C2 7 6 D1 46 _ 1
H 10 H1 3 C 27 6 D1 4 6_ 1 C2 7 6 D1 46 _ 1
H2 0 C2 76 D 14 6 _1
H2 H1 C 27 6 D1 4 6_ 1 C2 3 6D 7 9
H2 8 C2 7 6 D1 46 _ 1
2 3
H7
9 8
MT H 31 5 D1 1 1_ N4 5 6 7
H24 C 6 7D 67
H4 C 15 8 D1 5 8
H3 C1 5 8D 15 8
H27 C 1 58 D1 5 8
H2 6 C1 5 8D 15 8
3
2 3 4 5
H6
1 M TH 3 15 D1 1 1
9 8 7 6
2 3 4 5
H1 8
9 8 7 6
1
2 3 4 5
M TH 31 5 D1 1 1
2 5
H2 5
M12 M -MAR K1
M1 4 M-MA RK1
M6 M-M ARK1
M5 M-M ARK1
M 11 M7 M -MAR K1 M -MAR K1
M4 M-MA RK1
M1 0 M-M ARK1
M1 3 M-M ARK1
M3 M8 M -MAR K1 M -MAR K1
M9 M-MA RK1
M2 M-M ARK1
M1 M-M ARK1
2 3 4 5
1
9 8 7 6
1
2 3 4 5
M TH 31 5 D1 1 1
H1 7
9
1
M TH 31 5 D1 1 1_ N3 4 6 78
H 12
BUF _ PL T_ RST # 1 8,2 1 ,2 4
MC7 4 VHC 1G 0 8D F T 1G * 0_ 0 4
PC IE_ RST #
1
H8 C6 7 D6 7
U6 4
2
* 0_ 04
R419
H1 6 C2 7 6D 1 86
1 0 K _0 4
C3 88
2 3 4 5
H1 4
9 8 7 6
1 M TH 31 5 D1 1 1
H 22
1 M T H3 15 D1 1 1
9 8 7 6
2 3 4 5
H2 3
1 M TH 3 15 D1 1 1
9 8 7 6
2 3 4 5
H5
1 M TH 3 15 D1 1 1
9 8 7 6
2 3 4 5
H9
1
9 8 7 6
M TH 3 15 D1 1 1
9 8 7 6
M T H3 15 D 11 1
PWRGD, RST B - 27
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
VCORE_Core OFS/VFIX EN GND
Offset & Droop O
+3.3V +5V
SVI
VFIX
O
X
X O
O X
X X
CP U_ V DD0 P R21 9 1 0_0 6
CP U_ VDDNB 0520-J EMI CHG "*" CP U_V DDNB _RUN_ FB _ H 5
EMI C 96
.1 U_1 6V _0 4
C36
*.01 U_50 V_0 4
Meta l VID C odes SVC
SVD
Output
0 0
0 1
1.1 1.0
1
0
0.9
1
1
0.8
CP U_V DDNB _RUN_ FB _ L 5 VN I 5 VS PR2 20 10 _0 6
S GND5
1u _1 0V _0 6 P R38 *15 mi _ l sh ort
VFIX EN VID Codes
s m a r g a i D c i t a m e h c S . B
P C23 6
4 0 _ V 0 5 _ P 3 3
S GND5
SVC
SVD
Output
0
0
1.4
0
1
1.2
1 1
0 1
1.0 0.8
V IN PR1 75 10 _0 6
4 0 _ V 0 5 _ P 0 0 0 1
P C21 1 9 0 0 1 2 2 C C P P
0.1 u_ 50V _ 06
4 0 _ % 1 _ K 2 2
8 0 _ V 5 2 _ u 6 7 3 . 1 4
1 2
P R17 3 1 0_0 6
S GND5
4 0 _ V 0 5 _ P 0 0 0 1
PQ3 1A SP 8K 1 0S F D5TB
8
UGAT E _NB
1
8 0 _ V 5 2 _ u 8 7 5 . 4 C P
C P
C43 3 .1 U_1 6V _0 4
P C23 7
+ 2
3 30U _CA R31 5L CPU_ VD DNB
7
PHA S E _NB
4 7 7 0 1 2 R C t P P r o h s _ l i m 5 1 *
P L1 1
1
3A
2
4 7. UH_7 *7* 3.5
5 6
1
+
t r o h s l_ i m 5 1 *
P Q3 1B S P 8K 10 S FD5 TB
3
LGA TE _NB P R1 76 1 1.5 K_ 1% _04
2
P C13 4
P C2 08
22 0u _4 V_ D
1 0u _6 .3 V _X 5R_0 6
4
S GND5 PR1 77 44 2. K _0 4 3.3 VS 5V S
Sheet 27 of 35 VCORE_Core
3.3 VS PR1 83 *10 K_ 04 P R18 5
2 6 P WRGD_ V CORE
SGND5
P R 1 80
0 _ 06
P R 1 82
* 0 _ 06
PR 184
*1 0K_0 6
S GND5
* 15m li _s ho rt
5
CP U_S V D
5
CP U_S V C
1
PR1 78
*1 5mil _sh ort
3
PR1 09
*1 5mil _sh ort
4
PR1 19 E N_V CORE
*1 5mil _sh ort
PR1 92
0_ 06
5 6 7
PR1 95
PC2 20
255 _1 %_ 04 P R19 6
470 0P _5 0V _ 06
S GND5
P R19 3 1 07 K_ 1%_ 04
P R19 4 1 0K _1 %_ 04
54.9 K _1% _0 4
11
100 0P _5 0V _ 04 P C22 4 18 0P _5 0V _ 04
12
P R19 8
6.8K_ % 1 _ 04
P C22 6
10 00P_ 50 V_ 04
IS P _0 P R20 8 1 0_0 6
P R20 2
B N _ P
M O C
P C21 2 0.1 u_ 50V _ X7 R_06
8 9 7 7 1 1 R R P P 2 3 1 4 4 4
4 4 B N _ T E S F
B N _ N E S V
B N _ N T R
9 3
0 4
B N _ T E S C O
B N _ D
N G P
8 3
B N _ E T A G L
B N _ E S A H P
PW ROK
P U1
B N _ E T A G UBOO
T_NB
UGA T E_ 0
Pin 49 is GND Pin
SV D
P HA S E_ 0
SV C
P GND_ 0
ISL6265_QFN_48 6x6
ENA B LE
LGA T E_ 0
RBIA S
PV CC
P R18 1 1_ 06
35
P GND_ 1
FB _ 0
P HA S E_ 1
COMP_ 0
UGA T E_ 1
0 _ N S I 4 1
0 _ N E S V
0 _ N T R
1 _ N T R
1 _ N E S V
1 _ F F I D V
6 9 5 7 8 1 1 1 1 1 t t t r r r o o o h h h 1 _ s s s l_ l_ N l_ i i T 6 i m m R 0 m 5 _ 5 5 1 1 0 1 * * *
1 _ B F 0 2
B OOT_ 1
1 _ P M O C 1 2
1 _ W V 2 2
4 0 _ % 1 _ K 8 . 6
P C23 0 0 .1u_ 50 V_ X7 R_0 6 5 0 2 R P
IS N_0
6 0 2 R P
4 0 2
R P
7 0 2 R P
1 _ P S I 3 2
4 0 _ V 0 5 _ P 0 0 0 1
4 P R18 6 1 _06
34
UGA TE _0
33
PHA S E _0
PC2 15 0.1u _5 0V _X 7R_ 06
PQ1 7 IRF 7 41 3Z P BF
C59 9
*0.1 u_5 0V _ X7R_ 06
*0.1 u_ 50V _ X7 R _06
5 6 7 8
PQ2 3 AP 9 412 GM 4
1 2 3
PQ1 6
AP 9 412 GM LGA T E_ 0
0520-J EMI CHG
5V S
6 0 _ R 7 X _ V 0 5 _ P 0 0 0 1
P R18 8 *1 5m li _s ho tr
IS P _0 IS N_0
P C21 9 2 .2u_ 16 V _X7 R_0 6
P HAS E _1
5 6 7 8
4
UGA TE _1
PQ2 8 IRF 7 41 3Z P BF
8 8 8 8 0 0 0 0 _ _ _ _ V V V 5 V 5 5 5 2 2 2 4 2 _ 7 _ 1 _ 2 _ 5 u 5 7 u 2 u 2 2 u C 7 C . 2 7 . 7 . 4 C C . P 4 P 4 4 * * P * P *
C _ 9 + . 1 _ V 5 2 _ 5 u 2 5 1 1 * C P
1 _ N S I
P C2 25 0 .1u _5 0V _X 7R_ 06
5 6 7 8
4
4 2
PQ2 7 AP 9 412 GM
1 2 3
P R21 2 1 0_0 6
0 1 2 3 2 R 2 P C P
Par alle l
1.8V P R21 4 1 0_0 6
Close to CPU socket
P R21 3
* 1K_0 6 RTN_ 1
3 3 2 C P
6 0 _ V 0 5 _ 4 P 0 _ 0 % 0 7 4 1 _ K 1
4 3 2 C P
4 0 _ V 0 5 _ P 0 0 0 1
PQ2 6 1 2 3
AP 9 412 GM
0520-J EMI CHG
P R21 8 1 0_0 6 CP U_ VDD1
P R21 1
6 1 2 R P
4 0 _ 5 1 % 2 1 R _ P 5 5 2
7 1 2 R P
6 0 _ R 7 X _ V 0 5 _ P 0 0 0 1
CP U_V DD1
P R20 0 *1 5m li _s ho tr
3 9 . D 5 _ * V 6 . 5 6 2 . * _ 6 . F 6 U 2 V _ 0 3 5 3 1 . 1 3 C 2 P+ u _ + 0 6 6 5 5 2 C P
6 0 _ R 5 X _ V 3 . 6 _ u 0 1
4 0 _ V 5 Y _ V 0 1 _ u 2 2 . 0
4 0 _ R 7 X _ V 0 5 _ u 1 0 . 0
7 2 2 C P
8 2 2 C P
9 2 2 C P
P R20 1 *1 5m il_s ho r t
0514-J c h a n g e M- D 7 3 4 3 t o S C A R 2 50 330uF to 560uF
ISP _ 1
P R1 15
5V
V CORE _ON
P R 1 17
4 0 _ % 5 1 3 _ 2 K C 9 . P 4 5
P R 1 18
EN_ V CORE CP U_V DD1
* 0 _ 04
D
1 00 K _04
N O R V C B K
26 CP U_V DD_ EN
1 0K _0 4
EMI
P R1 12
0 _0 4
Z 33 01 1 D
G
0.1 u_ 50V _ 06
S GND5
S
P J6 P Q3 0 OP EN-1 mm M TN70 02 Z HS3 2
P C13 1 S GND5
PC4 5 . 0 1U_5 0V _ 04 P Q29 MT N700 2Z HS 3
G
S
B - 28 VCORE_Core
8 1 2 C P
3 .65K _ 1%_ 04
24
5 CP U_V DD1 _RUN_ FB _ H
7 1 2 C P
7 X _ V 0 5 _ u 1 0 . 0
P R20 9 4 .02K _ 1%_ 04
4 0 _ V 0 5 _ P 0 8 1
5 CP U_ VDD1 _RUN_ F B_ L
4 0 _ R
0 . 36 U H _ 10 *1 0 * 4. 1
C60 2
5 6 7 8
4
IS N_1
P C23 1 0 .1 u_ 50 V_ X7 R_0 6
6 1 2 C P
4 0 _ V 5 Y _ V 0 1 _ u 2 2 . 0
18A P L 10
P R19 9 1 _06
6 0 _ R 5 X _ V 3 . 6 _ u 0 1
0514-J c h a n ge M - D 7 3 43 t o S C A R 25 0 330uF to 560uF
1 2 3
25
5 CP U_V DD0 _RUN_F B _H 5 CP U_ VDD0 _RUN_ F B_ L
3 9 . D 5 _ * V 6 . 5 6 . * 2 _ 6 . F 6 7 _ U 0 1 V 3 1 5 1 3 . C 2 P+ u _ + 0 6 1 2 5 2 1 C P
P R18 9 *1 5m il_s ho r t
V IN
28
26
18A
0 . 36 U H _ 10 *1 0 * 4. 1
C6 01 5 6 7 8
30
27
CP U_V DD0
2 0 0 9 1 00 9
4
LGA T E _ 1
0624J Del PC23
8 8 8 8 0 0 0 0 _ _ _ _ V V V V 5 5 5 *0.1 u_ 50 V_ X7 R_0 6 2 5 2 2 3 2 _ 4 2 _ 0 3 _ 1 u 1 u _ 0 u 1 u 2 7 2 7 7 . C . 1 7 . C . C 4 C 4 P 4 P 4 P P * *
C60 0
PL7
32 31
C59 8
1 2 3
1 2 3
LGA T E_ 1
VDIF F _0
5 6 7 8
36
29
VW _0
V IN
7 3
B OOT_ 0
0 _ P S I
P R20 3 4.0 2K _1 %_ 04
5 4
PGOOD
3.65K_1% _0 4
Close to CPU socket
B N _ B F
OFS /V FIX E N
3 1
CP U_ VDD0
C C V
6 4
OCSE T
10 PC2 23
N I V
7 4
8 9
1K _ 1%_ 04 PR1 97
8 4
D N G
2
5 CPU_ P WRGD_ S VID_ REG
9 4
PC4 6 * .0 1U_ 50V _ 04
0520-J E MI C H G
Schematic Diagrams
0.9V, 1.8V, 1.8VS, 1.5VS 5V VIN A
VD DQ
Vout = 1.5V ( 1 + Ra / Rb ) PR 1 48
PC 1 6 9
PR 1 5 2
Ra
PR 14 5
PR 58
1 M_ 0 4
1 0 _0 6
PD 8
1 0 _0 6
3
PC 6 7 1 u _ 10 V_ 0 6
1 u _ 1 0V _0 6 6 8
PR 1 54
9
1 0 _0 6 PR 1 5 3 1 0 _ 06
10
PC 1 7 2
P C1 7 4
PR 15 5
PC 16 4
1 u _ 10 V_ 0 6
* 0 .0 68 u _ 50 V _ 0 6
1 0 _0 6
1 0 00 p _ 50 V_ X7 R _ 0 4 1 u _1 0 V_ 0 6
VSS A 2
PJ 10
1
T ON
B ST
C
7
1 . 8V _ P G
VIN
PC 1 62
23
VT T S VC CA
IL IM
PC 16 8
LX DL
21
PR 1 46 0 _ 06
VD DQ
O PEN-3 m m PR1 4 9
PC 1 65
20 K_ 1 % _ 04
4 .7 u _6 .3 V_ X5 R_ 0 6
12 13
PC1 6 6 P C1 7 1 1 0u _ 6 .3 V_X5 R _0 6
PC 1 70
* 4 .7 u_ 6 .3 V_ X5R _ 06
PL1 2
5 6 7 8
DD _ ON #
D D_ ON #
S
2
O PEN-6 m m PD 17 F M 58 2 2
+PC 15 8
+ PC1 5 6
2 2 0u _ 4 V_ V_ A
1 2 3
PC 1 57
*2 2 0u _ 4 V_ V_ A
A
Sheet 28 of 35 0.9V, 1.8V, 1.8VS, 1.5VS
PC1 5 9
0 .1 u _1 6 V_ Y5 V_ 0 4
0 .01 u _ 5 0V_ X7 R_ 0 4
1u _ 1 0 V_ 06
D N G
PG ND 1 PG ND 1 PG ND 2
18 16 17
PR 15 0 VSSA *1 5 m i l _ s h or t_0 6
5 2
PC 7 1 PQ7
G
6A
1 .8 VEN
4 7 K _0 4 D
2 0 ,2 5,2 6 ,2 9
P J2 1
C
PQ3 3 AP9 4 1 2G M
20 PC1 6 3
EN /PSV VT T EN
1.8 V VDD Q
2 .5 UH _6 .8 *7 .3 * 3.5
19
VD DP2 VD DP2
SC 4 86
P R 60
V DD P1
15 u _ 2 5V_ 6 .3 *4 .4 _ C
1 2 3
PR 1 47 7 .1 5 K_1 % _ 0 4
4
VT T VT T
+PC1 6 0
0 .1 u_ 5 0 V_ Y5 V_ 0 6
PQ3 2 AP9 4 0 8G M
5V
1 11
1 u _1 0 V_ 0 6
5 6 7 8
4
22
4
14 15
PC 16 1
0 .1 u _5 0 V_ Y5 V_ 0 6
C OM P
VSS A
1.5A
5V
2 6
24
FB R EF
DH
*0 .1 u _ 16 V_ Y 5V _0 4
1 0 K_ 1 %_ 0 4
5
0 .9 V
PG D
PC 17 3
PR 1 5 1
Rb
VD DQ S
P C1 6 7 2
2 K_ 1 % _0 4 1 0 0 p_ 5 0 V_ NPO _ 04
F M 0 54 0 -N
PU 8
MT N 70 0 2 Z HS 3
O.C.P Functi on Design
.1 U_ 1 6 V_X7 R _0 6
10uA * R(I li m) = OCP * Rds(on) 10uA* 4. 7K= OCP* 4mohm(IRF7832)
PR 5 9
OCP= 10uA*4.7K / 4mohm
VT T EN
5V 4 7 K_ 0 4 D
20 ,2 5 ,2 6,2 9
D D_ ON #
PR6 1 0_04
PQ6 G S
OCP= 11.75A
PC 7 2
MT N 70 0 2 Z HS 3
.1 U_ 1 6 V_X7 R _0 6 5V
1 .8 V PC1 9 5
PR6 2 2 5 ,2 6,2 9
SU SBL
PC1 9 4
0. 1u _ 1 6V _Y 5 V_ 04 10 u _ 6 .3V _X5 R _ 0 6
* 0 _0 4
5V
5V
P R 16 6
PR 1 6 5
* 10 K _ 0 4
SUSB L
5 9 7
1 PQ 3 8
G
PC2 0 1 22 0 0 p _5 0 V_ X7R _ 0 4
S
1 u _ 10 V_ 0 6
8
1 0 0K_ 0 4 D
25 ,2 6 ,2 9
1 .5V S_ PW RG D
PC 1 93
P U1 0 VIN VIN PO K EN G ND
V CN TL VO UT VO UT VF B
6
1 .5 VS
2.5A
4 3
2
Ra
PR 1 67
PC 2 04
8 .8 7 K_ 1% _ 0 4
6 8 p _5 0 V_ NPO _ 0 4 1 0 u _6 .3 V_ X5R _ 0 6 1 0 u _6 .3 V_ X5R _ 0 6 0 .1 u _1 6 V_ Y5 V_ 0 4
PC 1 96
PC 1 99
PC 1 97
A X6 6 1 0
M T N7 0 02 Z H S3 PR 1 68
Rb 0514-J power change OZ803 3 to AX66 10
1 0 K_ 1% _ 0 4
Vout = 0.8V ( 1 + Ra / Rb )
0.9V, 1.8V, 1.8VS, 1.5VS B - 29
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
1.1VS, 1.2V, 1.2VS VI N
CLOSE TO MOSFET 5V
+P C1 1 4
*1 5 u _2 5 V _ 1 .9_ C
PC6
PC5
PC3
4 .7 u_ 2 5 V _ X5 R _0 8
4 .7 u_ 2 5 V _ X5 R _0 8
0 .1 u_ 5 0 V _ Y 5 V _ 0 6
PR 1
1 0 _ 04
P C9 6
1 u_ 01 V_ 06
PR 7
1 0 _ 04
P C1 0 7
1 u _ 10 V_ 06
S G ND 1 S G N D 2 26 1 .1 V _ NB _P G
26
A
1 .2 V _ S B _ P G
A
PD1 F M 05 4 0 -N C
C
27 P C9 3
2A
*1 0 00 p _ 50 V _ X 7 R_ 0 4
PowerPlane
s m a r g a i D c i t a m e h c S . B
1.1VS 1
PR74 1 . 1V _ N B
5A
P L6 2 .5 U H_ 6 .8 *7 .3 *3 .5
2
OP E N -5 m m
Sheet 29 of 35 1.1VS, 1.2V, 1.2VS
P C1 0
1 00 p _ 5 0V _ N P O _ 0 4
Ra
12 K _ 1 % _0 4
PC14
1 u_ 1 0 V _ 60
17 6
P R 75 6 .8 K _1 % _ 0 6
3 2 1
PD9
2 20 u _ 6 .3V _6 .3 *6 _ B
3
4
* 10 _ 0 8
+ P C 94
P R5
1 u_1 0 V _06
PQ12 A P9 4 0 8 GM
8 7 6 5
C
P J5
PC7
PC8 0 .1 u _ 1 6 V _ Y 5 V _ 0 4
4
F M 5 82 2 A
5 2
PQ13 A P9 4 1 2 GM
8 7 6 5
4
3 2 1
7 26 24 8 22
Vout = 0.5V ( 1 + Ra / Rb ) Rb
P C3 1
P C2 6
P C2 7
0 .1 u _ 50 V _ Y 5V _0 6
4 .7 u _ 25 V _ X 5 R _ 0 8
4.7 u _ 2 5V _ X 5 R_ 0 8
P D2 F M0 5 4 0-N
P GO OD 1
P G OO D2
V DD P 1
V C CA 1
V DD P 2
V C CA 2
DH 1
TO N1
IL IM 1
TO N2
LX1
IL IM2
FBK1
L X2
V OU T1
1 000 p _ 50 V _ X7 R_ 0 4
P C1 1
1 000 p _ 50 V _ X7 R_ 0 4
11
S G N D 1S G ND 2
23
P R 85
1 M_0 4
9
P R 79
7 5 K0 _ 04
2A 5 6
B S T2
SC413
B S T1
25
20
D H2
DL1
P C1 2
13
D L2
E N/P S V 2
FBK2
E N/P S V 1
V OU T2
21 18
P C1 3 PR 8
Vout = 0.5V (1 + Ra / Rb )
7 8
0 .1 u _16 V_ Y 5V_ 0 4 4 5 . 3 6 K _ 1% _ 0 6
P Q2 1 A P 9 40 8 G M
19 16
5 6
12
7 8
A _ V _ V 4 4 _ 2 u 1 0 C 2 2 P *
PR98
P Q2 0 P D1 1 A P 9 41 2 G M F M5 8 22
4
10
C
1 0 _ 08
1 2 3 A
5V
PR6
1 2 D D N N G G A A
10 K _ 1 % _0 4
8 2
S GN D1
4 1
P C 1 22
1 2 D D N N G G P P 1
+
Power Plane 1 .2 V _ S B
P L9 2 .5U H_ 6 .8 *7 .3 *3 .5
1 2 3
B _ 6 * 3 . 6 _ V 3 7 . 2 6 _ 1 u C 0 2 P + 2
Ra
1 .2 V S
PJ8
6A
1
PR2
PC9
1 4K _1 % _ 0 4
2 0 p _5 0 V _ NP O_ 0 4
2
OP E N-6 m m
PR3 1 0 0 0p _ 5 0V _X 7 R_ 0 4
Rb
1 0K _1 % _ 0 4
PU4
5 1
S GN D2
SG ND 1
SGN D2
5 VS P R8 9 6 0.4 K _ 1 % _ 04 P R9 0 PQ18 * MT N 70 0 2 Z HS 3
D
3.3 V
1 0K _0 4
P C8 4
S
D
P C8 5
5 9 7
P Q2 4 * MT N 70 0 2 Z HS 3 G
P R 92
26
0_ 0 4
1 .2 V _ P G
3 .3 V
P R 65
8
1 0K _ 0 4
1 D
P R 77
Voltage 1.0V 1.1V
1 0 K _0 4
2 0,2 5 ,2 6 ,28 D D_ O N#
PQ 9
G S
M T N7 0 0 2Z HS 3
P C8 6 * 0 .1u _ 1 6 V _ Y 5 V _ 04
1u _ 1 0V _0 6
PU3 V IN V IN P OK
S T RP _ D A T A 1 0
S
STRP_DATA 0 1
3 .3V
P C8 3
1 0 u _ 6.3 V _ X 5 R_ 0 0 6.1 u _ 16 V _ Y 5V _ 0 4
G
V C NT L V OU T V OU T
GN D
VFB
S US B L
2 5 ,2 6 ,28 S US B L
P Q1 4 MT S N 7 00 2 Z HS 3
3 2
Ra
P R6 3
P C 79
10 K _ 1 % _0 4
6 8p _ 5 0 V _ NP O _0 4 1 0u _ 6 .3 V _X 5 R _0 6 1 0u _ 6 .3 V _ X5 R _0 6 0 .1u _ 1 6V _Y 5 V _ 04
P C8 1
P C8 2
P C7 8
A X 6 6 10 P R6 4
Rb
P C 95 . 1U _ 16 V _ 0 6
1.2 V
1A
4
EN
D
G
6
0514-J pow er change
20 K _ 1 % _0 4
Vout = 0.8V ( 1 + Ra / Rb )
OZ8 033 t o AX6610 S GN D2 P R7 8 5V
EMI
4 7K _ 0 4
1 .2 V
D
P R7 6 2 5,2 6 ,2 8 S US B L
0 _ 04
PQ15
G S
2 0 ,2 5 ,26 ,2 8 D D_ ON #
PR 87
*0 _ 0 4
P C9 8
.1 U_ 1 6 V _ 06 M TN 7 0 02 Z H S 3
S G ND 1
P R8 6 PR4 *1 5 mi l_ sh o rt_ 0 6 *1 5 mi l_ sh o rt_ 0 6
S G ND 1
B - 30 1.1VS, 1.2V, 1.2VS
S GN D 2
PC77
* 0.0 1u _50 V_ X7 R_ 04
PC80
0 .0 1u_ 50 V_ X7 R _04
Schematic Diagrams
VDD3, VDD5 PC1 7 9 0 .0 1 u _5 0 V_ X7 R_ 0 4
VIN1 L GAT E1 P R 55 PC 64 2 .2 u_ 6 .3 V_ Y 5V _0 6
C
PD 7
P D2 1 F M 0 5 40 -N
*F M0 5 4 0- N
1 0 _0 6
PC1 7 8 0 .0 1 u _5 0 V_ X7 R_ 0 4
C
S GN D4
C
A
VI N PR 4 4
1 0 K_ 0 4
1 2
2 0 K_ 1 % _0 4
1
D
S GN D4 20
A P
2
B F
3
L B F
EN L 19
AG ND 17 16
SGN D4
P R4 9
PC5 9
PR 4 5
* 1 0K _0 4
6 0 _
1 0 K_ 1 % _0 4 0
6 _ R 7 X _ V 5 2 _ u 1 . 0 *
R 7 X _ V 5 2 _ u 2 2 0 . 0
SG ND 4
P C6 0
SGN D 4
4
5
T A D U O D V V
C
P D1 9 F M 0 5 40 -N
SY S1 5V P C1 9 2
PR 4 8
5 1
1 u _2 5 V_ 0 8
3 1
2 1
PC1 8 2
6 INT VC C 2
7 PC 7 0
8 9
5 6
D N
LX
5 6
1 1
L G AT E1
VDD 5 PJ 4
4A
1
P R4 6 PQ3 5 AO4 4 6 8
PC 6 2
2
5m m
9 1 K_ 1 % _ 06
*2 2 0 p _ 50 V_ N PO_ 0 4 PC 7 4
% 1 _
S GN D4
PL 4 4 .7 UH _ 6 .8 *7 .3 *3 .5 1 2
1 2 3
K 7 3 1
PC 18 4
7 8
4
4 0 _
4 .7 u_ 2 5 V_ X5 R _ 0 8 4 .7 u_ 2 5 V_ X5R _ 0 8 SY S5 V
PQ3 6 AO4 4 6 8 1 2 3
10
G P
PC 18 3
*1 5 u _2 5 V_ 1 .9 _ C
7 8
4
1 u _ 2 5V _ 08
PC7 5
+
0. 1u _ 5 0 V_ Y5 V_ 0 6
BS T DH
4 1
2 2 0 0 p _5 0 V_ X7 R_ 0 4
SC418
VL D O
SC418
D O V P S D O L G P D P R V D
PC 6 8
VIN
EN /PSV IL IM
PU 2
C N
RT O N
18
4 0 _ R 7 X _ V 0 5 _ p 0 0 0 1
2 2 0 0 p _5 0 V_ X7 R_ 0 4
7 5 K_ 06
S GN D4
PC 6 1
SY S1 0V P C1 9 1
P D2 0 F M 0 5 40 -N A
PR 5 3 P R5 1
SY S5 V
PR 5 6
1 0 0 0 p_ 5 0 V_ X7 R_ 0 4 4 22 K _1 % _ 06
A
P D2 2 F M 0 5 40 -N
A
PC6 5
IN T VCC 2 PR 5 2
C
A
1 0 _0 6
PR5 0
1 31 K _1 % _0 4
P R 57
1 5 K _ 1 % _0 4
P R5 4
* 10 0 K _ 0 4
+PC 7 3
P R4 7
PC 6 3
Sheet 30 of 35 VDD3, VDD5
0 .1 u _1 6 V_ Y 5V _0 4
1 5 0 u_ 6 .3 V_ V _ A
1 0 K_ 1 % _ 06 P C6 9
PC 66
1 u _ 1 0V _0 6
1 u_ 1 0 V_ 0 6
*3 0 p _ 5 0V _N PO _0 4
SG ND 4 PN C 1
1 5m i l_ sh or t SG ND 4
SG ND 4
S YS5 V
IN T VC C2
P R1 6 1 0_06
P R1 6 0 * 0 _0 6
VIN A
PD1 8 F M 0 54 0 -N
Ra
P R1 5 8 PC1 8 9
P R1 6 2
P R 15 7
2 0 K _ 1 %_ 0 6
PR 15 6 1 5m il _ s ho rt 5 6
C
PR 16 4
1 0 K_ 1 % _ 04 10 0 p _ 50 V_ N PO _0 4
*1 0 m il _ s h o rt 3 1
12 11
4 1
5 1
PU9 SC4 1 2 A
6 1
C C H M . I . D L N N I
EN
LX
PG D
BST
VO UT
VCC
10 P R1 5 9
4 0 _ R 7 X _ V 0 5 _ u 1 0 . 0
* 1 0K _0 4
C980503
Rb PC1 9 0
P R1 6 3
2 .9 4 K_ 1 % _ 04 *3 3 p _ 50 V_ N PO _0 4
D N C C T N . . N N R G
8
7
6
5
4 .7 u_ 2 5 V_ X5 R _ 0 8
1
SYS 3V
PL 1 3 4 .7 UH _ 6 .8* 7 .3 *3 .5 2
VD D3 PJ 1 1
5A
1
2
2 5mm
5 6
7 8
PQ3 4 AO4 4 6 8
4
DL
PAD
PC 18 8
1
4 FB
PC 1 87
4 .7 u _ 2 5V _X5 R _ 08
PQ8 AO4 4 6 8 1 2 3
PC 1 81 0 .1 u _2 5 V_ X7 R_ 0 6
3
9
PC 76
7 8
4
1 0 K_ 0 4
P C1 7 7
PC 17 5 +
PC 1 85 0 .1 u_ 1 6 V_ Y5 V_ 0 4
1 2 3
17 PC 1 86
1 5 0u _ 6 .3 V_ V_ A
1 u _ 1 0V _0 6
0 .0 1u _ 5 0 V_ X7R _ 0 4
VDD3, VDD5 B - 31
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
Charger, DC In CHARGER
#Charge Curre nt 3.0 A VA
J A CK 1 2 DC -G 0 2 6-B 2 2
VA
P L5 HC B 45 3 2 K F -80 0 T 60
1 2 GN D1 GN D2
8 7 6 5
PR24 P C1
P C2
P C 92
P R 73
P Q1 1 A M4 83 5 P
1 3 0 K _1 % _ 04
4
0.1 u _ 50 V _ Y 5 V _ 06 0 .1u _ 5 0V _ Y 5V _ 0 6 0 .1u _ 50 V_ Y 5 V _ 0 6 1 0 K_0 8
4 1 0 _ 7 K R 0 0 P 2
PR17 1 0 K _ 1% _ 0 4
s m a r g a i D c i t a m e h c S . B
PC20
P C3 0
4 0 _ 0
4 0 _ 0
0 7 R P
9 6 R P
8 0 _ R 5 X _ V 5 2 _ u 7 . 4
6 0 _ V 5 Y _ V 0 5 _ u 1 . 0
6 0 _ V 5 Y _ V 0 5 _ u 1 . 0
1 9 C P
0 9 C P
8 8 C P
9 8 C P
P C 32
P C2 8
P C 55
P C1 1 6 1u _ 2 5V _ 0 8
A
0_04
1 2 3 4 5 6 7 8
V DD 3
P R2 8
A C _I N #
24
C
C
A
B
P Q2 2
TOTAL POWER ADJ
P R8 8
4 0 2 _ 1 % 1 R _ P K 0 1
PC25 1 00 p _ 50 V _ NP O _0 4
P C1 15
S
V_BAT PR9 2 0 0 K _0 4
P Q3 A O3 4 09 D
4 0 8 _ 1 % R 1 P _ K 0 2
0 _ 04
P R1 1
P C2 2
4 0 _ % 1 _ K 4 . 0 6
6 0 _ V 5 Y _ V 0 5 _ u 1 . 0
24 23 22 21 20 19 18 17 33
P C 11 1
M TN 70 0 2 Z HS 3
9 9 C P
9 0 1 C P
4 0 1 C P
5 0 1 C P
7 9 C P
9 2 C P
PIN25th FOR 2SCONNECT TOGND FOR 3SCO NNECT N.C. FOR 4SCONNECT TOVREFPIN P R 20
* 0_0 4
0 .1 u _5 0 V _Y 5 V_ 06
PR15 6 0 _ V 5 Y _ V 0 5 _ u 1 . 0
6 0 _ V 5 Y _ V 0 5 _ u 1 . 0
0 1 1 C P
6 0 1 C P
4 0 _ % 1 _ K 2 . 9 3
4 9 .9 K_1 % _ 04
CHARGE CURRENT ADJ
PR14 1 K _ 1 %_ 0 4
1 2 R P
PR13
S GN D6 S G N D 6 S G N D 6
2 2 K _ 1% _ 04
1 0 K _ 1% _ 0 4 S G ND 6
V_BAT
0.5V/1A 2 4 TO T A L_ CU R
0.5V/1A
2 4 CUR _ S E NS E
P R2 2 1
1 00 K_ 0 4
P Q4 3 A O3 4 15 S
D
P R2 2 6 1 00 K _ 0 4 CE C LM
M TN 7 00 2 Z HS 3
MT N7 0 0 2Z H S 3
V C HG-S E L 2 4 P Q4 2
P C 18
PC17
3 0P _5 0 V _0 4
3 0 P _5 0 V _ 04
3 0 P _ 50 V _ 0 4
JB A T T A 1 1 2 3 4
1 .5 M_ 0 4
0511-J Add f or 2800mABat.
2N 70 0 2 W
P R 84
5 B TD -0 5T I1 G
FOR C5500
MT N7 0 0 2Z H S 3
P R2 28 1 0 0 K _0 4
P C1 9
G S
S
P Q1
D
2 N 70 0 2 W
P R 22 7 P Q 45
2 4 CE L L _ CON T ROL S
P J1 O P E N-1 m m
FOR C4500 1 2 3 4
H C B 1 0 05 K F -1 2 1T 2 0 H C B 10 05 KF - 12 1T 20 H C B 1 0 05 K F -1 2 1T 2 0
5
7 6.8 K _ 1 %_ 0 4 P Q 44 S
D
G 1
PL1 P L3 PL2
*B T D-0 5 TI1 G P R2 23 2 M _1 % _ 04
D
G
1 00 K _ 0 4
G
B A T_ D E T S MD _ B A T S MC _ B A T
V O LT _ S E L
G
C T L1
G
0.1 u _ 05 V _ Y5 V _ 06
P R2 25 1 8 K _ 1% _ 0 6
D
CH G_ E N
P C 2 41
JB A T T A 2 24 24 24
P R2 6
D
0520-J EMI ADD
PIN 17th CONNECT TOBATCONN.
10 2 K _ 1% _ 04
SYS5V
P R2 2
0 _0 6
S GND 6
2
S G ND 6
B - 32 Charger, DC In
6 0 _ V 5 Y _ V 0 5 _ u 1 . 0
S GN D6
P R 81
SG ND 6
C EL LS
SYS5V
S
8 0 _ R 5 X _ V 5 2 _ u 7 . 4
V OL T_ S EL
9 0 1 2 3 4 5 6 1 1 1 1 1 1 1
P R2 2 2
PQ2
8 0 _ R 5 X _ V 5 2 _ u 7 . 4
C TL 1
P C 24 *2 2p _ 5 0V _N PO_ 04 P C 1 00 1 00 0 p _5 0 V _ X7 R_ 0 4 P R 82 2 2 K _ 1% _ 0 4 P C 1 01 1 00 0 p _5 0 V _ X7 R_ 0 4 P R 83
0623-J PW R Add
PQ4
G S
8 0 _ R 5 X _ V 5 2 _ u 7 . 4
B A T _ V OL T 2 4
P R 10
S YS 5 V
S GND 6
P R1 6 3 00 K _ 1% _ 0 4
G
D
1 2 B 2 S L B - X - D L T L V T N T C L
V CC C U U G E V IN O O P -INC1 C C TL 1 +IN C1 GND A CIN VREF TRERM AL PAD A COK RT 2 2 3 -INE 3 CS 1 P P A D J 3 A DJ 1 1 C C 2 2 2 E T T C C M M J O BA T T COM P 1 N U U N N D O I I I - O O + - A C CS GND
1 K _ 1 %_ 0 4
DT C1 1 4E U A E
*0 .1u _ 5 0V _ Y 5V _ 0 6
8 0 1 C P
8 0 _ R 5 X _ V 5 2 _ u 7 . 4
VA
P C1 6 0 .01 u _ 50 V _ X 7R _0 4
P D4 UD Z 1 6B
2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2
MB 3 9 A1 32
1 0K _ 1 % _0 4
5 2 R P
C E LL S
P U5
S G ND6
4 0 _ 0 *
P R2 7
0623-J PW R Add
PC15
10 K _ 0 4
P Q2 5 B S P 8 K 10 S F D 5T B
4
8 0 _ R 5 X _ V 5 2 _ u 7 . 4
0 . 1 u _5 0V _Y 5 V_ 06
0 .1 u_ 5 0V _Y 5V _ 0 6 0 .1 u_ 5 0 V _Y 5V _0 6 0.1 u _5 0 V _ Y5 V _ 06 0 .1 u _5 0 V _Y 5 V _0 6
24
0 _0 4
VA
PC4
VA
3
P R9 1
V_BAT
PR8 0 0 .02 _ 1 %_ 3 2 8 0 _ R 5 X _ V 5 2 _ u 7 . 4
8
2 7 R P
VI N
#Total Power 60W
PL8 1 0 UH_ 6 .8 *7 .3* 3 .5
7 5 6
PD3 F M 05 4 0-N C
P C2 1
0 .1 u _5 0 V _ Y 5 V _ 06 0 .1 u _5 0 V _ Y 5 V _ 06 0 .1 u_ 5 0V _Y 5V _ 0 6
Sheet 31 of 35 Charger, DC In
P Q 25 A S P 8 K 1 0 S F D5 T B 2 1 8 0 _ R 5 X _ V 5 2 _ u 7 . 4
4 0 _ K 0 0 1
V _B AT
1 2 3
P R 68 0 .0 2_ 1 %_ 3 2
3 2 1
#Charge Voltage12.6V
P Q1 9 A M4 8 3 5P 5 6 7 8
4
V IN
Schematic Diagrams
Click Board CLICK BOARD CVDD3 CVDD3
CC2 0.1u_16V_Y5V_04
CC1 *0.1u_16V_Y5V_04
C5VS
CC3 *0.1u_16V _Y5V_04
C5VS
CVDD3
CVDD3 CVDD3
CR360
CR359
220_04
220_04
1
CR358 220_04
220_04
LED
3
1
CR361
POWER ON 1
CGND 1 2 3 4
CTP_DATA CTP_CLK
85201-04051 CGND
6- 20-94A50- 104 6- 20-9 4AA0-104 6- 20-94A70- 104
CGND
CJ_TP2
CJ_TP1
CGND
CJ_TP3
1 CTP_CLK 2 CTP_DATA 3 CTPBUTTON_L 4 CTPBUTTON_R 5 6 85201-06051
1 CLED_PWR# 2 CLED_ACIN# 3 CLED_BAT_FULL# 4 CLED_BAT_CHG# 5 6 85201-06051
CGND
CD26 Y G S
RY-SP155HYYG4
4
2
CLED _BAT_FULL#
CLED_ACIN#
CLED_BAT_CHG#
6- 52-5 5002- 04B 6- 52-5 5001- 040 6- 52-5 5002- 042
6- 21- 91A00- 106 6- 21- 91A10- 106 6-20- 94A70- 104
RY-SP155HYYG4
4
CLED_PWR#
CGND
6- 21- 91A00- 106 6- 21- 91A10- 106 6- 20-94A70- 104
Y G S
2
BAT LED
3
CD27 2
6- 52- 55002- 04B 6- 52- 55001- 040 6- 52- 55002- 042
Sheet 32 of 35 Click Board
E5120Q
CSW1~4 2 1
4 3
LIFT KEY
1 3
RIGHT KEY
CSW1 TJG-533-S-T/R
2 4
1 3
CTPBUTTON_L
CSW2 TJG-533-S-T/R
5 6
1
9 8 7 6
2 3 4 5
MTH237D91 CGND
CH1 1
9 8 7 6
2 3 4 5
CGND
CH4 1
9 8 7 6
CGND
1 3
CTPBUTTON_L
CGND
2 3 4 5
MTH237D91 CGND
CSW3 *TJG-533-S -T/R 2 4
RIGHT KEY
5 6
6- 53- 3150B- 245 6- 53- 3050B- 240 6- 53- 3050B- 241
MTH237D91 CGND
1 3
CTPBUTTON _R
CGND
6-5 3-31 50B- 245 6- 53- 3050B- 240 6- 53- 3050B- 241
CH3
2 4
5 6
CGND
2 3 4 5
LIFT KEY
CH2 1
CSW4 *TJG-533-S -T/R 2 4 5
CTPBUTTON_R
6
CGND
6- 53- 3150B- 245 6- 53- 3050B- 240 6- 53- 3050B- 241
6- 53- 3150B- 245 6- 53- 3050B-240 6- 53- 3050B- 241
9 8 7 6
MTH237D91 CGND
CGND
CGND
Cl ic k B oar d B - 33
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
Au dio B oar d/USB USB PORT A_U SBVC C AL 5 HCB1 6 0 8KF -12 1 T 25 A_ U SBVCC A _5 V
5
50mils
F L G# V OUT 1
2
AC9
3
1 0u _ 1 0V_ Y 5V_ 0 8
4
A GN D
A_ USBVC C2
60 mil
A_U SBVC C AU 1
V I N 1 V OUT 2 V I N 2 V OUT 3 EN #
GND
6
50mils
AC7
+
1 0 0u _ 6 .3V_ B_ A
7 8 1
R T 97 1 5B GS
A G ND
AC 1
AC5
AC6
0. 1u _ 16 V_ Y5 V _ 0 4
0 .1u _ 16 V_ Y5 V _ 0 4
AUSB_ PN2 AUSB_ PP2
A G ND A GND
A GND
6-02-09715-920
AR1 0 L61 4
0 .1u _ 1 6V_ Y 5V_ 0 4 1
* 1 0 m i _l sh or t _ 04 3
AG ND AUSB_ PN2 _ R
2
AUSB_ PP2 _ R
3
1 2 *A W C M2 0 1 2F 2 S-1 6 1T 0 3 AR1 1
4
* 1 0 m i _l sh or t _ 04
A J_ USB 1 V+ D ATA_ L D ATA_ H G ND
PI N SW AP
s m a r g a i D c i t a m e h c S . B
1 3 2 4 D D D D N N N N G G G G
US0 4 03 6 BCA0 8 1
1 2 3 4 D D D D N N N N G G G G
6- 21- B49C0-104 6- 21- B49B0-104
AG ND
TO M/B
AUDIO JACK
Sheet 33 of 35 Au di o Bo ard/USB
AMIC 1-L
A_ 5 V
A A A A A A A
AL 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
HEAD PHON E-R HEAD PHON E-L MIC_ SEN SE SPK_H P# HP_ SENSE USB_ PN2 USB_ PP2
A SPKOU TR + A SPKOU TR -
AC1 0
AC 4
10 0 p _5 0 V_ NPO_ 0 4
1 0 0p _ 5 0V_ N P O_ 0 4
MIC IN
6- 20- B2800- 106
BLACK AHP_ SEN SE
A_ AUD G
ASPK_ HP# AHEAD PHO NE-R
AR3
6 8_ 0 4
AL 2
F CM 10 0 5K F -12 1 T03
AHEAD PHO NE-L
AR5
6 8_ 0 4
AL 3
F CM 10 0 5K F -12 1 T03
8 7 21 3 -14 0 0 G
A_AU DG AG ND
2 6 L 1 2SJ -T 3 51 -S2 3
F CM10 05KF -121 T03
AJ_ AU DIO1
A MIC1 -R A MIC1 -L
5 AJ _ MIC1 4 3 R
AMIC _ SENSE AL 4 F CM10 05KF -121 T03
AMIC 1-R
5 AJ _ HP1 4 R 3 2 6 1
AR 9
AR 8
AC3
AC2
*1 K_ 1 %_ 0 4
* 1K_ 1 % _0 4
1 00 p _ 50 V_ NPO _ 04
L
2SJ -T 3 51 -S2 3
1 00 p _ 50 V_ NPO _0 4
HEADPHONE
6- 20- 53A00- 114
BLACK
6-20- B2800-106
A_ AUD G
AC1 4
0 . 1u _1 6V _ Y 5V _ 04
AC1 5
0 . 1u _1 6V _ Y 5V _ 04
AC1 3
0 . 1u _1 6V _ Y 5V _ 04
AC1 6
0 . 1u _1 6V _ Y 5V _ 04
AGN D
ASPKO UT R+
AL 7 F C M1 0 05 KF -1 2 1T 0 3 1 2
ASPKO UT R-
AL8 F C M1 0 05 KF -1 2 1T 0 3 1 2
AH3 C5 9 D5 9
2 3 4 5
AH 2 1
9 8 7 6
2 3 4 5
M T H2 76 D 11 1 AGN D
B - 34 Audio Board/USB
AH4 1
9 8 7 6
MT H2 7 6 D1 1 1 AGN D AG ND
A G ND
ASPKO UT R+ _ R ASPKO UT R-_ R
AC8 1 80 p _ 50 V_ NPO _0 4
A_ AU D G A_ AUD G
A H1 C 5 9D 59
AC 11 1 0 0 0p _ 50 V_ X7R _ 04
AR1
* 1 0 m i _l s h or t _ 04
C4 5 5 1 80 p _ 50 V_ NPO _ 04
AJ _ SPKR1 J_SPK1
2 1 1 2 85 2 0 4-0 2 00 1 PC B F o otp rin t =8 5 2 04 -0 2 R
6- 20-43150-102 6- 20-43110-102
Schematic Diagrams
Power Switch Board POWER SW & LED & HOT KEY S_ 3 .3VS
S_ 3 .3VS SJ _ SW 1 1 2 3 4 5 6 7 8 9 10
S_ 3 .3 V
SR2 S_ 3.3 VS SJ _ SW 2
SM _B TN # SW EB _W W W # SW EB _EM AIL # SL ID_ SW #
SM GN D S_ VIN
* 5 05 0 0-0 1 0 41 -0 0 1L
20mil
20mil
Z4301 SC6
A
A
SD3 * HT -1 5 0N B-DT
SM G ND
6- 52-56001- 023 6- 52-56001- 028 6- 52-56000- 020 6- 52-56001- 022
6- 20- 94K10-108 10 pin & 8 pin co-lay
AC
1 0 0 K _ 1% _ 0 4
SU1 1
SM _BT N # SW EB_ W W W # SW EB_ EM AIL # SL ID_ SW #
8 8 48 6 -0 80 1
0 .1u _ 1 6V_ Y 5V_ 0 4
VC C
OU T
2
SLI D _ SW # A
D N
SC 2
SC1
G
3
SD 1
M H2 4 8- ALF A- ESO
0 .1 u _1 0 V_ X7 R_ 0 4
*1 00 p _ 50 V_ NPO _ 04
SM G ND H T-1 5 0N B-DT
SM GND SM GN D
C
SM G ND
C
SM G ND
6-52- 56001-023 6-52- 56001-028 6-52- 56000-020 6-52- 56001-022
SM GN D
SM GN D
6- 02-00248- LC2 6- 02-00268- LC1
SU1, SU2 3 1
FOR E5128Q
6- 53- 3150B-245 6- 53- 3050B-241 6- 53- 3050B-240
HOT KEY
6-53- 3150B-245 6-53- 3050B-241 6-53- 3050B-240
POWER BUTTON S M_ B T N#
5 6
1 3 5 6
PSW1~8
S W EB_ W W W #
1 3
SC 4
2 4 5
S AP_SW 1 T J G-5 3 3 -S-T/R
S W E B _E MA IL #
1 3
2 4
SC3
6
0 .1 u_ 1 6 V_Y 5 V_0 4 3 4
AP_KEY#
SR 3 * 10 0 K_ 1% _ 0 4
SM AIL _ SW 1 TJ G-5 3 3 -S-T /R 2 4
5
SR4 0 _ 04
0.1 u _ 16 V_ Y5 V_ 0 4
2
Sheet 34 of 35 Power Switch Board
6-53- 3150B-245 6-53- 3050B-241 6-53- 3050B-240
S_ VIN
WEB_EMAIL#
SW W W _SW 1 T J G-5 3 3-S-T /R 2 4
FO R E4120Q / E5120Q
6- 53-3150B-245 6- 53-3050B-241 6- 53-3050B-240
WEB_WWW#
SPW R _ SW 1 T J G-5 3 3-S-T /R 1 3
*BA V99 R ECT IF IER
22 0 _ 04
20mil
SAP_ O N
SD2 C
SR1
1 2 3 4 5 6 7 8
SM GN D
LID SWITCH IC S_ 3 .3 V
S_ 3 .3V
20mil
SAP_ O N
S_3 .3 V
POWER SWITCH LED
S A P _O N
SC5
6
SR 5 *4 7K_ 0 4
0.1 u _1 6 V_ Y5 V_ 04
1 2
S MGN D
SM GN D
S M GN D
SM G ND
SM G ND
S MG ND
S MG ND
SM GND
FOR E4120Q/ E5120Q
SM G ND
POWER BUTTON 1 3
SPW R _ SW 2 * TJ G- 53 3 -S-T /R
SM H1 2 4
SM_ BT N#
5 6
2 3 4 5
PSW1~8 3 4
SM GN D
SM H2 S MH5 H 7_ 0 D2 _ 3 H 7 _0 D 2_ 3
6- 53- 3150B-245 6- 53- 3050B-240 6- 53- 3050B-241
1
SMH3 9 8 7 6
2 3 4 5
M T H2 37 D 87 1 2
SM G ND SM GN D
1
SMH 4 9 8 7 6
2 3 4 5
MT H2 3 7D 87 SM GND
1
9 8 7 6
MT H2 3 7D 1 18 SM GND
SM GN D
SM GN D
FOR E5128Q
Power Switch Board B - 35
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
External ODD Board ODD BOARD FOR E5120Q
s m a r g a i D c i t a m e h c S . B
QJ_ODD2 S1 S2 S3 S4 S5 S6 S7
Sheet 35 of 35 External ODD Board
P1 P2 P3 P4 P5 P6
QJ_ODD1 S1 S2 S3 S4 S5 S6 S7
QJ_SATA_TXP1 QJ_SATA_TXN1 QJ_SATA_RXN1 QJ_SATA_RXP1
QGN D
Q GND
P1 P2 P3 P4 P5 P6
QJ_ODD_D ETECT# Q_5VS
Q_5VS QJ_SATA_ODD_ DA#
1-162-100562
242001-1 P IN
PIN GND1~2 =WG ND
QGN D
Q GND
GND1~3=QGND
6-21- 14010- 013 6-21- 14020- 013 6-21- 14030- 013
6-21- 13A00-0 13
Q_5VS
QC2
QC1
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
QGND
B - 36 External ODD Board
QH1 C237D91
QH4 C237D91
QGND
QGND
QH3 C67D67
QH2 C67D67
