Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG) PROCESSOR
2/7
( CLK,MISC,JTAG )
1.5 V
Processor Compensation Signals R 23 8
4 9 . 9 _ 1% _ 0 4
H_ CO MP 0
R 21 3
4 9 . 9 _ 1% _ 0 4
H_ CO MP 1
R 2 37
2 0 _ 1% _ 0 4
H_ CO MP 2
R 2 36
2 0 _ 1% _ 0 4
H_ CO MP 3
R 2 03 * 1 K_ 1% _ 0 4 R 20 6
DDR3 Compensation Signals SM _R CO MP_ 0
R 22 9
1 0 0 _ 1% _ 0 4
SM _R CO MP_ 1
R 23 0
2 4 . 9 _ 1% _ 0 4
SM _R CO MP_ 2
R 23 1
1 3 0 _ 1% _ 0 4
* 10 m il_ s h ort_ 0 4
BSS138( VGS 1.5V ) Q1 3 *R J U0 0 3N 0 3T 1 0 6 S D
SM_ DR AMR ST #
DD R3 _ DR AM RST #
1 0,1 1
R2 0 7 *1 0 0K _1 % G _ 04 DR AMR ST _C T RL 9 ,1 9
TRACE WIDTH 10MIL, LENGTH <500MILS
? ? IBEXCONTR OL
C3 1 1 *4 7 n _5 0 V_ 0 4 H_ C OM P3
A T2 3
H_ C OM P2
A T2 4
U 1 6B C OM P3
Processor Pullups 1 .1 VS_ VT T
H_ C OM P1
G1 6
H_ C OM P0
A T2 6
C OM P2 C OM P1 C OM P0
R 21 9
4 9 . 9 _ 1% _ 0 4
H_ CA TER R#
AH2 4
R 2 39
6 8 _ 04
H_ PR OC HO T# _ D
R 2 47
* 68 _ 0 4
H_ CP UR ST#
AK1 4
H_ C AT ERR #
A T1 5
19 ,2 8 H_ PEC I
R 24 8
3 6 H_ PRO CH OT #
* 10 m i _l s h ort_ 0 4 H_ PRO CH OT # _ D
I f PROCHOT# is not used, then it
AN2 6
SKT O CC #
C ATE RR #
PEC I
PR OC HO T#
must be terminated
witha 50-O pull -up resistor to VTT _ 1.1 rail.
AK1 5
1 9 H_ T HR MT R IP#
BC L K BCL K#
M I S C S
K C O T L H C
E R M A L
BCL K_ IT P BCL K_ IT P# PEG _C L K PEG _ CL K# DPL L _ REF _ SSC L K DP LL _ RE F _S SCL K #
3 C R S D I D M
SM_ D RAM RST # SM_ RC OM P[0 ] SM_ RC OM P[1 ] SM_ RC OM P[2 ] P M_ EXT_ T S# [0 ] P M_ EXT_ T S# [1 ]
A L1 5
1 6 H_ PM _ SYN C R 24 9
1 6,3 6 D ELA Y_ PW R GD
SY S_ AGEN T_ PW RO K AN1 4
* 0 _0 4
R 25 0
AP2 6
19 H _C PU PW RG D R 52
1 6 PM_ D RAM _ PW RG D
* 10 m il_ s ho rt_ 0 4
VD DPW R GO OD _ R
AK1 3
AM1 5
16 H _V TT PW R GD
Connect to the P rocessor (VTTPW RGO OD) VTT_1.1 VR pow er goodsi gnal to processor. Si gnal vol tage level is 1.1 V.
R 60
1 8 ,23 ,2 5 ,2 8 B UF _ PL T _R ST #
R ESET _O BS#
PM _S YN C
VC CPW R GO OD _ 1
* 10 m il_ s ho rt_ 0 4 AN2 7
1 . 5 K _ 1 % _ 04
Signal fromPCHt oPr ocessor Connect to PCH( PLT_RST#) (need s to be level translated f r o m3 . 3 V t o 1 . 1 V ) .
H_ PW RG D_ XDP
AM2 6
PL T _R ST # _R
A L1 4
R 61 7 5 0 _1 % _ 04
BCL K_ CP U_ P 1 9 BCL K_ CP U_ N 1 9
AR 30 AT 3 0 E1 6 D 16
CL K_ DP_P 15 C L K _ DP _ N 1 5
F6
S M_ DR AMR ST #
AL 1 AM 1 AN 1
S M_ RC OM P_ 0 S M_ RC OM P_ 1 S M_ RC OM P_ 2
R 23 3 R5 4
10 K _ 0 4 10 K _0 4
AN 15 AP1 5
P M_ EXTT S# [0 ] P M_ EXTT S# [1 ]
R5 3 R 23 2
*0 _0 4 * 0_0 4
R 23 4
* 1 2 . 4 K_ 1 % _ 0 4
VC CPW R GO OD _ 0
SM _D RA MPW R OK
VT T PW R GOO D T APPW R GO OD
P W R M A N A G E M E N T
M P B
XD P_ T MS XD P_ T DO _M XD P_ T DI_ R XD P_ PRE Q# XD P_ T DO _R
R 25 2 R 24 4 R 25 1 R 24 2 R 24 1
* 51_ 0 4 51 _ 0 4 * 51_ 0 4 * 51_ 0 4 * 51_ 0 4
& G A T J
XD P_ T CL K XD P_ T RST #
R 24 5 R 24 0
* 51_ 0 4 51 _ 0 4
XD P_ T DO _M
R 24 3
AT 2 8 AP2 7
AN 28 T C K AP 2 8 T M S AT 2 7 T RST # AT 2 9 TDI AR 27 T DO AR 29 T DI _M AP2 9 T DO _M AN 25 DB R# B PM# [0 ] B PM# [1 ] B PM# [2 ] B PM# [3 ] B PM# [4 ] B PM# [5 ] B PM# [6 ] B PM# [7 ]
AJ 2 2 AK2 2 AK2 4 AJ 2 4 AJ 2 5 AH 22 AK2 3 AH 23
Sheet 4 of 42 CPU 2/7 (CLK, MISC, JTAG)
CL K_ EXP_ P 1 5 CL K_ EXP_ N 1 5
A1 8 A1 7
1.1 VS_ VT T
T HER MT R IP# P RD Y# PRE Q#
H_ C PUR ST #
A1 6 B1 6
PM _EXT T S# _E C 3 T S# _D IMM 0 _1 1 0 ,1 1
XD P_ PREQ # XD P_ TC L K XD P_ TM S XD P_ TR ST # XD P_ TD I_ R XD P_ TD O_ R XD P_ TD I_ M XD P_ TD O_ M
1.1 VS_ VT T
R STI N#
PZ 98 9 2 7-3 6 4 1 -01 F
1 .5 VS_ CPU
* 10 m il_ s h ort_ 0 4XDP_ T DI_ M
3.3 V R5 0 1 .1 K_1 % _ 0 4
R 2 35 VD DPW R GO OD _ R U17
R6 2
R 24 6
* 1 . 5 K _ 1 % _ 04
DRA MPW R GD _ CPU
* 8. 2 K _ 04 3 .3V 3 ,1 2,1 4 ,1 5 ,16 ,1 8 ,1 9,2 0 ,2 1 ,23 ,2 4 ,2 5,2 9 ,3 0 ,31 ,3 3 ,3 4,3 5 1 .5V 9 ,1 0,11 ,2 1 ,23 ,2 7 ,2 9,3 1 ,3 3 ,36 1 .5V S_C PU 7,3 1 1 .1V S_V TT 2 ,6 ,7 ,1 4,1 5 ,1 6, 19 ,2 0 ,2 1,3 4 ,3 5, 36
5
1
4
IN 3 .3V
2
3 K_ 1% _ 0 4 3
1 .1 VS_ VT T _P W RG D 1 6 ,3 3 ,34
* MC 7 4VH C1 G 08 D F T 1G
Intel change 4.75K -->1.1K 12K -->3K
CPU 2/7 (CLK, MISC, JTA G) B - 5
B . S c h e m a t i c D i a g r a m s
