clevo+6-71-w24h0-d02a.unlocked.pdf

E5120Q/E5120Q-C, E5120Q/E5120Q-C, E5125/E5125-C, E5125/E5125-C, E5128Q, E5128Q-C

Preface

Notebook Computer E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C Service Manual P r e f a c e

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Preface

Notice The company reserves the right to revise this publication or to change its contents without notice. Information contained herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this pub lication nor are they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication. This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publication, except for copies kept by the user for backup purposes. Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement of that product or its manufacturer.

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Version 1.0 November 2010

Trademarks Intel, Intel Core, Intel Pentium and Intel Celeron are trademarks of Intel Corporation. Windows® is a registered trademark of Microsoft Corporation. Other brand and product names are trademarks and /or registered trademarks of their respective companies.

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Preface

Ab out t hi s Manual This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and inspection of personal computers. It is organized to allow you to look up basic information for servicing and/or upgrading components of the E5120Q/ E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook PC. The following information is included: Chapter 1, Introduction, provides general information about the location of system elements and their specifications. Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to u pgrade elements of the system. P r e f a c e

Appendix A, Part Lists Appendix B, Schematic Diagrams Appendix C, Updating the FLASH ROM BIOS

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Preface

IMPORTANT SAFETY INSTRUCTIONS Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to persons when using any electrical equipment: 1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet basement or near a swimming pool. 2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of electrical shock from lightning. 3. Do not use the telephone to report a gas leak in the vicinity of the leak. 4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may explode. Check with local codes for possible special disposal instructions. 5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output of 19V, 3.42A or 18.5V, 3.5A ( 65W) minimum AC/DC Adapter.

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CAUTION

This Comput er’s Optic al Device is a Laser Class 1 Produ ct

FCC Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: This device may not cause harmful interference. This device must accept any interference received, including interference that may cause undesired operation.

IV

Preface

Instructions for Care and Operation The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions: 1.

Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged. Do not expose the computer to any shock or vibration.

2.

Do not place anything heavy on the computer.

Keep it dry, and don ’t overheat it. Keep the computer and power supply away from any kind of heating element. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged. Do not expose it to excessive heat or direct sunlight.

3.

Do not place it on an unstable surface.

Do not leave it in a place where foreign matter or moisture may affect the system.

Don’t use or store the com puter in a humid environment.

P r e f a c e

Do not place the computer on any surface which will block the vents.

Follow the proper working procedures for the comp uter . Shut the computer down properly and don’t forget to save your work. Remember to periodically save your data as data may be lost if the battery is depleted. Do not turn off the power until you properly shut down all programs.

Do not turn off any peripheral devices when the computer is on.

Do not disassemble the com puter by yourself.

Perform routine maintenance on your computer.

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Preface 4. Avo id i nt erf eren ce. Keep the computer away from high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage your data. 5.

Take care when using peripheral devices. Use only approved brands of peripherals.

Unplug the power cord before attaching peripheral devices.

Power Safety

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The computer has specific power requirements: • •

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Power Safety Warning

•

Before you undertake any upgrade procedures, make sure that you have turned off the power, and disconnected all peripherals and cables (including telephone lines). It is advisable to also remove your battery in order to prevent accidentally turning the machine on.

• • •

Only use a power adapter approved for use with this computer. Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are unsure of your local power specifications, consult your service representative or local power company. The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one. When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire. Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices. Before cleaning the computer, make sure it is disconnected from any external power supplies. Do not plug in the power cord if you are wet.

Do not use the power cord if it is broken.

Do not place heavy objects on the power cord.

Preface

Battery Precaution s • • • • • • • •

Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer. Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire. Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode. Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service personnel. Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode or leak if exposed to fire, or improperly handled or discarded. Keep the battery away from metal appliances. Affix tape to the battery contacts before disposing of the battery. Do not touch the battery contacts with your hands or metal objects.

Battery Guidelines

P r e f a c e

The following can also apply to any backup batteries you may have. • • •

If you do not use the battery for an extended period, then remove the battery from the computer for storage. Before removing the battery for storage charge it to 60% - 70%. Check stored batteries at least every 3 months and charge them to 60% - 70%.

Battery Disposal The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste officials for details in your area for recycling options or proper disposal. Caution Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer. Discard used battery according to the manufacturer’s instructions.

Battery Level Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10% will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.

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Preface

Related Document s You may also need to consult the following manual for additional information: User’s Manual on CD/DVD This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup program. It also describes the installation and operation of the utility programs provided with the notebook PC.

System Startup 1. 2. 3. 4.

Remove all packing materials. Place the computer on a stable surface. Insert the battery and make sure it is locked in position. Securely attach any peripherals you want to use with the computer (e.g. keyboard and mouse) to their ports. 5. Attach the AC/DC adapter to the DC-In jack on the left of the computer, then plug the AC power cord into an outlet, and connect the AC power cord to the AC/DC adapter. 6. Use one hand to raise the lid/LCD to a comfortable viewing angle (do not exceed 135 degrees); use the other hand (as illustrated in Figure 1) to support the base of the computer (Note: Never lift the computer by the lid/LCD). 7. Press the power button to turn the computer “on”.

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Shut Down

135

Figure 1 Opening the Li d/LCD/Computer with AC/DC Adapter Plugged-In

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Note that you should always shut your computer down by choosing Shut Down from the Start Menu. This will help prevent hard disk or system problems.

Preface

Contents Introduction ..............................................1-1 Overview .........................................................................................1-1 Specifications ..................................................................................1-2 External Locator - Top View with LCD Panel Open ...................... 1-4 External Locator - Front & Right Side Views ................................. 1-5 External Locator - Left Side & Rear View ..................................... 1-6 External Locator - Bottom View .....................................................1-7 Mainboard Overview - Top (Key Parts) ......................................... 1-8 Mainboard Overview - Bottom (Key Parts) ................................. ...1-9 Mainboard Overview - Top (Connectors) .....................................1-10 Mainboard Overview - Bottom (Connectors) ............................... 1-11

Disassembly ...............................................2-1 Overview .........................................................................................2-1 Maintenance Tools ..........................................................................2-2 Connections .....................................................................................2-2 Maintenance Precautions .................................................................2-3 Disassembly Steps ...........................................................................2-4 Removing the Battery ......................................................................2-5 Removing the Hard Disk Drive .......................................................2-6 Removing the Optical (CD/DVD) Device ....... ............................... 2-8 Removing the System Memory (RAM) ..........................................2-9 Removing and Installing a Processor ............................................2-11 Removing the 3G Module .............................................................2-14 Removing the Wireless LAN Module ...........................................2-15 Removing the Bluetooth Module ..................................................2-16 Removing the Keyboard ................................................................2-17

Part Lists ..................................................A-1 Part List Illustration Location ........................................................ A-2 Top (E5120Q) ...................................................................... .......... A-3

Top (E5125) ................................................................................... A-4 Top (E5128Q) ................................................................................ A-5 Bottom ........................................................................................... A-6 DVD Dual Drive ............................................................................ A-7 LCD ............................................................................................ ... A-8

Schematic Diagrams.................................B-1 System Block Diagram ...................................................................B-2 Clock Generator ..............................................................................B-3 CPU 1/7 (DMI, PEG, FDI) ............................................ .................B-4 CPU 2/7 (CLK, MISC, JTAG) ....................................................... B-5 CPU 3/7 (DDR3) ............................................................................ B-6 CPU 4/7 (Power) .............................................................................B-7 CPU 5/7 (Graphics Power) ............................................. ................B-8 CPU 6/7 (GND) ..............................................................................B-9 CPU 7/7 (RESERVED) ................................................................B-10 DDR3 SO-DIMM_0 .....................................................................B-11 DDR3 SO-DIMM_1 .....................................................................B-12 LVDS, Inverter .............................................................................B-13 HDMI, CRT ..................................................................................B-14 IBEXPEAK- M 1/9 .......................................................................B-15 IBEXPEAK - M 2/9 ......................................................................B-16 IBEXPEAK - M 3/9 ......................................................................B-17 IBEXPEAK - M 4/9 ......................................................................B-18 IBEXPEAK - M 5/9 ......................................................................B-19 IBEXPEAK - M 6/9 ......................................................................B-20 IBEXPEAK - M 7/9 ......................................................................B-21 IBEXPEAK - M 8/9 ......................................................................B-22 IBEXPEAK - M 9/9 ......................................................................B-23 New Card, Mini PCIE ...................................................................B-24 3G, CCD, TPM .............................................................................B-25

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Preface

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Card Reader/LAN JMB251C ....................................................... B-26 LAN (JMC251C), SATA HDD, ODD ......................................... B-27 Audio Codec VIA1812 ................................................................. B-28 KBC-ITE IT8502E ....................................................................... B-29 LED, MDC, BT ............................................................................ B-30 USB, Fan, TP, Multi-Conn ........................................................... B-31 5VS, 3VS, 1.5VS .......................................................................... B-32 Power 3.3V/5V ............................................................................. B-33 Power 1.5V/0.75V, 1.8VS ............................................................ B-34 Power 1.1VS_VTT ....................................................................... B-35 Power VGFX_Core ...................................................................... B-36 V-Core .......................................................................................... B-37 AC_IN, Charger ........................................................................... B-38 Click Board .................................................................................. B-39 Audio Board/USB ........................................................................ B-40 Power Switch & LED Board ............................................ ............ B-41 External ODD Board .................................................................... B-42 Sequence ....................................................................................... B-43

Updating the FLASH ROM BIOS......... C-1 To update the FLASH ROM BIOS you must: C-1 Download the BIOS ................................... .................................... C-1 Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive .................................................................................... ............ C-1 Set the computer to boot from the external drive ........................... C-1 Use the flash tools to update the BIOS .......................................... C-2 Restart the computer (booting from the HDD) .............................. C-2

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Introduction

Chapter 1: Intro duct ion Overview This manual covers the information you need to service or upgrade the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/ E5128Q-C series notebook computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information about dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The manual is shipped with the computer. Operating systems (e.g. Windows Vista/ Window 7, etc.) have their own manuals as do application softwares (e.g. word processing and database programs). If you have questions about those programs, you should consult those manuals.

1 .I n t r o d u c t i o n

The E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook is designed to be upgradeable. See Dis assembly on page 2 - 1 for a detailed description of the upgrade procedures for each specific component. Please take note of the warning and safety information indicated by the “ ” symbol. The balance of this chapter reviews the computer’s technical specifications and features.

Overview 1 - 1

Introduction

Specifications

Processor Options

BIOS

Intel® Core™ i7 Processor

One 32Mb SPI Flash ROM

i7-640M (2.80GHz), i7-620M (2.66GHz)

Phoenix™ BIOS

4MB L3 Cache & 1066MHz FSB

Latest Specification Information The specifications listed here are correct at the time of sending them to the press. Certain items (particularly processor types/speeds) may be changed, delayed or updated due to the manufacturer's release schedule. Check with your service center for more details.

Intel® Core™ i5 Processor i5-540M (2.53GHz), i5-520M (2.4GHz), i5-450M (2.4GHz), i5-430M (2.26GHz)

(Factory Option) One Changeable 12.7mm(h) Super Multi Optical Device Drive


One Changeable 2.5" 9.5 mm (h) SATA HDD

Intel® Core™ i3 Processor i3-370M (2.4GHz), i3-350M (2.26GHz), i3-330M (2.13GHz) 3MB L3 Cache & 1066MHz FSB Intel® Pentium® Processor

n o i t c u d o r t n I . 1

Storage

P6000 (1.86GHz) 3MB L3 Cache & 1066MHz FSB Intel® Celeron® Processor

Audi o High Definition Audio Compliant Interface 2 * Built-In Speakers Built-In Microphone

Keyboard Full-size “WinKey” keyboard (with numeric keypad)

P4500 (1.86GHz)

CPU The CPU is not a user serviceable part. Accessing the CPU in any way may violate your warranty.


Pointing Device

LCD

Built-in Touchpad

15.6" (39.62) HD TFT LCD

Security

Memory

Security (Kensington® Type) Lock Slot BIOS Password

Two 204 Pin SO-DIMM Sockets Supporting DDR3 1066/ 1333 MHz Memory Memory Expandable up to 8GB

Core Logic Intel ® HM55 Chipset

Video Adapter Intel ® HM55 Integrated Video Shared Memory Architecture of up to 1748MB MS DirectX® 10 compatible

1 - 2 Specifications

Interface Three USB 2.0 Ports One HDMI-Out Port One Headphone-Out Jack One Microphone-In Jack One RJ-45 LAN Jack One DC-in Jack One External Monitor Port

Introduction Card Reader

Environmental Spec

Embedded Multi-In-1 Card Reader

Temperature

MMC (MultiMedia Card) / RS MMC

Operating: 5°C - 35°C

SD (Secure Digital) / Mini SD / SDHC/ SDXC Compatible

Non-Operating: -20°C - 60°C

MS (Memory Stick) / MS Pro / MS Duo

Operating: 20% - 80%

Relative Humidity

Communication

Non-Operating: 10% - 90%

Built-In Gigabit Ethernet LAN

Dimensions & Weight

(Factory Option) 300K/ 1.3M Pixel USB PC Camera Module

374mm (w) * 250mm (d) * 14.3 - 34.1mm (h)

(Factory Option) Bluetooth 2.1 + EDR Module

2.3 kg (with 48.84WH Battery and ODD)

(Factory Option) 3.75G/HSPA Half Mini-Card Module


(Factory Option) Combo WLAN (802.11b/g/n) and Bluetooth 3.0 Module (Factory Option) Intel® WiFi Link 1000 (802.11b/g/n) Wireless LAN Half Mini-Card Module (Factory Option) Third-Party 802.11b/g/n Wireless LAN Half Mini-Card Module

Power 6 Cell Smart Lithium-Ion Battery Pack, 48.84WH (Factory Option) 6 Cell Smart Lithium-Ion Battery Pack, 62.16WH (Factory Option) 4 Cell Smart Lithium-Ion Battery Pack, 32.56WH Full Range AC/DC Adapter AC Input: 100 - 240V, 50 - 60Hz DC Output: 19V, 3.42A or 18.5V, 3.5A (65W) Energy Star 5.0 Compliant

Specifications 1 - 3

Introduction Figure 1 Top View


External Loc ator - Top View wit h LCD Panel Open 1

1. PC Camera (Optional) 2. LCD 3. Power Button 4. LED Status Indicators 5. Keyboard 6. Built-In Microphone 7. Touchpad & Buttons

2

4

3

5

6 7

1 - 4 External Locator - Top View with LCD Panel Open

Introduction

External Locato r - Fron t & Right Side Views

Figure 2 Front View 1. LED Indicators

FRONT VIEW

1

Figure 3 Right Side View RIGHT SIDE VIEW

1

2

3

4

5

1. Microphone-In Jack 2. Headphone-Out Jack 3. USB 2.0 Port 4. Optical Device Drive Bay 5. Emergency Eject Hole

External Locator - Front & Right Side Views 1 - 5


Introduction

External Loc ator - Left Side & Rear View Figure 4 Left Side View 1. DC-In Jack 2. External Monitor Port 3. RJ-45 LAN Jack 4. HDMI-Out Port 5. 2 * USB 2.0 Ports 6. Vent 7. Multi-in-1 Card Reader

/

LEFT SIDE VIEW

1

2

3

4

5

6


Figure 5 Rear View

REAR VIEW

1. Security Lock Slot 2. Battery 1

1 - 6 External Locator - Left Side & Rear View

2

5

7

Introduction

External Locator - Bottom View Figure 6 Bottom View 1. Battery 2. Component Bay Cover 3. Vent 4. Hard Disk Bay Cover 5. Speakers 6. USIM Card Cover

1

3

3

2 6

3

3

3

4 Overheating

5

5

To prevent your computer from overheating, make sure nothing blocks any vent while the computer is in use.

External Locator - Bottom View 1 - 7


Introduction Figure 7 Mainboard Top Key Parts

Mainboard Overvi ew - Top (Key Parts)

1. JMC251C 2. Clock Generator 3. KBC-ITE IT8502E


2 3

1

1 - 8 Mainboard Overview - Top (Key Parts)

Introduction

Mainbo ard Overview - Bottom (Key Parts)

1

Figure 8 Mainboard Bottom Key Parts 1. Memory Slots DDR3 SO-DIMM 2. Mini-Card Connector (3.5G Module) 3. Audio Codec 4. USIM Card 5. Mini-Card Connector (WLAN Module) 6. Multi-in-1 Card Reader 7. Platform Controller Hub 8. CPU Socket (CPU installed)

8

7

6

4

2

5 3

Mainboard Overview - Bott om (Key Parts) 1 - 9


Introduction Figure 9 Mainboard Top Connectors


1. HDMI-Out Port 2. USB Ports 3. Speaker Cable Connector 4. Microphone Cable Connector 5. TouchPad Cable Connector 6. Click Board Connector 7. Audio Board Connector 8. Keyboard Cable Connector 9. Switch Board Cable Connector

Mainboard Overview - Top (Connector s)

9

1

8 2

4

5

6

2

7 3

1 - 10 Mainboard Overview - Top (Connectors)

Introduction

Mainboard Overview - Bottom (Connectors) 8

10

9

7

1 6

11 2

Figure 10 Mainboard Bottom Connectors 1. Battery Connector 2. ODD Connector 3. HDD Connector 4. Bluetooth Cable Connector 5. CPU Fan Cable Connector 6. RJ-45 LAN Jack 7. External Monitor Port 8. DC-In Jack 9. CCD Cable Connector 10.LCD Cable Connector 11. CMOS Battery Connector

5 4

3

Mainboard Overview - Bottom (Connectors) 1 - 11


Introduction


1 - 12

Disassembly

Chapter 2: Disassembl y Overview This chapter provides step-by-step instructions for disassembling the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/ E5128Q-C series notebook’s parts and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated). We suggest you completely review any procedure before you take the computer apart. Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are repeated here for your convenience. To make the disassembly process easier each section may have a box in the page margin. Information contained under the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the disassembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previous disassembly procedure. The amount of screws you should be left with will be listed here also. A box with a

will also provide any possible helpful information. A box with a

Information

contains warnings.

An example of these types of boxes are shown in the sidebar.

Warning

Overview 2 - 1

2 .D i s a s s e m b l y

Disassembly NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the battery is removed too).

Maintenance Tools The following tools are recommended when working on the notebook PC: • • • • • •

y l b m e s s a s i D . 2

M3 Philips-head screwdriver M2.5 Philips-head screwdriver (magnetized) M2 Philips-head screwdriver Small flat-head screwdriver Pair of needle-nose pliers Anti-static wrist-strap

Connections Connections within the computer are one of four types:

2 - 2 Overview

Locking collar sockets for ribbon connectors

To release these connectors, use a small flat-head screwdriver to gently pry the locking collar away from its base. When replacing the connection, make sure the connector is oriented in the same way. The pin1 side is usually not indicated.

Pressure sockets for multi-wire connectors

To release this connector type, grasp it at its head and gently rock it from side to side as you pull it out. Do not pull on the wires themselves. When replacing the connection, do not try to force it. The socket only fits one way.

Pressure sockets for ribbon connectors

To release these connectors, use a small pair of needle-nose pliers to gently lift the connector away from its socket. When re placing the c onnection, make sure the connector is oriented in the same way. The pin1 side is usually not indicated.

Board-to-board or multi-pin sockets

To separate the boards, gently rock them from side to side as you pull them apart. If the connection is very tight, use a small flat-head screwdriver - use just enough force to sta rt.

Disassembly

Maintenance Precautions The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or replacement job, take the following precautions: 1. 2. 3.

4. 5.

Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other components could be damaged. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. Avo id in terf erenc e. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage components and/or data. You should also monitor the position of magnetized tools (i.e. screwdrivers). Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged. Be careful with power . Avoid accidental shocks, discharges or explosions. •Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. •When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire.

Peripherals – Turn off and detach any peripherals. Beware of static disc harge. ICs, such as the CPU and main support chips, are vulnerable to static electricity. Before handling any part in the computer, discharge any static electricity inside the computer. When handling a printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that you use an anti-static wrist strap instead. 8. Beware of corrosi on. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils which can attract corrosive elements. 9. Keep your work environ ment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted to charged surfaces, reducing performance. 10. Keep track of the components . When removing or replacing any part, be careful not to leave small parts, such as screws, loose inside the computer. 6. 7.

Power Safety Warning Before you undertake any upgrade procedures, make sure that you have turned off the power, and disconnected all peripherals and cables (including telephone lines). It is advisable to also remove your battery in order to prevent accidentally turning the machine on.

Cleaning Do not apply cleaner directly to the computer, use a soft clean cloth. Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.

Overview 2 - 3


Disassembly

Disassembly Steps The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM THE DISASSEMBLY STEPS IN THE ORDER INDICATED.

To remove the Battery: 1. Remove the battery

To remove the Bluetooth Module: page 2 - 5

1. Remove the battery 2. Remove the Bluetooth Module

page 2 - 5 page 2 - 6

To remove the Keyboard:

To remove t he HDD: 1. Remove the battery 2. Remove the HDD y l b m e s s a s i D . 2

To remove the Optic al Device: 1. Remove the battery 2. Remove the Optical device

page 2 - 5 page 2 - 8

To remove the System Memory: 1. Remove the battery 2. Remove the system memory

page 2 - 5 page 2 - 9

To remove and install a Processor: 1. Remove the battery 2. Remove the processor 3. Install the processor

page 2 - 5 page 2 - 11 page 2 - 13

To remove th e 3G Modul e: 1. Remove the battery 2. Remove the 3G module

page 2 - 5 page 2 - 14

To remove the Wireless LAN Module: 1. Remove the battery 2. Remove the WLAN module

2 - 4 Disassembly Steps

page 2 - 5 page 2 - 15

1. Remove the battery 2. Remove the keyboard

page 2 - 5 page 2 - 16

page 2 - 5 page 2 - 17

Disassembly

Removing the Battery

Figure 1 Battery Removal

Turn the computer of f , and turn it over. Slide the latch 1 in the direction of the arrow ( Figure 1a). Slide the latch 2 in the direction of the arrow, and hold it in place ( Figure 1a). Slide the battery 63 in the direction of the arrow 4 ( Figure 1b ).

1. 2. 3. 4.

a. Slide latch at point 1 towards the unlock symbol and hold it in place. b. Slide the battery in the direction of the arrow.

b.

a. 2

1

3


4

3. Battery

Removing the Battery 2 - 5

Disassembly

Removing the Hard Disk Drive Figure 2 HDD Assembly Removal a. Locate the HDD bay cover and remove the screws.


The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm (h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in Chapter 4 of the User’s Manual ) when setting up a new hard disk.

Hard Disk Upgrade Process 1. Turn of f the computer, and remove the battery ( page 2 - 5). 2. Locate the hard disk bay cover and remove screws 1 & 2 ( Figure 2a).

a. HDD System Warning New HDD’s are blank. Before you begin make sure: You have backed up any data you want to keep from your old HDD.

1

2

You have all the CD-ROMs and FDDs required to install your operating system and programs. If you have access to the internet, download the latest application and hardware driver updates for the operating system you plan to install. Copy these to a removable medium.

• 2 Screws

2 - 6 Removing the Hard Disk Drive

Disassembly 3. 4. 5. 6. 7.

Remove the hard disk bay cover 63 (Figure 3b ). Grip the tab and slide the hard disk in the direction of arrow 4 ( Figure 3c ). Lift the hard disk 5 out of the bay 6 ( Figure 3d ). Remove the screw 7 - 10 and the mylar cover 11 from the hard disk 12 ( Figure 3e). Reverse the process to install a new hard disk (do not forget to replace all the screws and covers). b.

d.

6

5

Figure 3 HDD Assembly Removal (cont’d.) b. Remove the HDD bay cover. c. Grip the tab and slide the HDD in the direction of the arrow. d. Lift the HDD assembly out of the bay. e. Remove the screws and mylar cover.

e.

3

e.

c.

7 8 10

11 9

4

3. HDD Bay Cover 11. Adhesive Cover 12.HDD

• 4 Screws

12

Removing the Hard Disk Drive 2 - 7


Disassembly Figure 4 Optical Device Removal a. Remove the screw at point 1 . b. Use a screwdriver to carefully push out the optical device at point 2 .

Removing the Optical (CD/DVD) Device Turn of f the computer, remove the battery ( page 2 - 5) and hard disk (page 2 - 6). Remove the screw at point 1 (Figure 4a). Use a screwdriver to carefully push out the optical device 3 at point 2 ( Figure 4b ). Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The screw holes should line up). 5. Restart the computer to allow it to automatically detect the new device. 1. 2. 3. 4.

a.


b.

3

1

2

3. Optical Device

•

1 Screw

2 - 8 Removing the Optical (CD/DVD) Device

2

Disassembly

Removing the System Memory (RAM) The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting DDRIII (DDR3) Up to 1066/1333 MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules sup ported are 1024MB and 2048MB DDRIII Modules. The total memory size is automatically detected by the POST routine once you turn on your computer.

Memory Upgrade Process 1. 2. 3. 4.

Turn of f the computer, turn it over and remove the battery ( page 2 - 5). Remove screws 1 - 4 from the component bay cover ( Figure 5a). The RAM modules will be visible at point 5 on the mainboard (Figure 5b). Gently pull the two release latches ( 6 & 7 ) on the sides of the memory socket in the direction indicated by the arrows (Figure 5c). The RAM module 8 will pop-up (Figure 5d ), and you can then remove it .

a.

1

a. Remove the screws from the component bay cover. b. The RAM modules will be visible at point 5 on the mainboard. c. Pull the release latches. d. Remove the module.

d.

c.

2

Contact Warning

6 3 8

4 7

b.

Figure 5 RAM Module Removal

Be careful not to touch the metal pins on the module’s connecting edge. Even the cleanest hands have oils which can attract particles, and degrade the module’s performance.

5 8. RAM Module

• 4 Screws

Removing the System Memory (RAM) 2 - 9


Disassembly 5. Pull the latches to release the second module if necessary. 6. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot. 7. The module will only fit one way as defined by its pin alignment. Make sure the module is seated as far into the slot as it will go. DO NOT FORCE IT; it should fit without much pressure. 8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module. 9. Replace the component bay cover and the screws (see page 2 - 8). 10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.


2 - 10 Removing the System Memory (RAM)

Disassembly

Removing and Installing a Processor

Figure 6 Processor Removal

Processor Removal Procedure 1. Turn of f the computer, turn it over, and remove the battery ( page 2 - 5) and the component bay cover ( page 2 - 8). 2. Locate the heat sink. 3. Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label Figure 6b). 4. Carefully lift up the heat sink 4 ( Figure 6c) off the computer. a.

a. Locate the heat sink. b. Remove the screws from the CPU heatsink. c. Remove the CPU heat sink.

c.


4 A

b. 3 1

2

4. Heat Sink

•

3 Screws

Removing and Installing a Processor 2 - 11

Disassembly

Figure 7 Processor Removal (cont’d) d. Turn the release latch to unlock the CPU. e. Lift the CPU out of the socket.

5. 6. 7. 8.

Turn the release latch 5 towards the unlock symbol to release the CPU ( Figure 7d). Carefully (it may be hot) lift the CPU 6 up and out of the socket ( Figure 7e). Reverse the process to install a new CPU. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!). d.

5

5


Unlock

Lock

e.

Caution

6

6. CPU

2 - 12 Removing and Installing a Processor

The heat sink, and CPU area in general, contains parts which are subject to high temperatures. Allow the area time to cool before removing these parts.

Disassembly

Processor Installation Procedure 1. Insert the CPU (Figure 8a), pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!), and turn the release latch B towards the lock symbol ( Figure 8b). 2. Remove the sticker C (Figure 8c) from the heat sink. 3. Insert the heat sink D as indicated in Figure 8d. 4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 8d). 5. Replace the component bay cover (don’t forget to replace the fan cable) and tighten the screws ( page 2 - 9).

Figure 8 Processor Installation

A

a.

c.

a. Insert the CPU. b. Turn the release latch towards the lock symbol. c. Remove the sticker from the heat sink and insert the heat sink. d. Tighten the screws.

A


C

d.

b. B

D

3 1

2

Note: Tighten the screws in the order as indicated on the label.

A. CPU D. Heat Sink

•

3 Screws

Removing and Installing a Processor 2 - 13

Disassembly

Figure 9 3G Module Removal a. Locate the 3G module. b. Disconnect the cable and remove the screw. c. Remove the 3G module.

Remov ing the 3G Module 1. 2. 3. 4.

Turn of f the computer, turn it over, and remove the battery ( page 2 - 5) and the component bay cover ( page 2 - 9). The 3G module will be visible at point 1 on the mainboard (Figure 9a). Carefully disconnect the cable 2 , and then remove the screw 3 (Figure 9b). The 3G module 4 (Figure 9c) will pop-up, and you can remove it from the computer ( Figure 9d). a.


d.

c.

Note: Make sure you reconnect the antenna cable to socket ( Figure 9b). 4

1

no 3g b. 4

2 4. 3G Module

•

1 Screw

3

2 - 14 Removing the 3G Module

Disassembly

Removing the Wireless LAN Module 1. 2. 3. 4.

Turn of f the computer, turn it over, and remove the battery ( page 2 - 5) and the component bay cover ( page 2 - 9). The Wireless LAN module will be visible at point 1 on the mainboard (Figure 10a). Carefully disconnect the cables 2 & 3 , and then remove the screw 4 (Figure 10b). The Wireless LAN module 5 (Figure 10c) will pop-up, and you can remove it from the computer ( Figure 10d). c.

a.

Figure 10 Wireless LAN Module Removal a. Locate the WLAN. b. Disconnect the cables and remove the screw. c. The WLAN module will pop up. d. Remove the Wireless LAN module.

Note: Make sure you reconnect the antenna cable to the “1 + 2” socket ( Figure 10b).

5

1

b.

d. 4 3

5 5.Wireless LAN Module

2

•

1 Screw

Removing the Wireless LAN Module 2 - 15


Disassembly

Figure 11 Bluetooth Module Removal


a. Locate the Bluetooth module. b. Remove the screw and turn the module over. c. Disconnect the cable and the connector from the Bluetooth module. d. Lift the Bluetooth module out.

Removing the Bluetooth Module Turn of f the computer, turn it over, and remove the battery ( page 2 - 5) and the component bay cover ( page 2 - 8). The Bluetooth module will be visible at point 1 on the mainboard (Figur e 11a). Remove screw 2 (Figu re 11b) and turn the module over ( Figur e 11c). Carefully disconnect the cable 3 and separate the connector 4 ( Figur e 11c) from the Bluetooth Module. Lift the Bluetooth Module 5 (Figu re 11d) up and off the computer.

1. 2. 3. 4. 5.

a.

c.

d. 3

4

1

b.

5

5. Bluetooth Module

2 •

1 Screw

2 - 16 Removing the Bluetooth Module

Disassembly

Removing the Keyboard 1. Turn of f the computer, and remove the battery ( page 2 - 5). 2. Remove screws 1 - 2 from the bottom of the computer. Press at point 3 to unsnap the LED cover module (you may need to use a small screwdriver to do this Figure 12a). 3. Turn the computer over, unsnap up the LED cover module 4 from point 5 on the left of the computer, towards the right (Figure 12b). 4. Remove screws 6 - 10 from the keyboard ( Figure 12c). 5. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable 11. Disconnect the keyboard ribbon cable 11 from the locking collar socket 12 (Figure 12d) 6. Carefully lift up the keyboard 13 (Figure 12e) off the computer. a. d. 11 12

3

1

Figure 12 Keyboard Removal a. Remove screws from the bottom of the computer. b. Turn the computer over, unsnap up the LED cover module from point 5 towards the right . c. Remove screws from the keyboard. d. Carefully lift the keyboard up and disconnect the keyboard ribbon cable from the locking collar socket. e. Remove the keyboard.

2

b. 5

Re-Inserting the Keyboard

4 e.

When re-inserting the keyboard firstly align the four keyboard tabs at the bottom (Figure 12c) at the bottom of the keyboard with the slots in the case.

c. 6

7

8

9

10

13 4. LED Cover Module 13. Keyboard

•

7 Screws

Keyboard Tabs

Removing the Keyboard 2 - 17


Disassembly


2 - 18

Ap A p p end en d i x A : Part Par t L i s t s This appendix breaks down the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook’s construction into a series of illustrations. The component part numbers are indicated in the tables opposite the drawings. Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure to cross-check any relevant documentation. Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the total number of duplicated parts used. A .P a r t L i s t s

Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the time of publication. Over the product life, some parts may b e improved or re-configured, resulting in new part numbers.

A - 1

Part Part Lis t Illustration Location The following table indicates where to find the appropriate part list illustration. Table A - 1 Part List Illustration Location

s t s i L t r a P . A

A - 2

Part

E5120Q/E5120Q-C/E5125/ E5125-C/E5128Q/E5128Q-C

Top (E5120Q)

page A - 3

Top (E5125)

page A - 4

Top (E5128Q)

page A - 5

Bottom

page A - 6

DVD Dual Drive

page A - 7

LCD

page A - 8

Top (E5120Q)

Figure A - 1 Top (E5120Q)

非耐落

灰色

Top (E5120Q) A - 3

A .P a r t L i s t s

Top (E5125)


Figure A - 2 Top (E5125)

非耐落

灰色

A - 4 Top (E5125)

Top (E5128Q)

Figure 3 Top (E5128Q) 非耐落非耐落

非耐落

非耐落

非耐落

灰色

灰色

非耐落

灰色

Top (E5128Q) A - 5


Bottom


Figure A - 4 Bottom

A - 6 Bott om

DVD Dual Driv e

Figure A - 5 DVD Dual Drive

非耐落志精

DVD Dual Drive A - 7


LCD


Figure A - 6 LCD 頭厚非耐落頭厚非耐落

A - 8 LCD

Schematic Diagrams

Appendix B: Schematic Diagrams This appendix has circuit diagrams of the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C notebook’s PCB’s. The following table indicates where to find the appropriate schematic diagram.

Diagram - Page

Diagram - Page

Diagram - Page

System Block Diagram - Page B - 2

IBEXPEAK - M 2/9 - Page B - 16

LED, MDC, BT - Page B - 30

Clock Generator - Page B - 3


USB, Fan, TP, Multi-Conn - Page B - 31

CPU 1/7 (DMI, PEG, FDI) - Page B - 4


5VS, 3VS, 1.5VS - Page B - 32

CPU 2/7 (CLK, MISC, JTAG) - Page B - 5


Power 3.3V/5V - Page B - 33

CPU 3/7 (DDR3) - Page B - 6


Power 1.5V/0.75V, 1.8VS - Page B - 34

CPU 4/7 (Power) - Page B - 7


Power 1.1VS_VTT - Page B - 35

CPU 5/7 (Graphics Power) - Page B - 8


Power VGFX_Core - Page B - 36

CPU 6/7 (GND) - Page B - 9


V-Core - Page B - 37

CPU 7/7 (RESERVED) - Page B - 10

New Card, Mini PCIE - Page B - 24

AC_IN, Charger - Page B - 38

DDR3 SO-DIMM_0 - Page B - 11

3G, CCD, TPM - Page B - 25

DDR3 SO-DIMM_1 - Page B - 12

Card Reader/LAN JMB251C - Page B - 26

Audio Board/USB - Page B - 40

LVDS, Inverter - Page B - 13

LAN (JMC251C), SATA HDD, ODD - Page B - 27

Power Switch & LED Board - Page B - 41

HDMI, CRT - Page B - 14

Audio Codec VIA1812 - Page B - 28

External ODD Board - Page B - 42

IBEXPEAK- M 1/9 - Page B - 15

KBC-ITE IT8502E - Page B - 29

Click Board - Page B - 39

Table B - 1 SCHEMATIC DIAGRAMS

Version Note The schematic diagrams in this chapter are based upon version 6-7P-E51Q5-003. If your mainboard (or other boards) are a later version, please check with the Service Center for updated diagrams (if required).

B - 1

B . S c h e m a t i c D i a g r a m s

Schematic Diagrams

System Block Diagram CLICK BOARD

Calpella System Bl ock Diagram

6-71-E51Q2-D01A

POWER SWITCH BOARD

POWER GPU

POWER SWITCH+HOTKEY X 3 6-71-E51QS-D01A

Clock Generator RTM875N-632-VB-GRT

AUDIO BOARD

Arrandale PROCESSOR rPGA989/988

USB+EARPHONE+EXT.MIC 6-71-C4508-D02A

EXTERNAL ODD BOARD EXT. ODD 6-71-E51QN-D01

s m a r g a i D c i t a m e h c S . B

VDD3,VDD5

14.318 MHz

5V,3V,5VS,3VS,1.5VS,

800/1067 MHz DDR3 / 1.5V

DDRIII SO-DIMM0

SYSTEM SMBUS DDRIII SO-DIMM1

0.1"~13

SHEET 11

FDI HDMI

Sheet 1 of 42 System Block Diagram

CLICK BOARD

<8" LVD S SWI TCH

Ibex Peak-M Platform Controller Hub (PCH)

INTERNAL GRAPHICS

SPI

AZALIA MDC MODULE

TPM

128pins LQFP

27x27mm 1071 Ball FCBGA AZALIA LINK

LPC 0.5"~11" INT. K/B

EC SMBUS

BIOS SPI

PCIE THERMAL SENSOR W83L771AWG

SMART FAN

SMART BATTERY

SATA I/II 3.0Gb/s

HP OUT

INT SPK R AMP

Azalia Codec VIA VT1812

N7101 INT SPK L

MDC CON

33 MHz

14*14*1.6mm

MIC IN

RJ-11

32.768 KHz

EC ITE 8502E

1.1VS_VTT

AUDIO BOARD INTERNAL GRAPHICS

Synaptic LCD CONNECTOR,

VCORE

<=8"

<15" CRT SWITCH

810602-1703

1.5V,0.75VS(VTT_MEM)

DMI*4

0.5"~6.5"

CRT C ONNECTOR

TOUCH PAD

1.8VS

Memory Termination

100 MHz

INT MIC

24 MHz <12"

32.768KHz

USB2.0

<12"

480 Mbps

New Card SOCKET (USB3)

3G CARD (USB9)

Mini PCIE SOCKET (USB2)

JMICRO

JMC251 C LAN

CARD READER

25 MHz

1"~16"

RJ-45

SATA HDD

SATA ODD

USB0

USB1

USB4

AUDIO BOARD

B - 2 System Block Diagram

Bluetooth (USB11)

CCD (USB5)

7IN1 SOCKET

Schematic Diagrams

Clock Generator CLKGEN POWER

CLOCK GENERATOR CL K _ V CC 1

CL K_ V CC 2

R 13 4

15 CL K_ BUF _ R E F 14

3 3_ 0 4

XO UT XIN

27 28

REF _ 0 /CP U_ S EL

30

CL K _ SDAT A CL K _ SCL K

31 32

VD D_ DO T VD D_ 2 7 VD D_ S RC VD D_ CPU VD D_ REF

V DD_ S R C_ I/O V DD_ CP U_ I/O D OT _ 96 DO T_ 9 6# 27M 2 7 M_ SS

XT AL _O UT XT AL _IN

R E F _ 0/C PU_ S E L

SD A SC L

2 8 9 12 21 26 33

S RC _1 /SA T A S RC_ 1 #/S ATA# S RC _2 S R C_ 2#

CP U_ S T OP#

VS S _D OT VS S _2 7 VS S _SA T A VS S _SR C VS S _C PU VS S _R EF G ND

CPU _1 CP U_ 1# CPU _0 CP U_ 0# CK P W RGD /P D#

3 .3 V S

CL K _ VCC1

U7 1 5 17 24 29

15 18

L15

3 4

C LK _B U F _D OT 9 6_ P 1 5 C LK _B U F _D OT 9 6_ N 15

C2 0 5

C 19 7

C2 07

0 .1u _ 1 6V _ Y5 V_ 0 4

0 .1 u_ 1 6 V_Y 5V _ 0 4

1u _ 6.3 V _ X5R _0 4

* 15 m i _l s ho rt_ 0 6

6 7

0.1uF near the every power pin

10 11 13 14

16

C C C C

CP U _S T O P #

R148

2 .2 1 K _ 1% _ 0 4

20 19 23 22 25

LK _S AT A 1 5 LK _S AT A# 1 5 LK _P C IE_ ICH 1 5 LK _PC IE_ ICH# 1 5

3 .3 V S

1 .1 V S_V TT C LK _V C C2 L 14

C LK _B U F _B CL K _P 15 C LK _B U F _B CL K _N 1 5

C2 06

C1 9 6

0.1 u _ 16 V_ Y5 V _ 04

1 u_ 6 .3 V _X 5 R_ 0 4

* 1 5 m i l _ s h o r t _ 06

VDD_I /O c an be

CL K _ P W RG D

ranging from 1.05V to 3.3V

3 .3 V S

SL G 8S P5 8 5

Slego SLG8SP585 6-02-08585-EQ0 Realte k RTM875N-632- VB- GRT

R 14 9 1 0 K_1 % _ 04

Sheet 2 of 42 Clock Generator

0.1uF near the every power pin

D

SMBus

36

CL KE N #

Q1 2

R 14 6

MT N7 00 2 Z HS3

1 M_ 0 4

G S

Q1 1A MT DN 70 0 2Z H S6 R

EMI

2

D 15

S CL K _ SCL K

SMB _ CL K 6

CL K _ S CL K 1 0 ,11

6-22-1 4R31- 1B7 6-22-1 4R31- 1B6

1

G

3 .3V S X1

5 VS

1 2

4 3

RN 15 2 .2K _ 4 P 2 R_ 04

HS X5 30G_ 1 4.31 818M Hz 2

XIN

1

X OUT

R E F _ 0/C P U_ S EL

C 19 4

* 1 0 p _5 0 V _ N P O _ 0 6

G 3

15

4

SMB _ DAT A

D

CL K _ SDAT A

CL K _ S DA TA 1 0 ,11

S

C1 99

C 20 2

33 p _5 0V_ NP O_ 0 4

3 3 p_ 5 0 V _N PO_ 0 4

EMI

Capactior

5

Q1 1B MT DN 70 0 2Z H S6 R

CPU_SEL_During

CK_PEWGD Latch Pinl

3 .3V S

PIN _3 0 R 13 6

* 4. 7 K _0 4

CPU_0

C P U_ 1

133MHz

133MHz

1(0.7V-1.5V) 100MHz

100MHz

RE F _0 /CP U _ S EL

0(default) R 13 7

1 0K _ 0 4 5VS 1 3 ,17 ,2 0,2 1 ,2 6,2 7 ,30,3 1,35 ,36 3.3 V 3 ,4 ,12 ,1 ,41 5 ,1 6,1 8,1 9,2 0 ,21 ,2 3 ,24,2 5 ,29 ,3 ,0 31 ,3 3,3 4,3 5 3.3 VS 1 0 ,11 ,1 2,1 3 ,1 4,1 5 ,1 6,1 7 ,18 ,1 9 ,20 ,2 1 ,23 ,2 4,2 5 ,2 6,2 7 ,2 8,2 9 ,30 ,3 1 ,35,3 6 1.1 VS _ VT T 4 ,6 ,7 ,14 ,1 5 , 16 ,1 9, 20 ,2 1,3 4 ,3 5,3 6

Clock Generator B - 3


Schematic Diagrams

CPU 1/7 (DMI, PEG, FDI) PROCESSOR

1/7

( DMI,PEG,FDI )

U 16 A

16 16 16 16 16 16 16 16


16 16 16 16 16 16 16 16

Sheet 3 of 42 CPU 1/7 (DMI, PEG, FDI)

A2 4 C2 3 B2 2 A2 1

DM I_T XN0 DM I_T XN1 DM I_T XN2 DM I_T XN3

B2 4 D2 3 B2 3 A2 2

DM I_T XP0 DM I_T XP1 DM I_T XP2 DM I_T XP3

D2 4 G2 4 F23 H2 3

D MI_ R XN 0 D MI_ R XN 1 D MI_ R XN 2 D MI_ R XN 3 D D D D

MI_ MI_ MI_ MI_

R R R R

XP XP XP XP

D2 5 F24 E2 3 G2 3

0 1 2 3

16 16 16 16 16 16 16 16

F D I_ T XN 0 F D I_ T XN 1 F D I_ T XN 2 F D I_ T XN 3 F D I_ T XN 4 F D I_ T XN 5 F D I_ T XN 6 F D I_ T XN 7

16 16 16 16 16 16 16 16

F D I_ T F D I_ T F D I_ T F D I_ T F D I_ T F D I_ T F D I_ T F D I_ T

16 16

F DI_ F SY NC 0 F DI_ F SY NC 1

16

F DI_ IN T

E2 2 D2 1 D1 9 D1 8 G2 1 E1 9 F21 G1 8

D2 2 C2 1 D2 0 C1 8 G2 2 E2 0 F20 G1 9

XP0 XP1 XP2 XP3 XP4 XP5 XP6 XP7

It applies to Au burnd ale and Cl arksfi eld discrete graphic designs. If discrete graphic chip is used for Auburnd ale, VAXG(GFX core) rail can beconnected to GNDif motherboardonly supports discrete graphics andal soi na com mon motherboarddesign if GFXVRis notst uff ed. Onthe otherhand , if the VR is stuff ed,

F17 E1 7

DM DM DM DM

I_ I_ I_ I_

RX# RX# RX# RX#

[0 [1 [2 [3

PEG_ IC OM PI PEG _ ICO MPO PEG_ R CO MPO PE G_ RBI AS

] ] ] ]

DM I_ RX[0 ] DM I_ RX[1 ] DM I_ RX[2 ] DM I_ RX[3 ]

D M I

DM I_ T X# [0 ] DM I_ T X# [1 ] DM I_ T X# [2 ] DM I_ T X# [3 ] DM I_ T X[0 ] DM I_ T X[1 ] DM I_ T X[2 ] DM I_ T X[3 ]

F D I_T X# [0 ] F D I_T X# [1 ] F D I_T X# [2 ] F D I_T X# [3 ] F D I_T X# [4 ] F D I_T X# [5 ] F D I_T X# [6 ] F D I_T X# [7 ]

I n t e l ( R ) F D I

F D I_T X[0 ] F D I_T X[1 ] F D I_T X[2 ] F D I_T X[3 ] F D I_T X[4 ] F D I_T X[5 ] F D I_T X[6 ] F D I_T X[7 ] F D I_F SYN C[0 ] F D I_F SYN C[1 ]

C1 7

VAX G canbe l eft fl oati ngi n a comm on m otherboard design( Gfx VRkeeps VAXGfrom fl oating). In addition, FDI_RXN_[7: 0] andFDI_RXP_[7: 0] canbe left fl oatingon the PCH . FDI_TX[7:0] andFDI_ TX#[7:0] canbe left fl oati ng on the Auburndale.

16 16

F D I_IN T F18 D1 7

F DI_ L SYN C0 F DI_ L SYN C1

PE G_ RX# [0 ] PE G_ RX# [1 ] PE G_ RX# [2 ] PE G_ RX# [3 ] PE G_ RX# [4 ] PE G_ RX# [5 ] PE G_ RX# [6 ] PE G_ RX# [7 ] PE G_ RX# [8 ] PE G_ RX# [9 ] PEG_ R X# [1 0 ] PEG_ R X# [1 1 ] PEG_ R X# [1 2 ] PEG_ R X# [1 3 ] PEG_ R X# [1 4 ] PEG_ R X# [1 5 ]

F D I_L SY NC [0 ] F D I_L SY NC [1 ]

S C I H P A R G S S E R P X E I C P

TheGFX _I MON , FDI_ FSYNC[0], FDI_ FSYNC[1], FDI_ LSYNC[0], FDI_LSYNC[1], and FDI_INTsi gn als should bet i edt o GND(thr ough 1 K ? %resistors) in t hecomm on motherboarddesign case. Please not that if these signals are lef t fl oati ng, there are no

PEG _ RX[0 ] PEG _ RX[1 ] PEG _ RX[2 ] PEG _ RX[3 ] PEG _ RX[4 ] PEG _ RX[5 ] PEG _ RX[6 ] PEG _ RX[7 ] PEG _ RX[8 ] PEG _ RX[9 ] PE G_ RX[1 0 ] PE G_ RX[1 1 ] PE G_ RX[1 2 ] PE G_ RX[1 3 ] PE G_ RX[1 4 ] PE G_ RX[1 5 ] PEG _ TX# [0 ] PEG _ TX# [1 ] PEG _ TX# [2 ] PEG _ TX# [3 ] PEG _ TX# [4 ] PEG _ TX# [5 ] PEG _ TX# [6 ] PEG _ TX# [7 ] PEG _ TX# [8 ] PEG _ TX# [9 ] PE G_ T X# [1 0 ] PE G_ T X# [1 1 ] PE G_ T X# [1 2 ] PE G_ T X# [1 3 ] PE G_ T X# [1 4 ] PE G_ T X# [1 5 ] PEG _T X[0 ] PEG _T X[1 ] PEG _T X[2 ] PEG _T X[3 ] PEG _T X[4 ] PEG _T X[5 ] PEG _T X[6 ] PEG _T X[7 ] PEG _T X[8 ] PEG _T X[9 ] PEG _ TX[1 0 ] PEG _ TX[1 1 ] PEG _ TX[1 2 ] PEG _ TX[1 3 ] PEG _ TX[1 4 ] PEG _ TX[1 5 ]

f uncti onal i mpacts but a small amount of po w er (~15 m W) maybe wasted. VAXG_SENSE andVSSAXG_SENSEon Auburndale can be left as noconnect. DPLL_REF_SSC LK andDPLL_REF_SSCLK#can be c onnected to GND on Aubu rndale directly i f motherboard only supports dis crete graphics. I n a comm on motherboard design, t hese pins are driven via PCH(even if G raphics is disabled by BIOS) thus no external terminati oni s required.

Thermal Sensor near U16

20 mil

B2 6 A2 6 B2 7 A2 5

PEG_ IR CO MP_ R

R 20 9

4 9 .9 _ 1 % _ 04

EXP _R BIAS

R 20 8

7 50 _ 1 % _0 4

K3 5 J34 J33 G 35 G 32 F34 F31 D 35 E3 3 C 33 D 32 B3 2 C 31 B2 8 B3 0 A3 1 J35 H 34 H 33 F35 G 33 E3 4 F32 D 34 F33 B3 3 D 31 A3 2 C 30 A2 8 B2 9 A3 0 L33 M 35 M 33 M 30 L31 K3 2 M 29 J31 K2 9 H 30 H 29 F29 E2 8 D 29 D 27 C 26 L34 M 34 M 32 L30 M 31 K3 1 M 28 H 31 K2 8 G 30 G 29 F28 E2 7 D 28 C 27 C 25

PZ 9 8 9 2 7-3 6 4 1 -01 F

3 .3 V

Analog Thermal Sensor C 35 7

R 2 28

* 1 0 m i l s_ ho rt _ 04

3 .3 V C RIT _ TE MP_ RE P#

19

Q 14

* 0.1 u _ 16 V_ Y 5V _0 4

2

1 VCC

1 2

C

U1 8 VDD D+

T HE RM AL ER T

DGN D

SDA TA SC LK

4 6

C

A P M _ E X T T S #_ E C 4

D1 6

* C D B U 0 30 4 0

E

3 5

*W 8 3 L 7 71 AW G

B - 4 CPU 1/7 (DMI, PEG, FDI)

1:2 (4mi ls:8m ils)

T HER M_ VO L T 2 8

7 8

4 ,1 2,1 4 ,1 5 ,16 ,1 8 ,1 9 ,20 ,2 1 , 2 3,2 4 ,2 5 ,2 9,3 0 ,3 1 ,33 ,3 4 ,3 5 3.3 V 3

C359

GN D

0 .1 u _ 16 V_ Y 5V _0 4

B Q 10 *2 N3 9 0 4

OU T

T HER M_ AL ER T # 2 8

SM D_ CPU _ T HER M 1 5 ,2 8 SM C_ CPU _ T HER M 1 5 ,2 8

G7 1 1 ST9 U

C3 6 0 0. 1u _ 1 6V _Y 5 V_ 04

PL ACE NEAR U16

1

2

3

Schematic Diagrams

CPU 2/7 (CLK, MISC, JTAG) PROCESSOR

2/7

( CLK,MISC,JTAG )

1.5 V

Processor Compensation Signals R 23 8

4 9 . 9 _ 1% _ 0 4

H_ CO MP 0

R 21 3

4 9 . 9 _ 1% _ 0 4

H_ CO MP 1

R 2 37

2 0 _ 1% _ 0 4

H_ CO MP 2

R 2 36

2 0 _ 1% _ 0 4

H_ CO MP 3

R 2 03 * 1 K_ 1% _ 0 4 R 20 6

DDR3 Compensation Signals SM _R CO MP_ 0

R 22 9

1 0 0 _ 1% _ 0 4

SM _R CO MP_ 1

R 23 0

2 4 . 9 _ 1% _ 0 4

SM _R CO MP_ 2

R 23 1

1 3 0 _ 1% _ 0 4

* 10 m il_ s h ort_ 0 4

BSS138( VGS 1.5V ) Q1 3 *R J U0 0 3N 0 3T 1 0 6 S D

SM_ DR AMR ST #

DD R3 _ DR AM RST #

1 0,1 1

R2 0 7 *1 0 0K _1 % G _ 04 DR AMR ST _C T RL 9 ,1 9

TRACE WIDTH 10MIL, LENGTH <500MILS

? ? IBEXCONTR OL

C3 1 1 *4 7 n _5 0 V_ 0 4 H_ C OM P3

A T2 3

H_ C OM P2

A T2 4

U 1 6B C OM P3

Processor Pullups 1 .1 VS_ VT T

H_ C OM P1

G1 6

H_ C OM P0

A T2 6

C OM P2 C OM P1 C OM P0

R 21 9

4 9 . 9 _ 1% _ 0 4

H_ CA TER R#

AH2 4

R 2 39

6 8 _ 04

H_ PR OC HO T# _ D

R 2 47

* 68 _ 0 4

H_ CP UR ST#

AK1 4

H_ C AT ERR #

A T1 5

19 ,2 8 H_ PEC I

R 24 8

3 6 H_ PRO CH OT #

* 10 m i _l s h ort_ 0 4 H_ PRO CH OT # _ D

I f PROCHOT# is not used, then it

AN2 6

SKT O CC #

C ATE RR #

PEC I

PR OC HO T#

must be terminated

witha 50-O pull -up resistor to VTT _ 1.1 rail.

AK1 5

1 9 H_ T HR MT R IP#

BC L K BCL K#

M I S C S

K C O T L H C

E R M A L

BCL K_ IT P BCL K_ IT P# PEG _C L K PEG _ CL K# DPL L _ REF _ SSC L K DP LL _ RE F _S SCL K #

3 C R S D I D M

SM_ D RAM RST # SM_ RC OM P[0 ] SM_ RC OM P[1 ] SM_ RC OM P[2 ] P M_ EXT_ T S# [0 ] P M_ EXT_ T S# [1 ]

A L1 5

1 6 H_ PM _ SYN C R 24 9

1 6,3 6 D ELA Y_ PW R GD

SY S_ AGEN T_ PW RO K AN1 4

* 0 _0 4

R 25 0

AP2 6

19 H _C PU PW RG D R 52

1 6 PM_ D RAM _ PW RG D

* 10 m il_ s ho rt_ 0 4

VD DPW R GO OD _ R

AK1 3

AM1 5

16 H _V TT PW R GD

Connect to the P rocessor (VTTPW RGO OD) VTT_1.1 VR pow er goodsi gnal to processor. Si gnal vol tage level is 1.1 V.

R 60

1 8 ,23 ,2 5 ,2 8 B UF _ PL T _R ST #

R ESET _O BS#

PM _S YN C

VC CPW R GO OD _ 1

* 10 m il_ s ho rt_ 0 4 AN2 7

1 . 5 K _ 1 % _ 04

Signal fromPCHt oPr ocessor Connect to PCH( PLT_RST#) (need s to be level translated f r o m3 . 3 V t o 1 . 1 V ) .

H_ PW RG D_ XDP

AM2 6

PL T _R ST # _R

A L1 4

R 61 7 5 0 _1 % _ 04

BCL K_ CP U_ P 1 9 BCL K_ CP U_ N 1 9

AR 30 AT 3 0 E1 6 D 16

CL K_ DP_P 15 C L K _ DP _ N 1 5

F6

S M_ DR AMR ST #

AL 1 AM 1 AN 1

S M_ RC OM P_ 0 S M_ RC OM P_ 1 S M_ RC OM P_ 2

R 23 3 R5 4

10 K _ 0 4 10 K _0 4

AN 15 AP1 5

P M_ EXTT S# [0 ] P M_ EXTT S# [1 ]

R5 3 R 23 2

*0 _0 4 * 0_0 4

R 23 4

* 1 2 . 4 K_ 1 % _ 0 4

VC CPW R GO OD _ 0

SM _D RA MPW R OK

VT T PW R GOO D T APPW R GO OD

P W R M A N A G E M E N T

M P B

XD P_ T MS XD P_ T DO _M XD P_ T DI_ R XD P_ PRE Q# XD P_ T DO _R

R 25 2 R 24 4 R 25 1 R 24 2 R 24 1

* 51_ 0 4 51 _ 0 4 * 51_ 0 4 * 51_ 0 4 * 51_ 0 4

& G A T J

XD P_ T CL K XD P_ T RST #

R 24 5 R 24 0

* 51_ 0 4 51 _ 0 4

XD P_ T DO _M

R 24 3

AT 2 8 AP2 7

AN 28 T C K AP 2 8 T M S AT 2 7 T RST # AT 2 9 TDI AR 27 T DO AR 29 T DI _M AP2 9 T DO _M AN 25 DB R# B PM# [0 ] B PM# [1 ] B PM# [2 ] B PM# [3 ] B PM# [4 ] B PM# [5 ] B PM# [6 ] B PM# [7 ]

AJ 2 2 AK2 2 AK2 4 AJ 2 4 AJ 2 5 AH 22 AK2 3 AH 23

Sheet 4 of 42 CPU 2/7 (CLK, MISC, JTAG)

CL K_ EXP_ P 1 5 CL K_ EXP_ N 1 5

A1 8 A1 7

1.1 VS_ VT T

T HER MT R IP# P RD Y# PRE Q#

H_ C PUR ST #

A1 6 B1 6

PM _EXT T S# _E C 3 T S# _D IMM 0 _1 1 0 ,1 1

XD P_ PREQ # XD P_ TC L K XD P_ TM S XD P_ TR ST # XD P_ TD I_ R XD P_ TD O_ R XD P_ TD I_ M XD P_ TD O_ M

1.1 VS_ VT T

R STI N#

PZ 98 9 2 7-3 6 4 1 -01 F

1 .5 VS_ CPU

* 10 m il_ s h ort_ 0 4XDP_ T DI_ M

3.3 V R5 0 1 .1 K_1 % _ 0 4

R 2 35 VD DPW R GO OD _ R U17

R6 2

R 24 6

* 1 . 5 K _ 1 % _ 04

DRA MPW R GD _ CPU

* 8. 2 K _ 04 3 .3V 3 ,1 2,1 4 ,1 5 ,16 ,1 8 ,1 9,2 0 ,2 1 ,23 ,2 4 ,2 5,2 9 ,3 0 ,31 ,3 3 ,3 4,3 5 1 .5V 9 ,1 0,11 ,2 1 ,23 ,2 7 ,2 9,3 1 ,3 3 ,36 1 .5V S_C PU 7,3 1 1 .1V S_V TT 2 ,6 ,7 ,1 4,1 5 ,1 6, 19 ,2 0 ,2 1,3 4 ,3 5, 36

5

1

4

IN 3 .3V

2

3 K_ 1% _ 0 4 3

1 .1 VS_ VT T _P W RG D 1 6 ,3 3 ,34

* MC 7 4VH C1 G 08 D F T 1G

Intel change 4.75K -->1.1K 12K -->3K

CPU 2/7 (CLK, MISC, JTA G) B - 5


Schematic Diagrams

CPU 3/7 (DDR3) PROCESSOR

3/7

( DDR3 )

U16C U16D

SA_C K[0] SA_C K#[0] SA_CKE[0]

10 M_A_DQ[63:0]


M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

Sheet 5 of 42 CPU 3/7 (DDR3)

10 10 10

10 10 10

M_A_BS0 M_A_BS1 M_A_BS2

M_A_CAS# M_A_RAS# M_A_WE#

A1 0 C1 0 C7 A7 B1 0 D1 0 E1 0 A8 D8 F10 E6 F7 E9 B7 E7 C6 H1 0 G 8 K7 J 8 G 7 G1 0 J 7 J1 0 L 7 M 6 M 8 L 9 L 6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG 5 AJ 7 AJ 6 AJ1 0 AJ 9 AL1 0 AK1 2 AK8 AL 7 AK1 1 AL 8 AN8 AM1 0 AR1 1 AL1 1 AM 9 AN9 AT1 1 AP1 2 AM1 2 AN1 2 AM1 3 AT1 4 AT1 2 AL1 3 AR1 4 AP1 4

AC3 AB2 U7

AE1 AB3 AE9

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

SA_C K[1] SA_C K#[1] SA_CKE[1]

SA_C S#[0] SA_C S#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

A Y R O M E M M E T S Y S R D D

SA_DQ S#[0] SA_DQ S#[1] SA_DQ S#[2] SA_DQ S#[3] SA_DQ S#[4] SA_DQ S#[5] SA_DQ S#[6] SA_DQ S#[7]

SA_DQ S[0] SA_DQ S[1] SA_DQ S[2] SA_DQ S[3] SA_DQ S[4] SA_DQ S[5] SA_DQ S[6] SA_DQ S[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

M_CLK_DD R0 10 M_CLK_DD R#0 10 M_CKE 0 10

11 M_B_DQ [ 63 : 0] M_B_DQ0 B5 M_B_DQ1 A5 M_B_DQ2 C3 B3 M_B_DQ3 E4 M_B_DQ4 A6 M_B_DQ5 M_B_DQ6 A4 M_B_DQ7 C4 M_B_DQ8 D1 M_B_DQ9 D2 M_B_DQ10 F2 F1 M_B_DQ11 C2 M_B_DQ12 F5 M_B_DQ13 M_B_DQ14 F3 M_B_DQ15 G4 M_B_DQ16 H6 M_B_DQ17 G2 J6 M_B_DQ18 J3 M_B_DQ19 G1 M_B_DQ20 M_B_DQ21 G5 M_B_DQ22 J2 M_B_DQ23 J1 M_B_DQ24 J5 K2 M_B_DQ25 L3 M_B_DQ26 M1 M_B_DQ27 M_B_DQ28 K5 M_B_DQ29 K4 M_B_DQ30 M4 M_B_DQ31 N5 M_B_DQ32 AF3 AG1 M_B_DQ33 AJ3 M_B_DQ34 AK1 M_B_DQ35 M_B_DQ36 AG4 M_B_DQ37 AG3 M_B_DQ38 AJ4 M_B_DQ39 AH4 AK3 M_B_DQ40 AK4 M_B_DQ41 A M6 M_B_DQ42 M_B_DQ43 AN2 M_B_DQ44 AK5 M_B_DQ45 AK2 M_B_DQ46 AM4 AM3 M_B_DQ47 AP3 M_B_DQ48 AN5 M_B_DQ49 M_B_DQ50 AT4 M_B_DQ51 AN6 M_B_DQ52 AN4 M_B_DQ53 AN3 M_B_DQ54 AT5 AT6 M_ B_DQ55 AN7 M_B_DQ56 M_B_DQ57 AP6 M_B_DQ58 AP8 M_B_DQ59 AT9 M_B_DQ60 AT7 M_B_DQ61 AP9 M_B_DQ62 AR10 M_B_DQ63 AT10

M_CLK_DD R1 10 M_CLK_DD R#1 10 M_CKE 1 10

M_CS#0 10 M_CS#1 10

M_ODT 0 10 M_ODT 1 10

B9 D7 H7 M7 AG 6 AM 7 AN10 AN13

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

C9 F8 J9 N9 AH7 AK9 AP11 AT13

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

C8 F9 H9 M9 AH8 AK10 AN11 AR13

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG 8 T3 V9

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A _DM [7 : 0] 10

M_A _DQS#[7:0] 10

M_A _DQS[7:0] 10

M_A _A[15:0] 10

11 11 11

11 11 11

M_B_BS0 M_B_BS1 M_B_BS2

M_B_CAS# M_B_RAS# M_B_WE#

AB1 W 5 R7

AC5 Y7 AC6

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

PZ98927-3641-0 1F

PZ98927-3641-0 1F

B - 6 CPU 3/7 (DDR3)

SB_CK[0] SB_CK#[0] SB_CKE[ 0]

SB_CK[1] SB_CK#[1] SB_CKE[ 1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

B Y R O M E M M E T S Y S

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

M_CL K_DDR2 11 M_CL K_DDR#2 11 M_CKE2 11

M_CL K_DDR3 11 M_CL K_DDR#3 11 M_CKE3 11

M_CS#2 11 M_CS#3 11

M_ODT2 11 M_ODT3 11

D4 E1 H3 K1 AH1 AL 2 AR4 AT 8

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

D5 F4 J4 L4 AH2 AL 4 AR5 AR8

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

C5 E3 H4 M5 AG 2 AL 5 AP5 AR7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M _B_ DQS7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M _B_A10 M _B_A11 M _B_A12 M _B_A13 M _B_A14 M _B_A15

R D D SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA [ 10] SB_MA [ 11] SB_MA [ 12] SB_MA [ 13] SB_MA [ 14] SB_MA [ 15]

M_ B_DM[7:0] 11

M _B_DQS #[7:0]

11

M _B_DQS [7: 0] 11

M_ B_A[15:0] 1 1

Schematic Diagrams

CPU 4/7 (Power) PROCESSOR

4/7

( POWER )

U 1 6F

PROCESSOR CORE POWER VC O RE

ICCMAX Maximum Processor

SV 48

V CO RE C3 2 3 8 0 _ R 5 X _ V 3 . 6 _ u 2 2

C331

C335

C337

8 0 _

8 0 _

R 5 X _ V 3 . 6 _ u 2 2

R 5

8 0 _ R 5 X _ V 3 . 6 _ u 2 2

X _ V 3 . 6 _ u 2 2 *

C3 4 2

C352

C329

C318

8 0 _ R 5

8 0 _

8 0 _

8 0 _ R 5 X _ V 3 . 6 _ u 2 2

X _ V 3 . 6 _ u 2 2 *

C3 3 2 8 0 _ R 5 X _ V 3 . 6 _ u 2 2

R 5 X _ V 3 . 6 _ u 2 2

R 5 X _ V 3 . 6 _ u 2 2 *

C356

C355

C354

8 0 _

8 0 _

8 0 _

R 5

R 5 X _ V 3 . 6 _ u 2 2 *

R 5 X _ V 3 . 6 _ u 2 2

X _ V 3 . 6 _ u 2 2 *

V CO RE

C3 4 8 6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

C3 2 6 6 0 _ R 5 X _ V 3 . 6 _ u 0 1

C3 4 0 4 0 _ R 7 X _ V 0 1 _ u 1 . 0

C346

C345

C344

6 0 _ R 5 X _ V 3 . 6 _ u 0 1

6 0 _ R 5 X _ V 3 . 6 _ u 0 1

C325

C327

C347

6 0 _

6 0 _

R 5

R 5

X _

X _ V 3 . 6 _ u 0 1 *

6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

V 3 . 6 _ u 0 1 *

C339 6 0 _ R 5 X _ V 3 . 6 _ u 0 1

C338

4 0 _ R 7 X _ V 0 5 _ u 1 0 . 0

6 0 _ R 5 X _ V 3 . 6 _ u 0 1

C333 6 0 _ R 5 X _ V 3 . 6 _ u 0 1

48A

PROCESSOR UNCORE POWER 1 .1 V S_ V TT AG 3 5 AG 3 4 AG 3 3 AG 3 2 AG 3 1 AG 3 0 AG 2 9 AG 2 8 AG 2 7 AG 2 6 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD 3 5 AD 3 4 AD 3 3 AD 3 2 AD 3 1 AD 3 0 AD 2 9 AD 2 8 AD 2 7 AD 2 6 AC 3 5 AC 3 4 AC 3 3 AC 3 2 AC 3 1 AC 3 0 AC 2 9 AC 2 8 AC 2 7 AC 2 6 A A3 5 A A3 4 A A3 3 A A3 2 A A3 1 A A3 0 A A2 9 A A2 8 A A2 7 A A2 6 Y3 5 Y3 4 Y3 3 Y3 2 Y3 1 Y3 0 Y2 9 Y2 8 Y2 7 Y2 6 V3 5 V3 4 V3 3 V3 2 V3 1 V3 0 V2 9 V2 8 V2 7 V2 6 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 P2 9 P2 8 P2 7 P2 6

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

C C1 C C2 C C3 C C4 C C5 C C6 C C7 C C8 C C9 C C1 0 C C1 1 C C1 2 C C1 3 C C1 4 C C1 5 C C1 6 C C1 7 C C1 8 C C1 9 C C2 0 C C2 1 C C2 2 C C2 3 C C2 4 C C2 5 C C2 6 C C2 7 C C2 8 C C2 9 C C3 0 C C3 1 C C3 2 C C3 3 C C3 4 C C3 5 C C3 6 C C3 7 C C3 8 C C3 9 C C4 0 C C4 1 C C4 2 C C4 3 C C4 4 C C4 5 C C4 6 C C4 7 C C4 8 C C4 9 C C5 0 C C5 1 C C5 2 C C5 3 C C5 4 C C5 5 C C5 6 C C5 7 C C5 8 C C5 9 C C6 0 C C6 1 C C6 2 C C6 3 C C6 4 C C6 5 C C6 6 C C6 7 C C6 8 C C6 9 C C7 0 C C7 1 C C7 2 C C7 3 C C7 4 C C7 5 C C7 6 C C7 7 C C7 8 C C7 9 C C8 0 C C8 1 C C8 2 C C8 3 C C8 4 C C8 5 C C8 6 C C8 7 C C8 8 C C8 9 C C9 0 C C9 1 C C9 2 C C9 3 C C9 4 C C9 5 C C9 6 C C9 7 C C9 8 C C9 9 C C1 0 0

R E W O P L I A R V 1 . 1

VT T 0 _ 1 VT T 0 _ 2 VT T 0 _ 3 VT T 0 _ 4 VT T 0 _ 5 VT T 0 _ 6 VT T 0 _ 7 VT T 0 _ 8 VT T 0 _ 9 V TT 0 _ 1 0 V TT 0 _ 1 1 V TT 0 _ 1 2 V TT 0 _ 1 3 V TT 0 _ 1 4 V TT 0 _ 1 5 V TT 0 _ 1 6 V TT 0 _ 1 7 V TT 0 _ 1 8 V TT 0 _ 1 9 V TT 0 _ 2 0 V TT 0 _ 2 1 V TT 0 _ 2 2 V TT 0 _ 2 3 V TT 0 _ 2 4 V TT 0 _ 2 5 V TT 0 _ 2 6 V TT 0 _ 2 7 V TT 0 _ 2 8 V TT 0 _ 2 9 V TT 0 _ 3 0 V TT 0 _ 3 1 V TT 0 _ 3 2

C O R E S U P P L Y

V TT TOTAL 2 1A

4 2 1 0

C29

C3 0

C 3 24

C3 5

C 33

C301

C334

1 0 u _ 6. 3V _X5 R _ 0 6

*1 0 u _ 6. 3V _ X5 R _ 0 6

1 0 u _ 6. 3V _ X5 R _ 0 6

*1 0 u _ 6. 3V _ X5 R _ 0 6

*1 0 u _ 6 .3 V_ X5 R_ 0 6

2 2 u _ 6 .3V _ X5 R _ 0 8

2 2 u _ 6 .3 V_ X 5 R_ 0 8

C36

C303

C3 4

C3 2 8

ICCMAX_VTT Max Current

1 0 u _ 6. 3V _X5 R _ 0 6

1 0 u _ 6 .3 V_ X5R _ 0 6

10 u _ 6 .3 V _ X5 R_ 0 6

*1 0 u _ 6 .3 V_ X 5R _ 0 6

for VTT Rail SV 18

The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide

1. 1V S_ V T T

V V V V V V V V V V V V

C P U

A H1 A H1 A H1 A H1 J14 J13 H14 H12 G14 G13 G12 G11 F 14 F 13 F 12 F 11 E 14 E 12 D14 D13 D12 D11 C14 C13 C12 C11 B 14 B 12 A 14 A 13 A 12 A 11

TT TT TT TT TT TT TT TT TT TT TT TT

0 0 0 0 0 0 0 0 0 0 0 0

_ _ _ _ _ _ _ _ _ _ _ _

3 3 3 3 3 3 3 4 4 4 4 4

3 4 5 6 7 8 9 0 1 2 3 4

AF10 A E1 0 A C1 0 A B1 0 Y10 W 10 U10 T10 J12 J11 J16 J15

C304

C3 0 5

C3 1 2

2 2 u _ 6 .3 V_ X5R _ 0 8

22 u _ 6 .3 V_ X 5 R _ 0 8

2 2 u_ 6 .3 V_ X5 R _0 8

Sheet 6 of 42 CPU 4/7 (Power)

1.1VS_VTT + VT T_ 4 3 + VT T_ 4 4

R 216 R 215

Please note that the VTT Rail Values are

* 15 m li _ s h o rt_ 0 6 * 15 m li _ s h o rt_ 0 6

Auburndale VTT=1.05V 1 .1 V S_ VT T

1K PU to VTT and 1K P D to GND for POC

R 2 25

VCORE

P SI#

* 1 K_ 1% _ 0 4

A N3 3

PSI #

A A A A A A A A

H H H H H H H

P SI #

36 1 .1 V S_ VT T

R E S W D I O V P U P

VID [0 ] VID [1 ] VID [2 ] VID [3 ] VID [4 ] VID [5 ] VID [6 ] PR O C_ D PR S L PVR

C

K3 5 K3 3 K3 4 L3 5 L3 3 M3 3 M3 5 M3 4

_V _V _V _V _V _V _V

ID0 ID1 ID2 ID3 ID4 ID5 ID6

3 3 3 3 3 3 3

R 2 26

6 6 6 6 6 6 6

1 K_ 1 % _ 0 4 R2 2 3 1 K_ 1 % _0 4 PM _ DP RS LP V R

3 6

R2 2 2 G15 VT T _ SE L EC T

H _ VT TV ID1 *1 K_ 1 % _ 0 4

TO V CO RE POW ER CO NT ROL

A N3 5 ISE NS E

S E N I L E S N E S

VC C_ SE NS E VSS_ SE NS E

V T T_SE NS E VSS _S E N SE_ V T T

A J3 4 A J3 5

B 15 A 15

IM O N

36

VC C _ S EN SE 3 6 VS S _ SEN S E 36

V T T_ S E N S E

3 4

VCOR E 36 1 .1V S_ V T T 2 ,4 ,7 ,1 4 ,1 5 ,1 6,1 9 ,2 0 ,2 1 ,3 4 , 3 5 ,3 6

PZ 98 9 2 7 -3 6 4 1- 01 F

CPU 4/7 (Power) B - 7


Schematic Diagrams

CPU 5/7 (Graphics Power) PROCESSOR VG F X_ CO RE


9 . 5 * 6 . 6 * 6 . 6 _ V 5 . 2 _ u 0 6 5 +

( GRAPHICS POWER )

U 1 6G

C364

C 34 9

1 0 u _ 6. 3V _ X5 R _ 0 6

1 0 u _6 .3 V_ X5 R _0 6

C 3 50

C3 6 2

2 2 u _ 6. 3V _X5 R _ 08

2 2 u_ 6 .3 V_ X5 R_ 0 8

1 7 3 C

Sheet 7 of 42 CPU 5/7 (Graphics Power)

5/7

Please note that the VTT Rail Values are Auburndale VTT=1.05V Clarksfield VTT=1.1V

1 .1 VS_ VT T C3 1 4

C3 0 8

22 u _ 6 .3 V_ X5 R_ 0 8

22 u _ 6 .3 V_ X5 R_ 0 8

AT 2 1 AT 1 9 AT 1 8 AT 1 6 AR 2 1 AR 1 9 AR 1 8 AR 1 6 A P2 1 A P1 9 A P1 8 A P1 6 AN 2 1 AN 1 9 AN 1 8 AN 1 6 AM 2 1 AM 1 9 AM 1 8 AM 1 6 AL 2 1 AL 1 9 AL 1 8 AL 1 6 A K2 1 A K1 9 A K1 8 A K1 6 AJ 2 1 AJ 1 9 AJ 1 8 AJ 1 6 AH 2 1 AH 1 9 AH 1 8 AH 1 6

J24 J23 H25

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

VT T 1 _ 45 VT T 1 _ 46 VT T 1 _ 47

E S S E N N E I S L

VAXG _ SEN SE VSSAXG _ SEN SE

GF GF GF GF GF GF GF

s D I V

G R A P H I C S

S C I H P A R G

F D I

VI VI VI VI VI VI VI

D[0 D[1 D[2 D[3 D[4 D[5 D[6

] ] ] ] ] ] ]

G F X_ VR _E N G F X_ DP RSL PV R GF X_ IM O N

S L I A R

R E W O P

X_ X_ X_ X_ X_ X_ X_

V 5 . 1 3 R D D

AR2 2 AT 2 2

AM2 2 AP2 2 AN2 2 AP2 3 AM2 3 AP2 4 AN2 4

AR2 5 AT 2 5 AM2 4

GP UVC C SEN SE 3 5 GP UVS SSEN SE 35

DF DF DF DF DF DF DF

GT GT GT GT GT GT GT

GF XVR _ D PRS LP VR T P_ GF X_ IM ON

_ _ _ _ _ _ _

VID VID VID VID VID VID VID

_ _ _ _ _ _ _

0 1 2 3 4 5 6

R 36 1 R 45

3 3 3 3 3 3 3

5 5 5 5 5 5 5

D F GT _VR _ EN

* 1K _ 0 4 1 00 _ 1 % _ 0 4

1 .1 VS_ VT T

35

GF X_ IM O N 3 5

1. 5V S_ CP U

V DD Q1 V DD Q2 V DD Q3 V DD Q4 V DD Q5 V DD Q6 V DD Q7 V DD Q8 V DD Q9 VDD Q1 0 VDD Q1 1 VDD Q1 2 VDD Q1 3 VDD Q1 4 VDD Q1 5 VDD Q1 6 VDD Q1 7 VDD Q1 8

VT T 0 _5 9 VT T 0 _6 0 VT T 0 _6 1 VT T 0 _6 2

AJ 1 AF 1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

VDDQ 6A C5 5

C3 3 6

C330

C6 1

C5 8

1u _ 6 .3 V_ X5 R_ 0 4

2 2 u_ 6 .3 V_ X5 R_ 0 8

2 2 u _ 6. 3V _ X5 R _ 08

10 u _ 6 .3 V_ X5 R_ 0 6

1 0 u_ 6 .3 V_ X5 R_ 0 6

C3 4 1

C3 4 3

C39

C6 0

1u _ 6 .3 V_ X5 R_ 0 4

1 u _6 .3 V_ X5 R _0 4

1 u _ 6 .3 V_ X5R _ 0 4

1u _ 6 .3 V_ X5 R_ 0 4

+ C5 3 10 0 u _ 6 .3 V_ B_ A

1 .1 VS _V TT

P1 0 N1 0 L1 0 K1 0

C3 2 0

C6 4

10 u _ 6 .3 V_ X5 R_ 0 6

1 0 u_ 6 .3 V_ X5 R_ 0 6

1 .1 VS_ VT T

1 .1 VS_ VT T C3 0 6

C3 0 7

22 u _ 6 .3 V_ X5 R_ 0 8

22 u _ 6 .3 V_ X5 R_ 0 8

1 .1 VS _V T T

C3 0 9 C3 9 6 0 .0 1u _ 5 0 V_ X7 R_ 0 4

C3 5 1 0. 01 u _ 5 0 V_ X7R _ 0 4

22 u _ 6 .3 V_ X5 R_ 0 8

C3 0 2

K2 6 J27 J26 J25 H27 G28 G27 G26 F26 E2 6 E2 5

VT T 1 _ 48 VT T 1 _ 49 VT T 1 _ 50 VT T 1 _ 51 VT T 1 _ 52 VT T 1 _ 53 VT T 1 _ 54 VT T 1 _ 55 VT T 1 _ 56 VT T 1 _ 57 VT T 1 _ 58

22 u _ 6 .3 V_ X5 R_ 0 8

P E G

V 1 . 1

&

VT T 1 _6 3 VT T 1 _6 4 VT T 1 _6 5 VT T 1 _6 6 VT T 1 _6 7 VT T 1 _6 8

D M I

J2 2 J2 0 J1 8 H2 1 H2 0 H1 9

C3 1 5

C3 1 3

22 u _ 6 .3 V_ X5 R_ 0 8

2 2 u_ 6 .3 V_ X5 R_ 0 8

C4 1

C3 7

C38

C52

C56

C5 4

1u _ 6 .3 V_ X5 R_ 0 4

1 u _6 .3 V_ X5 R _0 4

2 .2 u _ 1 6V _ X5 R _ 06

4 .7 u _ 6 .3 V_ X5 R _ 0 6

1 0 u _ 6 .3V _ X5 R _ 0 6

10 u _ 6 .3 V_ X5 R_ 0 6

1 .8 VS

V 8 . 1

VC CP LL 1 VC CP LL 2 VC CP LL 3

L2 6 L2 7 M2 6

VCCPLL 0.6A

PZ 98 9 2 7 -3 6 41-0 1 F

1 .5 VS _ CPU 4 ,3 1 1 . 8V S 2 0 , 33 V GF X_ C OR E 3 5 1 .1 VS _ VT T 2 ,4, 6, 14 ,1 5 ,1 6 ,1 9 ,2 0 ,21 ,3 4 ,3 5 ,3 6 1 .5 V 4 , 9 , 10 , 1 ,12 1 , 23 , 2 7, 2 9 , 31 , 33 , 3 6

B - 8 CPU 5/7 (Graphic s Power)

Schematic Diagrams

CPU 6/7 (GND) PROCESSOR

6/7

( GND )

U16H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

U16I

V SS

PZ98927-3641-01F

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M1 0 L35 L32 L29 L8 L5 L2 K34 K33 K30

K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

Sheet 8 of 42 CPU 6/7 (GND)

VS S

F T C N

VSS_NC TF1 VSS_NC TF2 VSS_NC TF3 VSS_NC TF4 VSS_NC TF5 VSS_NC TF6 VSS_NC TF7

AT35 AT1 AR34 B34 B2 B1 A35

PZ98927-3641-01F

CPU 6/7 (GND) B - 9


Schematic Diagrams

CPU 7/7 (RESERVED) PROCESSOR

7/7

( RESERVED ) 1 .5 V

U1 6 E RS V D3 2 RS V D3 3

PCI- Express Configurat i on Sel ect

CFG0


CFG0

1 : Single PEG 0 : Bif urcati on enable R 22 7

* 3. 0 1K _ 04

R 35 R 39

1 0 MVR EF _ D Q_ DI M0 1 1 MVR EF _ D Q_ DI M1

*0 _ 04 *0 _ 04

VR EF _ C H_ A _ DI MM VR EF _ C H_ B _ DI MM

CFG3 - PCI - Express Stat i c Lane Reversal

Sheet 9 of 42 CPU 7/7 (RESERVED)

CFG3 CFG3

* 3. 0 1K _ 04

C F G0

C F G3 C F G4

C F G7

0 : Enabled; An external Dis pl ay Port devi ce i s connected to the Em bedded ispl ay Port

R 22 0

* 3. 0 1K _ 04

S S S S S S S S S S S S S S

VD VD VD VD VD VD VD VD VD VD VD VD VD VD

1 2 3 4 5 6 7 8 9 1 1 1 1 1

RS V D3 4 RS V D3 5 RS V D3 6 R SV D _ NC TF _3 7 RS V D3 8 RS V D3 9 0 1 2 3 4

R 211

*0 _ 0 4

R SVD8 6

A M3 0 A M2 8 A P3 1 A L3 2 A L3 0 A M3 1 A N2 9 A M3 2 A K3 2 A K3 1 A K2 8 A J2 8 A N3 0 A N3 2 A J3 2 A J2 9 A J3 0 A K3 0 H1 6

B1 9 A1 9 CFG7

R 22 4

* 3. 0 1K _ 04

R 20 5 R 20 4

* 15 m li_ s h ort _0 6 * 15 m li_ s h ort _0 6

H _R S VD 1 7_ R H _R S VD 1 8_ R

A2 0 B2 0 U9 T9 AC 9 AB 9

C1 A3

J2 9 J2 8 A3 4 A3 3 C3 5 B3 5

R SV D _ NC TF _4 0 R SV D _ NC TF _4 1

C F G [0] C F G [1] C F G [2] C F G [3] C F G [4] C F G [5] C F G [6] C F G [7] C F G [8] C F G [9] C F G [10 ] C F G [11 ] C F G [12 ] C F G [13 ] C F G [14 ] C F G [15 ] C F G [16 ] C F G [17 ] R S VD _ TP _8 6

D E V R E S E R

RS V D4 5 RS V D4 6 RS V D4 7 RS V D4 8 RS V D4 9 RS V D5 0 RS V D5 1 RS V D5 2 RS V D5 3 R SV D _ NC TF _5 4 R SV D _ NC TF _5 5 R SV D _ NC TF _5 6 R SV D _ NC TF _5 7 RS V D5 8

R S VD _ TP _5 9 R S VD _ TP _6 0 K EY RS V D6 2 RS V D6 3 RS V D6 4 RS V D6 5

V R E F _ CH _ A_ DIM M

A L2 6 AR 2

Q8 *A O3 4 0 2L S D

* 1 K_ 1% _ 0 4 MV R EF _ D Q_ DIM 0

R 2 12 G * 1 00 K _ 1 % _ 0 4

R37 * 1 K_ 1% _ 0 4

A J2 6 A J2 7

DR A MR ST _ CT R L 4,1 9

AP1 A T2 1 .5 V A T3 AR 1

A L2 8 A L2 9 A P 30 A P 32 A L2 7 A T3 1 A T3 2 A P 33 A R3 3 A T3 3 A T3 4 A P 35 A R3 5 A R3 2

E 15 F 15 A2 D15 C15 A J1 5 A H1 5

V R E F _ CH _ B _ DI M M

R38

Q9 *A O3 4 0 2L S D

* 1 K_ 1% _ 0 4 MV R E F _ D Q_ D I M 1

R 2 14 * 1 00 K _ 1 % _ 0 4 G

R40 * 1 K_ 1% _ 0 4 DR A MR ST _ CT R L 4,1 9

? ? IBEXCONTROL

RSV D 6 4 _R RSV D 6 5 _R

R 2 17 R 2 18

* 15 m i _l s h o rt _ 06 * 15 m i _l s h o rt _ 06

R S VD 15 R S VD 1 6 R S VD 1 7 R S VD 1 8 R S VD 19 R S VD 2 0 R S VD 21 R S VD 2 2

R S VD _ NC TF _2 3 R S VD _ NC TF _2 4

R S VD 26 R S VD 2 7 R S VD _ NC TF _2 8 R S VD _ NC TF _2 9 R S VD _ NC TF _3 0 R S VD _ NC TF _3 1

R S VD _ TP _6 6 R S VD _ TP _6 7 R S VD _ TP _6 8 R S VD _ TP _6 9 R S VD _ TP _7 0 R S VD _ TP _7 1 R S VD _ TP _7 2 R S VD _ TP _7 3 R S VD _ TP _7 4 R S VD _ TP _7 5

R S VD _ TP _7 6 R S VD _ TP _7 7 R S VD _ TP _7 8 R S VD _ TP _7 9 R S VD _ TP _8 0 R S VD _ TP _8 1 R S VD _ TP _8 2 R S VD _ TP _8 3 R S VD _ TP _8 4 R S VD _ TP _8 5

VSS

AA5 AA4 R8 AD 3 AD 2 AA2 AA1 R9 A G7 AE3

V4 V5 N2 AD 5 AD 7 W 3 W 2 N3 AE5 AD 9

A P 34

PZ 9 89 2 7 -3 6 41 -0 1 F

1.5 V

B - 10 CPU 7/7 (RESERVED)

R36

A H2 5 A K 26

? ? IBEXCONTROL

RSVD86 Connect t o GND

CFG7 Cl arksfi eld (onl y f or early samples pre- ES1) - Connect to GND wit h 3.01K Ohm/ 5% r e si s t or

A J1 3 A J1 2

AP23 02GN

1 : Disablled; No physi cal Display Port attached to Embedded Displ ay Port

CFG4

R R R R R R R R R R R R R R

R SV D _ NC TF _4 2 R SV D _ NC TF _4 3

CFG4 - Di spl ay Port Pres ence

CFG4

A P2 5 A L2 5 A L2 4 A L2 2 A J3 3 A G9 M2 7 L2 8 J1 7 H1 7 G2 5 G1 7 E3 1 E3 0

1 : Normal Operati on 0 : Lane Numbers Revers ed 15 - > 0 , 14 - > 1 , . . . R 22 1

AP2302GN

4 ,1 0, 11 ,21 ,2 3,2 7,29 ,3 1,3 3, 36

TP _R S VD 8 6

VSS (AP34) can be left NC is CRB implementation ; EDS/DG recommendation to GND

Schematic Diagrams

DDR3 SO-DIMM_0 SO-DIMM A 5

J DIM M2 A

M_ A_ A[1 5 :0 ]

M _A_ A0 M _A_ A1 M _A_ A2 M _A_ A3 M _A_ A4 M _A_ A5 M _A_ A6 M _A_ A7 M _A_ A8 M _A_ A9 M _A_ A1 0 M _A_ A1 1 M _A_ A1 2 M _A_ A1 3 M _A_ A1 4 M _A_ A1 5

Layout Note: signal/space/signa l: 8 / 4/ 8

5 5 5 5 5 5 5 5 5 5 5 5 5 5

M M M M

CHANGE TO STANDARD

M_ A_ BS0 M_ A_ BS1 M_ A_ BS2 M_ C S# 0 M_ C S# 1 _ CL K_ DD R0 _ CL K_ DD R# 0 _ CL K_ DD R1 _ CL K_ DD R# 1 M_ C KE0 M_ C KE1 M _A _C AS# M _A _R AS# M _A _W E#

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78

SA0 _ DIM 0 SA1 _ DIM 0

2 ,1 1 C L K_ SCL K 2,1 1 C LK _S DAT A 3 .3 VS

RN 3 1 0 K_ 8 P4R _ 0 4 1 8 SA1 2 7 SA0 3 6 SA1 4 5 SA0

5 5 5 _ _ _ _

DIM DIM DIM DIM

1 1 0 0

116 120

M_ O DT 0 M_ O DT 1 M_ A_ D M[7 :0 ]

SA1 _D IM 1 1 1 SA0 _D IM 1 1 1

5

109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200

M_ A_ D QS[7 :0 ]

5 M_ A_ D QS# [7 : 0 ]

M _A_ D M0 M _A_ D M1 M _A_ D M2 M _A_ D M3 M _A_ D M4 M _A_ D M5 M _A_ D M6 M _A_ D M7

11 28 46 63 136 153 170 187

M M M M M M M M

12 29 47 64 137 154 171 188

_A_ _A_ _A_ _A_ _A_ _A_ _A_ _A_

D D D D D D D D

QS0 QS1 QS2 QS3 QS4 QS5 QS6 QS7

M _A_ D QS# 0 M _A_ D QS# 1 M _A_ D QS# 2 M _A_ D QS# 3 M _A_ D QS# 4 M _A_ D QS# 5 M _A_ D QS# 6 M _A_ D QS# 7

1 .5 V

10 27 45 62 135 152 169 186

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 0 /AP A1 1 A1 2 /BC# A1 3 A1 4 A1 5 BA0 BA1 BA2 S0 # S1 # CK 0 CK 0# CK 1 CK 1# CK E0 CK E1 CA S# RA S# W E# SA0 SA1 SC L SD A OD T 0 OD T 1 DM 0 DM 1 DM 2 DM 3 DM 4 DM 5 DM 6 DM 7 DQ DQ DQ DQ DQ DQ DQ DQ

S0 S1 S2 S3 S4 S5 S6 S7

DQ DQ DQ DQ DQ DQ DQ DQ

S0 S1 S2 S3 S4 S5 S6 S7

# # # # # # # #

DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 D Q1 0 D Q1 1 D Q1 2 D Q1 3 D Q1 4 D Q1 5 D Q1 6 D Q1 7 D Q1 8 D Q1 9 D Q2 0 D Q2 1 D Q2 2 D Q2 3 D Q2 4 D Q2 5 D Q2 6 D Q2 7 D Q2 8 D Q2 9 D Q3 0 D Q3 1 D Q3 2 D Q3 3 D Q3 4 D Q3 5 D Q3 6 D Q3 7 D Q3 8 D Q3 9 D Q4 0 D Q4 1 D Q4 2 D Q4 3 D Q4 4 D Q4 5 D Q4 6 D Q4 7 D Q4 8 D Q4 9 D Q5 0 D Q5 1 D Q5 2 D Q5 3 D Q5 4 D Q5 5 D Q5 6 D Q5 7 D Q5 8 D Q5 9 D Q6 0 D Q6 1 D Q6 2 D Q6 3

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M

M_ A_ DQ [6 3:0]

_A _D Q0 _A _D Q1 _A _D Q2 _A _D Q3 _A _D Q4 _A _D Q5 _A _D Q6 _A _D Q7 _A _D Q8 _A _D Q9 _A _D Q1 0 _A _D Q1 1 _A _D Q1 2 _A _D Q1 3 _A _D Q1 4 _A _D Q1 5 _A _D Q1 6 _A _D Q1 7 _A _D Q1 8 _A _D Q1 9 _A _D Q2 0 _A _D Q2 1 _A _D Q2 2 _A _D Q2 3 _A _D Q2 4 _A _D Q2 5 _A _D Q2 6 _A _D Q2 7 _A _D Q2 8 _A _D Q2 9 _A _D Q3 0 _A _D Q3 1 _A _D Q3 2 _A _D Q3 3 _A _D Q3 4 _A _D Q3 5 _A _D Q3 6 _A _D Q3 7 _A _D Q3 8 _A _D Q3 9 _A _D Q4 0 _A _D Q4 1 _A _D Q4 2 _A _D Q4 3 _A _D Q4 4 _A _D Q4 5 _A _D Q4 6 _A _D Q4 7 _A _D Q4 8 _A _D Q4 9 _A _D Q5 0 _A _D Q5 1 _A _D Q5 2 _A _D Q5 3 _A _D Q5 4 _A _D Q5 5 _A _D Q5 6 _A _D Q5 7 _A _D Q5 8 _A _D Q5 9 _A _D Q6 0 _A _D Q6 1 _A _D Q6 2 _A _D Q6 3

5

J DIM M2 B 1 .5V 75 76 81 82 87 88 93 94 99 1 00 1 05 1 06 1 11 1 12 1 17 1 18 1 23 1 24

3 .3 VS

20mils C96

C9 7

1 u _ 6 .3V _X5 R_ 0 4

0.1 u _ 1 0V _X7 R_ 0 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS

1 99 VDD SPD 3 .3 VS R 72

20mils

1 98 30

4,1 1 T S# _ DIM M0 _ 1 4,1 1 D DR 3_ D RAM RS T# C 1 8 C 1 9

9 M VR EF _ DQ _D IM 0

77 1 22 1 25

1 0 K _ 1% _ 0 4

R2 0

*0 _ 0 4

2 . 2u _6 . 3 V _ X 5R _ 06 0 . 1u _1 0V _ X 7R _ 04 R19

1 1 26

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43

M VREF _D IM0 C8 2 C8 1

NC 1 NC 2 NC TE ST E V E N T# RESE T#

VREF _D Q VREF _C A

* 15 m il _ sh o r t _ 0 6

2 . 2u _6 . 3V _ X5 R _ 06 0 . 1u _1 0V _ X7 R _ 04

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1

S1 S1 S1 S1 S2 S2 S2 S2 S2 S2 S2 S2 S2 S2 S3 S3 S3 S3 S3 S3 S3 S3 S3 S3 S4 S4 S4 S4 S4 S4 S4 S4 S4 S4 S5 S5 S5

6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2

44 48 49 54 55 60 61 65 66 71 72 12 7 12 8 13 3 13 4 13 8 13 9 14 4 14 5 15 0 15 1 15 5 15 6 16 1 16 2 16 7 16 8 17 2 17 3 17 8 17 9 18 4 18 5 18 9 19 0 19 5 19 6

Sheet 10 of 42 DDR3 SO-DIMM_0

VTT _ M EM 0 1 2 3 4 5

VT T 1 VT T 2 G1 G2

20 3 20 4 GN D1 GN D2

AS0 A6 2 1-U 2 SN- 7 F

CLOSE TO SO-DIMM_0

AS0 A6 2 1 -U2 SN -7 F

1.5 V +

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

+ C 3 2 1

C3 5 3

C57

5 60 u _ 2 .5V _6 .6 * 6.6 * 5.9

*2 2 0 u_ 2 .5 V_ B_ A

1 0 u _ 6.3 V_ X5 R_ 0 6

C6 2 10 u _ 6 .3V _X5 R_ 0 6

C7 8 *1 0 u _6 .3 V_ X5 R_ 0 6

C 47 1 u _6 .3 V_ X5 R_ 0 4

C68 1 u _ 6. 3V_ X5 R_ 0 4

C70 * 1 u_ 6 .3 V_ X5R _ 0 4

R 63

1K _1 % _ 0 4

M VR EF _ DIM 0

+ C 3 16 * 5 60 u _ 2. 5V_ 6 .6 *6 .6 *5 .9

R65

C8 6

1 K_ 1 % _0 4

0 .1 u_ 1 0 V _ X7 R _ 04

1.5 V

C7 3

C4 8

C 44

C67

C4 6

C7 5

C 43

0 .1u _ 1 0 V _ X7 R _0 4

0 .1 u_ 1 0 V_ X7R _ 04

* 0.1 u _ 1 0V _X7 R_ 0 4

0 .1 u _ 10 V_ X7 R_ 0 4

0.1 u _ 1 0V _X7 R_ 0 4

0 .1u _ 1 0 V _ X7 R _0 4

*0 .1 u _ 1 0V_ X7 R_ 0 4

C1 0 1

C1 0 5

C 10 4

C106

1 0u _ 6 .3 V _ X5 R _0 6

*1 u _ 6 .3V _X5 R_ 0 4

1 u _ 6.3 V_ X5 R_ 0 4

1 u _ 6 .3V _X5 R_ 0 4

4 ,9 ,1 1, 21 ,2 3 , 2 7,2 9 ,3 1 ,3 3,3 6 1 .5 V 1 1,3 3 VT T _ MEM 2 ,1 1,1 2 ,1 3 ,14 ,1 5 ,1 6 , 17 ,1 8 ,1 9 ,20 ,2 1 ,2 3 ,24 ,2 5 , 2 6, 27 ,2 8 ,2 9,3 0 ,3 1 , 3 5,3 63 .3 VS

VT T _M EM

DDR3 SO-DIMM_0 B - 11


Schematic Diagrams

DDR3 SO-DIMM_1 CHANGE TO STANDARD SO-DIMM B 5

J DIM M1 A

M_ B_ A[1 5 :0]

M M M M M M M M M M M M M M M M

L a y o u t N o t e: signal/spac e/signal: 8/4/8


5 M _ B_ BS0 5 M _ B_ BS1 5 M _ B_ BS2 5 M _ CS# 2 5 M _ CS# 3 5 M_ C LK_ D DR 2 5 M_ C LK_ D DR # 2 5 M_ C LK_ D DR 3 5 M_ C LK_ D DR # 3 5 M _ CKE2 5 M _ CKE3 5 M_ B_ CAS # 5 M_ B_ RAS # 5 M_ B_ W E# 10 SA0 _D IM 1 10 SA1 _D IM 1 2,1 0 CL K_ SC LK 2 ,1 0 CL K_ SDA TA

Sheet 11 of 42 DDR3 SO-DIMM_1

5 5 5

5

_B _A 0 _B _A 1 _B _A 2 _B _A 3 _B _A 4 _B _A 5 _B _A 6 _B _A 7 _B _A 8 _B _A 9 _B _A 10 _B _A 11 _B _A 12 _B _A 13 _B _A 14 _B _A 15

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 0 /AP A1 1 A1 2 /BC# A1 3 A1 4 A1 5

109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200

SA0 _ D IM1 SA1 _ D IM1

BA0 BA1 BA2 S0 # S1 # CK 0 CK 0# CK 1 CK 1# CK E0 CK E1 CA S# RA S# W E# SA0 SA1 SC L SD A

116 120

M _ OD T2 M _ OD T3 M _B _D M[7 :0 ]

M _B _D QS [7:0 ]

5 M _ B_ DQ S # [7:0 ]

M M M M M M M M

_B _B _B _B _B _B _B _B

_D _D _D _D _D _D _D _D

M0 M1 M2 M3 M4 M5 M6 M7

M M M M M M M M

_B _B _B _B _B _B _B _B

_D _D _D _D _D _D _D _D

QS QS QS QS QS QS QS QS

M _B M _B M _B M _B M _B M _B M _B M _B

_D _D _D _D _D _D _D _D

QS #0 QS #1 QS #2 QS #3 QS #4 QS #5 QS #6 QS #7

OD T 0 OD T 1

11 28 46 63 136 153 170 187 0 1 2 3 4 5 6 7

DM 0 DM 1 DM 2 DM 3 DM 4 DM 5 DM 6 DM 7

12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186


S0 S1 S2 S3 S4 S5 S6 S7


S0 S1 S2 S3 S4 S5 S6 S7

# # # # # # # #

DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 DQ 1 0 DQ 1 1 DQ 1 2 DQ 1 3 DQ 1 4 DQ 1 5 DQ 1 6 DQ 1 7 DQ 1 8 DQ 1 9 DQ 2 0 DQ 2 1 DQ 2 2 DQ 2 3 DQ 2 4 DQ 2 5 DQ 2 6 DQ 2 7 DQ 2 8 DQ 2 9 DQ 3 0 DQ 3 1 DQ 3 2 DQ 3 3 DQ 3 4 DQ 3 5 DQ 3 6 DQ 3 7 DQ 3 8 DQ 3 9 DQ 4 0 DQ 4 1 DQ 4 2 DQ 4 3 DQ 4 4 DQ 4 5 DQ 4 6 DQ 4 7 DQ 4 8 DQ 4 9 DQ 5 0 DQ 5 1 DQ 5 2 DQ 5 3 DQ 5 4 DQ 5 5 DQ 5 6 DQ 5 7 DQ 5 8 DQ 5 9 DQ 6 0 DQ 6 1 DQ 6 2 DQ 6 3

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 1 29 1 31 1 41 1 43 1 30 1 32 1 40 1 42 1 47 1 49 1 57 1 59 1 46 1 48 1 58 1 60 1 63 1 65 1 75 1 77 1 64 1 66 1 74 1 76 1 81 1 83 1 91 1 93 1 80 1 82 1 92 1 94

M_ B_ DQ 0 M_ B_ DQ 1 M_ B_ DQ 2 M_ B_ DQ 3 M_ B_ DQ 4 M_ B_ DQ 5 M_ B_ DQ 6 M_ B_ DQ 7 M_ B_ DQ 8 M_ B_ DQ 9 M_ B_ DQ 1 0 M_ B_ DQ 1 1 M_ B_ DQ 1 2 M_ B_ DQ 1 3 M_ B_ DQ 1 4 M_ B_ DQ 1 5 M_ B_ DQ 1 6 M_ B_ DQ 1 7 M_ B_ DQ 1 8 M_ B_ DQ 1 9 M_ B_ DQ 2 0 M_ B_ DQ 2 1 M_ B_ DQ 2 2 M_ B_ DQ 2 3 M_ B_ DQ 2 4 M_ B_ DQ 2 5 M_ B_ DQ 2 6 M_ B_ DQ 2 7 M_ B_ DQ 2 8 M_ B_ DQ 2 9 M_ B_ DQ 3 0 M_ B_ DQ 3 1 M_ B_ DQ 3 2 M_ B_ DQ 3 3 M_ B_ DQ 3 4 M_ B_ DQ 3 5 M_ B_ DQ 3 6 M_ B_ DQ 3 7 M_ B_ DQ 3 8 M_ B_ DQ 3 9 M_ B_ DQ 4 0 M_ B_ DQ 4 1 M_ B_ DQ 4 2 M_ B_ DQ 4 3 M_ B_ DQ 4 4 M_ B_ DQ 4 5 M_ B_ DQ 4 6 M_ B_ DQ 4 7 M_ B_ DQ 4 8 M_ B_ DQ 4 9 M_ B_ DQ 5 0 M_ B_ DQ 5 1 M_ B_ DQ 5 2 M_ B_ DQ 5 3 M_ B_ DQ 5 4 M_ B_ DQ 5 5 M_ B_ DQ 5 6 M_ B_ DQ 5 7 M_ B_ DQ 5 8 M_ B_ DQ 5 9 M_ B_ DQ 6 0 M_ B_ DQ 6 1 M_ B_ DQ 6 2 M_ B_ DQ 6 3

M_ B _ D Q[ 6 3 : 0 ] 5

J DIM M1 B 1 .5V 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

3.3 VS

20mils

VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD

D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 D1 2 D1 3 D1 4 D15 D1 6 D1 7 D1 8

VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS3 VSS3 VSS3 VSS3 VSS3 VSS3 VSS3 VSS3 VSS3 VSS3 VSS4 VSS4 VSS4 VSS4 VSS4 VSS4 VSS4 VSS4 VSS4 VSS4 VSS5 VSS5 VSS5

199 VD DSPD

C9 8

C99

1 u_ 6 .3 V_ X5 R _0 4

0 .1 u _ 10 V_ X7 R_ 0 4

77 122 125

C2 2 C2 3

9 M VREF _D Q_ D IM1

R23

* 0_ 0 4

R 22

MV REF _ D IM1 C8 4 C8 3

NC 1 NC 2 NC T EST

198 30

4 ,1 0 TS# _ DI MM 0_ 1 4 ,1 0 DDR 3 _ DR AMR ST # 2 . 2u _6 . 3V _ X5 R _ 06 0 . u1 _ 10 V _ X 7 R _0 4

EVEN T # RE SET #

1 126

VR EF _ DQ VR EF _ CA

*1 5 m li_ s h ort_ 0 6 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43

2 . 2u _6 . 3V _ X5 R _ 06 0 . u1 _ 10 V _ X 7 R _0 4

2010/01/08

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS1 0 VSS1 1 VSS1 2 VSS1 3 VSS1 4 VSS1 5

6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2

44 48 49 54 55 60 61 65 66 71 72 1 27 1 28 1 33 1 34 1 38 1 39 1 44 1 45 1 50 1 51 1 55 1 56 1 61 1 62 1 67 1 68 1 72 1 73 1 78 1 79 1 84 1 85 1 89 1 90 1 95 1 96

VT T_ M EM

VT T 1 VT T 2 G1 G2

2 03 2 04 GN D1 GN D2

AS0 A6 2 1 -UAS N-7 F

AS0 A6 2 1 -UASN -7 F

CLOSE TO SO-DIMM_1 Layout Note: SO-DIMM_1 is place d farther from t he GMCH than SO-DIMM_0

1 .5 V

1.5 V

C8 5

C 63

C 42

C 51

C 71

C76

C79

*1 0 u _ 6.3 V_ X5 R_ 0 6

1 0 u_ 6 .3 V_ X5 R _ 06

1 0 u_ 6 .3 V_ X5R _ 06

1 u _6 .3 V_ X5 R _ 0 4

1 u _ 6.3 V_ X5 R_ 0 4

1 u _ 6.3 V_ X5 R_ 0 4

* 1u _ 6 .3 V_ X5 R _0 4

C1 0 9

C 25

C 66

C 22 8

C 49

C69

C72

C77

C50

C45

0 .1 u_ 1 0 V _ X7 R _0 4

0 .1 u_ 1 0 V_ X7 R _ 04

0 .1 u_ 1 0 V_ X7R _ 04

0 .1 u _1 0 V_ X7R _ 04

0 .1 u _1 0 V_ X7R _ 04

0 .1 u _1 0 V_ X7R _ 0 4

0 .1 u _1 0 V_ X7 R _ 0 4

0 .1 u _ 10 V_ X7 R _ 0 4

0 .1 u _ 10 V_ X7 R_ 0 4

0 .1 u _ 10 V_ X7 R _ 0 4

C1 0 2

C 10 7

C 10 8

C 10 3

1 0 u_ 6 .3 V _ X5 R _0 6

1 u _6 .3 V_ X5R _ 0 4

*1 u _ 6 .3V _X5 R_ 0 4

1 u _6 .3 V_ X5 R _ 0 4

R 64

1 K _ 1% _ 0 4

MVR EF _ DIM 1

R66

C8 7

1 K_ 1 % _0 4

0 .1 u_ 1 0 V_ X7 R _0 4

1 .5V

VT T _ MEM

B - 12 DDR3 SO-DIMM_1

4 ,9 ,1 0,2 1 ,2 3 ,2 7,2 9 ,3 1 ,33 ,3 6 1 .5 V 10 ,3 3 VT T _M EM 2 ,1 0 ,12 ,1 3 ,1 4, 15 ,1 6 ,1 7,1 8 ,1 9 , 20 ,2 1 ,2 3 ,24 ,2 5 ,2 6,2 7 , 2 8 ,2 9,3 0 ,3 1 , 35 ,3 63 .3 VS

Schematic Diagrams

LVDS, Invert er 3 .3 VS

EDID Mode

PANEL CONNECTOR VIN

2 1

3 RN 6 4 2 .2 K_ 4P2 R _0 4

VIN _L CD

L 25

J _ LC D1

80m ils

* 1 5 m il _ s ho r t _ 0 6

C3 0 0

C2 9 7

C2 9 4

0 .1 u_ 5 0V _Y 5V _0 6

0 .1 u_ 5 0V _Y 5V _0 6

0. 1u _ 50 V_ Y5 V_ 0 6

CLOSE TO LVDS CONN. PIN

17 17

LVD S-L CL KN L VDS-L CL KP

17 17

L VDS-L 1 N L VD S-L 1P

17 17

L VDS-L 0 N L VD S-L 0P

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

LVD S-L CL KN LVD S-L CL KP LVD S-L 1 N LVD S-L 1 P LVD S-L 0 N LVD S-L 0 P

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 87 2 1 6-3 0 0 6

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

P_ DD C_ DAT A P_ DD C_ CL K BRI GHT N ESS

BRIG HTNESS

P _ D D C _ D A TA 1 7 P_ D DC_ C K L 17

28

INV_ BL ON LVD S-L 2N LVD S-L 2P

LVD S-L 2N 1 7 LVD S-L 2P 17 3.3 VS

C 2 91 0 .1 u _1 6 V_ Y5 V _ 04

PLVD D C4

C6

4.7 u _ 6.3 V_ X5R _ 06

0 .1 u _1 6 V_ Y5 V_ 04

Sheet 12 of 42 LVDS, Inverter

PANEL POWER

3 .3V S

2A

R 16

*1 5 m li _ s ho rt_ 0 6

C1 5 C1 7

0 .1 u_ 1 6 V_Y 5 V_0 4

3 .3V

*0 .01 u _ 50 V_ X7R _ 04 D1 5

PL VDD U1 4 5

1 VIN VIN

C

2A

BRIG HT NESS

AC

VO UT

A

C2 9 0 *0 .1 u_ 1 6 V_Y 5 V_0 4

*BAV9 9 REC TIF IER 3

1 7 NB_ ENAV DD

2 EN

R1 3

GN D APL 3 51 2 A

10 0 K_ 1% _ 0 4

G5243A 6- 02- 05243- 9C0 APL3512A 6- 02-03512-9C0

INVERTER CONNECTOR 28

BKL _E N

R6 8

* 1 0 m il _ s ho r t _ 0 4

BKL _ EN_ R

R 67

C90

*1 0 0 K_ 1% _ 04

* 0 .47 u _ 10 V_ Y5 V_ 0 4

3.3 V 4 1

1

3.3 V U3 A 7 4L VC 08 PW 3

1 7 BL ON

4 1

Z 1 2 01

C8 9

4

2

BL ON

3. 3V

U 3B 7 4 LVC 0 8PW 6

*0 .1 u _1 6 V_ Y5 V_ 04

5 7

R 69

7

1 0 0K_ 1 % _0 4

4 1

19

SB_B LO N

Z 1 2 02

2 8,3 0

L ID_ SW #

8

1 0 0K _ 1 % _ 0 4

IN V_BL O N

Z 1 2 03 1 0 4 1

1 6,2 8 AL L _SY S_ PW RG D

U 3C 7 4 LVC 0 8PW

9

3.3 V R7 0

U 3D 7 4 LVC 0 8PW

12 11

7

R71

C9 3

1 M _0 4

0 .1u _ 1 6V_ Y 5V_ 0 4

13 7

3 0, 31 ,3 2 ,33 ,3 4 ,35 ,3 6 ,37 VIN 3 ,4 ,1 4,1 5 ,1 6,1 8 , 1 9,2 0 ,2 1, 23 ,2 4, 25 ,2 9 ,30 ,3 1 , 33 ,3 4 ,35 3 .3 V 2 ,1 0,1 1 ,1 3,1 4 ,1 5,1 6 , 1 7,1 8 ,1 9,2 0 ,2 1,2 3 ,2 4, 25 ,2 6, 27 ,2 8 ,29 ,3 0 ,31 ,3 5 ,36 3 .3 VS 3 1 ,32 SY S15 V

LVDS, Invert er B - 13


Schematic Diagrams

HDMI, CRT

R210

17 HDMIB_ D0BP 17 HDMIB_ D0BN 17 HDMIB_ CLKBP 17 HDMIB_ CLKBN HDMI _CT RLCL K HDMI_CT RLDATA

1 7 HDMI_CT RLCL K 17 HDMI_CT RLDATA


M_PORTB_ HPD# _R 3 .3VS

Sheet 13 of 42 HDMI, CRT

3.3 VS

Z 4 304

R 56 R 47

* 4. 7K _ 0 4 * 0_ 04

R2 9

4 99 _ 1% _0 4

R 49 R 58

DCC_ EN# PC0 PC1 Z 4 305

* 4. 7 K_ 0 4 * 4. 7 K_ 0 4

Z 4 306 Z 4 307

OUT _D1 + OUT _D1OUT _D2 + OUT _D2OUT _D3 + OUT _D3OUT _D4 + OUT _D4SCL_ SINK SDA_ SINK HPD_ SINK VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8]

34 3 5 OE_ 1 QE_ 2

GND[1] GND[2] GND[3] GND[4] GND[5] GND[6] GND[7] GND[8] GND[9] GND[10]

GN D

22 23

HDMIB_DATA2P HDMIB _DATA2 N

19 20

HDMIB_DATA1P HDMIB_DATA1N

16 17

HDMIB_DATA0P HDMIB_DATA0N

13 14

HDMIB_CL OCKP HDMIB_CL OCKN

28 29

HDMIB _EXT1_ SCL HDMIB _EXT1_ SDA

30

HDMIB _EXT1_ HPD

2 11 15 21 26 33 40 46

5VS

DCC_EN#

R 31

4. 7K _04

PC0

R 30

* 4. 7 K_ 04

PC1

CRT PORT

1 7 DAC_ VSYNC

J_ HDMI1 C31 7

10u _6 .3V_X5R_ 06

22 u_6 .3V_X5R_ 08 18

14 L5

1

2

12

4 3 * HD MI201 2F 2 SF -90 0T 04s- ho rt 2 4 R

R4 8

C4 0

0.1 u_ 16 V_ Y5V_0 4

*0 .1u _16 V_Y5 V_ 0 4 0 .1u _16 V_Y 5 V_ 04

C3 2

2 0K_1 %_ 04

HDMIB_DATA1P C27

C65

0.1 u_1 6V_ Y5V_0 4

0.1 u_ 16 V_ Y5V_0 4

PORT C_HPD

17 PORT C_HPD

16

FOR EMI

HDMIB_DATA1N

1 5 12 18 24 27 31 36 37 43

C319

HD MIB_ EXT1 _SDA

4 3

HDMIB _CLO CKP

1

L7

2

4 3 * HDMI20 12F 2 SF -90 0T 04 -sho rt 1 5 R

R2 7

M_PORTB_ HPD# _R

10 F L P 5 1 0 4 R R 0 E 0 4 2 2 0 4 0

F L P 5 0 R 0 E

8 6 4

0 4 2 2 0

R A V L *

4 0 R A V L *

F L P 5 6 0 4 R R 0 E 0 4 2 2 0 4 0 R A V L *

F L P 5 0 R 0 E 0 4 2 2 0 4 0 R A V L *

2

HOTPLUG DET ECT +5 V

DDC/CEC GND

SDA

SCL

RESERVED TMD SCL OCKTMD SCL OCK+

T MDSDAT A0 -

SHIEL D0 TMD SDATA1 TMD SDATA1 + SHIEL D2

CEC CLK SHI EL D

TMDS DATA0+ SHIELD1 T MDSDAT A2 TMDS DATA2+

19

HDMIB _EXT 1_ HPD

17 15

HDMIB _EXT 1_ SCL

13

9 7 3 4 R

5

C12 81 7-1 19A5 -L

5 5 R

3 3. VS

C3 10

C 59

0 .1u _16 V_Y5 V_ 04

* 0.1u _1 6V_Y5 V_0 4

U15 10 11 13 15 1

5VS

2

3 .3VS

7

3.3VS

8 4 4 4 0 0 0 _ _ _ 8 V 9 V 6 V 5 5 9 5 9 2 Y 9 2 Y 2 Y _ _ _ C V C V C V 0 0 0 1 1 1 _ _ _ u u u 2 2 2 2 2 . 2 . . 0 0 0

DDC_ IN1

DDC_OUT 1

DDC_ IN2

DDC_OUT 2

SYNC_IN1

SYNC_OUT 1

SYNC_IN2

SYNC_OUT 2

VCC_SYNC

VIDEO_ 1

VCC_VIDEO

VIDEO_ 2

VCC_DDC

VIDEO_ 3

BYP TPD7S0 19

GND

1 2

9

DDCDATA

12

DDCL K

14

CRT_ HSYNC R 15

33 _0 4

HSYNC

16

CRT_ VSYNC

33 _0 4

VSYN C

R 14

L4 L3 L2

17 DAC_ RED 17 DAC_ GREEN 17 DAC_ BL UE

3

BLUE

4

GRN

5

RED

R1 2

R11

R10

1 50 _1% _0 4

150 _1 %_ 04

15 0_ 1%_ 04

4 0 _ O P N _ V 0 5 _ p 0 1 0 1 C

4 0 _ O P N _ V 0 5 _ p 0 1 2 1 C

4 0 _ O P N _ V 0 5 _ p 0 1 3 1 C

F L - 9 5 P R 5 0 R 0 E 0 4 2 2 0 4 0 R A V L *

F L P 5 0 R 0 E 0 4 2 2 0 4 0 R

RED

0 0 5M F -600T01 . FF CM1 0 0 5M F -600T01 . F CM1 . CM10 0 5MF -600T01 4 0 _ O P N _ V 0 5 _ p 0 1 1 1 C

4

3

HDMIB _D AT A0 N

1

2

HDMIB_ DATA0P

L6 *HDMI2 01 2F 2SF -90 0T 04-s ho rt

4

3 HDMIB _D AT A2 N

1

2 HDMIB_ DATA2P

L8 *HDMI2 01 2F 2SF -90 0T 04-s ho rt

A V L *

J_ CRT1 10 8AH1 5F ST04 A1CC

4 0 _ O P N _ V 0 5 _ p 0 1 4 1 C

6

IP4772CZ16 6-02-47721-B60 TPD7S019 6-02-07019-B20

2 ,10 ,1 1,1 2,14 ,15 ,16,1 7,1 8,19 , 20 ,2 1,2 3,24 ,25 ,26,2 7,2 8,29 , 30 ,3 1,3 5,36 3.3VS 2 ,17 ,20,2 1,2 6,27 ,30 ,3 1,3 5,36 5VS

B - 14 HDMI, CRT

F L P 5 0 R 0 E 0 4 2 2 0 4 0 R A V L *

R 0 E 0 4 2 2 0 4 0 R A V L *

1

6- 19-31001- 266

RN1 2.2 K_ 4P2 R_04

F 4 4 L R P 5 0

3

5VS

4 3

FOREMI

HDMI_CEC

11

*1 0m il_s ho rt _ 04

3 .3VS

1 2

1 7 DAC_HSYNC

1_0 4

HDMIB _CLO CKN

RN7 2 .2K_4 P2R_ 04

1 7 DAC_DDCACL K

C A

C1

4 3

1 7 DAC_DDCADATA

C A

3 .3VS

PTN3360BBS 6-03- 03360- 030 PS8101 6- 03-08101- 032 4. 7K _04

C A

RN2 2 .2K_4 P2 R_0 4 1 2

PTN3 36 0BBS PIN 4 9= GND

R 57

C A

C A

39 3 8 IN_ D1+ IN_ D142 4 1 IN_ D2+ IN_ D245 4 4 IN_ D3+ IN_ D348 4 7 IN_ D4+ IN_ D49 8 SCL SDA 7 HPD 25 OE# 32 1 0 DC C_EN# RT _EN# 3 4 PC0 6 PC1 REXT

49

3.3VS

C A

RD1

BAV99 RECT IFIER

U2

17 HDMIB_ D1BP 17 HDMIB_ D1BN

5 VS

RD2 RD3 BAV99RECT IF IER BAV99 RECT IFIER

FOR I NTEL GRAPHI C 17 HDMIB_ D2BP 17 HDMIB_ D2BN

L 27 1 _0 4

For ESD

5VS

HDMI PORT

GRN BLUE 4 0 _ O P N _ V 0 5 _ p 0 1

1

9

2

24 10 mil

3

11

4 5 6

DDCD ATA

13

HSYNC

14

7

VSYNC

15

8 6 1 C

12

1 2 D D N N G G

DDCL K 4 0 _ R 7 X _ V 0 5 _ p 0 0 0 1 5 9 2 C

4 0 _ O P N _ V 0 5 _ p 0 2 2

4 0 _ O P N _ V 0 5 _ p 0 2 2

3 9 2 C

2 9 2 C

4 0 _ R 7 X _ V 0 5 _ p 0 0 0 1 7 C

Schematic Diagrams

IBEXPEAK- M 1/9 IBEXPEAK - M (HDA,JTAG,SATA)

RT CV CC 1

V D D3

A C

3

C 36 9

2 1

6-22- 32R76-0B4

R 30 4 2 0 K _ 1% _ 0 4

R T C_ X 2

X7 * MC -1 46 _ 3 2 .7 68 K H z

R253

RTC CLEAR

C3 9 9

1 K _ 1 % _ 04

Z o= 5 0 O ? 5 %

2

R 30 5 2 0 K _ 1% _ 0 4

J _ RT C1 1

1

TPM CLEAR

2 8 5 20 5 -0 2 70 1

R299

C4 0 0

JOPEN1 * OP E N_ 1 0 m li -1 MM

1 M _ 04

2 .2 u_ 1 6 V _ X5 R _ 06

R T CV C C

R 29 8

330 K_04

RT C _X 1 RT C _X 2

B13 D1 3

RT C _R S T #

C1 4

S RT C _R T C#

D1 7

S M_ IN T RU DE R #

A16

P CH _ INT V R ME N

A14

BIOS ROM

NC 1

C 2 09 S HO R T 0 .1 u _1 6 V _ Y 5V _0 4

A30

S P I_ V D D R1 6 3 3.3 K _ 1 % _ 0 4 S P I_ W P #

8

VDD

27

SO 3

R1 5 6 3.3 K _ 1 % _ 0 4 S P I_ HO L D# 7

WP#

CE# S CK

H OL D#

S P I_ S I

R 38 1

*0 _ 0 4

2

S P I_ S O

R 38 2

*0 _ 0 4

1

S P I_ CS 0 # R 38 3

*0 _ 0 4

6

S P I_ S CL K R 38 4

*0 _ 0 4

8 51 8 _ S PI_ S I 2 8 8 51 8 _ S PI_ S O

28 28

8 51 8 _ S PI_ S C L K

28

27

HD A _ S D IN0

29

HD A _ S D IN1

28

6-04- 25320-A70 6-04- 02532-470 6-04- 26321-470

ME _W E #

D 18 C

S C D 34 0 A

R 30 3

SPI_* = 1.5"~6.5"

R3 0 7

HD A _ DO C K _ E N #

Flash Descriptor Security Overide

R2 9 0

R 2 87

*2 0 0 _ 06

*2 0 0_ 0 6

* 20 0 _ 0 6

R 93 R282

H3 2 J30

P CH _ JT A G _ T CK _ B U F M 3 J OP E N3 * OP E N _ 10 m il -1 MM

2

3 .3 V S R 29 3

B29

*1 0 m il _ s ho rt_ 0 4

1 K _1 % _ 0 4

3 .3 V

*2 0 K _ 1 %_ 0 4

F30

F32

1

R2 9 5

G3 0

2 7 ,2 9 HD A _ S DO UT

M X 25 L 3 2 05 D M2 I-1 2 G

P1 C3 0

E32

8 51 8 _ S PI_ C S 0 #

4

VSS

HD A _ S P K R

HD A _ S P K R

2 7 ,2 9 HD A _ RS T #

5

SI

D2 9

2 7 ,2 9 HD A _ S Y N C

32Mbit U10

10 K _ 0 4 S E RIR Q *1 K _ 1 % _0 4 H DA _S P K R

P CH _ JT A G _ T MS

K3

P CH _ JT A G _ T DI

K1

P CH _ JT A G _ T DO

J2

P CH _ JT A G _ RS T #

J4

S P I_ S C LK

*1 0 K _ 1 %_ 0 4

*1 0 0_ 1 % _ 04

R2 8 8 *1 0 0_ 1 % _ 04

S P I_ CS 1#

iTPM ENABLE/DISABLE

S P I_ S I

R 26 3

S P I _ S O

* 1K _ 1 % _ 04 S P I_ S I

AV3 AY3

AY1

R 2 86 * 10 0 _ 1 % _0 4

RT C RS T #

H0 H1 H2 H3

/ / / /

LAD LAD LAD LAD

0 1 2 3

F W H 4 / LF RA M E #

S R TC RS T# L DR Q0 # C C L DR Q1 # / GP IO2 3 T P R L S E R IRQ

IN TR UD E R # IN TV RM E N

HD A _ B C LK S A T A 0 RX N S A TA 0R X P S A T A 0 TX N SATA0TXP

HD A _ S Y NC SPKR HD A _ RS T#

S A T A 1 RX N S A TA 1R X P S A T A 1 TX N SATA1TXP

HD A _ S D IN0 HD A _ S D IN1

S A T A 2 RX N S A TA 2R X P S A T A 2 TX N SATA2TXP

A D H I

HD A _ S D IN2 HD A _ S D IN3

HD A _ S D O

HD A _ DO C K _E N# / G P IO 33 HD A _ DO C K _R S T # / G P IO1 3

J T A G_ T CK

A T A S

S A T A 3 RX N S A TA 3R X P S A T A 3 TX N SATA3TXP S A T A 4 RX N S A TA 4R X P S A T A 4 TX N SATA4TXP S A T A 5 RX N S A TA 5R X P S A T A 5 TX N SATA5TXP

J T A G_ T MS J T A G_ T DI

G A T J

J T A G_ T DO J T A G_ R S T #

D 33 B33 C 32 A32

LP LP LP LP

C 34

C_ C_ C_ C_

A A A A

D D D D

0 1 2 3

24 24 24 24

,2 ,2 ,2 ,2

8 8 8 8

LP C_ F R A ME # 2 4 ,2 8

A34 F34 AB9

S E R IRQ

AK7 AK6 AK11 AK9

S A T A R XN 0 S A T A R XP 0 S A T A T X N0 SATATXP0

AH6 AH5 AH9 AH8


S ERI RQ

2 4,28

S A TA R XN 0 S A TA R XP 0 S A T A T XN0 S A T A T XP 0

26 26 26 26

S A TA R XN 1 2 6 S A TA R XP 1 26 S A T A T XN1 2 6 S A T A T XP 1 2 6

SATA HDD SATA ODD

AF11 AF9 AF7 AF6

Sheet 14 of 42 IBEXPEAK - M 1/9

AH3 AH1 AF3 AF1 AD9 AD8 AD6 AD5


AD3 AD1 AB3 AB1 1 .1 V S _ V T T

S A TA I CO MP O S A T A IC OM P I

AF16

S A T A IC OM P

R 89

3 7 . 4 _ 1 % _0 4

R 2 78

* 1 0K _0 4

AF15

3 .3 V S

R 26 4

3 3 _0 4

S P I_ S O _R

AV1

S P I_ C S 0 # S P I_ C S 1 #

S A TA LE D #

S P I_ M OS I

S A TA 0 G P / GP IO2 1

S P I_ M IS O

TPM FU NCTI ON:SPI_SI High Enabl e

I b e x P e ak -M _ Re v 0 _ 9

R 28 5

W W W W

S P I_ C LK S P I_ CS 0#

3 .3 V S R 28 9

F F F F

BA2

NO REBOOT STRAP: HDA_SPKR High Enable

P CH _ JT A G _ TM S P CH _ JT A G _ TD I P CH _ JT A G _ TD O P CH _ JT A G _ RS T #

R2 9 4

RT C X 1 RT C X 2

2

2 7 ,2 9 HD A _ B IT CL K 3 .3 V S

Co- layout X7, X8

U2 0 A

1 0 M_ 0 4

C 39 7 1 5p _ 5 0 V _ NP O _ 04

JOPEN2 * OP E N_ 1 0 m li -1 MM

2 .2 u_ 1 6 V _ X5 R _ 06

4 3

R 3 02 3 4

1

RT C _ V B A T 1

2

1 2

X8

A D1 7 B A T 5 4C S 3

J_RTC1

R T C_ X 1

1 T JS 12 5 DJ 4 A 4 2 0 P _ 32 .7 6 8 K Hz

RT C_ V B A T_ 1 2

1

6-22- 32R76-0B2 6-22- 32R76-0BG

C 40 2 1 5p _ 5 0 V _ NP O _ 04

2 .2 u_1 6 V_ X5R _ 0 6

I P S

S A TA 1 G P / GP IO1 9

T3

S A T A _ L E D#

Y9

O DD _ DE T E C T#

R 1 08

S A T A _ DE T# 1

R 2 74

S A TA _L E D # 2 9

V1

3 .3 V S

10K_4 O DD _ DE T E C T # 26 10K_04

* 4. 7 K _ 0 4 P C H _J T A G _T C K _ B UF

ESATA SATATXP2

C 16 8

* 0 . 01 u _5 0V _X 7R _ 0 4

S A T A T X N2

C 16 5

* 0 . 01 u _5 0V _X 7R _ 0 4

S A T A R XN 2

C 15 5

* 0 . 01 u _5 0V _X 7R _ 0 4

S A T A R XP 2

C 16 4

* 0 . 01 u _5 0V _X 7R _ 0 4

2 3 ,2 5 ,28 ,2 9 ,3 1 ,3 2,3 7 V D D3 21 R TC V C C 2 ,4 ,6 ,7 ,1 5 ,1 6,1 9 ,2 0 ,2 1,3 4 ,3 5 ,3 6 1.1 V S _V TT 3 ,4 ,1 2 ,1 5, 16 ,1 8 ,1 9, 20 ,2 1 ,2 3 ,24 ,2 5 ,2 9 ,30 ,3 1 ,3 3 ,3 4,3 5 3 .3 V 2 ,10 ,1 1 ,1 2 ,1 3,1 5 ,1 6 ,1 7,1 8 ,1 9 ,2 0,2 1 ,2 3 ,2 4, 25 ,2 6 ,2 7 ,28 ,2 9 ,3 0 ,31 ,3 5 ,3 6 3 .3V S

IBEXPEAK- M 1/9 B - 15


Schematic Diagrams

IBEXPEAK - M 2/9 IBEXPEAK - M (PCI-E,SMBUS,CLK)

SMB _C L K SMB _D A T A

RN 1 6 2 .2K _ 4P 2R _ 0 4 3 2 4 1

SML 0 _ DA T A SML 0 _ CL K

RN 1 1 2 .2K _ 4P 2R _ 0 4 3 2 4 1

U 20 B BG 3 0 BJ 3 0 BF29 BH 2 9

23 23 23 23

P CIE _ RX N 2_ N EW _ C A RD P CIE _ RX P2 _ NE W _ CA RD P CI E _ T X N 2_ N EW _ C A RD P CIE _ T X P2 _ NE W _ CA RD 23 23 23 23


P C IE _ R X N3 _ W L A N P C IE _ R X P 3 _W L A N PC IE_ T XN3 _ W L AN PC IE _ T XP 3 _W L AN

2 5 PCI E _ RXN 4_ G LAN 2 5 PCI E_ RXP4 _ GL A N 2 5 P CIE_ T XN 4_ G L AN 2 5 P CIE_ T XP4 _ GL A N

PCI-E x1


Lane Lane Lane Lane Lane Lane Lane Lane 3 .3 V

C 1 71 C 1 81

C 1 42 C 1 23

C 1 91 C 1 02

0 . 1u _1 0V _ X 7R _ 04 0 . 1u _1 0V _ X 7R _ 04

PC IE_ T XN2 _ C PC IE_ T XP2 _ C

0 . 1u _1 0V _ X 7R _ 04 0. 1u _1 0 V_ X7 R_ 0 4


0 . 1u _1 0V _ X 7R _ 04 0 . 1u _1 0V _ X 7R _ 04


0 0 0 0

AU 3 0 AT 3 0 AU 3 2 A V3 2 B A3 B B3 BD 3 B E3

2 2 2 2

BF33 BH 3 3 BG 3 2 BJ 3 2

Usage

1 2 3 4 5 6 7 8

AW3 B A3 BC 3 BD 3

B A3 4 AW34 BC 3 4 BD 3 4

WLAN NEW CARD 3G GLAN / CARD READER X X X X

AT 3 4 AU 3 4 AU 3 6 A V3 6 BG 3 BJ 3 BG 3 BJ 3

3 .3 VS

4 4 6 6

A K4 8 A K4 7 RN 8 1 0 K_ 8P 4 R_ 0 4 1 8 2 7 3 6 4 5

PC IEC L K R Q0 # P P P P

C IE C L KRQ 1 # C IE C L KRQ 0 # C IE C L KRQ 5 # E G_ B _ C LK RQ #

AM 4 3 AM 4 5 PC IEC L K R Q1 #

R 283

* 10 m i l _ sh or t _ 04

CL K _ SL O T2 _ O E#

N4

PC H_ BT _ EN #

H 14

SM B _ CL K

C8

SM B _ DA TA

J14

PC H_ U PE K_ IN IT #

C6

SM L 0_ C L K

G8

SM L 0_ D AT A

S M BC LK

P CH _ BT _E N# 2 3 ,2 9 S M B _C L K 2 SM B _ DA T A 2

PER N4 PER P 4 PET N 4 PET P4 PER N5 PER P 5 PET N 5 PET P5 PER N6 PER P 6 PET N 6 PET P6

18

SML 0 C LK S ML 0 DA TA M 14

L P D _S P I_ INT R #

E10

SM C_ C PU_ T H E R M

G 12

SM D_ C PU_ T H E R M

SM L 1 AL ERT # / G PIO 7 4 SM L 1 CL K / G PIO 5 8 SM L1 D AT A / G PIO 7 5

* E - Control ler I C Link P

PER N8 PER P 8 PET N 8 PET P8

PC IECL K RQ 2 #/ GPI O2 0

SMD _ CP U_ T HE RM SMC _ CP U_ T HE RM

RN 1 0 2 .2K _ 4P 2R _ 0 4 3 2 4 1

S MC _ CPU _ T HE RM 3 ,2 8 S MD _ CPU _ T HE RM 3 ,2 8 PEG _ CL KR E Q #

R 29 1

1 0K _ 04

L AN _C L KR E Q#

R 11 2

1 0K _ 04

CL _ D A T A1 T9 C L_ R S T 1 #

10Kpull -down to GND

G E P

CL KO UT _ PE G_ A_ N C LK OU T _ PEG _A _P C L KO UT _ D MI_ N CL KO U T_ D MI _P

CL KI N_ D MI_ N

CL K O U T_ P C IE 2 N CL K O U T_ P C IE 2 P

23

T11

C LK OU T _ DP _ N / C LK OU T _ BCL K1 _ N CL KO U T_ D P_ P / C L K O UT _ BC L K 1 _P


23

S M L 0 _D A T A

RN 1 3 1 0K _8 P4 R _ 0 4 1 8 2 7 3 6 4 5

T13

CL K O U T_ P C IE 0 N CL K O U T_ P C IE 0 P PC IECL K RQ 0 #/ GPI O7 3

S ML 0 _ CLK

CL _ C L K1

PEG _A _ CL KR Q# / G PIO 4 7 PER N7 PER P 7 PET N 7 PET P7

PCH _ BT _ EN# U SB_ OC # 8 9 LP D_ S PI _I NT R #

U SB_ OC # 8 9

PC H_ U PE K_ IN IT # 1 8

SM L 0 AL ERT # / G PIO 6 0

s u B M S


C L KIN_ D MI _P R E F C L KIN _B CL K_ N F CL KIN _ BC LK _P U B C L K IN _ D O T _9 6 N K CL K IN _ DO T _ 9 6P L C _ S AT A_ N / CK S SC D_ N mCC LL KIN o KIN _S A T A_ P / C KS SC D _P r F


H1

PE G _ CL KR EQ #

100-MHz Gen2 dif fer enti al clock to PCIe Graphics devic e.

AD43 AD45 AN4 AN2

AT1 AT3

C LK _E XP _ N 4 C LK _E XP _ P 4 PC H_ C L K _ DP _ N _ R PC H_ C L K _ DP _ P_ R

R2 6 6 R2 6 7

A W 24 B A2 4

A P3 A P1

C L K _D P _ N 4 C L K _D P _ P 4

100-MHz diff erenti al clock f romPCH to Pr ocesso r. Connect t o PEG_CLK#/PEG_CLKpins of the processo

C LK _ BUF _B CL K_ N 2 C LK _ BUF _B CL K_ P 2

F18 E18

C LK _ BUF _D O T9 6 _N 2 C LK _ BUF _D O T9 6 _P 2

AH13 A H 12

C 3 91

C L K _ S A TA # 2 C LK _ SA T A 2

P41

C LK _ BUF _R E F 1 4 2

J42 PC IECL K RQ 3 #/ GPI O2 5

*1 0 m _il s h o rt _ 0 4 *1 0 m _il s h o rt _ 0 4

C L K _ P C I E _I C H # 2 C L K _ P C I E _I C H 2

REF CL K1 4 IN

A8

2 3 W L AN _ CL K R EQ #

B9

SM B DA TA PER N2 PER P 2 PET N 2 PET P2

PC IECL K RQ 1 #/ GPI O1 8

AH 4 2 AH 4 1

2 3 CL K_ P CIE_ M IN I# 2 3 CL K_ P C IE _ M INI

S MB AL ERT # / G PI O 1 1

U4

AM 4 7 AM 4 8

2 3 C L K_ P C IE _ NE W _ CAR D # 2 3 C L K_ PCI E _ NE W _ CAR D 2 3 N EW C AR D _ C L KRE Q#

P9


C L K _ P C I _ FB

C L K IN_ P CIL O OPB ACK

R2 6 8

1

X6 F S X5 L _2 5 M H z

1 M_ 0 4

18

2 2p _5 0 V _ N P O _ 04

6-22- 25R00-1B4 6-22- 25R00-1B5

2

AM 5 1 AM 5 3

2 5 C LK _P CIE _G L AN # 2 5 CL K_ P CIE_ G L AN LA N_ C LK REQ #


X TA L2 5 _ IN XT A L 2 5 _ OU T

M9 PC IECL K RQ 4 #/ GPI O2 6 AJ 5 0 AJ 5 2

PC IEC LK RQ 5 #


H6 PC IECL K RQ 5 #/ GPI O4 4 A K5 3 A K5 1

PE G _ B_ CL K R Q #

CL K O U T_ P E G_ B _N CL K O U T_ P E G_ B _ P

P1 3 PEG _ B_ CL KR Q# / GP I O5 6

AH51 AH53

XT AL 25 _ IN XT AL 25 _ O UT

AF38

XCL K_ R CO M P

X CL K _ R CO MP

x e l F k c o l C

C 3 87 R 87

9 0 . 9 _ 1 % _ 04

1 .1 V S_ V T T

9 0. 9- O ? % pu l l u p to +VccI O (1.05V, S0rail )

T45 CL K O UT F L EX0 / G PIO 6 4 P43 CL K O UT F L EX1 / G PIO 6 5

CL K O UT F L EX2 / G PIO 6 6

T42

N 50 CL K O UT F L EX3 / G PIO 6 7

Ib e x Pe ak -M _ Re v 0 _ 9

3 .3 VS 2,1 0 ,1 1 ,1 2,1 3 ,14 ,1 6 ,1 7,1 8 ,1 9, 20,2 1 ,2 3 ,2 4 ,2 5, 26 ,2 7 ,2 8 ,2 9 ,3 0,3 1 ,3 5 ,3 6 1 .1 VS _ VT T 2 ,4 ,6 ,7 ,1 4, 16 ,1 9 ,2 0 ,2 1 ,3 4, 35 ,3 6 3 .3 V 3,4 ,1 2 ,1 4 ,1 6,1 8, 19 ,2 0 ,2 1,2 3 ,2 4, 25,2 9 ,3 0 ,3 1 ,3 3,3 4 ,3 5

B - 16 IBEXPEAK - M 2/9

3 .3 V

2 2p _5 0 V _ N P O _ 04

Schematic Diagrams

IBEXPEAK - M 3/9 IBEXPEAK - M (DMI,FDI,GPIO) U2 0 C

1 .1 V S _ V T T

R 26 1

3 3 3 3

D MI_ RX N 0 D MI_ RX N 1 D MI_ RX N 2 D MI_ RX N 3

3 3 3 3

D MI_ RX P 0 D MI_ RX P 1 D MI_ RX P 2 D MI_ RX P 3

3 3 3 3

DM I_ TX N 0 DM I_ TX N 1 DM I_ TX N 2 DM I_ TX N 3

3 3 3 3

DM I_ TX P 0 DM I_ TX P 1 DM I_ TX P 2 DM I_ TX P 3 49 . 9 _ 1 % _0 4

B C 24 B J 22 A W 20 B J 20 B D 24 B G 22 B A 20 B G 20

D MI0 R XP D MI1 R XP D MI2 R XP D MI3 R XP

B E 22 B F 21 B D 20 B E 18

D MI0 T X P D MI1 T X P D MI2 T X P D MI3 T X P

B H 25

I I D M D F

D MI_ Z C OM P

B F 25

DI_ DI_ DI_ DI_ DI_ DI_ DI_ DI_

R R R R R R R R

XN XN XN XN XN XN XN XN

0 1 2 3 4 5 6 7

F D I_ RX P 0 F D I_ RX P 1 F D I_ RX P 2 F D I_ RX P 3 F D I_ RX P 4 F D I_ RX P 5 F D I_ RX P 6 F D I_ RX P 7

D MI0 T X N D MI1 T X N D MI2 T X N D MI3 T X N

B D 22 B H 21 B C 20 B D 18

DMI _C OM P _ R

F F F F F F F F

D MI0 R XN D MI1 R XN D MI2 R XN D MI3 R XN

D MI_ IR CO MP

F D I_IN T F DI_ F S Y NC 0 F DI_ F S Y NC 1 F D I_ LS Y NC 0 F D I_ LS Y NC 1

3.3 V S

R 11 1

1 0 K _ 04

S Y S _ RE S E T #

S Y S _ P W R OK S B _ P W RO K

A UX P P W R OK _ R

10 K _ 0 4

R S MR S T#

S U S _P W R_ A C K

28 S U S _ P W R_ A C K

28

P W R _B T N #

P W R _B T N #

A C _P R E S E N T P M_ B A T L OW #

S W I#

S W I#

t n e m eS US _S T AT # / GP IO6 1 g a n S US C L K / GP IO6 2 a M

M E P W R OK

A 10

L A N _ RS T #

D RA M P W R OK R S MR S T #

M1

P W RB T N #

P7

A CP R E S E NT / G P IO 31

A6

TP23

P M S Y N CH

RI #

S L P _ LA N #

_T _T _T _T _T _T _T _T

XN0 XN1 XN2 XN3 XN4 XN5 XN6 XN7

3 3 3 3 3 3 3 3

F F F F F F F F

DI DI DI DI DI DI DI DI

_T _T _T _T _T _T _T _T

X X X X X X X X

3 3 3 3 3 3 3 3

P0 P1 P2 P3 P4 P5 P6 P7

F D I _I N T 3 F D I _ FS Y N C 0 3

B H1 3

F D I _ FS Y N C 1 3

BJ12

F D I _ LS Y N C 0 3

B G1 4


F D I _ LS Y N C 1 3

J 12

P CIE _W A K E #

Y1

P M_ C LK RUN #

P8

S 4 _S TA T E #

P C IE _W A K E# 2 3,2 5 P M _C L K RU N# 2 4 3 .3 V P CIE _ W A K E #

R12 1

1 K _ 1 %_ 0 4

P M_ S L P _ L A N#

R 12 7

* 10 K _ 0 4

S W I#

R 13 0

1 0K _0 4

S US _ P W R _ A CK

R 28 4

1 0K _0 4

P W R_ B T N #

R 10 9

* 10 K _ 0 4

A C_ P R E S E NT

R 11 5

1 0K _0 4

P M_ B A T L OW #

R 29 6

8 . 2 K _0 4

P M _C L K RU N#

R 27 1

8 . 2 K _0 4

A L L _ S Y S _ P W R GD

R 14 3

1 0K _ 04

S 4 _ S TA TE # 2 4

F3

P12

S L P _M #

DI DI DI DI DI DI DI DI

BF13

m e t s y S

SLP_S3#

F F F F F F F F

BJ14

r S LP _ S5 # / GP IO6 3 e w SLP_S4# o P

B A TL O W # / GP IO 7 2

F 14

B B1 8 BF17 B C1 6 B G1 6 AW16 B D1 4 BB14 B D1 2

E4

S US _ P W R _A CK / G P IO3 0

P5

1 8,2 8 A C _P R E S E N T

28

K5

C 16

RS M RS T# 10 K _ 0 4

C L K RU N# / GP I O3 2

P W RO K

D9

R 30 0

WAKE#

S Y S _ P W R OK

EXT-LAN

4 P M_ DR A M _P W RG D

28

S Y S _ RE S E T #

B 17

P M_ MPW RO K

R 29 7

T6 M6

BA18 B H1 7 B D1 6 BJ16 BA16 BE14 BA14 B C1 2

H7

S US C # 2 8 ,33 S US B #

SUS B #

2 3 , 28 , 3 1

3 .3 V S

K8 N2

BJ10 F6

H_ P M _ S YN C 4 P M_ S L P _ L A N# 2 8, 36 V C OR E _ ON

Ibe x P e a k- M_ Re v 0 _ 9

R1 3 9

*1 0 m li_ s ho rt_ 0 4

P M_ M P W RO K

3 .3 V 3 .3 V 3.3 V

3 .3V U8A 7 4 L V C0 8 P W

4 1

3 3 DD R1 . 5 V _ P W R GD SUSB#

3 3 1.8 V S _ P W RGD

1

3

2

4 1

4

U8 B 74 L V C 08 P W 6

4 1

4 ,3 3,3 4 1 .1 V S _ V T T_ P W R GD 1 .1 V S _ V T T_ E N

9

U 8C 7 4 LV C0 8 P W

4 1

12

4 ,3 6 DE L A Y _ P W RG D

8 10

U8 D 7 4 LV C 0 8P W 11

13

A L L_ S Y S _ P W RG D

5 7

A L L _ S Y S_ P W R GD

*1 0 m li _ s ho rt_ 0 4

S B _P W RO K

R1 4 2

*1 0 m li _ s ho rt_ 0 4

S Y S _ P W R OK

R1 4 5

7

7 7

R1 4 4

10 K _ 0 4

1 2 ,28

34 1 .1 V S _ V T T _E N R 14 1

2K 1_ % _ 0 4

H_ V T T PW R GD

4

C 4 70 ON

1 u _ 6.3 V _ X 5 R_ 0 4

R 13 8 1 K _ 1% _ 0 4

3 .3V S 2 ,10 ,1 1 ,1 2,1 3 ,1 4 ,15 ,1 7,1 8,1 9 ,2 0, 21 ,2 3 ,2 4,2 5,2 6, 27 ,2 8,29 ,3 0 ,3 1,3 5 ,3 6 3 .3V 3 ,4,1 2 ,1 4 ,15 ,1 8 ,1 9,2 0,2 1 ,23 ,2 4 ,2 5,2 9 ,3 0 ,31 ,3 3,3 4,3 5 1 .1V S _V TT 2 ,4 ,6 ,7, 14 ,1 5 ,19 ,2 0 ,2 1,3 4 ,3 5 ,36

IBEXPEAK - M 3/9 B - 17


Schematic Diagrams

IBEXPEAK - M 4/9 IBEXPEAK - M (LVDS,DDI) U20D T48 T47

12 BLON 12 NB_ENAVDD

Y48 12 P_DDC_CLK 12 P_DDC_DATA

3.3VS


R 96 R 97

* 10 K _0 4 * 10 K _0 4

L_CTR L_CLK L_CTRL_DATA

R83

2.3 7K_ 1% _04

LVD S_IBG


12 LVDS-L0N 12 LVDS-L1N 12 LVDS-L2N

12 LVDS-L0P 12 LVDS-L1P 12 LVDS-L2P

DAC_BLUE

13 DAC_GREEN 13 DAC_RED

R10 5

0_ 0 4

DAC_BLUE_R

*33p_50V_NPO _04

R99

0_04

DAC_GREEN_R

*33p_50V_NPO _04

R91

0_04

DAC_RED_R

C174

C166 *33p_50V_NPO _04

R1 04 R9 8 R9 2

S D V L

150_1% _04 150_1% _04 150_1% _04

DAC_BLUE_R DAC_GR EEN_R DAC_RED_R

AA52 AB53 CRT_BLUE AD53 CRT_GREEN CRT_RED V51 V53 CRT_DDC_CLK CRT_DDC_DATA

13 DAC_DD CACLK 13 DAC_DDCADATA

13 13 R8 8

1K_1% _04

Y53 Y51 CRT_HSYNC CRT_VSYNC

DAC_HSYNC DAC_VSYNC DA C_IR EF_R

AD48 AB51 DAC_IREF CRT_IRTN

T R C

BJ48 BG48

T51 SDVO_CT RLCLK T53 SDVO_C TRLDATA

LVD_VREFH LVD_VREFL

AV53 AV51 LVDSA_CLK# LVDSA_CLK BB47 BA52 LVDSA_DATA#0 AY48 LVDSA_DATA#1 AV47 LVDSA_DATA#2 LVDSA_DATA#3 BB48 BA50 LVDSA_DATA0 AY49 LVDSA_DATA1 AV48 LVDSA_DATA2 LVDSA_DATA3

BJ46 BG46

BF45 SDVO_INTN BH45 SDVO_INTP

AB46 V48 L_CTRL_CLK L_CTRL_DATA AP39 AP41 LVD_IBG LVD_VBG

AY51 AT48 LVDSB_DATA0 AU50 LVDSB_DATA1 AT51 LVDSB_DATA2 LVDSB_DATA3

C170

NEAR PCH

SDVO_STALLN SDVO_STALLP

AP48 AP47 LVDSB_CLK# LVDSB_CLK AY53 AT49 LVDSB_DATA#0 AU52 LVDSB_DATA#1 AT53 LVDSB_DATA#2 LVDSB_DATA#3

EMI 13

SDVO_TVCLKI NN SDVO_TVCLK INP

L_BKLTCTL

AB48 Y45 L_DDC_CLK L_DDC_DATA

AT43 AT42

12 LVDS-LCLKN 12 LVDS-LCLKP

L_BKLTEN L_VDD_EN

BG44 DDPB_AUXN BJ44 DDPB_AUXP AU 38 DDPB_HPD

e c a f r e t n I y a l p s i D l a t i g i D

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

B t r o P RN 5 2.2K_4P2R_04 3 2 4 1

BE44 DDPC_AUXN BD44 DDPC_AUXP AV40 DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

y a l p s i D

3.3VS

Y49 DDPC_CT RLCLK AB49 DDPC_C TRLDATA

O V D S

HDM I_CTRLCLK13 HDMI_CTRLDATA 13

PCH_DDPC_HPD HDMIB_D2BN_C HDMIB_D2BP_C HDMIB_D1BN_C HDMIB_D1BP_C HDMIB_D0BN_C HDMIB_D0BP_C HDMIB_CLKBN_C HDMIB_CLKBP_C

C125 C126 C111 C112 C113 C114 C115 C116

0.1u_10V _X7R _04 0.1u_10V _X7R _04 0.1u_10V _X7R _04 0.1u_10V _X7R _04 0.1u_10V _X7R _04 0.1u_10V _X7R _04 0.1u_10V _X7R _04 0.1u_10V _X7R _04

U50 DDPD_CT RLCLK U52 DDPD_C TRLDATA

HDMIB_D2BN 13 HDMIB_D2BP13 HDMIB_D1BN 13 HDMIB_D1BP13 HDMIB_D0BN 13 HDMIB_D0BP13 HDMIB_CLKB N 13 HDMIB_CLKB P 13

C t r o P y a l p s i D

5VS

BC46 DDPD_AUXN BD46 DDPD_AUXP AT 38 DDPD_HPD

G

PCH_DDPC_HPD

S

BJ40 DDPD_0N BG40 DDPD_0P BJ38 DDPD_1N BG38 DDPD_1P BF37 DDPD_2N BH37 DDPD_2P BE36 DDPD_3N BD36 DDPD_3P

Q7 MTN7002ZHS3 D

PORTC_HPD 13 R34 100K_1%_04

D t r o P y a l p s i D

IbexPeak -M_Rev0_9

Connect to GND PC H_ D DP C _HP D R33

*0_04

PO R TC H _P D

No Connect External Graphics (PCH I ntegrated Graphics Disable) External Graphics (PCH Integrated Graphics Disable)

2,10,11,12,13,14,15,16,18,19,20,21,23,24,25,26,27 ,2 8,29,30,31,35,36 3.3VS 2,13,20,21 ,2 6,27,30,31,35,36 5V S


Schematic Diagrams

IBEXPEAK - M 6/9 IBEXPEAK - M (GPIO,VSS_NCTF,RSVD) U20F E DP _ CAR D _D E T #

0213 R 27 2

3 .3 VS

Y3 B MBU SY # / G PIO 0

S_GPIO CHANGE TO EDP_CARD_DET# 1 K _ 1 % _ 04

28

ED P_ C ARD _ D E T #

SM I#

S MI #

C38

DG P U _ HPD _ IN TR #

D37

C LK OU T _ P C IE6 N C L KO UT _ P C IE6 P

T AC H 1 / G PIO 1 T AC H 2 / G PIO 6

R273

28

* 0 _ 04

27

SC I#

S CI #

J32

P CH _ M UT E#

F10

P CH _ MU T E# R 12 6

3. 3V

G PIO 8 * 10 K _0 4 HO S T _ AL ER T #1

R 10 1

3 .3 VS

BIOS RE COVERY DISABLE----NO STUFF (DEFAULT) ENABLE-----STUFF

L AN _ PH Y_ P W R _C T R L / GP IO1 2

R 2 70

* 1 0 K _0 4

AA2

R102

GPI O1 7

F38

* 0 _ 04

B IO S_ RE C

Y7

R 28 1

* 10 K _ 0 4

12

C RB _S V_ DE T

C L K O UT _ BC L K 0 _N / C LK OU T _ PC IE8 N

T AC H 0 / G PIO 17

C L KO UT _ BC L K0 _ P / C L KO UT _ P C IE8 P

S B_ BL O N

SB _B L ON

R280

AB1 2

S PI_ C S # 2

V1 3

S T P_ PC I#

M11

GPI O3 5

1 0 0 K_ 1 % _ 0 4

O I / GP IO2 4 P G

S CL O CK / G P IO 22

G PIO 2 7

R 27 9

* 1K_1% _04

T1 RC IN#

U P C

BD 1 0 T HR M T RIP#

V3

CR B _ SV_ D E T

P3

AW 2 2 T P2

R 26 9

3 C RI T_ T EM P _ R EP#

3. 3V

R 12 8 1 K _0 4

P CH _ MU T E# S P I_ CS #2 D R A MR S T _ C TR L

3 .3 VS

* 1 0 K _0 4

R N2 1 1 0 K_ 8 P 4 R _0 4 1 8 2 7 3 6 4 5 RN 4 1 0 K_ 8 P 4 R _0 4 1 8 2 7 3 6 4 5

S DAT A OU T 0 / G P IO 39

T P4

P CIE CL KR Q 6# / GP IO4 5

T P5

P CIE CL KR Q 7# / GP IO4 6

T P6

1 0 K _0 4

S V_ SET _ U P

AB6

CR IT _ T EMP _R E P #_ R

AA4

P CH _ GPI O5 7

S DAT A OU T 1 / G P IO 48

T P7

S AT A 5 GP / G PIO 4 9

T P8

G P IO 1 7

SC I# SM I# MF G_ M OD E ST P_ PC I#

DG PU _ HP D_ IN TR# CR IT _ T EM P_ RE P# _ R DG PU _ PR SNT # GP IO3 5

KB C_ R ST # 2 8 H _ CPUPW RG D R 25 9

56_04

H _ P E C I 4 , 28

3 .3 VS

R 255

56 _ 0 4

4

1. 1V S_ VT T 4

Calp ell a Desi gn Guide. NOTE: CRB uses a 54.9 O ?% s e ri e s r e s i s t o r a n d 5 6 - O pu l l - u p .

G PIO 5 7

T P9

AY 4 5

AV4 3 AV4 5

F8

AF 1 3 M1 8

TP 10 A4 A4 9 A5 A5 0 A5 2 A5 3 B2 B4 B5 2 B5 3 BE1 BE5 3 BF1 BF 5 3 BH1 BH2 BH 5 2 BH 5 3 BJ 1 BJ 2 BJ 4 BJ 4 9 BJ 5 BJ 5 0 BJ 5 2 BJ 5 3 D1 D2 D53 E1 E5 3

1 .1 V S _ VT T

AY 4 6

H OS T_ AL E RT # 1

RN 9 1 0 K_ 8 P 4 R _0 4 1 8 2 7 3 6 4 5

R 1 14

* 0_ 0 4

F1

* 10 K _ 0 4

* 1 0 m il _s ho rt _ 0 4

T P3

H3 DR A M RS T_C T RL

4 ,9 D RA MR ST _ C TR L

R 256 R 26 0

1 0 K _0 4

BB2 2 S LO A D / G P IO 3 8

* 0 _ 04

BC LK _ CPU _ P 4

R 27 7

Connected to PCH( THRM TRIP#) Rou t i ng guideli nes avail able in BA2 2 T P1

AB1 3

MF G _ M OD E

B C L K _C P U _ N 4

H_ P E CI_ R

BE1 0

V6


R100

R 10 7

PR OC PW RG D

AB7

SV _S E T _ UP

10K_04

28

H _ TH R MTR IP#

S AT A 2 GP / G PIO 3 6 DG P U _ PRS NT #

R 95

PE CI

BG 1 0

S AT A C LK RE Q# / G P IO 3 5 3 .3 VS

3 .3 VS

3. 3V S G A2 0

AM 3

S TP _ PCI # / GP IO3 4

NO STUFF [DETECT]

1 0 K _0 4

U2

AM 1

G PIO 2 8

CRB/SV DETECT

R 27 6 A 2 0G AT E


M EM _ L ED

3 .3 VS

AF 4 8 AF 4 7

T7

H10


C LK OU T _ P C IE7 N C L KO UT _ P C IE7 P

G PIO 1 5 3 .3 VS


K9

BIO S_ R EC

10K_04

C S I M

T AC H 3 / G PIO 7

AH 4 5 AH 4 6

N1 8 AJ 2 4

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_ SS_

N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N

CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT

F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3

D V S R

TP 11 TP 12

AK4 1 AK4 2

TP 13 TP 14

M3 2 N3 2

TP 15 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

M3 0 TP 16 N3 0 TP 17 H1 2

F T C N

TP 18 AA2 3 TP 19 AB4 5 N C _1 AB3 8 N C _2 AB4 2 N C _3 AB4 1 N C _4 T39 N C _5 P6 IN IT 3 _3 V# C1 0 TP 24

I be x Pe a k -M _ Re v 0 _ 9 R 10 3

* 10 K _ 0 4

DG P U _ PR SN T #

LOW: DGPU PRESENT


2 ,4 ,6 ,7 ,1 4 ,1 5 , 1 6 ,2 0 ,2 1, 34 ,3 5 ,3 6 1 .1 VS _V T T 3 ,4 ,1 2 ,1 4 ,1 5 ,1 6 ,1 8, 20 ,2 1 ,2 3 ,2 4 ,2 5 ,2 9 ,3 0 ,3 1, 33 ,3 4 ,3 5 3 .3 V 2 ,1 0 ,1 1 ,1 2 ,1 3, 14 ,1 5 ,1 6 ,1 7 ,1 8 ,2 0 ,2 1, 23 ,2 4 ,2 5 ,2 6 ,2 7 ,2 8 ,2 9 ,3 0, 31 ,3 5 ,3 63 .3 VS

Schematic Diagrams

IBEXPEAK - M 7/9 IBEXPEAK - M (POWER) 3 .3 VS

R90 H C B1 6 0 8K F -1 2 1 T2 5

.

1 .1 V S_ VT T

C 17 6

C 1 51

1 0 u _6 .3 V _X5 R _ 0 6

1u _ 6 .3 V_ X5 R _0 4

AB2 4 AB2 6 AB2 8 AD 2 6 AD 2 8 AF 2 6 AF 2 8 AF 3 0 AF 3 1 AH 2 6 AH 2 8 AH 3 0 AH 3 1 AJ 3 0 AJ 3 1

1 .1 V S_ VT T

1. 1V S_ VC C AP L L_ E XP

CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO

R R R R R R R R R R R R R R R

E[1 E[2 E[3 E[4 E[5 E[6 E[7 E[8 E[9 E[1 E[1 E[1 E[1 E[1 E[1

] ] ] ] ] ] ] ] ] 0 1 2 3 4 5

VC CA DAC [1 ] VC CA DAC [2 ]

] ] ] ] ] ]

T R E C R O C C C V

S D V L

VC C IO[ 24 ]

.

BJ 2 4 C3 7 2 *1 0 u _ 6 .3 V_ X5 R_ 0 6

1 .1 VS_ VT T

C3 7 5

C160

C 1 61

C1 3 6

C141

1 0 u_ 6 .3 V_ X5 R _ 06

1 u _ 6 .3 V_ X5 R_ 0 4

1 u _ 6 .3 V_ X5R _ 0 4

1 u_ 6 .3 V_ X5 R _ 04

1 u _ 6 .3 V_ X 5 R_ 0 4

3 . 3V S AN 3 5

1. 1V S_ VC CAP L L_ F DI

L 28 * HC B1 0 0 5 KF -1 2 1 T 2 0

AT 2 2 BJ 1 8 C3 7 0

VC C APL L EXP

AM 2 3

VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[ VC C IO[

25 ] 26 ] 27 ] 28 ] 29 ] 30 ] 31 ] 32 ] 33 ] 34 ] 35 ] 36 ] 37 ] 38 ] 39 ] 40 ] 41 ] 42 ] 43 ] 44 ] 45 ] 46 ] 47 ] 48 ] 49 ] 50 ] 51 ] 52 ] 53 ]

VSSA _ DAC [2 ]

V CC AL VD S V SSA_ L VD S

VC CT X_ L VD S[1 ] VC CT X_ L VD S[2 ] VC CT X_ L VD S[3 ] VC CT X_ L VD S[4 ]

5 VS

.

C 3 93

C392

AF 5 3

0 .0 1 u _ 50 V _X7 R _ 04

AF 5 1

AH3 8

R 86

AH3 9

C1 3 2

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0

3 .3 V S _ V C C A_ L VD

8 0 _ R 5 X _ V 3 . 6 _ u 2 2

C145

5

C 13 3

1 0 u _ 6 .3 V_ X5R _ 0 6

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0

3 .3 VS

C1 4 6 8 0 _ R 5 X _ V 3 . 6 _ u 2 2

*1 5 m i _l s h o rt_ 0 6

OU T

IN

3 2 SET

R8 1

1 0 u_ 6 .3 V_ X5 R _0 6

AP4 3 AP4 5 AT 4 6 AT 4 5

AD3 5

VC C3 _ 3 [4 ]

1

SHD N #

*2 3 .7 K_ 1 % _ 0 4 4

GN D

* APL 5 6 0 3 -33 B

*1 0 K_ 1 % _ 0 4

C 15 0 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

APL5603-33B 6- 02-56033- 4C0 G9091-330T11UF 6- 02-90913-4C0

1 .8 VS _V CC T X_ LV D

1 .8 VS L 11 HC B1 6 0 8 KF -1 2 1 T 2 5

.

C1 4 0

C1 3 9

C135

C1 3 4

0. 01 u _ 5 0 V_ X7 R_ 0 4

0 .0 1u _ 5 0 V_ X7 R_ 0 4

1 0 u _ 6 .3 V_ X5 R_ 0 6

10 u _ 6 .3 V_ X5 R_ 0 6


AB3 5

VC C3 _ 3 [3 ]

3 .3 VS

C1 5 9 0. 1u _ 1 6 V_ Y 5V _ 04 1 .5 VS _ 1. 8V S

VC C VRM [2 ]

I M D * E I C P

VC C IO[ 54 ] VC C IO[ 55 ]

VC C 3 _3 [1 ]

VC C VR M[1 ] VC C F D IPL L VC C IO[ 1]

Ib e x Pe a k -M _ Re v 0 _ 9

I P S / D N A N I D F

VC C DM I[1 ] VC C DM I[2 ]

AT 2 4

AT 1 6

1 .1 VS _ VT T

AU1 6 C1 2 7 1 u _ 6 .3 V_ X5 R_ 0 4

VC VC VC VC VC VC VC VC VC

C C C C C C C C C

PN PN PN PN PN PN PN PN PN

AND AND AND AND AND AND AND AND AND

[1 [2 [3 [4 [5 [6 [7 [8 [9

] ] ] ] ] ] ] ] ]

AM1 6 AK1 6 AK2 0 AK1 9 AK1 5 AK1 3 AM1 2 AM1 3 AM1 5

V_ NV RAM _ VC CQ

1 .8 VS

R7 5 C1 5 2

R76

* 1 5m i l _ s ho r t _0 6

0. 1u _ 1 6 V_ Y 5V _ 04

3. 3V S VC C VC C VC C VC C

ME3 _ 3 [1 ] ME3 _ 3 [2 ] ME3 _ 3 [3 ] ME3 _ 3 [4 ]

AM8 AM9 AP1 1 AP9

3 .3 V S

*0 _ 0 4

3 .3 V

VC CM E3 .3 V R 79

* 1 5 m il_ s h o rt_ 06

R 82

* 0_ 0 4

C1 3 8 0 .1 u_ 1 6 V_ Y 5 V_ 0 4

1 .1 VS_ VC CD PL L _ F D I R25 7

* 1 5 mi l _ s ho rt _ 0 6 3 ,4 ,1 2 ,1 4 ,1 5 ,1 6, 18 ,1 9 ,2 1 , 2 3 ,2 4 ,2 5 ,2 9, 30 ,3 1 ,3 3 ,3 4 ,3 5 2 3 ,3 1 ,3 6 2 ,1 3 ,1 7 ,2 1 ,2 6, 27 ,3 0 ,3 1 ,3 5 ,3 6 21 7 ,3 3 2 ,1 0 ,1 1 ,1 2, 13 ,1 4 ,1 5 ,1 6 ,1 7 , 1 8 ,1 9, 21 ,2 3 ,2 4 ,2 5 ,2 6 ,2 7 ,2 8, 29 ,3 0 ,3 1 , 3 5 ,3 6 2 ,4 ,6 ,7 ,1 4 ,1 5 , 1 6, 19 ,2 1 ,3 4 ,3 5 ,3 6

1 .5 VS

U5

R8 0

C1 5 6

AB3 4

S O M C V H

*1 0 u _ 6. 3V _ X5 R _ 0 6

1 .1 VS_ V TT

VSSA _ DAC [1 ]

L12 H CB1 6 0 8 KF - 12 1 T 2 5

AE5 0 AE5 2

VC C3 _ 3 [2 ] AN 2 0 AN 2 2 AN 2 3 AN 2 4 AN 2 6 AN 2 8 BJ 2 6 BJ 2 8 AT 2 6 AT 2 8 AU 2 6 AU 2 8 AV2 6 AV2 8 AW26 AW28 BA2 6 BA2 8 BB2 6 BB2 8 BC 2 6 BC 2 8 BD 2 6 BD 2 8 BE2 6 BE2 8 BG 2 6 BG 2 8 BH 2 7 AN 3 0 AN 3 1

1 .1 VS_ VT T

C C C C C C C C C C C C C C C

AK2 4

L29 * BKP1 0 0 5 HS 12 1 _ 0 4

1 . 5 V S _1 . 8 V S

VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC

VCC A_ D A C _ 3. 3V S

POWER

U20G

1 . 8 VS

3 .3 V 1 .5 VS 5 VS 1 .5 VS_ 1 .8 VS 1 .8 VS 3 .3 VS 1 .1 VS_ VT T

1 .5 V S _ 1.8 V S

R 2 58 R 2 54

* 15 m il_ s h o rt_ 0 6 * 0 _0 4



Schematic Diagrams

IBEXPEAK - M 8/9 Volt age Rai l Volta ge

IBEXPEAK - M (POWER) 1 .1 VS_ VCCA _C LK

L3 2 *H C B 1 0 05 K F -1 2 1T 2 0

U2 0 J

52mA

1 .1 VS _ V TT

AP5 1 AP5 3

C3 8 3

C3 8 4

*1 0 u _6 .3 V_ X5 R _0 6

*0 .1 u_ 1 6 V_Y 5 V _0 4

VCC ACL K[2 ]

VCC LAN [1 ]

320mA

AF 2 4

T P_ PCH _ VCC DSW

VCC LAN [2 ]

Y2 0 DCP SUSBY P

1 u_ 6 .3 V_X5 R_ 0 4 C1 7 2 A D3 8 0.1 u _ 16 V_ Y5 V_ 0 4 A D3 9

1849mA


A D4 1

1 .1VS _VT T C3 7 3

C1 4 8

AF 4 3

2 2u _ 6 .3V_ X 5 R_ 0 8

1u _ 6 .3V_ X5 R_ 0 4

AF 4 1

VCC ME[1 ] VCC ME[2 ]

B S U

VCC ME[3 ] VCC ME[4 ] VCC ME[5 ]

AF 4 2 VCC ME[6 ] V3 9


C3 7 4

C1 4 2

V4 1

2 2u _ 6 .3V_ X 5 R_ 0 8

1u _ 6 .3V_ X5 R_ 0 4

V4 2

VCC ME[7 ] VCC ME[8 ] VCC ME[9 ]

Y3 9 Y4 1

VCC ME[1 0 ] VCC ME[1 1 ]

Y4 2 1 .1 VS_ VT T

C 1 77

VCC ME[1 2 ]

0 . 1 u _1 6V _Y 5 V _ 0 4

1.1 VS_ V C CA_ A _ DP L

L3 1 HC B 10 0 5 KF -1 21 T 2 0

VCC RT CEXT C 38 1

2 2 u _6 .3 V _ X5 R _0 8

1 u _6 .3 V_ X5 R _0 4

68mA

* 0 _0 4 1.1 VS _ VC CA_ B_ DPL

*2 20 u _ 4V_ V_ B

DCP RT C

R 2 62

L3 0 HC B 10 0 5 KF -1 21 T 2 0

+ C3 82

V9

1 .5 VS_ 1 .8VS

C 3 86

C 3 85

C 37 8

2 2 u _6 .3 V _ X5 R _0 8

1 u _6 .3 V_ X5 R _0 4

69mA

A U2 4 VCC VRM [3] BB5 1 BB5 3 B D5 1 B D5 3

C 154

1 u_ 6. 3 V _X 5 R _0 4

A H2 3 AJ 3 5 A H3 5

C 131

1 u_ 6. 3 V _X 5 R _0 4

AF 3 4

C 157

1 u_ 6. 3 V _X 5 R _0 4

A H3 4 AF 3 2 V1 2

C 1 75 C 1 73

VCC ADPL L A[1 ] VCC ADPL L A[2 ]

s u o e n a l l e c s i M

0 . 1 u _1 6V _Y 5 V _ 0 4 0 . 1 u _1 6V _Y 5 V _ 0 4

CIO CIO CIO CIO

[5 [6 [7 [8

] ] ] ]

VCC ADPL L B[1 ] VCC ADPL L B[2 ] VCC IO[2 1 ] VCC IO[2 2 ] VCC IO[2 3 ]

V2 4 V2 6 Y2 4 Y2 6

C1 4 7 1 u_ 6 .3 V_X5 R_ 0 4

V2 8 U2 8 U2 6 U2 4 P2 8 P2 6 N2 8 N2 6 M2 8 M2 6 L2 8 L2 6 J2 8 J2 6 H2 8 H2 6 G2 8 G2 6 F28 F26 E2 8 E2 6 C2 8 C2 6 B2 7 A2 8 A2 6

3 .3V

142.6mA C1 8 1 0 .1u _ 1 6V_ Y 5V_ 0 4

3 .3 V_ VCC PUSB R1 0 6

* 1 5 mi l _ sh or t _ 60

1.1/1. 05 < 1 (mA) 5 < 1 (mA )

V5RE F_Sus Vcc3 _3

5 3.3

< 1 (mA ) 0.357

VccA Clk

1.05

0.052

VccA DAC VccA DPLLA

3.3 1.05

0.069 0.068

VccA DPLLB Vcca pllEXP

1.05 1.05

0.069 0.040

VccC ore VccD MI

1.05 1.05

1.432 0.058

VccD MI

1.1

0.061

VccF DIPLL VccI O

1.05 1.05

0.037 3.062

VccL AN VccM E

1.05 1.05

0.320 1.849

VccM E3_3 Vccp NAND

3.3 1.8

0.085 0.156

C1 7 8

VccR TC

3.3

2 (mA)

0 .1u _ 1 6V_ Y 5V_ 0 4

VccS ATAPLL VccS us3_3

1.05 3.3

0.031 0.163

VccS usHDA VccV RM

3.3 1.8/1. 5

0.006 0.196

VccV RM VccA LVDS

1.05 3.3

< 1 (mA ) < 1 (mA )

VccT X_LVDS

1.8

0.059

1.1 VS_ V T T 5 V_PC H_ VC C5 REF SU S D 11

U2 3

S C D 34 0 A

C

V2 3

R 12 3

VCC IO[5 6 ] F24

3.3 V 5V

10 0 _ 1% _ 0 4

C1 8 2

V 5 REF _ SUS

1 u_ 6 .3 V_X 5 R_ 0 4

D 10

VCC 5 REF

d n a k c o l C

VCC SUS 3_ 3 [1 ] VCC SUS 3_ 3 [2 ] VCC SUS 3_ 3 [3 ] VCC SUS 3_ 3 [4 ] VCC SUS 3_ 3 [5 ] VCC SUS 3_ 3 [6 ] VCC SUS 3_ 3 [7 ] VCC SUS 3_ 3 [8 ] VCC SUS 3_ 3 [9 ] VC CSU S3 _3 [1 0 ] VC CSU S3 _3 [1 1 ] VC CSU S3 _3 [1 2 ] VC CSU S3 _3 [1 3 ] VC CSU S3 _3 [1 4 ] VC CSU S3 _3 [1 5 ] VC CSU S3 _3 [1 6 ] VC CSU S3 _3 [1 7 ] VC CSU S3 _3 [1 8 ] VC CSU S3 _3 [1 9 ] VC CSU S3 _3 [2 0 ] VC CSU S3 _3 [2 1 ] VC CSU S3 _3 [2 2 ] VC CSU S3 _3 [2 3 ] VC CSU S3 _3 [2 4 ] VC CSU S3 _3 [2 5 ] VC CSU S3 _3 [2 6 ] VC CSU S3 _3 [2 7 ] VC CSU S3 _3 [2 8 ]

V5 REF

C P L / O I P G / I C P

C

K4 9

R 11 6

S C D 34 0 A 1 0 0 _1 % _0 4

3 .3 VS 5V S

C 1 83 VCC 3_ 3 [8 ] VCC 3_ 3 [9 ]

J3 8

3. 3VS

L3 8

C1 6 9

M3 6

0 .1u _ 1 6V_ Y 5V_ 0 4

VCC 3 _3 [1 0 ] VCC 3 _3 [1 1 ] VCC 3 _3 [1 2 ]

1 u _ 6.3 V _ X 5R _ 04

N3 6 P3 6

3. 3VS

U3 5

C1 8 0

VCC 3 _3 [1 3 ] 0 .1u _ 1 6V_ Y 5V_ 0 4

VCC IO[2 ]

VCCIO 3062mA 1 .1 VS_ VT T

1 .1 V S_ VT T VC VC VC VC

AF 2 3

1 .1VS _VT T C1 4 3

POWER

VCC ACL K[1 ]

S0 Iccm ax Curr ent (A )

V_CP U_IO V5RE F

VCC 3 _3 [1 4 ]

AD1 3

VCC IO[3 ] VCC IO[4 ] VC CSAT AP L L [1 ] VC CSAT AP L L [2 ]

DCP SST

L3 3 *HC B 1 00 5 KF -1 2 1T 2 0

1.1 VS_ V CC AP L L

AK3 AK1

1 .1VS_ VT T C3 8 8

C3 8 9

*1 u _ 6.3 V_ X5R _ 04

*1 0 u_ 6 .3 V_X5 R_ 0 6

VCC SST 1 .1V_ IN T_ VC CSU S

Y2 2

DCP SUS

AH2 2 VC CIO [9 ]

20.4mA 3 .3 V

P1 8

C1 8 8

U1 9

0.1 u _ 16 V_ Y5 V_ 0 4

U2 0

VCC SUS3 _ 3[3 0 ]

U2 2

3 .3 VS

357mA

V1 5

C1 7 9

V1 6

0.1 u _ 16 V_ Y5 V_ 0 4

Y1 6

<1mA 1 .1VS_ VT T C1 4 4

C1 3 7

C1 6 2

1u _ 6 .3V_ X5 R_ 0 4

0 .1u _ 1 6V_ Y 5V_ 0 4

0.1 u _ 16 V_ Y5 V_ 0 4

C1 8 6

C1 8 7

0 .1u _ 1 6V_ Y 5V_ 0 4

0.1 u _ 16 V_ Y5 V_ 0 4

2mA RT CVC C

VCC SUS3 _ 3[3 1 ] VCC SUS3 _ 3[3 2 ]

VCC 3_ 3 [5 ] VCC 3_ 3 [6 ] VCC 3_ 3 [7 ]

AT 1 8

A U1 8


VCC SUS3 _ 3[2 9 ]

A1 2

VCC VRM [4 ]

C P L / O I

A T A S

AD2 0 VCC IO[1 1 ] VCC IO[1 2 ]

P G / I C P

VCC IO[1 3 ] VCC IO[1 4 ] VCC IO[1 5 ] VCC IO[1 6 ]

U P C

VCCM E[1 3 ] VCCM E[1 4 ] VCCM E[1 5 ] VCCM E[1 6 ]

C T R Ib ex Pe a k-M _ Re v 0 _9 VCC RT C

AF 2 2

VC CSU SHDA

1 .1 V S_ VT T

AD1 9 AF 2 0 AF 1 9 AH2 0

AB1 VCC IO[1 7 ] AB2 VCC IO[1 8 ] AB2 V C C I O [ 1 9 ] A D2 VCC IO[2 0 ]

HDA

1 .5 VS_ 1 .8VS

AH1 9

V_C PU_ IO [1] V_C PU_ IO [2]

AT 20

VCC IO[1 0 ]

C1 6 7 1 u_ 6 .3 V_X5 R_ 0 4

9 0 2 2

AA3 4 Y3 4 Y3 5 AA3 5

1 4 RT C V CC 2 ,1 0,1 1 ,1 2,1 3 ,1 4,1 5 ,1 6, 17 ,1 8 , 19 ,2 0 ,23 ,2 4 ,25 ,2 6 ,27 ,2 8 ,29 ,3 0 ,31 ,3 5 ,3 63 . 3 V S 2 0 1 .5 VS_ 1 .8V S 2 ,13 ,1 7 ,20 ,2 6 ,27 ,3 0 ,31 ,3 5 ,3 6 5 VS 4,9 ,1 0 ,11 ,2 3 ,27 ,2 9 ,31 ,3 3 ,3 6 1 .5 V 24 ,3 0 ,31 ,3 3 ,3 4 5 V 3 ,4 ,1 2, 14 ,1 5 ,16 ,1 8 ,19 ,2 0 ,23 ,2 4 ,25 ,2 9 ,30 ,3 1 ,33 ,3 4 ,3 53 .3 V 2 ,4 ,6,7 ,1 4 ,15 ,1 6 ,19 ,2 0 ,34 ,3 5 ,3 6 1 .1 VS_ VT T

1.1 VS_ VT T

1.5 V_ VCC SUSH DA L3 0

R 1 29 C1 8 9

R 13 1

1 u _6 .3 V _ X5 R _0 4

1 .5 V * 1 5 mi l _ sh o r t _0 6 * 0_ 0 4

3 .3V

Schematic Diagrams

IBEXPEAK - M 9/9 IBEXPEAK

U20H AB16 VSS[0] AA19 VSS[1] AA20 VSS[2] AA22 VSS[3] AM1 9 VSS[4] AA24 VSS[5] AA26 VSS[6] AA28 VSS[7] AA30 VSS[8] AA31 VSS[9] AA32 VSS[10] AB11 VSS[11] AB15 VSS[12] AB23 VSS[13] AB30 VSS[14] AB31 VSS[15] AB32 VSS[16] AB39 VSS[17] AB43 VSS[18] AB47 VSS[19] AB5 VSS[20] AB8 VSS[21] AC 2 VSS[22] AC 52 VSS[23] AD 11 VSS[24] AD 12 VSS[25] AD 16 VSS[26] AD 23 VSS[27] AD 30 VSS[28] AD 31 VSS[29] AD 32 VSS[30] AD 34 VSS[31] AU 22 VSS[32] AD 42 VSS[33] AD 46 VSS[34] AD 49 VSS[35] AD 7 VSS[36] AE2 VSS[37] AE4 VSS[38] AF 12 VSS[39] Y13 VSS[40] AH 49 VSS[41] AU 4 VSS[42] AF 35 VSS[43] AP13 VSS[44] AN 34 VSS[45] AF 45 VSS[46] AF 46 VSS[47] AF 49 VSS[48] AF 5 VSS[49] AF 8 VSS[50] AG 2 VSS[51] AG 52 VSS[52] AH 11 VSS[53] AH 15 VSS[54] AH 16 VSS[55] AH 24 VSS[56] AH 32 VSS[57] AV18 VSS[58] AH 43 VSS[59] AH 47 VSS[60] AH 7 VSS[61] AJ 19 VSS[62] AJ 2 VSS[63] AJ 20 VSS[64] AJ 22 VSS[65] AJ 23 VSS[66] AJ 26 VSS[67] AJ 28 VSS[68] AJ 32 VSS[69] AJ 34 VSS[70] AT5 VSS[71] AJ 4 VSS[72] AK12 VSS[73] AM4 1 VSS[74] AN 19 VSS[75] AK26 VSS[76] AK22 VSS[77] AK23 VSS[78] AK28 VSS[79] IbexPeak-M _Rev0_9

-

M

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

(GND)

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL 2 AL 52 AM1 1 BB44 AD 24 AM2 0 AM2 2 AM2 4 AM2 6 AM2 8 BA42 AM3 0 AM3 1 AM3 2 AM3 4 AM3 5 AM3 8 AM3 9 AM4 2 AU 20 AM4 6 AV22 AM4 9 AM7 AA50 BB10 AN 32 AN 50 AN 52 AP12 AP42 AP46 AP49 AP5 AP8 AR 2 AR 52 AT11 BA12 AH 48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW 14 AW 18 AW 2 BF9 AW 32 AW 36 AW 40 AW 52 AY 11 AY 43 AY 47

AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF3 9 H16 H20 H30 H34 H38 H42

U20I VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W5 2 Y1 1 Y1 2 Y1 5 Y1 9 Y2 3 Y2 8 Y3 0 Y3 1 Y3 2 Y3 8 Y4 3 Y4 6 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y4 7 AT12 AM6 AT13 AM5 AK45 AK39 AV14


IbexPeak-M_Rev 0_9



Schematic Diagrams

New Card, Mini PCIE 3 .3 V C 4 59

NEW CARD(Port 8)

BUF _ PL T _R ST #

1 4 2

1 .5 VS 3.3 VS

3 .3 V

* 0 . 1u _1 6V _ Y 5 V _0 4

5

U2 6 *M C7 4V HC1 G 08 D F T1 G

3

3 .3 V

R 3 36

R 33 8

C2 1 0

C 2 24

C2 2 0

* 1 00 K_ 1 %_ 0 4

* 10 0 K_ 1% _ 0 4

*0 .1 u_ 1 0 V_X7 R_ 0 4

* 0 .1u _ 1 0V_ X7 R_ 0 4

*0 .1 u_ 1 0 V_X7 R_ 0 4

U 25 17

J _ NEW 1

AU XIN

PER ST # AUXOU T

2

3 .3 VIN

3 .3 VOU T 1 .5 VOU T

8

N C_ RST #

15

N C_ 3 .3VA UX

3

N C_ 3 .3V

36mils 48mils

N C_ PERST #

11

N C_ 1 .5V

48mils

13 12 14 15 10 9

12 1 .5 VIN


10 9

CPP E# CPUS B# 6 19

4 ,1 8 ,25 ,2 8 BUF _ PL T _R ST # 1 8 U SB_ OC# 2 3 1 6 ,2 8,3 1 3.3 V

Sheet 23 of 42 New Card, Mini PCIE

3 .3 VS

1 .5 VS

1

SUS B#

R 34 7

NC _C PPE# NC _C PUSB# 1 6 ,25 P C I E _ W A K E # 1 5 NEW CAR D_ CL KRE Q#

SY SRST # OC #

17 4 11 16

PCIE_ W AKE# R 1 70

3 .3 VS

1 0 K _0 4

19 18

1 5 CL K_ PCIE _N EW _ CAR D 1 5 CL K_ PCIE_ N EW _ CAR D#

ST BY#

PER ST# + 3.3 VAU X + 3.3 V + 3.3 V + 1.5 V + 1.5 V CPP E# CPU SB# W AKE# CL KR EQ# REF CL K+ REF CL K-

1 0 K _0 4 4 5 13 14 16

3 .3V

NC NC NC NC NC

18 20

R CL KEN SH DN #

N C_ RC L KEN R 33 9 N C_ SHD N# R 35 5

* 10 K _ 0 4 * 10 K _ 0 4

3 .3V

15 15 15 15

7 21

G ND G ND

Port 3

* W 8 3L 3 5 1Y G

22 21 25 24

P CIE_ RXP2 _ NEW _ CA RD P CIE_ RXN2 _ NEW _C ARD PCIE_ T XP2_ N EW _ CAR D PCIE_ T XN2 _ NEW _ CAR D

3 2

1 8 U SB_ PP3 1 8 U SB_ PN3

PET p 0 PET n 0 PER p0 PER n0

R ESER VED R ESER VED

USB _D + USB _D -

6- 02-83351-9Q0

C4 4 3

C4 6 4

C 45 1

*0 .1 u _1 6 V_ Y5 V _ 04

*0 .1 u_ 1 6 V_ Y5 V _ 04

*0 .1 u _1 6 V_ Y5 V_ 0 4

8 7

1 5 SM L0 _ DAT A 1 5 SM L0 _ CL K

ENE P2231 pin3,4,15,22

SMB _D AT A SMB _C LK

has internally * 13 0 8 01 -0 2

pul led hig h (170K ohm)

MINI CARD (WLAN,Port 5) Layout Show "WLAN(Wimax, 802.11N)" Note

20 mil PC IE_ W AKE#

3 .3V S

R 31 2

1 0K _0 4

1 3 5 7 11 13 9 15

1 5 W L AN _C L KREQ # 1 5 C L K_PC IE_ MIN I# 1 5 C L K_P CIE_ MIN I

J _ MIN I1 W AKE# CO EX1 CO EX2

3 .3VA UX_0 1 .5 V_0 UIM _ PW R U IM_ DAT A U IM_ CL K U IM_ RESET U IM_ VPP

CL KR EQ# REF CL KREF CL K+ GN D0 GN D1

G ND5

2 6 8 10 12 14 16

3 .3 V W LAN 1 .5V

20 mil

1.5 V R3 2 5

R 39 7

PC H_ BT _ EN#

0_ 0 4

* 1 5 mil _ s h o rt _ 06

C4 3 8 *0 .1 u _1 6 V_ Y5 V _ 04

4

KEY 21 27 29 35 23 25 31 33

28 W L AN_ DE T# 15 PC IE_ RXN3 _ W L AN 1 5 PCIE _R XP 3_ WL AN 1 5 PCIE _T XN3 _ W L AN 1 5 PCIE_ T XP 3_ W L AN

28 2 8 ,29

3 IN1 BT_ EN

R 36 2

* 0 _ 0 4

R 35 9

0 _ 04

28

8 0 DET # 3.3 V M INI_ CL K1 M INI_ DAT A1 M INI_ RST # 1

VD D3

R 31 5

* 0_ 0 4

17 19 37 39 41 43 45 47 49 51

GN D2 GN D3 GN D4 GN D1 1 PET n 0 PET p 0 PER n0 PER p0 Re s e rv e d0 Re s e rv e d1 GN D1 2 3 .3V AUX_ 3 3 .3V AUX_ 4 GN D1 3 Re s e rv e d2 Re s e rv e d3 Re s e rv e d4 Re s e rv e d5

G ND6 G ND7 G ND8 G ND9 G ND 10 W _ DISA BLE# PER SET# SMB_ CL K SMB_ DAT A U SB_ DUSB_ D+ 3 .3VA UX_1 1 .5 V_1 1 .5 V_2 3 .3VA UX_2 LE D_ W W AN# L ED_ W L AN# LE D_ W PAN#

18 26 34 40 50 20 22 30 32 36 38 24 28 48 52 42 44 46

R 32 6 * 10 K_ 0 4

3. 3VS

W L AN _EN 2 8,29

BU F _P LT _ RST # BT _ DET #

20 mil

3 .3 VAUX_ 1

40 mil 20 mil

2 8, 2 9 U SB_P N2 1 8 U SB_P P2 1 8

R 32 9

* 15 m li_ s ho rt_ 0 6

W LA N1 .5 V 3 .3V W L AN_ L ED# 2 8 ,29

8 8 91 0 -5 20 4 M-0 1 15 ,2 9 PCH _BT _ EN#

R 39 6

0 _ 04

4 ,9,1 0 ,1 1,2 1 , 2 7,2 9 ,3 1, 33 ,3 6 1.5 V 2 0, 31 ,3 6 1.5 VS 3 ,4 ,12 ,1 4 ,15 , 1 6 ,18 ,1 9 ,20 ,2 1 ,2 4,2 5 , 2 9,3 0 ,3 1,3 3 ,3 4,3 5 3 .3 V 2,1 0 ,1 1,1 2 ,1 3, 14 ,1 5 , 16 ,1 7 ,18 ,1 9 ,20 ,2 1 ,24 ,2 5 , 2 6,2 7 ,2 8,2 9 ,3 0,3 1 ,3 5, 3 63 . 3 V S 1 4 ,2 5,2 8 ,2 9,3 1 ,3 2,3 7 V D D 3

B - 24 New Card, Mini PCIE

3 .3 V

8 0 CLK

28

Port 2

GN D GN D GN D GN D G ND1 G ND2

5 6

1 20 23 26 G ND 1 G ND 2

Schematic Diagrams

3G, CCD, TPM MINI CARD 3G(Port 6)

3G POWER

Layout Show " 3.5G(HSDPA)" Note

3 G_ 3.3 V

G5243A 6- 02- 05243- 9C0 APL3512A 6-02- 03512-9C0

3 .3V

3A 120mils J _ 3G 1 1 3 5

W AKE# CO EX1 CO EX2

7 11 13 9 15

3.3 VAU X_ 0 1. 5V_ 0 UIM_ PW R UIM _D AT A UIM _ CL K UIM _R ESET UIM _ VPP

CL KR EQ# REF CL KREF CL K+ GN D0 GN D1

60mils

2 6 8 10 12 14 16

U 12 5

3 G_ 3 .3V

3A 120mils

1 VIN

VOU T 2 G ND

U IM_ PW R U IM_ DAT A U IM_ CL K U IM_ RST U IM_ VPP

C1 90

0.1 u _ 16 V_ Y5 V_ 04

R 1 76

+ C2 34

C1 93 0.1 u _1 6 V_ Y5 V_ 04

* 1 5m li _ s ho rt_ 0 6

4

22 0 u_ 4 V_ V_B

1 0u _ 6.3 V_ X 5R _0 6

3 SS

C2 4 1

EN A P L3 5 12 A

R1 7 3

C2 3 1

*1 0 0K _1 % _0 4

0 .1u _ 1 6V_ Y 5V_ 0 4

C2 30

4

*0 .01 u _ 50 V_ X7 R _0 4

GN D5

KEY 21 27 29

28

GN D2 GN D3 GN D4

35 23 25 31 33

3 G_ D ET#

3 G_ 3 .3V

C2 13

C4 14

0.1 u _ 16 V_ Y5 V_ 04

10 u _6 .3 V_ X5 R _0 6

GN D6 GN D7 GN D8 GN D9 GN D1 0

GN D1 1 PET n 0 PET p 0 PER n0 PER p0

17 19 37 39 41 43 45 47 49 51

Re s e rv ed 0 Re s e rv ed 1 GN D1 2 3 .3V AUX_3 3 .3V AUX_4 GN D1 3 Re s e rv ed 2 Re s e rv ed 3 Re s e rv ed 4 Re s e rv ed 5 8 8 91 0 -5 20 4 M-0 1

W _ DISABL E# PERSET # SM B_ CL K SM B_D AT A US B_D U SB_ D+ 3.3 VAU X_ 1 1. 5V_ 1 1. 5V_ 2 3.3 VAU X_ 2 L ED _W W AN# L ED_ W L AN# L ED _W P AN#

18 26 34 40 50

2 8 3 G _PO W ER

20 22 30 32 36 38 24 28 48 52 42 44 46

3 G _E N

R 1 60

* 1 5 mi l _ sh o rt _ 06

From SB GPIO Pin default HI Power P lane: Suspend

28 3

L19 *W C M2 0 12 F 2 S-1 61 T 0 3-s h o rt 4

2

1

S3: Defined USB_ PN9 1 8 U S B _P P 9

1 8

3 G_ 3 .3V

3 G_ 3 .3 V

R 14 0 C4 1 5

Sheet 24 of 42 3G, CCD, TPM

SIM CONN

60mils

4 .7 K _ 0 4

+C 19 8

*0 .1 u _1 6 V_Y 5 V_0 4 2 2 0u _ 4 V_V_ B

J_ SIM 1 R 32 2 * 10 m il _ s ho rt_ 0 4 U IM_ CL K

C3 C2 C1

U IM_ RST U IM_ PW R C 42 4

LOCK (TOP VIEW) U IM_ CL K U I M _R S T U IM_ PW R

R 31 0 * 10 m il _ s ho rt_ 0 4

U IM_ DAT A U IM_ VPP U IM_ GN D

C7 C6 C5

U IM_ DAT A U IM_ VPP

OPEN

2 2 p_ 5 0 V_N PO_ 0 4

C1 77 0 6 61 -1 SIML OC K

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0 *

LPC reset timing:

[PVT-1]

LPCPD# inactive to LRST# in active 3 2~96us

U14 L L L L

PC_ PC_ PC_ PC_

AD AD AD AD

26 23 20 17

0 1 2 3

L L L L

AD0 AD1 AD2 AD3

21 18 PC LK _T PM

L CL K 22 16 27 15

1 4 ,28 L PC_ F R AME# 18 PL T _R ST # 1 4 ,28 S E R I R Q 16 PM _C L KRUN # R 19 9

1 6 S4 _ ST ATE#

C 40 3

C4 0 5

2 2 p _5 0 V_N PO_ 0 4

2 2 p _5 0 V_N PO_ 0 4

22 p _ 50V_ NP O _0 4

3 .3 VS

TPM 1.2

Asserted before enteringS3

1 4,2 8 1 4,2 8 1 4,2 8 1 4,2 8

C 4 04

* 0_ 0 4 T PM_ L PCPD # T PM_ BAD D TPM _ PP

V DD1 V DD2 V DD3

10 19 24

7 7 2 C

TPM

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0 *

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0 *

CCD 5V L1

0 8 2 C

6 5 2 C

C3

3 .3 VS

L PCPD # 9

G PIO G PIO2

6 2 13

14

T EST I

C5

C8

C9

1 00 K_ 1 %_ 0 4

1 u _6 .3 V_X5 R_ 0 4

0 .1u _ 1 6V_ Y 5V_ 0 4

1 u_ 6 .3 V_X5 R_ 0 4

1

5

R8

XT AL O

8

MJ_CCD1

R9

1 00 K_ 1% _ 0 4

XTAL I

N C_ 1 N C_ 2 N C_ 3

G

C 25 5

T EST BI/BADD 7

48 mil

0 .1 u _1 6 V_ Y5 V _0 4

VSB

28

TPM 30 0 1 1 TPM 30 0 2 3 TPM 30 0 3 12

HI: A CCESS LOW: NORMAL( Internal PD) HI: 4E/ 4FH TPM _BADD LOW: 2E/ 2F H

C2

1 u _6 .3 V_ X5 R_ 0 4

* 0.1 u _1 6 V_ Y5 V_ 04

J _C CD1

T PM 30 0 4 T PM 30 0 5

R7

G ND _1 G ND _2 G ND _3 G ND _4

4 11 18 25

3 3 0K _ 0 4 D

XTALI

PP

TPM_PP

* 15 m li _ s ho rt_ 0 6

*1 u _ 6.3 V_ X5R _0 4

5 L F RAM E# L RESE T# SER IRQ C LKR UN #

5 V_ CC D

Q4 MT P3 4 03 N3 S D

C 27 2

XTALO

4 3

X4 * MC - 14 6 _ 32.7 68 KH z

1 2

6- 22-32R76- 0B4

C2 4 4

28

CC D_ EN

CCD _ EN

Q5 MT N7 0 02 Z H S3

G

18 USB_ PN5 18 USB _PP5 2 8 C CD _D ET #

CCD _D ET #

S

1 2 3 4 5 8 52 0 5-0 5 0 01

From H8 default HI

C 2 50

*1 8p _ 5 0V_ NPO _ 04

* 1 8p _ 50 V_ NPO _ 04

* SL B96 3 5 TT XTAL O PC LK_ T PM

R 18 6

* 33 _0 4

C 266

* 10p _50 V_ NPO _06

Co-l ayout X4, X9

XTAL I

3 ,4 ,12 ,1 4 ,15 ,1 6 , 18 ,1 9,2 0 ,2 1,2 3 ,2 5,2 9 ,3 0,3 1 , 3 3,3 4 ,35 3 .3 V 2 ,1 0,1 1 ,12 ,1 3 ,14 ,1 5 , 16 ,1 7 ,18 ,1 9 ,20 ,2 1,2 3 ,2 5,2 6 ,2 7,2 8 , 2 9,3 0 ,3 1,3 5 ,36 3 . 3 V S 2 1,3 0 ,3 1,3 3 ,34 5 V

3 .3V S T PM _L PC PD#

R 20 0

* 10 K _0 4

T PM _PP

R 19 0

* 10 K _0 4

T PM _BAD D

R18 8

* 1 0 K _ 1% _ 0 4

R18 5

* 1 0 K _ 1% _ 0 4

1 2

4 3

X9 *1 T J S12 5 DJ 4 A4 20 P_ 32 .7 6 8KH z

6-22- 32R76-0B2 6-22- 32R76-0BG

3G, CCD, TPM B - 25


Schematic Diagrams

Card Reader/LAN JMB251C SD _C L K

JMC251C

C2 7 0

close to PIN33 SD_ CL K

R 18 7

2 2 _ 1 %_ 0 4

(>20mil)

L3 5

R EGL X R 31 4

* 4 . 7K _0 4 SD _ CD # SD XC_ POW ER

VC C_ C ARD

1 0K _0 4 * 10 K _0 4

S D_ W P M S_ INS#

0 .1u _ 1 6 V_Y 5 V_ 04

C276 2 .2 u _ 6.3 V_ X5 R_ 0 6

0 1 D D 1 1 E L E L _ _ O I N N N D A A O S M L L I

Card Reader Pull High/Low Resistors


DVD D

Sheet 25 of 42 Card Reader/LAN JMB251C

DVD D

M DIO 1 0 M DIO 9 M DIO 8 A VDD 12 _ 5 2

R 35 1

* 15 m il_ s ho rt_ 0 6

R 35 0

2 6 L AN_ M DIP0 2 6 L AN_ M DIN 0 * 15 m il_ s ho rt_ 0 6 26 26

L AN_ M DIP1 L AN_ M DIN 1

3 .3 V_ LAN 2 6 L AN_ M DIP2 2 6 L AN_ M DIN 2 * 15 m il_ s ho rt_ 0 6

R 34 9

26 26

. D V D D

L AN_ M DIP3 L AN_ M DIN 3

49 50 51 52 53 54 A VDD 12 _ 5 5 5 5 56 57 58 59 L AN _ MD IP2 6 0 L AN _ MD IN2 6 1 A VDD 12 _ 6 2 6 2 L AN _ MD IP3 6 3 L AN _ MD IN3 6 4

R E N W A O S 3 2 1 X L 0 B D D D D D L _ P _ _ _ _ D G V _ D _ V E 3 C D D D D . X 3 S S S S S D R D S

For JMC251/261 only

MD IO1 0 MD IO9 MD IO8 VDD VIP_ 1 VIN _1 AVD D1 2 VIP_ 2 VIN _2 GN D AVD D3 3 VIP_ 3 VIN _3 AVD D1 2 VIP_ 4 VIN _4

(LQFP 64)

V DD3

C 45 7

R 20 2

R 1 77 * 1 5m il_s h o rt _ 06

10 u _ 6. 3V_ X5 R_ 0 6

0 .1 u_ 1 6 V_ Y5 V _ 0 4

Pi n# 33

VDD RE G VC C3 V PW RC R T EST MP D W AKE N LA N_ L ED2 CR _ LE D R ST N CPPE N GN D V DDI O MD IO6 MD IO1 2 MD IO1 4 N C R_ CD 0 N

R 3 54 * 0_ 0 6

3 .3 VS VC C_ CAR D

C4 4 4 0.1 u _ 16 V_ Y 5V _0 4

Pi n#7

Pin#13

AVDD 1 2_ 5 2

AVD D1 2 _ 55

R

C 28 6

D D V D

5

R 3 48 * 1 5m il _s h o rt_ 06

U27 O UT

IN

S HD N#

* 2 K_ 1% _ 0 4

4

(>20mil) R 1 98

SET

G ND

C2 8 7 0.1 u _ 16 V_ Y 5V _0 4

Pin#55

3.3 VS VD D3

4 0 _ R 5 X _ V 3 . 6 _ u 1

2

* 1 0K _1 % _ 04

M PD

0 .1 u_ 1 6 V_ Y5 V_ 0 4

Pi n#62

VD D3

3 .3 V_L AN

C 42 5

0 .1 u _1 6 V_ Y5 V _ 0 4

1 0 u _6 .3 V_ X5R _ 06

Pi n# 32

0. 1u _ 1 6V _Y 5 V_0 4

Pin#31

C4 6 3 *0 .1 u_ 1 6 V_ Y5 V_ 0 4

Pin#43

ISON

ISON

R 3 44

1 0 K _1 %_ 04

R 1 92

* 1 0 0K _ 1% _0 4

PC IE_ W AKE#

1 6, 2 3 PC IE_ W AKE#

8 6 2 0 3 _ R t r o h s D _ D l i

A

V m D 5 1 *

C

* 1M _0 4 X5

PC IE_ RXP4 _ GL AN 15 P CIE_ R XN 4 _G L AN 1 5 SD _C D# SD _D 2 SD _D 3 SD _BS

Card Reader Power VC C_ CA RD

VC C_ C ARD

R 31 6 7 5 _1 % _ 0 4

SD _C L K

VC C_ C ARD

LAN XIN

C4 1 3 3 .3 V_ LA N

0 .1u _ 1 6V _Y 5 V_ 04

1

2 2p _ 5 0 V_N PO _0 4

C 42 2

0 .1 u _ 16 V_ Y5 V_ 0 4

C2 6 1

Pin#2

22 p _ 5 0V_ N PO_ 0 4

1 0u _ 6 .3 V_X5 R_ 0 6

Pi n# 2

6-22-25R00-1B4 6-22-25R00-1B5 *1 0 u _ 6.3 V_ X5 R_ 0 6

0.1 u _ 16 V_ Y 5V _0 4

0 .1 u_ 1 6 V_ Y5 V_ 0 4

0 .1 u_ 1 6 V_ Y5 V_ 0 4

Pi n#59 Reserv ed

Pin#59

Pi n#2

Pi n#21

Placeallcapacitors closedto chip. The subscriptin each CAP incicates the pin numberofJMC251/JMC261that s hould be closedto.

B - 26 Card Reader/LAN JMB251C

LA N _ P C I E _W A K E # 2 8

VC C_ CAR D

SD _D 0 SD _D 1 SD _W P

SD _C L K SD _D 3 MS _IN S# SD _D 2 SD _D 0 SD _D 1 SD _BS

P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21

J _C ARD -RE V1 CD_SD DAT 2 _S D CD/ DAT 3 _S D CMD _ SD VSS_ SD VDD _S D CL K_ SD VSS_ SD DAT 0 _S D DAT 1 _S D W P_ SD VSS_ MS VCC _M S SCL K_ MS DAT 3 _M S INS_ MS DAT 2 _M S SDIO /DA T 0 _ MS DAT 1 _M S BS_ MS VSS_ MS MD R0 1 9 -C0 -1 04 2

3 .3 V_L AN

C2 4 0

LA N _ PCIE _W A KE#

4 IN 1 SOCKET SD/MMC/MS/MS Pro 0 . 1u _ 1 0V _ X 7R _ 04 0 . 1u _ 1 0V _ X 7R _ 04

C 26 8

C 46 1

1 0K _ 0 4

SCD 3 4 0

0 .1u _ 1 6V _Y 5 V_ 04

F SX5L _ 2 5 MH z C2 4 8

C4 6 0

3.3 V * 0_ 0 6

3. 3V_ L AN

R31 9

*1 0 u _6 .3 V_ X5 R_ 0 6

C 28 5

3 .3V _L AN

VDD 3 28

For JMC251 C

Pi n#43

0 . 1u _1 6V _ Y 5V _ 04

C2 3 7

Pin#31

Pi n#7 Reserved

R 18 4

0 .1 u_ 1 6 V_ Y5 V_ 0 4

* 4. 7 K _ 04

C 2 39

R 35 7

L ANXO UT

C 28 8

R32 1

(>20mil) C 2 33

PCIe Differential Pairs = 100 Ohm

P CIE_ T XN4 _GL AN 15 PC IE_ TXP4 _GL AN 1 5 C L K_ PCIE_ G LA N 1 5 C LK_ PC IE_ GL AN # 15

2

1 00 K _1 %_ 04

3.3 VS

(>20mil) C4 5 3

Pi n#3 2

C4 4 7

3 .3 V_L AN

R 3 20

G9141 APL5603- 12B(no R201,R198)

BUF _PL T _ RST # 4 ,1 8,2 3 ,2 8

A VDD 12 _7

C 28 9

R 3 58 * 0 _0 6

C 4 69

3

C4 2 0 0 .1 u_ 1 6 V_ Y5 V_ 0 4

Pi n#52

1 2 3

A0 A1 A2

1

*G 91 4 1

1 0u _ 6 .3 V_X5 R_ 0 6

C 2 35 C 2 36

AVDD 1 2_ 6 2

G ND

3 .3 V

7

WP

D1 9 7 3 3

3 .3 V_ LAN

0 .1 u_ 1 6 V_ Y5 V_ 0 4

SC L SD A

4

R 2 01

L AN_ PC IE_ W AKE# 2 8

LA N_ SCL LA N_ SDA

VC C

6 5

Pi n#33

DV DD

MPD

SD_ W P M DIO 12 MD IO1 4 SD_ C D#

U2 1 8

* AT 24 C 02 BN

(>20mil)

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 1 1 1 1 1 1 1 6 0 3 _ 1 T 7 r t _ _ # 2 o 2 3 S N U I O 1 h 1 7 s X D 1 N X D _ O O I l N N D i D I I _ D A A V m V D S L L A 5 A M M M 1 *

AVD D1 2 _ 13

C 44 9

* 4 . 7K _0 4

L AN _SD A

1 2 K_ 1% _ 0 4 AVDD 1 2_ 7

L AN _SC L R 31 8

3 .3 V

1 3 2 2 3 1 3 1 1 D 7 T D T D D C N P O O D N D N P D I I _ X U K K D P V N L X V D R E I O L V X N X X D R A X X C C A R R G T T A M M C

J MC 25 1 _ C

* 4 . 7K _0 4

VDD 3

1 0 1 N D 5 4 3 2 1 0 2 D 1 O O X D D I O O O 1 N L O O N I O I O I O I E E D D I I I B S G G L L I D D D D D D D F D _ _ D V V M M M M M M M N N A A L L

JMC251 C

R 31 7

(>20mil) C4 5 0

7 5 4 3 2 1 0 8 6 4 3 8 4 4 6 4 4 4 4 4 4 3 9 3 3 7 3 3 5 3 3 4

U 13

DVD D

D VDD

SW F 2 5 20 C F -4 R7 M-M C2 7 1

R 31 1 R 31 3

3 .3 V_ L AN

Switching R egulator

near Pi n# 41

*1 0 p _5 0 V_ NPO _ 06

3 .3 VS

V CC _C ARD

C4 2 3

C4 1 0

C 2 38

C4 1 9

0 .1u _ 1 6V _Y 5 V_ 04

4. 7u _ 6 .3V _X5 R_ 0 6

0 .1 u _1 6 V_ Y5 V_ 0 4

0 .1u _ 1 6V _Y 5 V_ 04

Near Cardreader CONN 1 4,2 3 ,2 8 ,29 ,3 1 ,3 2, 37 V D D 3 26 D VD D 2, 10 ,1 1 ,1 2,1 3 ,1 4 ,15 ,1 6 ,1 7,1 8 ,1 9 ,20 ,2 1 ,2 3, 24 ,2 6 ,2 7,2 8 ,2 9 ,30 ,3 1 ,3 5,3 6 3 .3 VS 3,4 ,1 2 ,1 4,1 5 ,1 6 ,18 ,1 9 ,2 0, 21 ,2 3 ,2 4,2 9 ,3 0 ,31 ,3 3 , 3 4,3 5 3 .3 V

GN D GN D

P2 2 P2 3

clevo+6-71-w24h0-d02a.unlocked.pdf

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