CMOS Digital Integrated Circuits
Ch6 CMOS Inverters: Switching Characteristics and Interconnect Effects I
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6.1 Introduction CMOS Inverters Inverters – Dynamic Analysis Analysis and and Design Goals
• Understand the detail dynamic analysis of the CMOS inverter. • Understand one set of design from CMOS equations. • Understand the basic CMOS design process using the CMOS static and CMOS design form dynamic equations.
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CMOS Dynamic Analysis: Capacitance Model for CMOS V DD
C gs,p
C sb,p
C db,p
V in
V out
C gd,p C gd,n
FO C db,n
C gs,n
3
C sb,n
C int
C g
Fig. 6.1 Cascoded CMOS Inverter stages
CMOS Dynamic Analysis: Capacitance Model for CMOS • The aggregate capacitance driven by the output node of a CMOS inverter is in detail working from left to right, • C load = C input + C int + C g in which C input = C gd,n + C gd,p + C db,n + C db,p (intrinsic component) C int = interconnect capacitance
(extrinsic component)
C g = thin-oxide capacitance over the gate area
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CMOS Dynamic Analysis: Delay-Time Definitions V in
idealized step input
V OH
V 50% = V OL+(V OH -V OL) / 2 = (V OH +V OL) / 2 .
V 50% V OL V out
t τ PHL
τ PLH
V OH
PHL
= t 1-t 0
PLH
= t 3-t 2
V 50% P
V OL V out
t 0
t 1 τ fall
+
PHL
)/2
PLH
Fig. 6.3
t
t 2 t 3
V 10% = V OL+0.1(V OH -V OL)
τ rise
V 90%
=(
V 90% = V OL+0.9(V OH -V OL)
V 10% t A 6
t B
t C
t D
t
fall
= t B-t A
rise
= t C -t D
Fig. 6.4
6.3 Calculation of Delay Times CMOS Dynamic Analysis Delay-Time Calculation (First Order Estimates)
• The simplest approach of calculating the propagation delay is based on estimating the average capacitance current during charge down/up. τ PHL =
τ PLH =
where
I avg, HL =
1 2
C load (V OH −V 50%) I avg, HL C load (V 50% −V OL) I avg, LH
[iC (V in =V OH ,V out =V OH ) + iC (V in =V OH ,V out =V 50%)]
1
I avg, LH = [iC (V in =V OL,V out =V 50%) + iC (V in =V OL,V out =V OL)]
2
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CMOS Dynamic Analysis Delay-Time Calculation ( More Accurate)(1/4)
• The propagation delay can be found more accurately by solving the state equation of the output node. The current flowing through C load is a function V out as
dV out = iC = i D, p − i D,n C out dt C out
i D,p V in
iC V out
i D,n
dV out = iC = − i D ,n dt
• τ PHL: PMOS is off. The equivalent circuit during high-tolow output transition is V in
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i D,n nMOS
V out
C load
Fig. 6.5
CMOS Dynamic Analysis: Delay-Time Calculation (2/4) The nMOS operates in two regions, saturation and linear, during the interval of τ PHL . τ PHL
V out V OH =V DD V OH -V T,n V 50%
nMOS in saturation nMOS in linear region t
t 0 t 1’ t 1
Fig. 6.6
• Saturation Region i D,n=(k n /2)(V in-V T,n )2=(k n /2)(V OH -V T,n )2
» Plug i D,n into C load dV out /dt=-i D,n , and integrate both sides, we get t 1’ -t 0 = 2C load V T,n /[k n(V OH -V T,n )2 ]
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CMOS Dynamic Analysis: Delay-Time Calculation (3/4) • Linear Region i D,n= (k n /2)[2(V in - V T,n )V out - V out 2] = (k n /2)[2(V OH - V T,n )V out - V out 2]
» Plug i D,n into C load dV out /dt=-i D,n, and integrate both sides, we have ⎛ 4(V − V , ) ⎞ C t 1 − t 1 = '
τ P HL
=
load
κ n (V DD − V T ,n )
ln ⎜
⎝
DD
V 50%
T n
⎟ ⎠
⎡ 2V T ,n ⎛ 4(V DD − V T ,n) ⎞ ⎤ + ln ⎜ − 1⎟ ⎥ ⎢ V D D κ n (V DD − V T , n) ⎣ V DD − V T , n ⎝ ⎠⎦ C load
• Finally, since V OH =V DD and V OL=0, we have V out
τ PHL
V OH V OH -V T,n
nMOS in saturation nMOS in linear region
V 50%
10
t 0 t 1’ t 1
t
Fig. 6.6
CMOS Dynamic Analysis: Delay-Time Calculation (4/4) • τPLH: NMOS is off. The equivalent circuit during low-toV DD high output transition is V in
pMOS
i D,p
V out
C load
• With the similar way (t0 t1’ t1 0 saturation linear ), we can have τ P LH = 11
|VT,p|
V50%
⎡ 2 VT,p ⎛ 4(V DD − V T ,p ) ⎞⎤ ln + −1⎟⎥ ⎢ ⎜⎜ ⎟⎥ − − ( ) V DD κ p V DD V T , p ⎢V D D V T , p ⎝ ⎠⎦ ⎣ C load
6.4 Inverter Design with Delay Constraints CMOS Inverter Design Design for Performance • Keep capacitance small • Increase transistor size » Watch out for self-loading! • Increase V DD
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CMOS Inverter Design: Delay as a Function of V DD
•V DD increases τ PHL/τ PLH decreases. However, the power consumption also increases. 5.5 5 4.5 ) d 4 e z i l a 3.5 m r o n 3 ( L H p
2.5 2 1.5 1 0.8
1
1.2
1.4
1.6
V
DD
14
1.8
(V)
2
2.2
2.4
CMOS Inverter Design: Device Sizing (1/5)
3.8
x 10
-11
(for fixed load)
3.6 3.4 3.2
) c e 3.0 s ( p
Self-loading effect: Intrinsic capacitances dominate
2.8 2.6 2.4 2.2 2. 0
2
4
6
8 S
10
12
14
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CMOS Inverter Design: Device Sizing (2/5) NMOS/PMOS Ratio -11
x 10 5
4.5
PLH
PHL
) c e 4 s (
R = W p / W n
p
P 3.5
3 1
1.5
2
2.5
3
R
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3.5
4
4.5
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CMOS Inverter Design: Device Sizing (3/5) small
Self-Loading Effect
C load = C gd,n(W n) + C gd,p(W p) + C db,n(W n) + C db,p(W p) + C int +C g = f (W n ,W p)
• Using the junction capacitance expressions in Chapter 3, we have C db,n = (W n Ddrain+x j Ddrain)C j0,n K eq,n+(W n+2Ddrain)C jsw,n K eq,n C dp,n = (W p Ddrain+x j Ddrain)C j0,p K eq,p+(Wp+2Ddrain)C jsw,p K eq,p
• Therefore, C load can be rewritten as C load = α0+ αnW n+ α pW p
where 0
= Ddrain(2C jsw,n K eq,n+2C jsw,p K eq,p+x j C j0,n K eq,n+x j C j0,p K eq,p)+C int +C g
n
= K eq,n(C j0,n Ddrain+C jsw,n)
p
= K eq,p(C j0,p Ddrain+C jsw,p)
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CMOS Inverter Design: Device Sizing (4/5) • Therefore,
τ PHL
and τ PLH are
⎞ ⎡ 2V T ,n ⎛ 4 (V DD − V T ,n ) ⎞⎤ ⎛ α 0 + α nW n + α pW p ⎞ ⎛ L n + ln ⎜⎜ −1⎟⎟⎥ ⎟⎟ × ⎢ ⎟ × ⎜⎜ W n V DD ⎝ ⎠ ⎝ μ nC ox (V DD − V T ,n ) ⎠ ⎢⎣V DD − VT ,n ⎝ ⎠⎥⎦
τ PHL = ⎜
⎞ ⎡ 2 V T , p ⎛ 4 (V DD − V T , p ) ⎞⎤ ⎛ α 0 + α nW n + α pW p ⎞ ⎛ L p ⎟× ⎢ + ln ⎜ − 1 ⎟⎥ ⎟×⎜ ⎜ ⎟ ⎜ ⎟⎥ − ⎢ − W V V V μ , p DD T p DD C V V T,p ) ⎝ ⎠ ⎝ n ox ( DD ⎠ ⎣ ⎝ ⎠⎦
τ P LH = ⎜
• The ratio between the channel widths W n and W p is usually dictated by other design constraints such as noise margins and the logic inversion threshold. Let’s this transistor aspect ratio be defined as R W p /W n . Then, the propagation delay can be ⎛ α 0 + (α n + Rα p )W n ⎞ represented as τ PH L = Γ n ⎜ ⎟
τ PL H
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W n ⎝ ⎛ α n ⎜ α 0 + ( R + α p )W p = Γ p ⎜ W p ⎜ ⎝
⎠ ⎞ ⎟ ⎟ ⎟ ⎠
CMOS Inverter Design: Device Sizing (5/5)
• As we continue increase the values of Wn and Wp, the propagation delay will asymptotically approach a limit value for lager Wn and Wp, limit
τ PHL = Γn(α n + Rα p) limit
α n ( = τ P L H Γ p R +α p)
• The propagation delay times cannot be reduced beyond the above limits, and the limit is independent of the extrinsic capacitances. 19
CMOS Inverter Design: Impact of Rise Time on Delay 0.35
0.3 ) c e s n (
0.25
L H p
0.2
0.15
0
0.2
0.4
0.6
0.8
1
rise (nsec)
2
τ PHL
=
2 τ PHL(step input)
τ P LH
=
2 τ PLH (step input)
( ) +( )
+
τ r
2
2
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τ f
2
Propagation delay increases since both PMOS and NMOS are on during the charge-up and charge-down events.
CMOS Inverter Design Impact of Channel Velocity Saturation The drain current is linearly dependent on V GS I sat = κ Wn (V GS -V T ) Propagation delay only has a weak dependence on the supply voltage V DD
Cload V 50% = τ PH L ≈ I sat
Cload (V DD / 2) κ Wn
(V D D −V T )
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CMOS Dynamic Analysis: Dynamic Power Dissipation (1/2) •The dynamic power dissipation can be derived as follows. P dyn,avg = V DD I DD,avg
•With I DD,avg taken over one clock period T . The capacitance current which equals the current from the power supply (assuming I Dn = 0 during charging) is I D = C load
dV out dt
•Rearranging and integrating over one clock period T T
∫
I D dt = 0
V DD
∫
0
C load dV out
•Gives 22
I DD,avg T = C load V DD
CMOS Dynamic Analysis: Dynamic Power Dissipation ( 2/2)
• Solving for I DD,avg and substituting in P avg :
1
2 2 = = C load V DD C load V DD f Pavg
T
• In terms of SPICE simulation, the authors offer a circuit called power meter. • It should be noted here the our simple Cload may underestimate the power dissipated. • In terms of SPICE simulation, it offers a circuit called power meter.
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