Introductio Introduction n - Chapter Chapter 1
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Silicon VLSI Technology , Modeling . . , . . and P. B. Griffin
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Introducti Introduction on - Chapter Chapter 1
INTROD INTR ODUC UCTION TION - Chapter 1 , the technologies used to manufacture ICs. • We will will p place lace a special special em emphasis on comp computer simulation tools to help understand these processes . • some technology areas than in others, but in all areas they have made tremendous progress in recent years. SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Introduction - Chapter 1
• an n egra e c rcu s. • Progress due to: Feature size reduction - 0.7X/3 years (Moore’s Law). Increasing chip size - ≈ 16% per year. “Creativit ” in im lementin functions. SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Introduction - Chapter 1
Semiconductor Progress , , layer depth, layer-to-layer tolerances), power per active component, operating voltage • Increasing: chip size, wafer size, circuit density, , , • cycle
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Introduction - Chapter 1
Device Scaling Over Time
Feature Size 100µm
Era of Simple Scaling
10µm
Cell dimensions
1µm Scaling + Innovation (ITRS)
130 nm in 2002
0.1µm 10nm
18 nm in 2018
Transition Region
Invention
Quantum Effects Dominate
1nm
Atomic Dimensions
0.1nm 1960
1980
2000
2020
2040
Year
• The era of “easy” scaling is over. We are now in a period where technology and device innovations are required. Beyond 2020, new currently unknown inventions will be required. SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Introduction - Chapter 1
Year of Production Technology Node (half pitch)
1998
2002
2004
2007
2010
2013
2016
2018
250 nm 180 nm
130 nm
90 nm
65 nm
45 nm
32 nm
22 nm
18 nm
100 nm
70 nm
53 nm
35 nm
25 nm
18 nm
13 nm
10 nm
512M
1G
4G
16G
32G
64G
128G
128G
550
1100
2200
4400
8800
14,000
0.9-1.2
0.8-1.1
0.7-1-0
06-0.9
0.5-0.8
0.5-0.7
MPU Printed Gate Length DRAM Bits/Chip (Sampling)
256M
2000
MPU Transistors/Chip (x106) Min Su
l Volta e volts
1.8-2.5
1.5-1.8
1.2-1.5
ITRS at http://public.itrs.net/ (2003 version + 2004 update) – on class website.
• Assumes CMOS technolo dominates over entire roadma . • 2 year cycle moving to 3 years (scaling + innovation now required).
• 1990 IBM demo of Å scale “lithography”. • Technology appears to be capable of making structures much smaller than currently known device limits. SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Introduction - Chapter 1
Intel – From Sand to Silicon
• http://www.intel.com/pressroom/kits/chipmaking/ –
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
Linewidth vs. Fab Cost
Fab Cost ($M) Linewidth (nm)
10000
M $ ( t s o C b a F
1000
100
.
) m u ( h t d i w e n i L
10 100mm
150mm
200mm
300mm
450mm
1 . 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025
Advantages and Challenges Associated with the Introduction of 450mm Wafers :A position paper report submitted b the ITRS Startin Materials Sub-TWG June 2005. http://public.itrs.net/papers.html SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Introduction - Chapter 1
Moore’s Law On April 19, 1965 Electronics Magazine published a paper by Gordon Moore in which he made a prediction about the semicon uctor in ustry t at as ecome t e stu o egen . “The number of transistors incorporated in a chip will a roximatel double ever 24 months.” Known as Moore's Law, his prediction has enabled widespread proliferation of technology worldwide, and today as ecome s or an or rap ec no og ca c ange.
http://www.intel.com/pressroom/kits/events/moores_law_40th/index.htm?iid=tech_mooreslaw+body_presskit SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Introduction - Chapter 1
Historical Perspective
• Invention of the bipolar transistor - 1947, Bell Labs. • Shockley’s “creative failure” methodology
N
N
P
P
N
N
• Grown junction transistor technology of the 1950s N P
N
P
N
N SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
• Bardeen, Brattain and Shockley – Point Contact Transistor in 1947 at Bell Laboratory – Followed by the bipolar transistor
• – J ack Kilby demonstrated in 1958 • Texas Instruments
– • Fairchild Semiconductor
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Introduction - Chapter 1
Physical Devices • an po ar unct on rans stors • Field Effect Transistors (FET) – – J unction FET (J FET)
• Others: – – – –
PN J unction Resistor Ca acito Photo-Diode and Photo-Transistor
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
In N
N In
• Alloy junction technology of the 1950s. P N P
N
N
N
P N
• Double diffused transistor technology of the 1950s.
P N
N
P N P
N
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
Si O2 N
P
Fairchild, late 1950s). • First “passivated” junctions.
N P
N N
P N
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
Photolitho ra h • Basic lithography process – – – – –
A l hotoresist Patterned exposure Remove photoresist regions Mask
Light
Strip remaining photoresist Photoresist Deposited Film Substrate Film deposition
Photoresist application
Exposure
Etch mask
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
Etching
Development 15
Resist removal © 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
Planar Integrated Circuit • Patterning of multiple photoresist patterns and processing steps create a planar integrated circuit – – – –
P regions N regions Metal Contact Holes Metal Pattern
Analog BJT
Vsource
Ground
Base Emitter
Collector
N
P
N
P
Resistor
P Resistor
N SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
Planar Digital IC • Complimentary Metal-Oxide-Semiconductor (CMOS) – N-channel MOS Field Effect Transistors NMOS – Mask Layers: P-well N-well P+ N+ Gate Contact L1 L1-L2 via L2-L3 via L3
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
P+
N
P+
N+
N Well
P
N+
P Well
PMOS
NMOS
P 17
Thickness Substrate: >500 um Active Layer: < 1 um © 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
Multiple Metal Layers • Metal Planarization requ re or mu p e metal layers – – – – – –
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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Metal De osition Patterning Fill Dielectric Contact vias Contact Deposition
© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
Silicon Technology Leadership and the New Scaling Paradigm Mark Bohr, Intel Senior Fellow, Logic Technology Development April 18, 2007
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Introduction - Chapter 1
Computer Simulation Tools (TCAD) • manufacturing can now be simulated. • Simulation is now used for: – Designing new processes and devices. – Exploring the limits of semiconductor devices and technology (R&D). – “Centering” manufacturing processes. – Solving manufacturing problems (what-if?)
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
• Simulation of an advanced local oxidation process.
photoresist exposure.
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
BASIC DEVICE PHYSICS SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
Challenges For The Future • Having a “roadmap” suggests that the future is well defined and there are . • The truth is that there are enormous technical hurdles to actually achieving the forecasts of the roadmap. Scaling is no longer enough. • 3 stages for future development: “Technology Performance Boosters”
Invention
c e Sidewall Spacer Poly Gate
Gate eecrc
Silicide Source S/D Ext
Rchan
Gate
???
Drain S/D Ext
Substrate
Materials/process innovations
SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
• Spin-based devices • o ecu ar ev ces • Rapid single flux quantum • Quantum cellular automata • Resonant tunneling devices • Single electron devices
Beyond Si CMOS Device innovations IN 5-15 YEARS 23
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Introduction - Chapter 1
Broader Impact of Silicon Technology
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Part of 12 x 12 array
Indiv idual Actuator
Cornell University .
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-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 • Many other applications e.g. MEMs and many-1.4 new device structures e.g.0.0carbo nano u e ev ces, a use as c s con ec no ogy or a D r ca on.
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© 2000 by Prentice Hall Upper Saddle River NJ
Introduction - Chapter 1
Summary of Key Ideas • ICs are widely regarded as one of the key components of the information age. • Basic inventions between 1945 and 1970 laid the foundation for today's silicon industry. • For more than 40 years, "Moore's Law" (a doubling of chip complexity every 2-3 years) has held true. • power consumption, high performance and flexible design options. Future projections suggest these trends will continue at least 15 more years. • Silicon technology has become a basic “toolset” for many areas of science and engineering. • design for many years. CAD tools are now being used for technology design. • Chapter 1 also contains some review information on semiconductor materials sem con uc or ev ces. ese op cs w e use u n a er c ap ers o e ex . SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin
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© 2000 by Prentice Hall Upper Saddle River NJ