ASICs. ASICs...T ..THE HE COUR COURSE SE (1 WEEK WEEK))
INTRODUCTION TO ASICs The diff differ eren ence ce betw betwee een n full full-c -cus usto tom m and and semi semicu cust stom om ASIC ASICs s • The The diff differ eren ence ce Key concepts: The betw betwee een n stan standa dard rd-c -cel ell, l, gate gate-a -arr rray ay,, and and prog progra ramm mmab able le ASIC ASICs s • ASI ASIC desi design gn flow flow • Desi Design gn econ econom omic ics s • ASIC ASIC cell cell libr librar ary y An ASIC (“a(“a-si sick ck”) ”) is an application-specific integrated circuit gate equival equivalent ent is a NAND gate F = A • B (IBM uses A gate ses a NOR gate), or four tran transi sist stor ors s
gates per chi chip, 60’s), mediumHistory of integration: small-scale integration: small-scale integration (SSI, ~10 gat scale integration (MSI, ~100 ~100–1 –100 000 0 gat gates per per chi chip, 70’s 70’s)), large-scale integration (LSI, ~100 ~1000– 0–10 10,0 ,000 00 gate gates s per per chip chip,, 80’s 80’s), ), very large-scale integration (VLSI, ~10,00 ~10,000–1 0–100, 00,000 000 gate gates s per per chip chip,, 90’s 90’s), ), ultralarge scale integration (ULSI, ~1M–10M gates per chip) precede ded d History of technology: bi technology: bipo polar lar techno technolog logy y and transistor–transistor logic (TTL) prece metal-oxide-silicon (MOS) tech techno nolo logy gy beca becaus use e it was was diffi difficu cult lt to make make meta metall-ga gate te n-ch n-chan an-nel MOS (nMOS or NMOS); the the intr introd oduc ucti tion on of complementary MOS (CMOS, neve neverr cMO cMOS) great greatly ly reduc reduced ed powe powerr The featu feature re size size is the smallest shape you can make on a chip and is measured in λ or lambda Origin of ASICs: the stand standar ard d parts parts , init microelectronic ic systems systems , initia iall lly y used used to desi design gn microelectron glue logi logic c , cust custom om ICs ICs , dynamic randomwere ere grad gradua uallly repla eplace ced d wit with a comb combin inat atio ion n of glue access memory (DRAM) and static RAM (SRAM) History of ASICs: The IEEE Custom Integrated Circuits Conference (CIC (CICC) C) and and IEEE Inter- national ASIC Conference Conference docu docume ment nt the the deve develo lopm pmen entt of ASIC ASICs s Application-specific standard products (ASSPs) are a cross betw etween standar dard parts and ASICs
1.1 Types of ASICs ICs are made on a wafer . Cir Circui cuits are are bui built up wit with succ succes essi sive ve mask mask lay layer ers s . The number of masks used to define the interconnect and and othe otherr layer ayers s is dif differ ferent ent betw betwee een n full-custom ICs and progra programmab mmable le ASI ASICs Cs
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ASICS... THE COURSE
silicon die
A silicon chip or integrated cicuit (IC) is more properly called a die
0.1 inch
(a)
(b)
1.1.1 Full-Custom ASICs full-custo stom m ASI ASIC C. All mask layers are cust ustomized in a full-cu
It only makes sense to desi esign a full ull-cust custom om IC if there ere are no libraries availabl able. Full Full-c -cus usto tom m offe offers rs the high highes estt perf perfor orma manc nce e and and lowe lowest st part part cost cost (sm (smalle allest st die die size size)) wit with the disa disadv dvan anta tage ges s of incr increa ease sed d desi design gn time time,, comp comple lexi xity ty,, desi design gn expe expens nse, e, and and high highes estt risk risk.. Micr Microp opro roce cess ssor ors s were were excl exclus usiv ivel ely y full full-c -cus usto tom, m, but but desi design gner ers s are are incr increa easi sing ngly ly turn turnin ing g to semi semicu cust stom om ASIC ASIC tech techni niqu ques es in this his area area too. too. Othe Otherr exam exampl ples es of full full-c -cus usto tom m ICs ICs or ASIC ASICs s are are requ requir irem emen ents ts for for high high-v -vol olta tage ge (aut (autom omob obilile) e),, analog analog/di /digit gital al (commu (communic nicati ations ons), ), or senso sensors rs and and actu actuat ator ors. s. 1.1.2 Standard-Cell–Based ASICs
A cell-based ASIC (CBIC —“sea-bick”) • Standard cells • Possibly megacells , megafunctions , fullcustom blocks , system-level macros (SLMs), fixed blocks , cores, or Functional Standard Blocks (FSBs) • All mask layers are customized—transistors and interconnect • Custom blocks can be embedded • Manufacturing lead time is about eight weeks.
standard-cell area
1 2
3
fixed blocks
4
5
0.02in 500 µm
datapath h compiler compiler and a datapat datapath h library library . Cell In datapath (DP) logic we may use a datapat Cells s such such as arithmetic and logical units (ALUs) are pitch-matched to each oth other to improve timing and and densi density ty..
ASICs... THE COURSE
1.1 Types of ASICs
VDD
m1
cell bounding box (BB)
n-well contact
ndiff pdiff A1 metal2
Z B1
via
poly ndiff cell abutment box (AB) p-well pdiff pdiff GND 10λ
Looking down on the layout of a standard cell from a standard-cell library 1.1.3 Gate-Array–Based ASICs gate arra array y , masked gate array , MGA, or predif prediffus fused ed array array uses macros (books ) to A gate turnaroun ound d time time and base arra array y made from a base base ce cell ll or primitive reduce turnar and comp compri rise ses s a base cell . Ther There e are are thre three e types ypes::
• Chan Channe nele led d gat gate arr arrays ays • Chan Channe nelllles ess s gate gate arra arrays ys • Stru Struct ctur ured ed gate gate arra arrays ys
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ASICS... THE COURSE
expanded view of part of flexible block 1
no connection connection metal2
to power pads terminal VSS VDD
250 λ
to power pads
metal1
VSS VDD
Z feedthrough
row-end cells
cell A.11
cell A.14
cell A.23 cell A.132
metal2
I1
metal1
spacer cells
metal2
power cell
metal1
rows of standard cells
50 λ
Routing a CBIC (cell-based IC) • A “wall” of standard cells forms a flexible block • metal2 may be used in a feedthrough cell to cross over cell rows that use metal1 for wiring • Other wiring cells: spacer cells , row-end cells , and power cells
A note on the use of hyphens and dashes in the spelling (orthography) of compound nouns: Be careful to distinguish between a “high-school girl” (a girl of high-school age) and a “high s chool girl” (is she on drugs or perhaps very tall?). We write “channeled gate array,” but “channeled gate-array architecture” because the gate array is channeled; it is not “channeled-gate array architecture” (which is an array of chan-
neled-gates) or “channeled gate array architecture” (which is ambiguous). We write gate-array–based ASICs (with a en-dash between array and based) to mean (gate array)-based ASICs.
ASICs... THE COURSE
1.1 Types of ASICs
1.1.4 Channeled Gate Array
A channeled gate array
base cell
• Only the interconnect is customized • The interconnect uses predefined spaces between rows of base cells • Manufacturing lead time is between two days and two weeks
array of base cells (not all shown)
1.1.5 Channelless Gate Array
base cell
A channelless gate array (channel-free gate array , seaof-gates array , or SOG array) • Only some (the top few) mask layers are customized— the interconnect • Manufacturing lead time is between two days and two weeks.
1.1.6 Structured Gate Array
array of base cells (not all shown)
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An embedded gate array or structured gate array (masterslice or masterimage )
ASICS... THE COURSE
embedded block
• Only the interconnect is customized • Custom blocks (the same for each design) can be embedded array of base cells (not all shown)
• Manufacturing lead time is between two days and two weeks.
1.1.7 Programmable Logic Devices
Examples and types of PLDs: read-only memory (ROM) • programmable ROM or PROM • electrically programmable ROM , or EPROM • An erasable PLD (EPLD) • electrically erasable PROM, or EEPROM • UV-erasable PROM, or UVPROM • mask-programmable ROM
• A mask-programmed PLD usually uses bipolar technology Logi Logic c array arrays s may be either a Programmable Array Logic (PAL ® , a regi regist ster ered ed trad tradem emar ark k of
AMD) or a programmable logic array (PLA (PLA)); both both have have an AND plane and an OR plane
A programmable logic device (PLD) • No customized mask layers or logic cells • Fast design turnaround
macrocell
• A single large block of programmable interconnect • A matrix of logic macrocells that usually consist of programmable array logic followed by a flip-flop or latch
programmable interconnect
ASICs... THE COURSE
1.2 Design Flow
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1.1.8 Field-Programmable Gate Arrays
A field-programmable gate array (FPGA) or complex PLD • None of the mask layers are customized • A method for programming the basic logic cells and the interconnect
programmable basic logic cell
• The core is a regular array of programmable basic logic cells that can implement combinational as well as sequential logic (flip-flops) • A matrix of programmable interconnect surrounds the basic logic cells • Programmable I/O cells surround the core
programmable interconnect
• Design turnaround is a few hours
1.2 Design Flow A design flow is a sequence of steps to design an ASIC Design ign entry entry. Using a hardware description language (HDL) or sche 1. Des schema mattic ent entry. ry.
2. Logic —logi gic c cell cells s and and thei theirr conn connec ecti tion ons. s. Logic sy synth nthes esis is . Produces a netlist —lo System m partiti partitioni oning ng . Divi 3. Syste Divide de a large arge syst system em int into ASIC ASIC--size sized d piec pieces es..
4. Prelay ons corr orrectly. Prelayou outt simula simulation tion. Check to see if the design functions 5. Floorplanning . Arrange the blocks of the netlist on the chip. 6. Placement . Decide the locations of cells in a block. 7. Routing . Make Make the the conn connec ecti tion ons s bet between ween cel cells and and bloc blocks ks.. 8. Extraction . Dete Determ rmin ine e the the resi resist stan ance ce and and capa capaci cita tanc nce e of the the inte interc rcon onne nect ct.. 9. Postlayout Postlayout simulation simulation . Check to see the design still works with the added loads of the interconnect.
1.3 Case Study SPAR SPARCs Csta tati tion on 1: Bett Better er perf perfor orma manc nce e at lowe lowerr cost cost • Compa ompact ct size size,, reduc educed ed powe powerr, and and qui quiet oper operat atio ion n • Redu Reduce ced d numb number er of part parts, s, easi easier er asse assemb mbly ly,, and and impr improv oved ed reli reliab abililit ity y
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start prelayout simulation
logical design
design entry 4
1 VHDL/Verilog logic synthesis
netlist
2 A system partitioning
B
3 A
postlayout simulation
floorplanning 9
5
placement 6
circuit extraction
chip
block
physical design
routing 8
back-annotated netlist
7
logic cells
finish
ASIC design flow. Steps 1–4 are logical design, and steps 5–9 are physical design The ASICs in the Sun Microsystems SPARCstation 1 SPARCstation 1 ASIC
Gates (k-gates)
1 2
SPARC integer unit (IU) SPARC floating-point unit (FPU)
20 50
3
Cache controller
9
4 5
Memory-management unit (MMU) Data buffer
5 3
6
Direct memory access (DMA) controller
9
7
Video controller/data buffer
4
8
RAM controller
1
9
Clock generator
1
ASICs... THE COURSE
1.4 Economics of ASICs
The CAD tools used in the design of the Sun Microsystems SPARCstation SPA RCstation 1 Design level
ASIC design
Board design
Mechanical design
Management
Function
Tool
ASIC physical design
LSI Logic
ASIC logic synthesis
Internal tools and UC Berkeley tools
ASIC simulation Schematic capture
LSI Logic Valid Logic
PCB layout
Valid Logic Allegro
Timing verification
Quad Design Motive and internal tools
Case and enclosure
Autocad
Thermal analysis Structural analysis
Pacific Numerix Cosmos
Scheduling
Suntrac
Documentation
Interleaf and FrameMaker
1.4 Economics of ASICs We’ll compare the most popular types of ASICs: an FPGA, an MGA, and a CBIC. The figures ures in the follo ollowi wing ng sect sectio ions ns are are appr approx oxim imat ate e and and used used to illus llustr trat ate e the the diff differ eren entt com compoponent nents s of cost cost.. 1.4.1 Comparison Between ASIC Technologies
Example of an ASIC part cost : A 0.5 µm, 20k20k-ga gate te arr array might ight cost cost 0.01 0.01–0 –0.0 .02 2 cent cents/ s/ga gate te (for more than han 10,000 part parts) s) or $2–$4 –$4 per part, but an equivalent FPGA might be $20. When does it make sense to use a more expensive part? This is what we shall examine next.
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1.4.2 Product Cost
In a product cost there are fixed costs and variable costs (the number of produc ducts sold old is the sales volume ): total product cost = fixed product cost + variable product cost × products sold In a product made from parts the total cost for any part is total part cost = fixed part cost + variable cost per part × volume of parts For For exam exampl ple, e, supp suppos ose e we have have the the foll follow owin ing g (ima (imagi gina nary ry)) cost costs: s: • FPGA FPGA:: $21, $21,80 800 0 (fixe (fixed) d) $39 $39 (var (varia iabl ble) e) • MGA: MGA: $86, $86,00 000 0 (fixed fixed)) $10 $10 (var (variiable able)) • CBIC CBIC $146 $146,0 ,000 00 (fixed fixed)) $8 (var variabl iable) e) Then Then we can can calc calcul ulat ate e the the foll follow owin ing g break-even volumes : • FPGA FPGA/M /MGA GA ≈ 2000 2000 part parts s • FPGA FPGA/C /CBI BIC C ≈ 4000 4000 part parts s • MGA/ MGA/CB CBIC IC ≈ 20,0 20,000 00 part parts s
cost of parts $1,000,000 break-even FPGA/CBIC
CBIC $100,000
MGA FPGA
break-even MGA/CBIC break-even FPGA/MGA
$10,000 10
100
1000
10,000
100,000
number of parts or volume
Break-even graph
ASICs... THE COURSE
1.4 Economics of ASICs
11
1.4.3 ASIC Fixed Costs Examples of fixed costs: training cost for a new electronic design automation (EDA) sys syshardwa ware re and and soft softwa ware re cost cost • productivity • production test and design for test • tem • hard programming costs for an FPGA • nonrecurring-engineering (NRE) • test vectors and test-program development cost • pass (turn or spin) • profit model repres represent ents s the the profit flow duri product velocity velocity • se seco cond nd sourc source e during ng the the product lifetime • product
Training: Days Cost/day Hardware Software Design: Size (gates) Gates/day Days Cost/day Design for test: Days Cost/day NRE: Masks Simulation Test program Second source: Days Cost/day Total fixed costs
Spreadsheet, “Fixed Costs”
FPGA $800
MGA $2,000 2 $400
$10,000 $1,000 $8,000
CBIC $2,000 5 $400
$10,000 $20,000 $20,000 10,000 500 20 $400
5 $400 $10,000 $40,000 $20,000
10,000 200 50 $400 $2,000
10,000 200 50 $400 $2,000
5 $400 $30,000
5 $400 $70,000
$10,000 $10,000 $10,000 $2,000
$2,000 5 $400
$21,800
$50,000 $10,000 $10,000 $2,000
5 $400 $86,000
5 $400 $146,000
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sales per quarter, s
ASICS... THE COURSE
peak sales s 1
$20M
lost sales
product introduction
$10M
end of product life
s 2
t1
Profit model
Q1
Q2 Q3 Q4 t2 delay to market, d
Q1
Q2
t3
time
ASICs... THE COURSE
1.4 Economics of ASICs
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1.4.4 ASIC Variable Costs Factors affecting fixed fixed costs: waf costs: wafer er size size • wafer wafer cost cost • Moore’s Law (Gor (Gordo don n Moor Moore e of Inte Intel) l) density • gate gate utilization utilization • die die size size • die per wafer • defect defect density density • yield • die die cost cost • gate density
• profit margin (dep (depen ends ds on fab or fabless ) • pric price e per per gate gate • part cost
FPGA Wafer size Wafer cost Design Density Utilization Die size Die/wafer Defect density Yield Die cost Profit margin Price/gate Part cost
Spreadsheet, “Variable Costs”
MGA
6 1,400 10,000 10,000 60 1.67 88 1.10 65 25 60 0.39 $39
CBIC
6 1,300 10,000 20,000 85 0.59 248 0.90 72 7 45 0.10 $10
6 1,500 10,000 25,000 100 0.40 365 1.00 80 5 50 0.08 $8
Units inches $ gates ga gates/sq.cm % sq.cm de defects/sq.cm % $ % cents
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cents/gate 1.00 CBIC 2 µm CBIC 1.5 µ m CBIC 1 µm 0.10 CBIC 0.6 µ m FPGA 1 µ m FPGA 0.6 µm
–32%/year 0.01 1984
1986
Example price per gate figures
1988
1990
1992
1994
1996
ASICs... THE COURSE
1.5 ASIC Cell Libraries
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1.5 ASIC Cell Libraries You can: (1) use a design kit from the ASIC vendor (2) buy an ASIC-vendor library from a library vendor (3) you can build your own o wn cell library (1) is usually a phantom library —the cells are empty boxes, or phantoms , you hand off your design to the ASIC vendor and they perform phantom instantiation (Synopsys CBA) (2) involves a buy-or-build decision. You need a qualified cell library (qualified by the ASIC foundry ) If you own the masks (the tooling) you have a customer-owned tooling (COT, pro-
nounced “see-oh-tee”) solution (which is becoming very ve ry popular) cell ll layou layoutt • behavioral behavioral model model • Ver(3) (3) invo involv lves es a comp comple lex x library development process: ce Ver-
ilog ilog/V /VHD HDL L model model • timing model • test est stra strattegy egy • characterization • circuit extraction • process control monitors (PCMs) or drop-ins • cell schematic • cell icon • layout versus schematic (LVS) check • cell icon • logic synthesis • retargeting • wire-load model • routing model • phantom
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1.6 Summary Key concepts:
• We could define an ASIC as a design style that uses a cell library • The The diff differ eren ence ce betw betwee een n full full-c -cus usto tom m and and semi semicu cust stom om ASIC ASICs s • The The diff differ eren ence ce betw betwee een n stan standa dard rd-c -cel ell, l, gate gate-a -arr rray ay,, and and prog progra ramm mmab able le ASIC ASICs s • The ASIC design flow • Desi Design gn econ econom omiics incl includ udin ing g par part cost cost,, NRE, NRE, and and brea breake keve ven n vol volume ume • The contents and use of an ASIC cell library Types of ASIC ASIC type
Family member
Custom mask layers
Custom logic cells
All
Some
Full-custom
Analog/digital
Semicustom
Cell-based (CBIC) Masked gate array (MGA)
All Some
None None
Programmable
Field-programmable gate array (FPGA)
None
None
Programmable logic device (PLD)
None
None
1.7 Problems Sugg Sugges este ted d home homewo work rk:: 1.4, 1.4, 1.5, 1.5, 1.9 1.9 (fro (from m ASICs... the book )
1.8 Bibliography (ISSN N 0192-1 0192-1541 541,, http://techweb.cmp.com/eet), EDN (ISS (ISSN N 0012-7 0012-7515 515,, EE Times (ISS http://www.ednmag.com), EDAC EDAC (Ele (Elect ctro roni nic c Desi Design gn Auto Automa mati tion on Comp Compan anie ies) s) (http://www.edac.org), The The Elec Electr tric ical al Engi Engine neer erin ing g page page on the Wor World Wide Wide Web Web (E2W3 E2W3)) (http://www.e2w3.com), SEMA SEMATE TECH CH (Semic (Semicond onduct uctor or Manufa Manufactu cturin ring g Techn Technol ol-http:/ /www.semate sematech.org ch.org), The ogy) (http://www. The MIT Semi Semico cond nduc ucto torr Subw Subway ay (http://wwwmtl.mit.edu), EDA companies at http://www.yahoo.comunder Business_and_Economyin Companies/Computers/Software/Graphics/CAD/IC_Design, The The MOS MOS Impl Implem emen enta tati tion on Servi Service ce (MOS (MOSIS IS)) (http://www.isi.edu), The The Micr Microe oele lect ctro roni nic c Syst System ems s News Newsle lett tter er at http://wwwece.engr.utk.edu/ece, NASA (http://nppp.jpl.nasa.gov/dmg/jpl/loc/asic )
ASICs... THE COURSE
1.9 References
17
1.9 References Glass lasser er,, L. A., A., and and D.W. Dobb Dobber erpu puhl hl.. 1985 1985.. The Design and Analysis of VLSI Circuits. Read Readin ing, g, MA: MA: Addi Addison son-W -Wes esle ley, y, 473 473 p. ISBN ISBN 0-2010-201-125 1258080-3. 3. TK7874 TK7874.G5 .G573. 73. Deta Detaililed ed anal anal-ysis ysis of circ circui uitts, but but lar largel gely nMOS nMOS.. Mead, ad, C. A., and L. A. Conway. 1980. 80. Introduction to VLSI Systems. Read Readin ing, g, MA: MA: Addi Addiso sonnWesl Wesley ey,, 396 396 p. ISBN ISBN 0-2010-201-043 0435858-0. 0. TK7874 TK7874.M3 .M37. 7. Weste este,, N. H. E., E., and and K. Eshr Eshrag aghi hian an.. 1993 1993.. Principles of CMOS VLSI Design: A Systems Per- 2nd ed. ed. Read Readin ing, g, MA: MA: Addi Addiso sonn-We Wesl sley ey,, 713 713 p. ISBN ISBN 0-20 0-2011-53 5337 3766-6. 6. spective. 2nd TK7874 TK7874.W4 .W46. 6. Concen Concentra trates tes on fullfull-cus custom tom desig design. n.
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