CCS Technical

CCS Technology Synopsys Interoperability Forum November 9, 2005 Bill Mullen Vice President of Engineering Synopsys, Inc.

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Composite Current Source (CCS) Timing

Timing

Noise

Power













Delay Calculation Requirements • Driver Model: drive arbitrary interconnect, including • • •

high-impedance nets Receiver model: complex input capacitance Efficient characterization Vdd & Temperature scaling for IR drop, multi-V dd, DVFS, corners

load1













NLDM Based Driver/Receiver Models Cinp + -

Rd

v(t)

Reduced-Order Network Model Input cap – single value

Driver Model •

Ramp voltage source, fixed drive resistance

Receiver Model • min/max rise/fall input caps













Basics of CCS Timing Driver model i(t,v) Nonlinear Current Source

Receiver model

C1

C2

C1, C2 vary with 

Input slew



Output load



Rise vs. fall



State of cell

Load1













Characterization for NLDM Pin Capacitance

Cell Delay / Slew Tables

input slew 0.7 0.5 0.2

Cinp (single value)

0.1

input slew 0.7

3.31

3.61

3.98

4.12

5.32

0.5

2.72

3.12

3.43

3.82

4.25

0.2

2.22

2.54

2.72

3.11

3.47

1.31

1.75

1.99

2.31

2.77

0.1 .023 .047 .065 .078 .091

output cap

.023 .047 .065 .078 .091

output cap















Characterization for CCS Timing Receiver Model input slew 0.7 0.5

C1,C2

C1,C2 C1,C2 C1,C2 C1,C2

C1,C2

C1,C2 C1,C2 C1,C2 C1,C2

Driver Model input slew 0.7 0.5













CCS Receiver Model Advantage CCS Receiver Model matches both delay & slew













Vdd and Temperature • •

CCS Timing enables high accuracy delay calculation for wide range of Vdd and Temperature For power-aware design styles: 

Single Vdd

lib_1.2v.db













Constraint Arcs: Vdd & Temperature • Constraint arc (timing check) values depend on Vdd and Temperature

• CCS Timing supports nonlinear scaling of constraint arcs













CCS Timing Results















Results: STARC, TSMC













Customers Demonstrate CCS Accuracy













CCS Timing Summary













Composite Current Source (CCS)













Noise Analysis







































































































































Composite Current Source (CCS) Power

Timing

Noise

Power













Power Library Requirements • Address needs of Multi-Voltage designs 

Multi-Rail cells (Vdd, Vss)



Non-zero ground rail



MTCMOS (power gating)

• Static and dynamic rail analysis 

Support accurate voltage (IR) drop calculation

• Single library / model for all power related













Power Gating (MTCMOS) Reduce Leakage by turning block off Vdd

Vsleep

Fine Grain: Sleep transistor within each cell IN

MTCMOS

Block A

LVt

OUT

VirtualVdd

Sleep

Block B Sleep-mode Power switch control

Block C

Coarse Grain: Sleep transistor for entire block VDD













Introducing CCS Power •

•

Switching current waveform for each power or ground pin 

Finer time resolution



Full Multi-Voltage support

Equivalent parasitics as seen from the power network 

• •

Allows fast yet accurate rail analysis

Support for macro power modeling for memory and IP Unified library model for power optimization, power analysis, rail analysis













Characterization for NLPM Libert Lib erty y Non Non-Li -Linea nearr Power Power Model Model

Internal Energy per transition

3.31 0.7 input 0.5 slew 0.2 0.1

3.61

3.98

4.12

5.32

2.72

3.12

3.43

3.82

4.25

2.22

2.54

2.72

3.11

3.47

1.31

1.75

1.99

2.31

2.77

.023 .047 .065 .078 .091















Characterization for CCS Power

Dynamic Current Waveform per transition per Rail













CCS Power Characterization •

HSPICE Simulation: AND gate with rising input  

Power pin (Vdd) current Ground pin (Vss) current













Advantages: Time Resolution

• Captures complete power and ground pin













Dynamic Rail Analysis • Compute instance-specific voltage drop at all power/ground pins

• Requires cell model for switching and nonswitching cases













Equivalent Parasitics for NonSwitching Case • Essential for accurate accurate rail analysis – additional decoupling cap • Cpar per input state for each power or ground pin • Rpar per input state for each power or ground pin to each output















CCS Power Summary













CCS Summary













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CCS Technical

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