Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+ EEC 751 CAD OF ELECTRONICS LAB PSPICE Experiments 1. Transient Analysis Analysis of BJT inverter using step input. 2. DC Analysis (VTC) of BJT inverter with and without paraeters. !. Transient Analysis of "#$% inverter using step input. &. Transient Analysis Analysis of "#$% inverter using pulse input. '. DC Analysis (VTC) of "#$% inverter with and without paraeters. . Analysis of C#$% inverter using step input. . Transient Analysis of C#$% inverter using step input with paraeters. *. Transient Analysis of C#$% inverter using pulse input. +. Transient Analysis of C#$% inverter using pulse input with paraeters. 1,. DC Analysis (VTC) of C#$% inverter with and without paraeters. 11. Transient - DC Analysis of "$ /ate inverter. 12. Transient - DC Analysis of "A"D /ate
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+ 0perient "o1 Aim: Transient analysis of BJT inverter using %tep input Softwre !se": 3%34C0 T#eor$: 1% I"e& In'erter Di(it& )te
The ideal 4nverter odel is iportant 5e6ause it gives a etri6 5y whi6h we 6an 7udge the 8uality of a6tual ipleentation. 4ts VTC is shown in figure 1.1 and has the following properties 4nfinite gain in the transition region9 and gate threshold lo6ated in the iddle of the logi6 swing9 with high and low argins e8ual to the half of the swing. The input and output ipedan6e of the ideal gate are infinity and :ero9 respe6tively.
*% D$nmi+ Be#'ior of In'erter Di(it& )te
;igure1.2 illustrates illustrates the 5ehavior of the inverter digital gate using BJT
There are three regions for the a5ove voltage transfer 6hara6teristi6 1. Cut
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+ ,i - ,i& The transistor Begins to turn on. • ,i& / ,i / ,i#. The transistor is in forward a6tive region and operates as Aplifier. •
•
,i - ,o# %The transistor will 5e deep is saturation9 Vo = V6e(sat).
A easure of sensitivity to noise is 6alled "oise #argin ( N0) whi6h 6an 5e epressed 5y
"l = Vil Vil > Vo Vol. "h = Vo Voh > Vih. Vih. S+#emti+s:
Sim&tion w'eforms:
Res&t: The transient analysis of BJT inverter using step unit in 3%34C0 has 5een su66essfully done and the wavefors were plotted su66essfully. su66essfully. The wavefors tally with the epe6ted 5ehavior of the BJT inverter.
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+ 0perient "o* Aim: Transient analysis of C#$% inverter using pulse input Softwre !se": 3%34C0 T#eor$: ;igure 5elow shows the 6ir6uit diagra of a stati6 C#$% inverter. 4ts operation is readily understood with the aid of the siple swit6h odel of the #$% transistor9 the transistor is nothing ore than a swit6h with an infinite off resistan6e (for ? VGS ? @ ?VT ?VT ?)9 ?)9 and a finite on
Fig 3.1: %tati6 C#$% inverter. V DD stands for the supply voltage. This leads to the following interpretation of the inverter. hen Vin is high and e8ual to VDD9 VDD9 the "#$% transistor is on9 while the 3#$% is off. This yields the e8uivalent 6ir6uit of ;igure !.2. A dire6t path eists 5etween Vout and the ground node9 resulting in a steady
;ig !.2 %wit6h odels of C#$% inverter. inverter. The nature and the for of the voltage
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+ IDSp = > IDSn VGSn = Vin VGSp = Vin > Vin > VDD VDSn = Vout VDSp = Vout > Vout > VDD The load
Transforing 3#$% I-V 3#$% I-V 6hara6teristi6 to a 6oon 6oordinate set (assuing VDD = 2.' V). Fi(re 2%2 Transforing
Fi(re 2%3 oad 6urves for "#$% and 3#$% 3# $% transistors of the stati6 C#$% inverter ( VDD = 2.' V). The dots represent the d6 operation points for various input voltages.
The resulting load lines are plotted in ;igure !.&. ;or a d6 operating points to 5e valid9 the 6urrents through the "#$% and 3#$% devi6es ust 5e e8ual. /raphi6ally9 this eans that the d6 points ust 5e lo6ated at the interse6tion of 6orresponding load lines. A nu5er of those points (for Vin = ,9 ,.'9 19 1.'9 29 and 2.' V) are arEed on the graph. As 6an 5e o5served9 all operating points are lo6ated either at the high or low output levels. The VTC of the inverter hen6e ehi5its a very narrow transition :one. This resu result ltss fro fro the the high high gain gain duri during ng the the swit swit6h 6hin ing g tran transi sien ent9 t9 when when 5oth 5oth "#$% "#$% and and 3#$% 3#$% are are siultaneously on9 and in saturation. 4n that operation region9 a sall 6hange in the input voltage results in a large output variation. All these o5servations translate into the VTC of ;igure !.'.
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+
Fi(re 2%5 VTC of stati6 C#$% inverter9 derived fro ;igure '.& ( VDD = 2.' V). ;or ea6h operation region9 the odes of the transistors are annotated F off9 res(istive)9 or sat(urated). S+#emti+s: VCC XSC1
3.3V Q3
Ext Trig + _ B
A
V1
0.5u 1.25u
0 V 3.3 V 6usec 12usec Vi
Q1
+
_
+
_
Vo C1 500fF
0.5u 1.25u
Fig -./ CM!S inverter 0it1 pulse input sc1ematic circuit
Sim&tion w'eforms:
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+
Res&t: The transient analysis of C#$% inverter using pulse input in 3%34C0 has 5een su66essfully done and the wavefors were plotted su66essfully. The wavefors tally with the epe6ted 5ehavior of the C#$% inverter.
0perient "o
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+ Aim: Transient analysis of C#$% inverter using step input Softwre !se": 3%34C0 T#eor$: ;igure 5elow shows the 6ir6uit diagra of a stati6 C#$% inverter. 4ts operation is readily understood with the aid of the siple swit6h odel of the #$% transistor9 the transistor is nothing ore than a swit6h with an infinite off resistan6e (for ? VGS ? @ ?VT ?VT ?)9 ?)9 and a finite on
Fig 3.1: %tati6 C#$% inverter. V DD stands for the supply voltage. This leads to the following interpretation of the inverter. hen Vin is high and e8ual to VDD9 VDD9 the "#$% transistor is on9 while the 3#$% is off. This yields the e8uivalent 6ir6uit of ;igure !.2. A dire6t path eists 5etween Vout and the ground node9 resulting in a steady
;ig !.2 %wit6h odels of C#$% inverter. inverter. The nature and the for of the voltage
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+ I DS p = > I DS n V GS Vin > V DD GS n = Vin V GS GS p = Vin > V DS n = Vout V DS p = Vout > Vout > V DD The load
Transforing 3#$% I-V 3#$% I-V 6hara6teristi6 to a 6oon 6oordinate set (assuing VDD = 2.' V). Fi(re 2%2 Transforing
Fi(re 2%3 oad 6urves for "#$% and 3#$% 3# $% transistors of the stati6 C#$% inverter ( VDD = 2.' V). The dots represent the d6 operation points for various input voltages.
The resulting load lines are plotted in ;igure !.&. ;or a d6 operating points to 5e valid9 the 6urrents through the "#$% and 3#$% devi6es ust 5e e8ual. /raphi6ally9 this eans that the d6 points ust 5e lo6ated at the interse6tion of 6orresponding load lines. A nu5er of those points (for Vin = ,9 ,.'9 19 1.'9 29 and 2.' V) are arEed on the graph. As 6an 5e o5served9 all operating points are lo6ated either at the high or low output levels. The VTC of the inverter hen6e ehi5its a very narrow transition :one. This resu result ltss fro fro the the high high gain gain duri during ng the the swit swit6h 6hin ing g tran transi sien ent9 t9 when when 5oth 5oth "#$% "#$% and and 3#$% 3#$% are are siultaneously on9 and in saturation. 4n that operation region9 a sall 6hange in the input voltage results in a large output variation. All these o5servations translate into the VTC of ;igure !.'.
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+
Fi(re 2%5 VTC of stati6 C#$% inverter9 derived fro ;igure '.& ( VDD = 2.' V). ;or ea6h operation region9 the odes of the transistors are annotated F off9 res(istive)9 or sat(urated). S+#emti+s: VCC XSC1
3.3V Q3
Ext Trig + _ B
A
V2
0.5u 1.25u
5nsec
Q1
+
_
+
_
Vo C1 500fF
0.5u 1.25u
Fig -(/ CM!S inverter 0it1 step input sc1ematic circuit
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+ Sim&tion w'eforms:
Res&t: The transient analysis of C#$% inverter using step input in 3%34C0 has 5een su66essfully done and the wavefors were plotted su66essfully. The wavefors tally with the epe6ted 5ehavior of the C#$% inverter.
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+ C0OS NAND )te:
Figure *2-3 shows a two input CMOS NAND gate, output pull-up is provided ! two "MOS in parallel #onne#tions, while two NMOS with series #onne#tion provide an output pull-down to ground.
Otpt 4i(# Stte: This state is o5tained 5y two 6ases 4f 5oth inputs are low9 the two 3#$% are in a6tive operation providing an output pull
ith a single input low9 an output pull up path to VDD is eist through the 6orresponding
3#$%9 with the 6orresponding "#$% is off and no 6urrent is pass through "#$% . 4n ea6h 6ase V$G = VDD. Otpt Low Stte: This state is o5tained only if the two inputs are high as follow9 if A and B inputs are high9 "A and "B are in a6tive operation 9 while 3A and 3B are off9 so no output pull up path to VDD is availa5le and the 6urrents 4D9"A = 4D9"B = ,9 and V$ = ,.
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+
C0OS NOR )te:
Figure *2- shows a two input CMOS NO$ %ate, the NO$ &un#tion #an e otained with CMOS pairs' "MOS devi#es in series to provide pull-up #on(guration and NMOS devi#es in parallel to provide pull-down #on(guration.
Otpt Low Stte: The output low 6an 5e o5tained 5y two 6ases 4f 5othe input are high9 the gate to sour6e voltage for 5oth "#$% 5rings the into a6tive operation providing providing an a6tive pull
4f any input in high the 6orresponding "#$% is in a6tive operation to provide an output pull<
down to ground. 4n ea6h 6ases V$ = ,. Otpt 4i(# Stte: This state 6an 5e o66urred only if the two inputs are low9 where 5oth "A and "B are off9 while the 3#$% devi6es are in a6tive operation to provide an output pull
Pro+e"re: Prt 1: 1. Constru6t the 6ir6uit shown in Fi(re 1%19 VDD = 'V 2. ;ind the truth ta5le filling the following
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+
!. ;illing the following ta5le and Draw the VTC of this gate
&. Deterine V$G9V$9V4G9V4 ). Draw the *+C o& this gate ! using the Or#ad .
Department of Electronics & Communication Engineering SET, IFTM University, Moradabad CD !F E"ECT#!$ICS "% EEC'()*+
