Basic Building Block

Design of CMOS Analog Integrated Circuits

Franco Maloberti

Basic Building Block F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

INVERTER WITH ACTIVE LOAD • The simplest form of gain stage, the DC gain is given by the slope of the curve

F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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Small signal analysis:

C1 = Cgs1 + Cgs1,ov C2 = Cgd1 + Cgd1,ov

C3 = Cdb1 + Cdb2 + Cgd2 + Cgd2,ov + CL

At low frequency:

Since:

Av =

Vout − g m1 = Vin g ds1 + g ds 2

g m = 2µCox

W ID L

g ds = λI D


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It results:

W 2µ1Cox    L 1 Av = − ID λ n + λp

(

)

• The DC gain increases as the square root of the bias current is decreased. This holds until the devices enter the subthreshold region.


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At high frequency: • Miller’s theorem is applied to C 2 • The output total capacitance is C2 + C3 • The output resistance is 1/(gds1 + gds2) • The transfer function has one pole

ωp =

(

)

λn + λ p ID g ds1 + g ds 2 = C2 + C3 C 2 + C3

The unity gain frequency is:

W 2µ1Cox   1 1 g m1 1 L fT = ωp A v (0 ) = = 2π 2π C 2 + C 3 2π C 2 + C3

ID

It increases as the square root of the bias current increases • Due to Miller’s theorem the input capacitance becomes: Cin = C1 + C2(1 - Av) if |Av| >> 1 it can become significant to the stage driving it. F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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Example Simulate an inverter with active load (VDD = 5 V) as the following figure with BSIM3 V2 Models. Find the DC gain and unity gain frequency.

Observe that the achieved gain is about 47 dB; the unity gain frequency is fairly good, being around 500 MHz and the phase margin is about 87 degrees. F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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CASCODE The cascode gain stage is used to attenuate the Miller effect on node 1.

Bias voltage such to keep M1 in the saturation region

VB > Vsat ,1 + VGS2 = Vsat ,1 + VTh ,n + Vsat ,2 =

"" = VTh,n +

I1 W 2µ n Cox    L 1

+

I1 W 2µ n Cox    L 2


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Small signal analysis:

C1 = Cgs1 + Cgs1,ov

C2 = Cgd1 + Cgd1,ov

C4 = Cgs2 + Cgs2,ov + Cdb1 + Csb2

C3 = Cgd2 + Cgd2,ov + C gd3 + Cgd3,ov + Cdb2 + Cdb3 + CL

For low frequency, neglecting gds1 and gds2:

gm1vin = -gm2v1 = -gds3v0

Hence:

Av =

v0 g = − m1 v in g ds3

A1 =

v1 g = − m1 v in gm2

The Miller effect is significantly reduced if gm1 ≈ gm2 F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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At high frequency: The circuit has two nodes: the output and node 1. • The capacitance at the output is C3 • The output impedance is 1/gds3 (neglecting the impedance at the drain of M2 ) • The capacitance at the node 1 is (C2 + C4) • The impedance at the node 1 is 1/gm2 • The pole associated to the output node is:

f p,out =

1 1 1 g ds3 = 2 π τout 2π C3

• The pole associated to the node 1 is:

1 1 1 g 2m 2 / ζ f p,1 = = 2π τ1 2π g m 2 (C 2 + C 4 ) + g m1C2 Where ζ = (1 + rds3/rds2) F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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Since gm >> gds, fp,out is dominant. • The gain-bandwidth product is:

f T = f p,dom A v =

1 g m1 2π C3

If a good phase margin is needed, it must be:

g m1 gm2 / ζ < C3 (C2 + C 4 ) + g m1C 2

This conditiin can be fulfilled by increasing CL.


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Impedance at the drain of M2:

vx =

i + g m2vs2 ix + x g ds1 g ds 2

rD 2 =

 g  vx = rds1 + rds 2 1 + m 2  ≅ rds1g m 2 rds 2 ix  g ds1 

vs 2 =

ix g ds1


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Impedance at the node 1,r1:

v x = R a1i x + rds 2 (i x − g m v x ) rs 2 =

1  rds3  ζ 1 +  = g m 2  rds 2  g m2


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CASCODE WITH CASCODE LOAD • Transconductance gain stage

The gain is increased by increasing gm or rout. F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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• In the improved version the transconductance of M1 is increased by the factor

(IM

4

+ IM5

)

IM4

• VB1 and VB2 must keep M1 and M4 out the triode region VB1 > Vsat,1 + VGS2 VB2 < VDD - Vsat,4 - VGS3 The figure plots the folded structure useful if we need to raise the voltage source of M1 F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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Small signal analysis: The output impedance is (conventional version):

rout =

(rds1g m 2 rds 2 )(rds4 g m 3rds3 ) rds1g m 2 rds 2 + rds 4g m3 rds3

[for the improved and folded version rds1 must be replaced with (rds1//rds5)] The DC gain is:

A v = −g m1

(rds1g m 2 rds 2 )(rds 4g m3rds 3 ) ≅ 1 (g rds1g m 2 rds 2 + rds 4g m3 rds 3

2

m rds

)2

The circuit has three nodes: • The output node • The source of M2 • The source of M3 F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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The transfer function will have three poles. The dominant one is the output pole

f p,out =

1 1 2 π rout C out

f2 =

1 1 2 π r2 C 2

f3 =

1 1 2π r3C3

Cout, C2, C 3 capacitances incident on nodes 1, 2, 3. At low frequency:

rout =

(rds1g m 2 rds 2 )(rds 4g m3rds3 ) rds1g m 2 rds2 + rds 4 g m3 rds 3

r2 =

1  g m 3rds 3rds 4  1 +  rds1 gm2  rds 2 

r3 =

1  g m 2 rds1rds 2  1 +  rds 4 gm3  rds3  rout >> r2 , r3


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At high frequency:

r2 →

1 gm2

r3 →

1 g m3

• Output swing: The output swing is limited by the conditions for which one of the transistors of the stage is brought out of saturation

Vout −max = VB 2 + VGS3 − Vsat 3

Vout −min = VB1 + VGS2 − Vsat 2

VB1 and VB2 must keep M1, M4, and M5 out of the triode region.


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Example Simulate the folded cascode amplifier, shown in the following figure, with VDD = 3.5V. Use the models BSIM 3V2 to find the gain and the phase from input to output and from input to node 2.

We observe that the gain and the phase plots of the output show a 20 dB roll-off with a good phase margin (60 degrees). The low frequency gain is 77 dB and the unity gain frequency is around 80 MHz. The behavior of the gain from the input to node 2 is interesting: above the dominant pole, it holds 14 dB, just 2 dB more than the expected value gm1/gm2. At low frequency climbs to 34 dB. F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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DIFFERENTIAL STAGE

M1, M2 in saturation with (W/L)1 = (W/L)2

assume:

I1 =

µC ox  W  2   (VGS1 − VTh ) 2  L 1

I2 =

µC ox  W  2   (VGS 2 − VTh ) 2  L 2

VGS1 = VGS0 +

vin 2

; VGS2 = VGS0 −

vin 2


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The output variable is the differential current:

W ∆I = I1 − I 2 = µC ox   vin (VGS0 − VTh )  L 1 since the bias current can be expressed as:

W ISS = I1 + I 2 = µC ox   (VGS0 − VTh )2  L 1 it results:

W ∆I = v in µC ox   ISS  L 1

at small signal: ∆i = v in g m

with a common mode signal:

iCM =

g m v CM v ≈ in 1 + 2g m ri 2 ri

CMMR =

id iCM

≅ 2g m ri


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Example

W ∆ I = v µ C  ISS . Consider an n-channel differential pair using in ox  Verify equation L  1 (W/L) = 100 µm and Iss = 100 µA.

The transconductance transfer function is fairly linear over a wide range of input signal. It starts to saturate only when the input signal approaches the overdrive voltage of the differential pair (75 mV). F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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SOURCE FOLLOWER Used as buffer or as DC-level shifter

at low frequency:

(g ds1 + g ds 2 )v out + g ds1v out − g m1v gs1 = 0

hence:

Av =

v out g m1 = vin g m1 + g ds1 + g ds 2 + g mb1


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If g m1 >> g ds1 + g ds2 + g mb1 then A v ≈ 1 at high frequency:

A v (S ) ≅

where:

C1 C1 + Cout

C = C L + C gd 2 + Cgd 2ov + C db2 + C sb1

C1 = Cgs1 + Cgs1ov

The output impedance is obtained by applying a test source Vx at the output node.

i x = (g ds1 + g ds 2 + g mb1 + g m1 )v x Hence:

R out =

1 1 ≅ g ds1 + g ds 2 + g mb + g m1 g m1

The output is not symmetrical. For n-channel input device

Vout −max = VDD − VGS1

Vout − min = Vsat 2


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Example Simulate the large signal behavior and derive the dc small signal voltage gain. IB = 0.1 mA and VDD = 3.3 V.

The output voltage, practically, follows the input shifted by VGS. However, due to the body effect, the value of VGS is not constant; it rises from 713 mV to 1.13 V. Therefore, the inputoutput characteristic is not 1 but 0.81. The figure shows also the dc gain: its value ranges from 0.74 to 0.86 quite well match as theoretical results. F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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IMPROVED OUTPUT STAGES Performances improved by the use of negative feedback.

i x = (g m1 + g ds 2 )v x + g m 4 v 2

R out =

v 2 = g m1rds 3v x

1 g m1 (1 + g m 4 rds3 ) + g ds 2


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Class AB push-pull:

 2L3 2L 4 V12 = VGS 3 + VGS 4 = VTh ,n + VTh , p + I 5  +  µ n W3Cox µp W4 Cox 

   

let:

W W   = k   L 1  L 3

W W   = k   L 2  L 4

With Rout = 0:

VGS1 ≈ VGS3 ;

VGS 2 ≈ VGS 4 ;

I1 = I 2 = kI5 ;

The output conductance is:

g out = g m1 + g m 2 With resistive load, the drop voltage across the output resistance determines (going out current):

VGS1 > VGS3 ;

VGS 2 < VGS 4 ;

I 2 = I1 − Iout


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For a given load I2 --> 0; the output conductance becomes gout = gm1 In general an output stage has the following equivalent circuit:

(

2 R out = R out 0 1 + α1I out + α 2 Iout + ...

)

It determines harmonic distortion


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Class AB push-pull with gain stage

Vg1 ≈ Vg 2

if it is verified the condition:

1 g m4

+

1 g m5

<< rds6


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Voltage divider • Analog circuits normally have only two dc voltage supplies

• In order to obtain dc bias voltages, voltage dividers can be used

• Resistive or capacitive dividers can be used, however they are complex or silicon area consuming

• MOS in the diode configuration can be used The transistors are in saturation

kW kW 2 2   (VDS1 − VTh 1 ) =   (VDS 2 − VTh 2 ) 2  L 1 2  L 2

VDS1 + VDS 2 = VDD F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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V1 = VDS1 =

α V − α 2VTh2 α2 VDD + 1 DS1 α1 + α 2 α1 + α 2

W α1 =    L 1

W ; α2 =    L 2

It results a voltage division of VDD plus an offset. If a signal (usually undesired) is superposed to VDD, the small signal equivalent circuit must be considered.

C1 = C gs1 + C db1 + C sb2

; C 2 = C gs 2

At low frequency (assuming gm2>>gds2 and gm1>>gds1) F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

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g mb g m1 g m1g m2 V1 = Vdd ⋅ 1 1 g mb + + g m1 g m 2 g m1g m 2 1

At high frequency

V1 = VDD ⋅

+

C2 C1 + C 2

It results an injectin of the noise from the power supply (VDD)


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Level Shifter Essential for NMOS circuits, useful for CMOS circuits • High-impedance level shift • Low-impedance, or “battery”, level shift

High Input Impedances:


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∆V = VGS =

2L I + VTh = Vov + VTh kW

• Body effect neglected • Threshold voltage variation effect (∆VTh ≈ +150 mV) • Input and output swing limitation Level shift threshold-independent:

∆V =

 2  L  L ( I − I ) − − I   2    1 2 k   W 1  W  2 

(assuming M1 in saturation and neglecting λ) usually ∆V < VTh


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Low Impedances: • It behaves like a voltage source

2L I + VTh kW

a)

∆V = VDS =

b)

 2L   2L  ∆V = VGS1 + VGS2 = VTh1 + VTh2 +   I1 +   I2 kW kW  1  2 a) Simple level shifter b) Shunt feedback level shifter

a) rout = 1/gm b) affected by twice voltage threshold variation


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Basic Building Block

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