11/ 8/ 12
ASI C in int erv ie iew Ques t ion & An Ans wer: AS ASI C Ve Verif ic ic at ion Share
0
More
Nex t Blog»
Create Blog
Sign In
ASIC interview interview Question & Answer A blog to collect the interview questions and answer for ASIC related positions
FPGA Sof tware FPGA tware Design Tool ispLEVER Starte r Trial Trial Download in 3 Easy Steps LatticeSemi.com/
semiconductor design desi gn Electronic Engineering Tim Times India daily news , technical paper & more www.eetindia.co.in
Yamaha FZ Yamaha 16/FZS for Sale Buy/Sell Buy/Sell Secon Secon d Han d Bikes Bikes & Get Best Deals. Quick, Easy & Free! Quikr.com/Yamaha-Moto Quikr.c om/Yamaha-Moto …
V erification ation.. Show al Showing post s with label ASIC Verific alll post postss Wednesday, April 21, 2010
ASIC Verification Interview Questions 1) What if design engineer and verifi cation engineer do do the the same mistake in Test bench BFM(Bus Functional Model) and RTL(DUT)? How can you able to detect errors? Answer: Ans wer: 1. Code reviews & protocol checkers checkers 2. IP gets verified in multipl multiple e environments environments .. like block block level level test bench, out of box tes tbench tbench (connecting (connecting DUT back to back) , full fledged testbench using proven BFM, SoC level testbench using processor and all that that etc... this all environments SHOULD SH OULD be execut ex ecuted ed by diferent persons and so you should be able able to catch that bug bug in one of this testbench ... 3. customer will catch the problem ( worst wors t case ) 2) If you got a failure from the the custom customer, er, how do you you debug this? How do you prevent it to happen again?
Learn C, C++, C# Find Top IT Institutes in India.Get all info on Courses,Admission,Fe Cours es,Admission,Fees es . www.Shiksha.com/C++-C www.Sh iksha.com/C++-C… …
TestBench VHDL Verilog C
Answer: Ans wer: 1. Fi rst, try to reproduce reproduce the problem problem in your own environment. Try to get customer's vector, so you can inject i nject the same v ector to create create the problem problem in house. 2. I f you confirm the problem problem and and fix them, you should put the the new ass ertion or test tes t to catch the problem problem again. Add this new test in the future test plan, so the problem will not happen again.
Graphic Graph ical al tes t bench generation generation for VHDL, VHDL, Verilog, Verilo g, & SystemC Syste mC www.s w.sy yncad.com
Labels ASIC Flow (1) asic-interview.blogspot.in/search/lab asic-interview.blogspot.in/search/label/ASIC el/ASIC Verification
Posted by Roy Chan at 9:40 AM
1 comment:
Labels: ASIC Verification
1/3
11/8/12
ASIC interv iew Question & Answer: ASIC Verif ication
ASIC Gate (3) ASIC Logic (4) ASIC Syste mVerilog (10) ASIC timing (2) ASIC Verification (1)
Get Common Platform IP
C++ (2) Design Complier (1) Memory Interface (1) Networking (2) perl (9)
Search by node, process & IP vendor Find Common Platf orm IP now. ChipEstimate.com/CommonPlatform
PLL (1) Previous Interview Qu estions (1) PrimeTime (1) SVA (2) Verilog Interview Q uestions (6)
Home
Blog Archive
Subscribe to: Posts (Atom)
▼ 2010 (49)
Search This Blog
Older Posts
► November (1) ► October (2)
Search
► June (2) ► May (2) ▼ April (7)
SystemVerilog I nterview Question 9 SystemVerilog I nterview Quest ions 7 SystemVerilog I nterview Quest ions 6 SystemVerilog I nterview Question 5 SystemVerilog interview Questions 4 Systemverilog I nterview Quest ions 3 ASIC Verification Interview Questions ► February (12) ► January (23)
Visitor's counter
Visitor Counter
About Me Roy Chan
asic-interview.blogspot.in/search/label/ASIC Verification
2/3
11/8/12
ASIC interv iew Question & Answer: ASIC Verif ication
Specialties in ASIC Design and Verification from front-end to backend activities, including RTL coding, verification (testbench development, testcase generation and test regression), logic synthesis, static timing analysis, Place and route, power analysis, ECO and final tapeout process. Currently, I am still looking for a new c areer. View my complete profile
There was an error in this gadget
asic-interview.blogspot.in/search/label/ASIC Verification
3/3
