6T CMOS SRAM CELL Design Report

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FOREWORD eSilicon is a fabless semiconductor company founded in 2000 and based Sunnyvale, California. eSilicon designs and manufactures digital CMOS ASICS. eSilicon is considered a pioneer of the fabless ASIC model and is the world’s largest fabless ASIC supplier. eSilicon’s headquarters is in Sunnyvale, California. eSilicon has offices in Allentown, PA, New Providence, NJ, Bucharest, Romania, Yokihama, Japan and VietNam(on design center in Ho Chi Minh city and another in Da Nang city) eSilicon provides physical design, design for test insertion, package design, product qualification, IP licensing, and manifacturing services for difital CMOS ASICs. eSilicon has announced products in 25um,18um, 13um, 90nm, 65nm,40nm and 28um process technologies. Customer ASICs have been announced in a wide range of appplications including digital cameras, portable multimedia players, inkjet printers, networking and high performance computing. In February 2008 it was announced that eSilicom had licensed Avago Techologies high performance 90nm and 65nm SerDes technology for use in eSilicon’s customer’s designs. For the purpose of enabling studens to have access to the real working environment. Electronics-Telecommunications Department, Da Nang University of Technologies And Union Corporation eSilicon Vietnam have created favorable conditions for us to practice at company. I would send the most sincere gratitude to company, whom enthusiastically helped us during prative.

Reporter : Vo Thanh Liem

Supporter : Nguyen Ba Mich

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CONTENTS FOREWORD………………………………………………………….……………...1 CONTENTS………………………………………………………………….……….2 CHAPTER1 UNIX OVERVIEW………………………………………………….…3 CHAPTER2 SCHEMATIC AND CIRCUIT SIMULATION………………………6 2.1 Schematic………………………………………………………………………....6 2.2 Circuit Simulation……………………………………………..………………….8 2.3 Inverter Simulation…………………………………………………..…………...9 2.3.1 Inverter Introduction…………………………………………………..………..9 2.3.2 Inverter Simulation………………………………………………..……………9 CHAPTER3 MINI PROJECTS : 6T CMOS SRAM CELL………………..………13 3.1 SRAM overview………………………………………………………...………13 3.2 6T SRAM CELL Simulation………………………………………….…...……17



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CHAPTER1

UNIX OVERVIEW

UNIX OPERATING SYSTEM Unix is an operating system which was first developed in the 1960s, and has been under constant development ever since. By operating system, we mean the suite of programs which make the computer work. It is a stable, multi-user, multi-tasking system for servers, desktops and laptops. Unix systems also a graphical user interface(GUI) similar to Microsoft Windows which provides an easy to use enviroment. Howeverm knowledge of Unix is required for operations which aren’t convered by a graphical, or for when there is no windows interface available, for example, in a telnet session. The Unix operating system is made up of three parts : the kernel, the shell and the programs. The Kernel The kernel of Unix is the hub of the operating system : it allocates time and memory to programs and handles the filestore and communications in response to system calls. As an illustration of the way that the shell and the kernel work together, suppose a user types rm myfile(which has the effect of removing the file myfile). The sghell searches the filestore for the file containing the program rm, and then request the kernel, through system calls, to execute the program rm on myfil. When the process rm myfile has finished running, the shell then returns the Unix prompt % to the user, indicating that it is waiting for further commands.



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The shell The shell acts as an interface between the user and ther kernel. When a user logs in, the login program checks the username and password, and then starts another program called the shell. The shell is a command line interpreter(CLC). It interprets commands the user types in and arranges for them to be carried out. The commands are themselves programs: when they terminate, the shell gives the user another prompt(% on our systems). The adept user can custumise his/her own shell, and users can use different shell on the same machine. Staff and students in the school has certain features to help the user iputting commands. Filename Completion – By typing part of the name of a command, filename or diractory and pressing the [Tab] key, the tcsh shell will complete the rest of the name automatically. If the shell finds more than one name beginning with those letters you have typed, it will beep, prompting you to type a few more letters before pressing the tab key again. History – The shell keeps a list of the commands you have typed in. If you need to repeat a command, use the cursor keys to scroll up and down the list or type istory for a lisy of previous commands. Several shell available with Linux including: Bourne, C, Korn shell …etc. But we consider only C-shell.



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How to use Shell To use shell (You start to use your shell as soon as you log into your system) you have to simply type commands. What is Shell Script ? Normally shells are interactive. It means shell accept command from you (via keyboard) and execute them. But if you use command one by one (sequence of 'n' number of commands) , the you can store this sequence of command to text file and tell the shell to execute this text file instead of entering the commands. This is know as shell script. Shell script defined as: "Shell Script is series of command written in plain text file. Shell script is just like batch file is MS-DOS but have more power than the MS-DOS batch file." Why to Write Shell Script ? • • • • •

Shell script can take input from user, file and output them on screen. Useful to create our own commands. Save lots of time. To automate some task of day today life. System Administration part can be also automated.



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CHAPTER 2

SCHEMATIC & CIRCUIT SIMULATION

2.1 SCHEMATIC To complete a schematic we have to go through these steps : Start Custom Designer

Creat A Design Database

Create A Schematic

Topology Overview

Create Instance

Add Pins

Add Wires

Create Wire Names

Check And Save The



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Step 1 : To Run Custom Design(CD) sofware, we have to create C-script, which includes path of CD run-file, path of license-key file, path of library definition files(library difination file indicate to path of library folder), and some other necessary information. Step 2 : Creating a design folder. Step 3 : Creating schematic cells in design folder. Step 4 : Overviewing topology. Step 5: Adding instances and changing accordingly the parameters of instances, then arranging reasonable in order and wiring the pins of instances. Step 6 : Adding input and output pins Step 7 : Creating wire names Step 8 : Check and Save.



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2.2 CIRCUIT SIMULATION To simulating a circiuit, we must first run Simulation Sofware. To running Simulation Sofware we have to create a C-script, which includes path of run-file, path of license-key file, path of input and ouput file.

+ Input file : including paths of 4 files : options file(some options for simulation : file.option), netlist file(the wired of instances : file.spi), setup file(initial circuit paramaters and input waveforms : file.setup ) and model file(parameter of instances). + Output file : containing simulation results.



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2.3 INVERTER SIMULATION 2.3.1 Inverter Inverter is most basic gate in CMOS technology. It includes pull-up network with PMOS and pull-down network with NMOS. Ouput signal be inverted compared with input signal. 2.3.2 Inverter Simulation a\ Vout follow on Vin



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0-2ns : Vin=0, Vout=Vdd : P1 turn on, ouput be pulled up to Vdd and N0 turn off, holding high impedance state. 2-2,02ns : Vin increase from 0V to Vdd to cause P1 impadence ascending and impadence N0 descending. At the moment, from source to mass seeing Rp1 and Rn0 as two serial resistors, so current follow from source to mass drop on ouput a voltage : Vout=Vdd.Rn0/(Rn0+Rp1) So when Vin descending then Vout ascending until Vin is 0 then Vout is Vdd. There is an inportant point of inverter should be noted that delay Td(the time distance between 50% amplitude of input and output), suppose that Vout is floating, if Vout


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b\ Idd theo Vsup

In this simulation, we vary voltage supply, increasing linearly from 0.8Vdc to 1Vdc. Based on result show that, when voltage supply increase then Idd current increase nonlinearly(in absolute value).



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c\ Idd theo Width

In this simulation, we vary width of PMOS from 100nm to 500nm. Based on the results show that Idd current increases(in absolute value) when channel width increases, but as voltage, it does not inrease linearly.



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MINI PROJECT

Chapter 3

DESIGN AND SIMULATION 6T CMOS SRAM CELL 3.1 SRAM Overview There are two key features to SRAM - Static Random Access Memory, and these set it out against other types of memory that are available : 1. The data is held statically : this means that the data is held in the semiconductor memory without the need to be refrehed as long as the power is applied to the memory. 2. SRAM is a from of random access memory : a random access memory is one in which the locations in the semiconductor memory can be written to or read from in any order, regardless of the last memory location that was accessed.

There are many different types of semiconductor memory that are available these days. Choices need to be made regarding the correct memory type for a given application. Possibly two of the most widely used types are DRAM and SRAM memory, both of which are used in processor and computer scenarios. Of these two SRAM is a little more expensive than DRAM. However SRAm is faster and cinsumes less power especially when idle. In addition to this SRAM memory is easier to control than SRAM as the refresh cycles do not need to be taken into account, and in addition to this the way SRAM can be accessed is more exactly random access. A further advantage if SRAM is that it is more dense than SRAM As a result of these parameters, SRAM memory is used where speed or low power are considerations. Its higher density and less complicated structure also lend it to use in semiconductor memory scenarios where high capacity memory is used, as in the case of the working memory within computer. Reporter : Vo Thanh Liem


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A 6T CMOS SRAM cell is the most popular SRAM cell due to its superior robustness, low power and low-voltage operation. Therefore, we will discuss its operation and design in greater detail. An SRAM cell must be designed such that it provides a nondestructive read operation and a reliable write operation. These two requirements impose contradicting requirements on SRAM cell transistor sizing. SRAM cell transistor ratios that must be observed for successful read and write operations are discussed in the following sections. 6T CMOS SRAM CELL :

6T SRAM Cell stored one binary bit have six Transistors comprises two CrossCoupled Inverter and two Access Transistors. In this format the circuit has two states, and these equate to the logical “0” and “1” states. In addition to the four transistors in the basic memory cell, and additional two transistors are required to control the access to the memory cell during the read and write operations. This makes a total of six transistors, making what is termed a 6T memory cell.

READ-WRITE CIRCUIT 6T CMOS SRAM CELL :



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Sense amplifiers (SA) are an important component in memory design. The choice and design of a SA defines the robustness of bit line sensing, impacting the read speed and power. Due to the variety of SAs in semiconductor memories and the impact they have on the final specs of the memory, the sense amplifiers have become a separate class of circuits. The primary function of a SA in SRAMs is to amplify a small analog differential voltage developed on the bit lines by a read-accessed cell to the full swing digital output signal thus greatly reducing the time required for a read operation. Since SRAMs do not feature data refresh after sensing, the sensing operation must be nondestructive, as opposed to the destructive sensing of a DRAM cell. A SA allows the storage cells to be small, since each individual cell need not fully discharge the bit line. The function of the SRAM Write Driver is to quickly discharge one of the bit lines from the precharge level to below the write margin of the SRAM cell. Normally, the write driver is enabled by theWrite Enable (WE) signal and drives the bit line using full-swing discharge from the precharge level to ground. The order in which the word line is enabled and the write drivers are activated is not crucial for the correct write operation.



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3.2 6T SRAM CELL Simulation6T SRAM CELL Schematic



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********************************* * THIS IS INPUT FOR SIMULATION *

.option POST = 1 .option BRIEF = 1 .option DCSTEP = 1 .inc "/data/training/trainee/center/pdk/models/28hp/hspice_options" .inc "/data/training/trainee/center/pdk/models/28hp/cln28hp_tt_model" .inc "/users/vliem/general/circuit/my_design/cell/cell.spi" .inc "/users/vliem/general/circuit/my_design/cell/cell.setup" .end

********************************* The input file contains some options; the path indicates instances model(cln28hp_tt_model) location; the path indicates netlist file(cell.spi), netlist file decribes how the gate of instances wired by functions; the path indicates detup file(cell.setup), setup file decribes initial circuit parameters, sweeping in time or frequency or others domain, wave form for input gates …etc.



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*********************************** *THÍS IS SET UP FOR SIMULATION*

.temp = 25 .param Vsup=0.8 VVDD Vdd 0 Vsup VVSS Vss 0 0 .ic V(out)=Vsup V(out_b)=0 Vpcbl pcbl 0 PULSE (0 Vsup 30ns 0.01ns 0.01ns 30ns 60ns) Vwl wl 0 PULSE (0 Vsup 30ns 0.01ns 0.01ns 30ns 60ns) Vwe we 0 PULSE (Vsup 0 30ns 0.01ns 0.01ns 30ns 60ns) Vd d 0 PULSE (0 Vsup 30ns 0.01ns 0.01ns 30ns 120ns) .TRAN 0.01ns 1000ns .PROBE TRAN v(*) i(*)

*********************************** Setup file sets initial circuit parameters : temparature is 25 degrees Celsius, voltage supply source is 0.8Vdc, pcbl wl we d gates are supplied PULSE wave form with time domain parameters follow to that syntax. And we simulate on time domain from 0ns to 1000ns with step is 0.01ns(TRAN 0.01ns 1000ns).



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Netlist file is quite long to add details into this documents, we only consider a basic syntax of the netlist file : ------------------------------------------------------------------------------------------------.subckt nmos b d g s ln=0 mm=1 nnf=1 wn=0 xi0 d g s b nch_mac l='ln' w='(wn*nnf)' multi='mm' nf='nnf' sd=0.1u ad=7.5e-15 + as=7.5e-15 pd=3.5e-07 ps=3.5e-07 nrd=1.333276 nrs=1.333276 dfm_flag=0 .ends nmos xn1 vss out out_b vss nmos ln=0.035u wn=0.28u -------------------------------------------------------------------------------------------------

The italic is define for nmos b d g s (bulk drain gate source) and some default parameters as lengh, width …etc. nmos model is taken from model file. The bold is define for instances or input-output wired together. Here are b d g s will be connected to the corresponding vss vout out_b vss, and n1 is changed two parameter are lengh and width.



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1 Write Process

0-1ns

initial circuit values out=1; out_b=0; pcbl=1; wl=0; d=x; pcsa=1; saen=0;

(Vdd logic level is 1). 1-2ns pcbl=0 causing Pc1,Pc2,P7 turn on and C5-C6 charged from 0 to Vdd. Because P7 turn on, so bl and blx voltage are balance or both C5-C6 voltage are Vdd. we=0 causing P11,P12 turn off isulating Read Circuit and Sensing Ciruit from Cell, at the same time making logic level of two NOR output opposite with ‘d’, and controlling Write Operation.



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2-3ns

Suppose we write 0 on cell, this mean d=0 causing I2=1,I1=0. So N29 turn

on and N30 turn off. At the same time wl=Vdd causing N11,N22 turn on. Because C5-C6 have been charged up to Vdd so C5 discharged through N29 to mass and C6 discharged through N22, N2 to mass(because out=Vdd, out_b=0 so N2 turn on and N1 turn off). However

N29 : w/l=2u/0.035u N22 : w/l=0.21u/0.035u N2 : w/l 0.28u/0.035u

So

Rn29 << Rn22+ Rn2(*)



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a) From (*) we show that C5 would be discharged much faster than C6 causing bl voltage reduced faster than blx voltage. bl voltage reduced fastly causing P27 turn on fastly,N2 turn off fastly, which full blx voltage up to Vdd and blx voltage reduced slowly causing P28 turn on slow so blx kept at high voltage(nealy equal to Vdd). In C5 discharged operation, VGSn11 ascending(VGSn11=Vdd-Vbl), VDn11=Vdd so when VGSn11 < VT that n11 still turn off, but when VGSn11 > VT that n11 turn on, and there are the current follow from supply source to P1, N11, N29, mass. Vout=(Vdd.(Rn11+Rn29)/(Rp1+Rn11+Rn29)) Because Rn11+Rn29 < Rp1 so Vout < Vtrip1 causing Vout tendancy pulled-down to mass, then out start pulled-down to mas. b) At the same time with a) Capacitor C6 discharged through N22, N2, mass also. N2 : w/l=0.28u/0.035u N22 : w/l=0.21u/0.035u Nên Rn22 > Rn2 Vout_b = ((Vblx.Rn2)/(Rn2+Rn22)) Vout_b pulled-up upper mass but Vout_b < Vtrip2 so Vout_b havn’t been pulled-up to Vdd. Until Vout reduced, N2 turn weaker and Vout_b increase again. This process amplifiered by Cross-Coupled Inverter(Possitive feedback) causing Out=0 : P2 turn on, N2 turn off, out_b=Vdd : P1 turn off, N1 turn on. 3-4ns :

bl charged again by pcsa=0, we=1 . Until wl=1, N11 turn on, C5 discharged

through N11, N1 to mass so Vout increase upper than mass but Vout still smaller than Vtrip1 because of Rn1 < Rn11. Same to Vout_b.



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*Write ‘1’ process operate same to writing ‘0’ but writing ‘0’ operate at out_b not out, this mean that writing ‘1’ at out. 2 Read Process

2-3ns :

we=Vdd causing P11,P12 turn on; pcsa=0 causing P9,P10 turn on, putting

Vdd on rbl, rblx but there is resistor on P11 betwwen supply source and capacitor C5 so C5 charged not full and C13 same to.

3-4ns :

saen=Vdd causing N16 turn on(sensing circuit start to oparate).



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Because bl, rbl and blx, rblx charged not full (Vbl=Vc5=0.6V, Vrbl=Vc13=0.74V). And wl=Vdd so C5,C13 discharged through two way : N11, N1, mass and N15, N16, mass. C6, C14 discharged through only way : N17, N6, mass. On the other hand, size of N15,N16 and N17,N16 are same together, so C15,C13 discharged faster than C6,C14. And Rn11,Rn1 >> Rn15,Rn16 so C5,C13 discharged much faster, causing Rn17 rapid increase, as do C6,C14 discharged slowly(N15 still turn on). Until rbl recuded upper Vtrip of NOR_out gate then this gate would be opposite state. 3 Toàn bộ quá trình ghi và đọc



6T CMOS SRAM CELL Design Report

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