Simple 6T SRAM implementation ELECTRONICS FINAL PROJECT (1ST YEAR ELECTRICAL ENGINEERING)
Azza Abdelhamid Faiad SECTION 9 | ID:290
1
Introduction ..................................................................................................... 2
2
Review of literature ......................................................................................... 2 2.1
2.1.1
For a read operation ............................................................................ 3
2.1.2
For a write operation ........................................................................... 3
2.2 3
SRAM basics .............................................................................................. 2
Different SRAM topologies and architecture ............................................. 3
Materials and Methods.................................................................................... 4 3.1
Hardware implementation ........................................................................ 4
3.2
LTspice simulation ..................................................................................... 5
4
Results ............................................................................................................. 6
5
Conclusion ....................................................................................................... 8
6
References ....................................................................................................... 8
Simple 6T SRAM simulation The usage of SRAM is continuously increasing in system-on-chip (SOC) designs. Process technology scaling has contributed remarkably in improving the performance of and area density of SOC. The SRAM cell typically utilizes the minimum sized transistor in order to realize a high density. With the result impact of increased intra die variations with the technology scaling is more pronounced on the SRAM cells. SRAM cells must be able to hold, read and write data. Ideally very fast, on minimum area, with low leakage and high yield. The goal is to design a cell that provides the best trade-off between all these qualities. The objective of this report is to describe the design and implementation of a 6-transistor SRAM cell as a direct application of MOSFETs (utilized as switches). The basic operation and constraints of static RAM will be discussed, along with transistor sizing for device stability. The design will be covered using a symbolic schematic, as well as a hardware implementation. Finally, the read and write operations will be confirmed by simulation (using LTspice)
The SRAM cell incorporates a static latch, comprising two cross-coupled inverters, so that it does not require periodic refreshing to retain the stored information like DRAM, provided that there is adequate power supply voltage for the cell.
Figure 1: Schematic diagram of typical 6T SRAM
The 6-T SRAM cell operates as follows:
The bit-lines are usually pre-charged to a high level (VDD) and then the word-line is selected (pulsed to a high level). On the side of the cell storing a logical ‘0’ (i.e., a low voltage), the bit-line is discharged via the pass-gate transistor and pull-down transistor, so that a differential voltage develops between the bit-lines. This differential voltage should be large enough for a sense amplifier to detect the state of the cell. The differential voltage should not be too large, however; otherwise the cross-coupled inverters could flip their state. (The read operation should be nondestructive.) The cell beta ratio, which is the ratio of the strength (drive current) of the pull-down transistor to that of the pass-gate transistor, should be sufficiently large to ensure that such a read disturbance does not occur.
The bit-lines are driven to complementary voltage levels via a write driver and then the wordline is selected. On the side of the cell for which the bit-line voltage is logical ‘0’ (i.e., a low voltage), the internal storage node is discharged through the pass-gate transistor. The cross-coupled inverters raise the voltage on the opposite storage node and latch the cell. The discharging strength of the pass-gate transistor must overcome the restoring strength of the pull-up transistor. The cell gamma ratio, which is the ratio of the strength of the pass-gate transistor to that of the pull-up transistor, should be sufficiently large to ensure that write failure does not occur.
The transistors within a 6-T SRAM cell must be sized properly (since drive current is proportional to transistor width) for the cell to meet both read and write margin specifications to guarantee proper operation. There is a fundamental tradeoff, therefore, between cell yield and cell layout area (i.e., cost). This tradeoff is manipulated by the need to include design margin for processinduced variations in transistor threshold voltage (VT) since drive current is a function of VDD – VT. Various alternative SRAM bit-cell architectures have been proposed to reduce cell area or to decouple the requirements for read stability and write-ability. Among these topologies:
The 4-T SRAM cell consists of two PMOS pass-gate transistors and two NMOS pull-down transistors, resulting in relatively smaller cell area than the 6-T SRAM design. It maintains a logical ‘1’ state at one of the internal storage nodes via PMOS transistor off - state leakage current. This results not only in higher static power consumption but also in l arger susceptibility to VT variation (since transistor off-state leakage current varies
exponentially with VT), so that the 4-T SRAM cell architecture is not promising for sub-22 nm SRAM technologies.
The 7-T SRAM cell utilizes dedicated word- lines and bit-lines f or read vs. write operations to avoid the possibility of a read disturbance even if the read SNM is lower than 0, so that minimum-width transistors can be used for minimal cell area. The 8-T SRAM cell also utilizes dedicated word-lines and bit-lines for read vs. write operations, but uses complementary bit-lines for write operation as does a 6-T SRAM cell. Write disturbance is still a general issue for these alternative cell architectures. The 10-T SRAM cell decouples the storage nodes from the bit-lines to improve read stability, but requires the use of peripheral write-assist circuitry. These alternative SRAM cell architectures each have undesirable tradeoffs in cell area or performance as compared to the 6-T SRAM cell. This thesis therefore focuses on technological approaches to improve the scalability of the 6-T SRAM cell.
Project implementation was achieved through 2 main methodologies
The following materials were used in implementing 1 cell 6TSRAM
8 2N7000 N-channel MOSFETs
4 IRF 9540 P-channel MOSFETs
1 LED
1 Resistor to match LED current
2 Buttons
2 Resistors 1k
Wires
A breadboard
5 Volt Power Supply
Procedures
1. 6T SRAM cell It is 2 CMOS inverters with an enable circuit on both sides. The output of one inverter is connected to the input of the other and vice versa. This creates a simple latch because when one of the inputs is low, that inverter's output goes high, this makes the other inverter's input high, so its output is now low. To change the inverters' states, a high current is plugged into the low side AND a low current on the high side. This pulse is enough to change the input of that inverter, so the output changes, and the circuit latches again, but in the opposite state. The enables connect and disconnect it from the rest of the circuit.
2. The N-channel MOSFET will turn on when it's gate is brought up to the supply voltage, typically 3.3v or 5v, and turn off when the gate it brought down to ground. 3. The P-channel MOSFET will turn on when it's gate is brought down to ground and turn off when it's gate is brought up to the supply. 4. Construction of 2 inverters. They are simply a IRF 9540 and a 2N7000 with their drains connected together. 5. Now we are going to connect the inverters together. The output of one is connected to the input of the other. To do this, connect a wire to pin 2 of a transistor on the left inverter and connect it to the output of the other transistor. The output of the inverter is where pin 3 of the IRF 9540 and pin 1 of the 2N7000 are connected together. Repeat this, but with the input of the right inverter and the output of the left one. 6. The enable is simple. One 2N7000 has its rounded side facing you, the other has its flat side facing you. The right-most pin of the left transistor is connected to the left-most pin of the right transistor. Next, the gates get connected together via a wire. Lastly, we need to connect the enable to the SRAM bit. To do this, put a wire on either the very left or very right pin. Next, put the other end of the wire on the gate of the closest inverter. 7. Making another enable on the other side of the circuit, and connect it up. 8. Connect the gates of the enables together then connect another wire from ground to one of the gates. 9. Add the LED and resistor by putting a resistor on the output or gate of one inverter then to the positive lead of the LED and ground the negative lead of the LED. 10. Plug in your power supply, turn the supply on and enable the circuit by disconnecting the gates from ground and setting to +5v. The LED should turn on, or off. If it holds its state, disable the circuit and switch the wires around, as in the input that was grounded should be set high and vice versa. If the LED still doesn't change, check your circuit. 11. One pin gets tied to +5v and the other is tied to ground through a resistor. The output of the button is the pin that is tied to ground. 12. The Write Enable button output connected to the enable gates. The output of the Bit Line button is connected to the first inverter's input. Its output goes to the enable and to the second inverter's gate. Its output goes to the other enable. I'm not going into detail on building the inverters, because I already covered that. 13. To turn the power supply on again and try out your new RAM. To verify the operation of 6TSRAM, the LED's state changes when the write enable is high, but it should latch when the write enables it low.
To achieve a simulation of a single cell of 6T SRAM, 0.35u CMOS Spice models [13] were used and thus Setting up 0.35u CMOS symbols and model library for LTspice was installed. The following schematic was constructed to achieve low power reading process as the peak voltage was 1.5 V.
Figure 2: Schematic of 0.35um 6T SRAM (writing process)
Different time ranges (from 10-40 ns to 10-20 us) were tested for the bit line and bit line bar pulses based on literature as well as curve optimization on LTspice.
Hardware implementation results were verified by constructing the previously mentioned circuit in hardware implementation subsection. The results were computed by a simple test on the LED, multiple pushes were tested to assure the writing and reading process.
Figure 3: Voltage pulses were plotted for each voltage source in the schematic: word line, bit line, bit line bar
Figure 4: Full simulation of Q nodes
Figure 5: Writing low process
Figure 6: Writing high process
The simulation results above demonstrate that this 6T SRAM cell design operates correctly for all reading functions: write HIGH, write LOW. As Fig. 6 shows, the write HIGH function is successful in flipping the bit, changing q from LOW to HIGH. Similarly, Fig. 5 shows that the write LOW function is successful, flipping the bit again and changing q from HIGH to LOW. Here, it’s worth noting that although Fig. 14 is virtually identical to Fig. 12 (just with the bit-lines and the q-nodes reversed), during the write LOW q drops to 0V, and it’s there before the word line finishes rising. While this may make it might seem like writing a LOW is faster than writing a HIGH. Whatever data value is being written, the same period of time is needed for the cell to become stable.
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