Share
Report Abuse
Next B l o g»
Cre ate B l og
VLSI Concepts You will find the basics of VLSI design in this place. Join Club Mahindra Today 7 Days Of Holidays Every Year For Next 25 Yrs. Sign Up Now & Enjoy. ClubMahindra.com/Fun-F Jobs For 2-10 Yrs Exp Jobs For 2-10 Yrs Exp Professionals Submit Your Resume On Shine.com Now www.Shine.Com/Te GSI Technology SRAMs Fas Fastes testt networking networking memories on the planet. Availabl e NOW. www.gsitechnology.com
Home
Content
V LS LSI Glos sa sar y
Dif f er er en ent File For ma mats ( f ile ex te tens io ions )
THURSDAY, APRIL 7, 2011
Contac t Me
SEARCH T HIS BLOG
Search
"Setup and Hold Hold Time" : Stati Static c Timing Analysis (STA) basic (Part 3a)
powered by
TOTAL PAGEVIEW S
P ar ar t 1
P ar ar t 2
P ar ar t 3a 3a
P ar art 3b 3b
P ar art 3c 3c
P ar ar t 4
P ar ar t 5
P ar ar t 6
41,913 FOLLOWERS
Static Ti ming analys analysis is is divided i nto several several parts: parts: Part1 -> Timing Paths Part2 -> Time B orr orrowing owing Part3a -> Basic Basic Concept Of Se tup and Hold Part3b -> Basic Concept of Setup and Hold Vi olati on Part3c -> -> Practical Examples for Setup and Hold Tim e / Viol ation Part4 -> Delay Note: Part 4, 5 and 6 are still still under development.
Its been long time, people are asking about Setup and Hold time blog. Finally time come for that. :) The way we will disc discus uss s this concept concept in the foll owing manner 1. What is SetUp and Hold tim e? 2. Definition of Setup and Hold.
POPULAR POSTS
Join this site "Timing Paths" : Static Timing Analys is (STA) basic (Part 1)
I saw that lots of people are confused with respect to this concept. And the reason reas on of this are 1. They know know the definition but don't know know the origin or say concept concept behind Setup and Hold timing. 2. They know the formula for calculating setup and hold violation but don't know how this formula formula come in picture.
Members (27) More »
"Setup and Hold Time" : Static Timing Analys is (STA) basic (Part 3a) "Setup and Hold Time Violation" : Static Timing Analys is (STA) basic (Part 3b) "Examples Of Setup "Examples and Hold time" : Static Timing Analys is (STA) basic (Part 3c)
3. Setup and Hold Violation. 4. How to calculate the Setup and Hold violation in a design?
with Googl Googl e Fri end Connect
"Time Borrowing" : Static Timing Analys is (STA) basic (Part 2) Antenna Anten na Eff ects Synopsy s Design Design Constraints Constrain ts (SDC) Basics
3. They become conf confus use e by few of the terminology li ke capt capture ure path delay, l aunch path delay, previous clock cycle, cycle, current clock cycle, cycle, data path delay, slew, setup slew, hold slew, min and max concept, slowest path and fastest path, min and max corner, best and worst case etc during the explanation of Setup and Hold Timings/Violation.
How To Read SPEF
I hope I can clarify your confusion. Let me explain this and if you face any problem le t me know. know.
Basic of Timi Timing ng Analy Anal y sis in Physical Design
Clock Reconvergence Reconvergen ce Pessimism (CRP) basic
Alr eady a member? Sign in
BLOG ARCHIVE
▼ 2011 (16) ► August (1) ► May (1) ▼ April (2) "Setup and Hold Time Violation" : Static Timing An... "Setup and Hold Time" : Static Timing Analys is (ST... ► March (5) ► February (7) ► 2010 (5)
What is Setup and Hold time? ABOUT ME
► 2008 (1)
Sign In
understand it with respect to a S ystem as shown i n the fig. An Input DIN and external cl ock CLK are buffered and passes through combinati onal l ogic before they reach a synchronous input a nd a cl ock input of a D fli pflop (positive e dge triggered). Now to capture the data correctly at D fli p flop , data should be present at the time of positive edge of cl ock signal at the C pin ( to know the detail just read basis of D flipflop). Note: here we are assumin g D fli p fl op is ideal so Zero hold and setup time for this.
you View prof i
Ve Ve Ex Re xer
G Ex pe hi Vi ww SetUp and Hold Time of a System
Fr in There may be only 2 condition. Tpd DIN > Tpd Clk For capture the data at the same ti me when Clock signal (positive clock edge) reaches at pin C, you have to apply the in put Data at p in DIN "T s(in)=(Tpd DIN) - (Tpd Clk)" ti me before the positive cl ock edge at pin CLK. In other word, at DIN pin, Data should be stable "Ts(in)" ti me before the positive clock edge at CLK pin. This Time "Ts(in)" is know as Setup time of the System. Tpd DIN < Tpd Clk For capture the data at the same time when clock signal (positive clock edge) reaches at pin C, input Data at pin DIN should not change before "Th(in)= (Tpd Clk) - (Tpd DIN)" time. If it will change, positive clock edge at pin C will capture the next data. In other word, at DIN pin, Data should be stable "T h(in)" time after the p ositive clo ck edge at CLK pi n. This time "Th(in)" is know as Hold Time of the System. From the above condition it l ooks like that both the conditi on can't exist at the same ti me and you are right. But we have to consider few more things in this. Worst case and best case (Max delay and min delay) Because of environment conditi on or because of PVT , we can do thi s analysis for the worst case ( max delay) and best case ( min delay) also. Shortest Path or Longest path ( Min Del ay and Max del ay) If combinational logic has multiple paths, the we have to do this analysis for the shortest path ( min delay) and longest path ( max del ay) also. So we can say that above conditi on can be l ike this. Tpd DIN (max) > Tpd Clk (min) SetUp time == Tpd DIN (max) - Tpd Clk (min) Tpd DIN (min) < Tpd Clk (max) Hold time == Tpd Clk (max) - Tpd DIN (min) For example for combinational logic del ays are Data path (max, min) = (5ns, 4 ns) Clock path (max, min) = (4.5ns, 4.1ns) Then Setup time= 5-4.1=0.9ns Hold tim e is = 4.5-4=0.5ns Now simi lar type of explanation we can give for a D flip fl op. There is a combin ational logic between C and Q , between D and Q of the Flipflop. There are different delays in those conbinational logic and based on there max and min value , a flipflop has Setup and Hold tim e. One circuitry of the positive edge triggered D fli p is shown below.
FOLLOW BY EMAIL
Ev ev ne Cl olx.
FP Ve Di us i ki t ww
Gr Pr Pe pl Si ww
Submit
Positive Edge Triggered D flip-flop
There are different ways for making the D flip flop. Like by JK fli pflop, master slave fli pflop, Using 2 D type l atches etc. Si nce the internal circuitry is different for each type of Fli pflop, the Setup and Hold tim e is different for every Flipflop. Definition: Setup Time: Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous circuits such as the flip-flop. Or In short I can say that the amount of time the Synchronous input (D) must be stable before the active edge of the Clock. The Time when input data is available and stable before the clock pulse is appli ed is called Setup ti me. Hold time: Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flip-flop. Or in short I can say that the amount of time the synchronous input (D) must be stable
after the active edge of clock.
The Time after clock pulse where data i nput is held stable is called hold ti me.
Setup and Hold Violation: In simple languageIf Setup time is Ts for a flip-flop and if data is not stable before Ts time from active edge of the clock, there is a Setup violation at that flipfl op. So if da ta is changing in the non-shaded area ( in the above fig ure) before active clock edge, then it's a Setup violati on. And If hold time is Th for a flip flop and if data is not stable after Th time from active edge of the clock , there is a hold violation at that flipfl op. So if da ta is changing in the non-shaded area ( in the above fig ure) after active clock edge, then it's a Hold violati on. How to calculate the setup and hol d violati on in a design.. pl ease see the next blog. <<< P revious
Posted by your VLSI at 3:09 PM
Reactions:
Next >>>
10 comm ents: anil said... this is really usef ul... thank you very m uch... Really looking forward f or your f uture posts.. . April 20, 2011 5:41 PM
your VLSI said... Thanks f or such comments . I will update you once there will be any new post. y ou can also subscribe to my blog or by t witter account to get a regular update. April 21, 2011 10:27 AM
Anon ymous said.. . Nice explanation with usef ul examples. Thanks! ! April 23, 2011 11:26 PM
Anon ymous said.. . y our work is really v ery helpful.. July 6, 2011 12:25 AM
Anon ymous said.. . Thanks man ur work cleared most of my concepts.... July 14, 2011 11:14 PM
Anon ymous said.. . it was like drinking water in the middle of t he desert. so satisf y ing August 3, 2011 2:35 AM
your VLSI said... one of t he nice compliment I ev er get. thanks man August 3, 2011 2:20 PM
Anon ymous said.. . what is meaning of negativ e propagation delay ? and how to obtain it? August 11, 2011 2:50 AM
naveen said... Hey. . This blog is awesome. I was v ery c onfused with setup and hold time. I had to attend NVIDIA interv iew. Very happy tat i got t o know this blog at the right time. I was able to answer qns on setup and hold time v iolations. And i got selected.. Thanks a lottt ttt ttt ttt :) August 12, 2011 5:44 PM
your VLSI said... Hi Nav een, Thanks f or compliment.. and congrats f or NVIDIA selection. i am happy f or you. Hi Anonymous- with respect to negativ e propagation delay .. I am going to post it in FAQ section. Y ou will find that soon. Drop a mail to my mail id ... I will let y ou know as soon as I post their. August 16, 2011 11:52 AM
Post a Comme nt
Comment as: Selectprofile... PostComment
Preview
Links to this post Create a Link Newer Post
Home
Subscribe to: Post Comments (Atom)
Vlsi expert group. Simple template. Powered by Blogger .
Older Post
