Static Timing Analysis
Selva Kumar R.
[email protected]
Overview
Even though a digital circuit may be logically correct, one needs to know how it will perform on physical implementation Timing analysis is required • To meet a performance specification • To evaluate how the design operates Timing Analysis : Point-point analysis of design without stimulus vectors
Overview
Even though a digital circuit may be logically correct, one needs to know how it will perform on physical implementation Timing analysis is required • To meet a performance specification • To evaluate how the design operates Timing Analysis : Point-point analysis of design without stimulus vectors
Session Topics Timing Paths Clock Skew Timing Constraints Slack
Timing Analysis A ‘N’ bit input design to be verified completely requires a 2N test patterns N patterns and applying The approach of generating 2 them at different time & sequence is impractical The complexity of analysis of netlist is reduced by breaking the process into two steps • One of functional verification • Other of timing Verification The process of verifying the netlist through test benches and test patterns after P&R is P&R is known as Dynamic Timing Analysis • Requires input from user / verification engineer
Dynamic Timing Analysis
Dynamic timing analysis / simulation guarantees 100% coverage Though this guarantee comes at a cost of time • Time of generation of patterns • Time of application of patterns etc
It is design specific One method cannot be used to all designs Hence for each design a unique test bench needs to be created A generalized approach app roach is required so that
STA – What is Static Timing Analysis? •Static Timing Analysis is a method of calculating the expected timing of a digital circuit without requiring simulation. •STA is method of analyzing and validating the timing performance of a design. Advantages: Much faster than gate-level simulation. Exhaustive Proper circuit functionality is not checked. Vector generation NOT required.
What is Timing Analysis? D
Q
Data
Output
QB
Clk
OutputBar
What are our circuit timing requirements?
Clk 0
100
200
300
400
500
Data
Setup Requirement Hold Requirement
Data Cannot Change Within These Windows
Timing Terminologies
Setup Time : Time for which data should be stable at the input of the ff before the arrival of clock (active edge) at the ff’s clock pin Hold Time : Time for which data should be stable at the input of the ff after the arrival of clock (active edge) at the ff’s clock pin
THOLD
Metastability
For any flop to work its setup time and hold time requirements should be met
STA Process STA happens in three steps Circuit is broken down to sets of timing paths Delay of each path is calculated Path delays are checked to see if timing constraints have been met
Timing Paths ‘Timing’ refers to the time taken by data to travel from one point to the other The point at which data is expected to originate is considered a ‘start point’
• Input Port • Clock Pin of sequential elements
The location at which data considered as the stop point • Output Port • Data Pin of sequential elements
terminates
is
Three Steps in Timing Analysis
• Circuit is broken down into sets of timing paths. • Delay of each path is calculated. • Path delays are checked to see if timing constraints have been met.
What is a Timing Path?
•A Timing Path is a point-to-point path in a design which can propagate data from one flip-flop to another. •Each path has a startpoint and an endpoint •Startpoints: •Input ports, Clock pins of flip-flops •Endpoints: •Output ports, Data input pins of flip-flops
Timing Terminologies
Critical Path
: Theoretically path which has maximum delay Arrival Time : Time taken by data to reach a end point from a specific start point. Depends on complexity of logic through which data traverses Required Time : Time at which data is required at a particular end point. Depends on the requirements / specifications Slack : Difference in required time and arrival time. For a design to work the slack value should always be positive
Timing Paths
Depending on the logic through which data propogates a design can be considered to comprise of 4 paths • • • •
input –> reg : Data from Input port to the first flip-flop reg –> reg : Data from one flip-flop to another ff reg –> out : Data from last flip-flop to output port input –> output : Data from Input – Output with no sequential components in between
Timing paths Input Reg Reg Input
-> -> -> ->
Reg Reg Output Output
• Input / Output also called as ‘Pad’ / ‘Pin’ • ‘Reg’ can be any of - flop, latch, RAM etc • ‘Reg’ also called as clock / setup
Input –> Reg
Path which starts at any input port and ends at the data pin of any sequential element that is first encountered Is controlled by the capture clock Data may start independently but must reach the sequential element before clock reaches the element
Reg –> Reg
Path which starts at the clock pin of a ff or enable pin of latch and ends at the data pin of any sequential element that is next encountered
Reg –> Reg
Path which starts at the clock pin of a ff or enable pin of latch and ends at the data pin of any sequential element that is next encountered Is controlled by both the launch as well as capture clock Data leaves the first sequential element on the clock and then races forward to reach the next sequential element before clock / enable reaches the element
Reg –> Out
Path which starts at the clock pin of a ff or enable pin of latch and ends at the output port of the design Clock launches the data after which data runs uncontrolled
Input –> Output
Path which starts at any input port and ends at any output port without traversing through any sequential element Clock has no role to play in this path Is seen mainly in purely combinational circuits practically rare in designs
Timing Paths Example
How many start points are there in the circuit How many end points are there in the circuit How many paths are there in the circuit
Anatomy Of A Sequential Path
Flip Flop
Combinational Logic
Flip Flop
φ
φ
Tclock-to-Q
Tlogic
Tsetup
One clock cycle
T cycle = T clock −to −Q + T combo + T setup
Propagation Delay
Delay of a cell depends on many factors such as • Operating Conditions • Functionality of the cell • Type of Inputs
Based on the factors above a cell can propagate data either quickly or slowly Depending on the kind of analysis being done at any point of time one needs to consider either minimum delays or maximum delays
Real world effects All parameters vary based on PVT which stands for Process, Voltage, Temperature. • Higher voltage usually speeds things up. • Higher temperature usually slows things down. • Process variation is more difficult to quantify. Most datasheets specify maximum delays.
Delay Types Assume the ‘and’ gate shown below has a maximum delay of 3 ns at max operating conditions and for a 0-1 transition Let the ‘and’ gate have a delay of 0.6 ns at minimum operating conditions and for a 1-0 transition Which is the delay to be considered for analysis?
Clock Skew Clock feeds multimillion flip-flops Theoretically clock should arrive at same instance at all flip-flops – Practically impossible
Clock Skew •
Clock Skew: The maximum difference in arrival time of the clock signal to each register in the design
Clock arrival time at 1.1ns
Clock arrival time at 1.3ns
clock Skew = 1.3ns - 1.1ns = .2ns
•It is also defined as the difference in time that a single clock signal takes to reach two different registers.
Clock Skew Variation in arrival of clock at clock pin of subsequent / consecutive flip-flops is known as skew
Clock Jitter
The difference in arrival of clock at different flip-flops could be due to • Jitter – cycle to cycle variation in clock period due to aging of oscillator, anomalies in the pll etc
Clock Skew
Skew can be considered to be of two types • When clock arrives earlier than expected – generally known as negative skew • When clock arrives later than expected – generally known as positive skew
+ve skew can occur when data & clock travel in same direction can occur when data & clock -ve skew travel in opposite directions
Positive & Negative Skew In
R 1 D Q
CLK
Combinational Logic
R 2 D Q
Combinational Logic
R 3 D Q
t CLK2
t CLK1
delay
• • •
t CLK3
delay (a) Positive skew
In
R 1 D Q
Combinational Logic
t CLK1
R 2 D Q
Combinational Logic
t CLK2
delay
D Q t CLK3
delay (b) Negative skew
R 3
CLK
• • •
Positive Skew T CLK + δ CLK1
T CLK
1
3
δ CLK2
2
4 δ + t h
+ve skew Tclk + δ >= tcq1 + tcombo + t su2 (th2 + δ) < tcq1 + tcombo Launching edge arrives before the receiving edge
Negative Skew T CLK - δ
1
CLK1
CLK2
2
T CLK
3
4 δ
-ve skew Tclk - δ >= tcq1 + tcombo + t su2 (th2 - δ) < tcq1 + tcombo Receiving edge arrives before the launching edge
Timing Terminologies
Critical Path
:
Theoretically path which has maximum delay Arrival Time : Time taken by data to reach a particular end point from a specific start point. Depends on complexity of logic through which data traverses Required Time : Time at which data is required at a particular end point. Depends on the requirements / specifications Slack : Difference in required time and arrival time. For a design to work the slack value should always be positive
Maximum Frequency
For a circuit to meet its specifications the minimum time period or maximum frequency at which it works should be identified The frequency of operation of a circuit depends on the logic of the paths Each of the four kinds of paths have different required times
Frequency Calculations
Arrival Time = TCOMBO, Max
Required Time = TCP + TClock_Delay - TSETUP
Frequency Calculations
Arrival Time : TClk-Q + TCombo, MAX
Required Time = TCP + TClock_Skew - TSETUP
Frequency Calculations
Arrival Time : TCombo, MAX
Required Time : Explicit Timing Constraint (If Specified)
Frequency Calculations
Arrival Time = TClk-Q + TCombo, MAX
Required Time = Explicit Timing Constraint (If Specified)
Problem 1
Find The maximum Frequency for the circuit shown in figure below
Solution Methodology
Step One : Find the total number of paths in the design Step Two : Identify the paths that are constrained by clock Step Three : Identify the arrival times of all the paths identified in step 2 above Step Four : Identify the required time equations of all paths identified in step 2 Step Five : Equate the arrival times and required times of all relevant paths to obtain the time periods Step Six : Select the maximum applicable clock frequency from the clocks identified in step 5
Solution
Three paths in the design • Input – Reg • Reg – Reg • Reg – Out
Reg – Out path not constrained hence can be discarded for timing calculation Relevant Paths are Input – Reg and Reg – Reg Input – Reg Path • Arrival Time = 3 • Required Time = CP + 0.5 + 0.6 -Tsetup= CP + 1.1 0.65 • Equating the 2, CP = 3
1.1 + 0.65 = 2.55
Solution
Reg – Reg Path • Arrival Time = 0.5 + 0.6 + 1.4 + 4 = 6.5 • Required Time = 0.5 + 0.7 + 0.8 + CP – 0.75 = CP + 1.25 • Equating the two, CP = 6.5 – 1.25 = 5.25
Two time periods available from the calculations 5.25, 2.55. Though first path can work if clock time period is 5.25 the second path can not work if clock time period is 2.55 Hence the maximum clock frequency at which the circuit can work is 1/5.25
Problem 2
Paths from Q1 to Q1:
None
Paths from Q1 to Q2: TW ≥ max tPDFF +tJKsu = 20 +10 = 30 ns TW ≥ max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 ns Paths from Q2 to Q1: TW ≥ max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns Paths from Q2 to Q2: TW ≥ max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 47 ns
TW ≥ 47 ns
Problem 3
Find the maximum applicable clock frequency for the circuit shown in figure below
Problem 4
For the circuit shown in figure below find the maximum applicable clock frequency
Problem 5
For the circuit shown in figure below find the maximum applicable clock frequency
Failure / Data loss Due To Large Skew “A” Ain
Flip Flop
“B” Aout
Combinational Logic
Bin
Flip Flop
clk
δ delay
If new data (Ain) gets to point “B” before clock does, system will fail by simply skipping over old data…
For this illustration - ignore tsetup
Clock arrives at point “A” “A” Ain
Flip Flop
“B” Aout
Combinational Logic
clk
δ delay
T = 0ns
Bin
Flip Flop
Data arrives at comb logic input “A” Ain
Flip Flop
“B” Aout
Combinational Logic
clk
δ delay
T = tclk-to-Q
Bin
Flip Flop
Data Exits Comb Logic “A” Ain
Flip Flop
Aout
Combinational Logic
clk
δ delay
T = tclk-to-Q + tlogic
“B” new Bin Flip Bin
Flop
Clock Reaches “B” “A” Ain
Flip Flop
Aout
Combinational Logic
“B” new Bin Flip Bin
Flop
clk
δ delay
T = tclk-to-Q + tlogic
T = tδ
Failure!!! “A” Ain
Flip Flop
Aout
Combinational Logic
“B” new Bin Flip Bin
Flop
clk
δ delay
What happened to old Bin??? If tclk-to-Q+tlogic < tδ it fails…
New Bin
Example 1 D Q
CK
Q
Q
TW ≥ max tPFF + tsu
For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20ns TW ≥ max (max tPLH + tsu, max tPHL + tsu) TW ≥ max (25+20, 40+20) = 60
Example 2 D
Q
Q
CK
TW ≥ max tPFF + max tPINV + tsu
Example 3
D Q
Q0
0
MUX
D
Q
Q1
1
Q
Q
CK
TW ≥ max tPFF + max tPMUX + tsu
False paths • Paths that physically exist in a design but are not logic/functional paths • These paths never get sensitized under any input conditions Mux 1 A
Mux 2 C
B1
C1
C2
OUT
B2
B
S
Total 4 timing paths PATH 1 – A-C-C1-C2-OUT PATH 2 – A-C-OUT PATH 3 – B-B1-B2-C-C1-C2-OUT PATH 4 – B-B1-B2-C-OUT Only path1 and 4 above are valid logic paths as select line for the 2 muxes are the same
