CPU Organization a) Fundamentals:
The Primary function of CPU is to execute sequences of instructions, that is, programs which are stored in an external memory. The program execution is therefore carried as follows: 1. The CPU transfers the instructions and, their input data (Operands) from main memory to registers in the CPU. 2. The CPU executes the instructions in their stored sequence except when the execution sequence is explicitly altered by a branch instruction. 3. When necessary, the CPU transfers output data from the CPU registers to main memory. b) External Communication: When no cache memory is present as in figure 1.1, 1.1, the CPU communicates directly with the main memory M, which is typically a high-capacity multichip random-access memory (RAM). The CPU is significantly faster than M, that is, the read or write to CPU registers is 5 to 10 times faster than it can read or write to a RAM. Instructions
CPU Data
Main Memory M
Figure 1.1 Processor memory communication without Cache
To remedy this situation, many computers have a cache memory CM positioned between the CPU and main memory as in figure 1.2. 1.2. The cache CM is smaller and faster than main memory and may reside, wholly or in part, on the same chip as the CPU. The cache is designed to be tr ansparent ansparent to the CPU’s instructions and it permits the CPU to perform a memory load or store operation in a single clock cycle. Instructions
CPU
Instructions
Cache Memory CM
Data
Main Memory MM Data
External Memory M
Figure 1.2 Processor memory communication without Cache
The CPU communicates with the IO devices in the same way as it communicates with the main memory. The IO devices are associated with addressable registers to which the CPU can load or store a word. If the IO data transfers are implemented by memory-referencing instructions, it is called as memory-mapped memory-mapped IO I O. Some computers employ IO instructions that are distinct from memory referencing instructions. These instructions produce control signals to which IO ports, but not memory locations, respond. The second approach is sometimes called as IO-mapped IO
c) User and Supervisor modes:
The programs executed by general purpose computers fall into two broad groups: user programs and supervisor programs. programs. A user or application application program handles a specific application, application, such as word processing. A supervisor program, on the other hand, manages various routine aspects of computer system on behalf of its users; it is typically part of the computer’s operating system. Examples of supervisory functions are transferring data between secondary and main memory. In normal operation the CPU continually switches between back and forth between user and supervisor programs. The CPU is designed such that it can receive requests for supervisor services directly from secondary memory units and other IO devices. Such a request is called an interrupt. When an Interrupt occurs, the CPU suspends the current execution and transfers to an interrupt handling program called called Interrupt Interrupt Service Service Routine. Routine. d) CPU operation: Begin
Are there instructions waiting?
Fetch the next instruction
Execute the instruction
Are there interrupts waiting?
Figure 1.3 Overview of CPU behavior
Transfer to interrupt handling program
The flowchart in figure 1.3 summarizes the main functions of a CPU. The sequence of operations performed by the CPU in processing an instruction constitutes an instruction cycle. cycle . While the details of the instruction cycle may vary with the type of instruction, all instructions require two major steps: a fetch step during which a new instruction is read from the external memory M and an execute step during which the operations specified by the instruction are executed. e)
Accumulator-based CPU:
The CPU organization proposed by Von Neumann and his colleagues for the IAS computer is the basis for most subsequent designs. It comprises a small set of registers and the circuits needed to execute a functionally complete set of instructions. In many early designs, one of the CPU registers, the accumulator played a central role, being used to store an input or output operand in the execution of many instructions. The instructions are fetched by the program control unit PCU, whose main register is the program counter PC. They are executed in the data processing unit DPU, which contains an n-bit arithmetic-logic unit (ALU) and two data registers AC and DR. Most instructions perform the operation of the form X1:= f i (X1, X2) Where X1 and X2 denote CPU registers (AC, DR, or PC) or an external memory location M(adr). The operation f i performed by the ALU ALU are addition, subtraction, subtraction, shifting and and logical logical operations. Memory addresses are stored in two address registers in the PCU: the program counter PC, which stores the address of the next instruction to be executed, and the general purpose address register AR. The instruction fetched from memory is placed in Instruction Register (IR). The two essential memory addressing instructions are the load and store. The load instruction for our sample CPU is AC:=M(adr)
This transfers a word from the memory location with address adr to the accumulator. The corresponding store instruction is M(adr):=AC
This transfers a word from the accumulator to a memory location. The corresponding store instruction is f)
Architecture extensions:
There are many ways in which the basic design of accumulator based CPU can be improved. Most CPU’s contain the following extensions, which significantly increases their performance performance and ease ease of programming. programming.
i)
Multipurpose register set for storing data and addresses:
There are additional registers for storing instructions and data. These are called as general purpose registers. The third generation IBM/360-3670 has around 32 such registers. The set general registers are now usually referred to as register file. ii)
Additional data, instruction and address types:
Most CPU’s have instructions to handle data and addresses with several different word sizes and formats. It also has various addressing modes, giving the various ways of fetching the operands. iii)
Register to indicate computation status:
A status register also called as condition code or flag register indicates infrequent or exceptional conditions resulting from the instruction execution. Status register also indicates the supervisor and user states. Conditional branch instructions can check the status register, and branch accordingly. accordingly. iv)
Program Control Stack:
Various special registers and instructions facilitate the transfer of control among programs due to procedure calling or external external interrupts. interrupts. The stack stack memory memory is intended intended for saving key information about an interrupted program through push operations so that the saved information can be retrieved later using pop operations. A CPU register called stack pointer automatically keeps track trac k of the stack’s entry point.
Figure 1.4 A typical CPU with general register organization
g) Instruction Set:
Type Data Transfer
Data Processing
Program Control
Figure 1.5 Instruction set for the general CPU organization
The above figure gives the possible instruction set for our simple accumulator based CPU. The above 10 instructions have the flavor of the instruction sets of some recent RISC machines, which demonstrate that small instruction sets can be both complete and efficient.
h) Pipelining:
i)
Coprocessors:
