CS 251, Winter 2017, Assignment 4.0.1 3% of
course mark
Due Wednesday, March 8th, 4:30PM Lates accepted until 11:00 AM March 9th with a 15% penalty
1. (5 points) In the diagram below, the multicycle multicycle computer from the course notes is executing executing the instruction 200 state. The ID/EX ID/EX register register bank has NOT yet 200 add $2,$4,$ $2,$4,$6 6 in the ID state. been written. In the figure below, there are six dark lines, each above one of the data lines in the datapath. Above each dark line write the value on the dataline; if the value on the data line can not be determined from the information given, write ’?’. 0 M u x 1
IF/ID
ID/EX
EX/MEM
MEM/WB
Add 4
Add
Add result
Shift left 2
PC
Address Instruction memory
n o i t c u r t s n I
Read register 1
Read data 1 Read register 2 Registers Read Write data 2 register
0 M u x 1
Write data
Zero ALU ALU result
Address Data memory Write data
16
Sign extend
32
1 2 3 4 5 CONTROL
1
Read data
1 M u x 0
2. (10 points) Consider the following MIPS code sequence: 100 104 108 112
add lw add sw
$2, $1, $2, $1,
$3, $4 100($2) $3, $2 60($2)
(a) (5 pts) In the diagram below, each row is labeled with an executed instruction. Mark all data dependencies by drawing straight lines (similar to the the blue lines of Fig. 4.52 of the 5th edition) between when the result is in the register file and when it needs to be taken from the register file. Assume that the code is to run on the pipelined datapath of Fig. 4.51 of the 5th edition; this datapath implements neither stalling nor forwarding. For each data dependency, label it either as a hazard or as a non-hazard.
100 add $2, $3, $4
104 lw $1, 100($2)
108 add $2, $3, $2
CC1
CC2
IM
Reg
IM
CC3
CC4
CC5
DM
Reg
Reg
IM
112 sw $1, 60($2)
DM
Reg
IM
2
CC6
CC8
Reg
DM
Reg
CC7
Reg
DM
Reg
(b) (5 pts) Modify the code to remove the data hazards by inserting a minimum number of NOPs. In your solution, give both new and old line numbers.
New Line # Old line # Code
3
3. (5 points) This question refers to the pipelined datapath without forwarding, shown below and in Figure 4.51 in the textbook. Consider the instructions 100 104 108 112
add $1, $3, $5 sw $4, 40($8) sub $4, $1, $4 beq $1, $2, 60
Consider the pipeline when the 100 add instruction is in the WB stage, the 104 sw instruction is in the MEM stage, the 108 sub instruction is in the EX stage, and the 112 beq instruction is in the ID stage. In the figure below, label all of the control signals (including both those coming directly out of the control unit and those coming out of the pipeline registers) with their appropriate values, using don’t cares where appropriate. In this figure, the instructions have been drawn above the appropriate set of pipeline registers. We have also filled in the solution for the WB stage, and given the names of the control signals whose values you need to determine for the other three stages. beq $1,$2,60
sub $4,$1,$4
sw $4, 40($8)
add $1,$3,$5
PCSrc
ID/EX
0 M u x 1
WB
Control
IF/ID
EX/MEM
M
WB
EX
M
MEM/WB WB
Add 4
PC
Add Add result
e t i r W g e R
Address Instruction memory
n o i t c u r t s n I
Branch
Shift left 2
e t i r W m e M
ALUSrc
Read register 1
Read data 1
Read register 2 Registers Read Write data 2 register
Zero ALU ALU result
0 M u x 1
Write data
Address
Data memory
g e R o t m e M Read data
Write data Instruction16 [15–0]
Sign extend
Instruction [20–16]
Instruction [15–11]
32
6
ALU control
0 M u x 1
1 M u x 0
MemRead
ALUOp
RegDst
MemtoReg= Branch= MemWrite= RegDst= ALUOp= ALUSrc=
RegWrite= MemRead=
MemtoReg= Branch= MemWrite= RegDst= ALUOp= ALUSrc=
4
RegWrite= MemRead=
MemtoReg= RegWrite= Branch= MemRead= MemWrite=
RegWrite=1 MemToReg=0
4. (3 points) This question refers to the pipelined datapath from Question 3, on page 4 of this assignment. State how many bits wide the Intermediate Register ID/EX must be in order to store all the required data and control bits. You must show your work.
5
5. (5 points) This question refers to the pipelined datapath with forwarding in Figure 4.56 of the textbook. Consider the instructions 100 add $1, $2, $4 104 add $2, $4, $1 108 sub $3, $2, $1
Consider the situation when the 100 add instruction is in the WB stage, the 104 add instruction is in the MEM stage, and the 108 sub instruction is in the EX stage. In the figure below, trace back each of the two inputs to the ALU through the MUXes back to the appropriate set of pipeline registers. sub $3,$2,$1
add $2,$4,$1
add $1,$2,$4
ID/EX WB Control IF/ID
PC
Instruction memory
n o i t c u r t s n I
EX/MEM
M
WB
EX
M
MEM/WB WB
M u x Registers
ALU M u x
IF/ID.RegisterRs IF/ID.RegisterRt IF/ID.RegisterRt IF/ID.RegisterRd
Rs Rt Rt Rd
Data memory
EX/MEM.RegisterRd
M u x Forwarding unit
6
MEM/WB.RegisterRd
M u x
6. (5 pts) Given the following code segment below, re-write the code (code rearrangement) to avoid as many stalls and hazards as possible. Assume the datapath implements data forwarding and load-use stalling . Indicate any instructions that have a data hazard between itself and a prior instruction using (*) beside that instruction. You may insert NOP instructions, only if code rearrangement cannot be used. Rewrite the code and perform code rearrangement where necessary to remove data hazards.
* Original Code Rearrangement 100 addi $7, $0, 24 104 addi $5, $0, 16 108 lw $6, 100($5) 112 add $3, $6, $8 116 lw $8, 100($7) 120 sw $8, 100($5) 124 sw $6 , 100($7) 128 lw $6, 0($7) 132 add $4, $6, $3 136 slt $5, $6, $2
7
Additional exercises for pipeline architecture: •
Exercise 4-9, 4-11, 4-13, 4-14.
8