VLSI Design Flow The system prototyping methodology is a natural outgrowth of recent developments in software and hardware facilities intended to make it simple for designers with an idea for a particular application to turn that idea into a working system based on very large scale integrated chips. Today VLSI CMOS technologies deliver individual integrated circuits (ICs) and containing millions of gates, sufficient to implement substantial systems-on-a chip or major subsystems-on-a chip. System-on-chip design may involve the expertise from many fields of electronics such as signal processing, communication, device physics etc. and so on. It is unreasonable to expect the architect of a speech recognition system, for example, to be an expert in device physics as well as in signal processing. The MeadConway methodology for integrated-circuit design makes VLSI technology available to such an application designers. The problem encountered designing very large scale integrated circuits are fundamentally different from the problems encountered in the design of small scale integrated circuits. The differences require a different methodology of design and the new methodology requires a new set of tools. At one time design automation was attempted, but the effort later was shifted to Computer-aided design, it was under-stood that fully automation without human intervention is a formidable task. So the effort was on to use of computers with human intervention for obtaining a critical decision is more meaningful approach. The procedures for design, simulation, verification or test involve CAD tools. A major goal of computer-aided design is to produce correct designs without the need for checking. This goal of correctness by construction permeates the design methodology and tools. These tools can be very specific to the design methodology. The mating of the tools to the design style allows more powerful tools to be constructed and leads to much greater productivity from the designers. The structured design methodology of Mead and Conway is an approach to VLSI system design that attacks the problems of complex chip designs. The structured design methodology is similar in concept to structured programming: the design proceeds in a top-down manner in which the problem is decomposed and refined. The structured design methodology has two major parts: hierarchy and regularity. Hierarchial techniques have long been used to design complex systems. Hierarchies are used to partition designs and common parts of a design can be factored out and specified only once. By introducing regularity into a system, the design problem is reduced in complexity as subunits are replicated many times and connections between units are simplified. Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible. A good example of regularity is the design of array structures consisting of identical cells – such as a parallel multiplication array. Regularity can exist at all levels of abstraction: If the designer has a small library of well-defined and well-characterized basic building blocks, a number of different functions can be constructed by using this principle. Regularity usually reduces
the number of different modules that need to be designed and verified, at all levels of abstraction. Design description: VLSI design style mainly uses three domains of design description, viz. the behavioral, the description of the function of the design; the structural, the description of the form of the implementation; and the physical, the description of the physical implementation of the design. There are many possible representations of a circuit in each description, and judicious choice of representations is important in tool design. A simplified view of design flow is shown in Fig. 1. Regardless of the actual size of the project, the basic principles of structured design will improve the prospects of success. System Specification
Functional (Architecture) Design Behavioral Representatio
Functional Verification Logic Design
Logic (Gate-level) Representati
Logic Verification
Circuit Design Device Modeling Circuit Representatio
Circuit Verification
Physical Design Layout Representation
Layout Verification
Fabrication & Testing Figure: 1
At the beginning of a design it is important to specify the requirements without unduly restricting the design. The object is to describe the purpose of the design including all aspects, such as the functions to the realised, timing constraints, and power dissipation requirements, etc. Descriptions in block level may show either data flow, control flow, or both. The individual blocks generally correspond to hardware modules. Functional design specifies the functional relationships among subunits or registers. In general, a description of the IC in either the functional or the block diagram domain consists both of the input-output description, and the way that this behavior is to be realised in terms of subordinate modules. In turn each of these modules is described both in terms of input-output behaviors and as an interconnection of other modules. These hierarchical ideas apply to all the domains. The internal description of a module any be given in another domain. If a module has no internal description then the design is incomplete. Ultimately this hierarchy stops when the internal description is in terms of mask geometry, which is primitive. Hierarchy and modularity are used in block diagrams or computer programs. In these domains hierarchy suppresses unnecessary details, simplifies system design through a “divide-and-conquer” strategy and leads to more easily understood designs that are more readily debugged and documented. It can be summarized in a way that when we want to design a digital system, we need to specify the system performance which is called “system specification”. Then the system must be broken down into subunits or registers. So we have a functional design which specifies the functional relationships among subunits or registers. “Architecture” usually means the functional design, system specification and often including part of the subsequent logic design. To plan the Architecture of a VLSI chip, it is always easier to conceive the system in a similar line to Mead & Conway approach, which they described as OM project at CALTECH. Figure 2 illustrates the block diagram of that system. It consists of basically 6-sub blocks e.g. 1. 2. 3. 4. 5. 6.
Manager chip Data path chip Memory chip Controller chip I/O Devices and Clock chip
The data path chip performs mainly the data computations. The sequence of computations are mainly controlled either by the controller or by the instructions fetched from the microcode instructions unit. The main subsystems of the data path unit are Arithmetic logic Unit (ALU), shifter, register arrays, and different type of processing elements (PEs) which perform some definite jobs. The memory manager chip contains the addresses of the data memory and provides the link to communicate between the sub blocks. It supports the different data structures. It takes the decision to push or pop data.
The clock generation block supplies the two clock signals for the chip. According to the need in some chip a single clock is available, which can generate two clock phases onchip. The controller part is generally having the microprogram counter that stores the microcode memory address and its structure is very similar controller of computer system. The system bus interface sub block provides synchronous/ asynchronous communication with the outer systems. Data bus Microcode Microcode address
Microcode External flags
Microcode enables
Microcode Controller Flag
External data
System bus
Flags and enables Interface
Data chip External enable
Bus enables
Interface enables
Data chip enables Clock Clock Clock
External hold
Manager Hold
Memory address
Memory
Manager microcode
Manager address ROM
Figure 2: Block diagram of an OM system The design of VLSI processor may be subdivided in for major sections. 1. 2. 3. 4. 5.
High level design Operative part design Control part design Memory design Design of miscellaneous parts (interrupt mechanism, clock system, pads, etc…).
The next step is the Logic design of networks which constitutes subunits or registers. When a system architecture or logic networks are designed, performance and errors are checked by CAD programs, called as “logic simulation”. The subject of the logic design is to decide overall structure of blocks, their interconnection pattern, to specify the structure of data path and to control sequences of data path. Logic simulator does the
logic verification considering the propagation delays of interconnection signals and the element delay. Simulator also checks whether the network contains hazards analysis. Logic design and simulation is a key issue in VLSI CAD. The flow of logic design process is determined by the level at which the design can begin-system level, behavioral level or functional level. Logic design consists of a series of design steps leading from a higher level to a circuit description at the logic level. The three design process i.e behavioral level, structural level and physical level can be represented as shown in Figure 3 and Figure 4 shows different possible refinement for the three main levels of design representations including the different synthesis steps at each level.
Figure 3: Examples for the design levels
Figure 4: Levels of representation and design Today, the following design phases of digital circuits have become widely recognized. Figure 5 shows the relationship between these design phases. (1) Architecture design (2) Register transfer level design (3) Gate level design (4) Cell design (5) Layout design (6) Test program design
Simulators are used in every design phase except for the layout design phase, and play important roles for the evaluation of system performance, the functional verification and the timing verification.
Figure 5: Design flow for VLSI logic circuits There are the following four types of logic simulators according to the levels of abstraction of simulated elements as shown in Table 1. Simulation primitive SWITCH GATE FUNCTION RTL
Example TRANSISTOR AND gata ADDER etc. user coded primitive
Signal value 0/1, strength 0/1 0/1 0/1, vector
Table 1: Simulation primitive
(1) Switch level simulators (2) Gate level simulators (3) Functional level simulators (4) Register transfer level simulators (5) Simulators used in the logic design Logic networks have to be converted into electronic circuits. When designers specify electronic circuit requirements such as speed, power supply voltage, types of logic operations, and signal level tolerances, it is desirable to have CAD programs which automatically design electronic circuits meeting all requirements, and specify parameters such as dimensions of transistors and magnitudes of currents. For this electronic circuit design and simulation, CAD programs perform complex numerical analysis calculations of nonlinear differential equations which characterize electronic circuits. Since we need to finish calculation within a reasonable time limit, keeping the required accuracy, many advanced numerical analysis techniques are used. The CAD programs usually yield the analysis of transient behavior, direct-current performance, stationary alternating-current performance, temperature, signal distortion, noise interference, sensitivity and parameter optimization of the electronic circuits. The layout system is used to convert block/cell placement data into actual locations, and to construct a routing maze containing all spacing rules. The format used for relative cell placement data is the same for automatic as for manual placements in order to simplify their interchange. In fact, the output of the automatic placement program can be modified by hand before input into the chip building step as manual placement data. The layout for random-logic networks in the most time-consuming stage throughout the entire sequence of LSI/VLSI chip design. After having finished the layout, designers usually check by CAD programs whether the layout conforms to the layout rules. As the integration size of LSI/VLSI chips becomes larger, design verification and testing at each design stage is vitally important, because any errors which sneak in from the previous design stages are more difficult to find and more expensive, since once found, we need to redo the previous design stages. As the integration size increases, the test time increases very rapidly, so it is crucial to find a good way to test within as short a time as possible, though it appears very difficult to find good solutions. Complete test and design verification with software or hardware (i.e., computers specialized in testing) is usually done to find a design mistake. The last domain in which the design of an IC can exist include the mask set, and of course, the final fabricated chip followed by prototype testing. In the summary, the following domains of description have been used in the design. ¾ ¾ ¾ ¾ ¾
Architectural level (including functional and block diagram) Logic and network level. Electronic circuit level Layout : Placement & Routing Prototype testing
