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VHDL coding tips and tricks: VHDL code for BCD to 7-segment display converter Share
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VHDL code for BCD to 7-segment display converter 0 tweets
tweet Here is a program for BCD to 7-segment display decoder. The module takes 4 bit BCD as input and outputs 7 bit decoded output for driving the display unit.A seven segment display can be used to display decimal digits.They have LED or LCD elements which becomes active when the input is zero.The figure shows how different digits are displayed:
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library IEEE IEEE; ; use IEEE IEEE. .STD_LOGIC_1164 STD_LOGIC_1164. . ALL; IEEE. .STD_LOGIC_ARITH STD_LOGIC_ARITH. . ALL; use IEEE IEEE.STD_LOGIC_UNSIGNED. .STD_LOGIC_UNSIGNED. ALL; use IEEE entity test is port ( clk : in std_logic std_logic; ; bcd : in std_logic_vector std_logic_vector( (3 downto 0); --BCD input segment7 : out std_logic_vector std_logic_vector( (6 downto 0) -- 7 bit decoded output.
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); end test test; ;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7. architecture Behavioral of test is begin clk,bcd) ) process (clk,bcd BEGIN if (clk clk'event 'event and clk clk= ='1') then case bcd is "0000"=> => segment7 <= <="0000001" "0000001"; ; when "0000" when "0001" "0001"=> => segment7 <= <="1001111" "1001111"; ; when "0010" "0010"=> => segment7 <= <="0010010" "0010010"; ; "0011"=> => segment7 <= <="0000110" "0000110"; ; when "0011" "0100"=> => segment7 <= <="1001100" "1001100"; ; when "0100" when "0101" "0101"=> => segment7 <= <="0100100" "0100100"; ; when "0110" "0110"=> => segment7 <= <="0100000" "0100000"; ; "0111"=> => segment7 <= <="0001111" "0001111"; ; when "0111" "1000"=> => segment7 <= <="0000000" "0000000"; ; when "1000" when "1001" "1001"=> => segment7 <= <="0000100" "0000100"; ;
-- '0' -- '1' -- '2' -- '3' -- '4' -- '5' -- '6' -- '7' -- '8' -- '9' --nothing is displayed when a number more than 9 is given as input. when others=> segment7 <= <="1111111" "1111111"; ; end case;
vhdlguru.blogspot.in/2010/03/vhdl-code-f vhdlguru.blogspot.in/2010/03/vhdl-code-for-bcd-to-7-segm or-bcd-to-7-segment-display.html ent-display.html
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VHDL coding tips and tricks: VHDL code for BCD to 7-segment display converter end if;
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end process;
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end Behavioral;
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If you want a decimal number to be display ed using this c ode then convert the corresponding code into BCD and then instantiate thi s module for each digit of the BCD code.
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LIBRARY ieee; USE ieee.std_logic_1164. ALL; use IEEE.STD_LOGIC_ARITH. ALL;
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ENTITY test_tb IS END test_tb;
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ARCHITECTURE behavior OF test_tb IS signal clk : std_logic := '0'; signal bcd : std_logic_vector(3 downto 0) := (others => '0'); signal segment7 : std_logic_vector(6 downto 0); constant clk_period : time := 1 ns; BEGIN uut: entity work.test PORT MAP (clk,bcd,segment7); clk_process : process begin
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clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; stim_proc: process
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begin for i in 0 to 9 loop
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bcd <= conv_std_logic_vector(i,4); wait for 2 ns; end loop; end process;
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END;
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VHDL coding tips and tricks: VHDL code for BCD to 7-segment display converter Raphael Andreoni October 26, 2010 1:25 AM
VHDL code for BCD t
Hi, I'm trying to implement the sum of two numbers with 5 bits and s how in two digits SSD, but with no success , do you have any idea how to do this?
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I had success with decimal counter until 99, but how make this work whit the sum, I don't know.
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How to write a testben ► ► February 2010 (1)
Jtesla July 21, 2011 2:02 AM Can som e one help m e with the code for Four bit BCD decimal COUNTER using VHDL and the 74LS90. I'm us ing Xilinx 12.1 and I'm really struggling with the logic gate code. my email is
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sumdt October 19, 2011 10:25 PM Please help me! Write a VHDL code to perform the function of multiplier which the inputs are from Dip Switch and outputs display to 7-segment LED with BCD. X : dip 1~4represents value 0~15 Y : dip 5~8represents value 0~15 Thanks you so much Reply
sandeep October 21, 2011 6:43 PM write a VHDL prog to display number on BCD-7 segm ent display , input given from ps /2 keyboard Reply
mar'd December 21, 2011 7:55 PM can you help me to get a VHBL program for 64 bit CSA Reply
blogzworld May 8, 2012 10:50 PM Can you post the synthesis report. Reply
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