IC616 Basics Open Library Manager Click on Tools --> Library Manager , to bring up the Library manager manager window. In the Library manager window, you can view a list of libraries on on the left. Click on any of them to view the list of cells that particular librar y contains. This list shows up in the 'Cell' pane. Each of thee cells may also have multiple views such as 'schematic', 'schematic', 'symbol 'symbol etc An image of the 'Library Manager' window is shown in the screenshot screenshot
Create New Library Click on File --> New Library.. Type in the name of the the library (test123 in the figure). Double click the libs libs folder to ensure that the new library is stored in the /home/username/work /home/username/work _cad_65nm/libs/ folder (this makes for better organization) You will then get a window "Technology File for new library". Choose "Attach to an existing technology library" as shown in the screenshot Click on "OK" Choose "umc65ll" as the technology library in the next window ("Attach library to technology library") that shows up Click on "OK"
Create Schematic Now we can create new cells in this library we have just created. We will will first make an inverter as our first cell. Go to the Library Manager window. Ensure that the library you have created is highlighted in the "Librar y" pane on the left. Click on File--> New --> "Cell View" .You will get a window as shown shown in the figure. Ensure that the librayy name is correct, and the view is "Schematic" . Enter a cell name of your choice . Here we have called it "inv_65".
NOTE NOTE This will bring up a small window (when done first time) asking if you like to use an alternative license. Click on Always If you click on "Never" by mistake, please refer to the FAQ below to fix the issue
This will bring up the schematic editor window.
Press 'i' on the keyboard to instantiate a cell. Here we will first need to instantiate the NMOS , and PMOS transistors. "Add Instance" window pops up. Browse to select the library as "umc65ll". Choose the NMOS transistor to be "N_12_LLHVT". Ensure that the View is set to "symbol". Place the transistor on the schematic editor window. Press 'i' again to instantiate the PMOS transistor "P_12_LLHVT". Press 'w' to activate the wire tool Click start and end points to draw wire between them Press 'p' to add a port Add port "In" of Direction Input Add port "Out" of Direction Output Add port "VDD" of Direction InputOutput Add port "GND" of Direction InputOutput Hit "Shift+x" to Check and Save the schematic You should NOT NOT get any errors or warnings A snapshot of this instantiation window is shown here
Create Symbol Click on Create --> Cellview --> From Cellview... Ensure that 'To View Name' is 'Symbol' Ensure that 'Tool/Data Type' is SchematicSymbol' Click on OK
This opens the 'Symbol Generation Options' window Move the "GND" to Bottom Pins Click on OK
Use toolbar (highlighted in the figure) to create a neat symbol of an inverter Hit "Shift+x" to Check and Save the schematic Again no errors or warnings are expected here! A snapshot of this is shown here
Create a Testbench Create a New schematic in the current library (inv_65_tb) Press "i" and instantiate the inverter you just created This is done by choosing the library (test123), Cell (inv_65) and View (Symbol) Instantiate a dc voltage source library (analogLib), Cell (vdc) and View (Symbol) Edit its properties by selecting the dc voltage source and pressing "q" Set the field "DC Voltage" to 1 V Leave the other fields at their default value and Click OK Instantiate a pulse voltage source library (analogLib), Cell (vpulse) and View (Symbol) Edit its properties by selecting the dc voltage source and pressing "q" Set the fields "Voltage 1" to 0 V, "Voltage 2" to 1 V, "Period" to 10n, "Delay time" to 1n, "Rise time" to 100p, "Fall time" to 100p and "Pulse width" to 5n Leave the other fields at their default value and Click OK Instantiate "gnd" library (analogLib), Cell (gnd) and View (Symbol) Instantiate "No Connection" library (basic), Cell (noConn) and View (Symbol) Make the connections as shown in the figure Label nets by pressing "l" as shown in the figure Hit "Shift+x" to Check and Save the schematic Again no errors or warnings are expected here!
Simulating your design Click on Launch --> ADE L NOTE This will bring up a small window (when done first time) asking if you like to use an alternative license. Click on Always If you click on "Never" by mistake, please refer to the FAQ below to fix the issue In the "ADE L" window, Click on Analyses --> Choose... In the "Choosing Analyses" window, Select the "tran" radio button (this is selected by default) Set "Stop Time" as 100n Select "Conservative" Click on OK In the "ADE L" window, Click on Outputs --> To Be Plotted --> Select On Design This will cause the schematic editing window (ADE L) to become highlighted Click on the nets to be plotted (IN and OUT in this case) In the "ADE L" window, Click on Simulation --> Netlist and Run This will cause the output waveforms to be plotted as shown in the figure
First Assignment Please create a 2-page report of you work. Submission procedure will be updated shortly! 1. Create a Inverter Schematic and Symbol as explained above and measure the delay between input and output Spend some time exploring the tool, this will help you in future assignments. 2. Create a Chain of 11 inverters and measure delay between input and output. 3. (Optional) Create a ring-oscillator using the above chain of 11 inverters. Can you make them oscillate? What is the frequency of oscillation? Can you measure the power consumption?
Virtual Box
Download the virtual box file here
(accessible with-in campus only)!
Layout Setup Follow these instructions to setup layout editor and Calibre DRC, LVS and PEX flows Copy the required files for the smart login of your PC (test for DESE Lab)
cp cp cp cp
‐r ‐r ‐r ‐r
/home/smart/work_cad_65nm/Runsets ~/work_cad_65nm/ /home/smart/work_cad_65nm/.cdsinit ~/work_cad_65nm/ /home/smart/work_cad_65nm/.cdsenv ~/work_cad_65nm/ /home/smart/work_cad_65nm/calview.cellmap ~/work_cad_65nm/
VirtualBox users setup VirtualBox users can login to
[email protected] and copy the same files/folders to the corresponding directories Password is same as username "smart" Tip: You avoid typing the password repeatedly by installing sshpass "yum install sshpass" scp scp scp scp
‐r ‐r ‐r ‐r
[email protected]:work_cad_65nm/Runsets ~/work_cad_65nm/
[email protected]:work_cad_65nm/.cdsinit ~/work_cad_65nm/
[email protected]:work_cad_65nm/.cdsenv ~/work_cad_65nm/
[email protected]:work_cad_65nm/calview.cellmap ~/work_cad_65nm/
Become root on your virtual machine by typing the command "su" Password will be mentioned in class. Then execute the following 4 lines as root You will be prompted for the password smart in the last 3 lines
cd /opt/umc65nmll/G‐9FD‐LOGIC_MIXED_MODE65N‐LL_LOW_K_UMK65FDKLLC00000OA‐FDK‐Ver.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/UMK65FDKLLC00000OA_B10/RuleDec scp
[email protected]:/opt/umc65nmll/G‐9FD‐LOGIC_MIXED_MODE65N‐LL_LOW_K_UMK65FDKLLC00000OA‐FDK‐Ver.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/UMK65FDKLLC scp
[email protected]:/opt/umc65nmll/G‐9FD‐LOGIC_MIXED_MODE65N‐LL_LOW_K_UMK65FDKLLC00000OA‐FDK‐Ver.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/UMK65FDKLLC scp ‐r
[email protected]:/opt/umc65nmll/Documents /opt/umc65nmll/
Video Tutorial Links A Video tutorial is available in three parts at Part 1 - Transistor basic views
- 5:43
Part 2 - Layout of Inverter, DRC, LVS, and PEX
- 31:59
Run DRC at 18:00 Run LVS at 24:34 Run PEX at 28:34 Part 3 - Simulating with PEX (Calibre) Netlist
- 2:29
Layout editor (brief) Beginner Guide (Notes) Note: To ensure that there are no warnings after PEX extraction, use capital letters for all port/pin names (there is some issue with our Calibre PEX extraction flow or the tool itself). Launch --> Layout XL Read the message and click OK (twice) Connectivity --> generate --> All from source Select only Instances (Deselect "IO Pins" and "PR Boundary") and Click OK Hit "Shift + F" to display all layers Options --> Display Minimum grid spacing is 5nm (loosely speaking), so change the settings accordingly Minor spacing 0.005 Major spacing 0.05 X Snap Spacing 0.005 Y Snap Spacing 0.005 Poly layer is called PO1 PMOS transistors require a NTAP use M1-NWELL contact NMOS transistors require a PTAP use either M1-PSUB or M1-PACTIVE contact During PEX extraction at the "Calibre View Setup", select the radio buttons - Calibre View Type: schematic; Create Terminals: Create all terminals; Device Placement: Arrayed
Quick Shortcuts Fit Screen
f
View layers of instances
Shift + f
Don't show layers inside instances Ctrl + f Draw Rectangle
r
Draw Via/Contact
o
Draw label
l (Select _CAD TEX layer)
Move Object
m
Copy Object
c
Scale Object
s
Zoom-in
z
Zoom-out
Shift + z
Rul er
k (ri ght -click t o edit propert ies -- rem ove snap t o edges)
Clear Ruler
Shift + k
P at h t ool
p or S hif t + p (depends on your conf igurat ion)
Gravity
g (toggles ON and OFF)
Documentation Some helpful documentation can be found in the following file (including screen-shots) Note that our own setup differs slightly from the one described in the documents below: User Guide
/opt/umc65nmll/G‐9FD‐LOGIC_MIXED_MODE65N‐LL_LOW_K_UMK65FDKLLC00000OA‐FDK‐Ver.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/doc/FDK_OA_User_Guide_V1_2.pdf
DRC Rules file
/opt/umc65nmll/Documents/TLR/G‐03‐LOGIC_MIXED_MODE65N‐LL‐TLR‐Ver.1.18_P1.pdf
Layer information
/opt/umc65nmll/Documents/Intercap/G‐04‐LOGIC_MIXED_MODE65N‐LOW_K‐INTERCAP‐Ver.1.2_P1.pdf
RTL to GDS flow This section would cover the basic set of commands and the back-end tool flow required to synthesize the RTL and then take it through PnR to arrive at a GDS.
Logic Synthesis Synthesis is the process by which a behavioural RTL code is converted to a structural netlist, with the specified area, power and performance constraints. The inputs to the synthesis flow are the RTL, the constraints (.sdc file) and the timing libraries (.lib files). We would be using Cadence RTL Compiler (RC) as our synthesis tool. Firstly, ensure that you're working in c-shell
tcsh
Create your working directory. For this example, we will assume that your design name is "counter"
mkdir ~/counter_synthesis cd ~/counter_synthesis Replace counter with
Copy the required setup files and scripts to your working directory
cp ‐rf ~/synthesis_setup_files/* .
Create a directory for the RTL files
mkdir rtl
Copy your RTL file/files to this directory
cp ./rtl
Now all the required files are present in the counter_synthesis directory. Let's see what files are present ls ‐ltr
You should see the following files and directories :setup.g, constraints_top.g, template.tcl, library, rtl Setup.g is the basic setup file which initializes few variables. We need to edit this file. We'll use vim editor to edit files. For very basic vim commands, please see the end of this section. Please search online if you need more commands.
vim setup.g
On line number 11, please specify your rtl files. These files should be present in your rtl directory. By default, the line would look like this
set FILE_LIST
{mem.v top.v mux_2to1.v phase_inc.v}
Change it to
set FILE_LIST
{ , etc..}
On line number 16, you need to specify your top module name. By default, the line would look like this
set DESIGN
top
Change it to
set DESIGN
Close the file setup.g Next, open constraints_top.g
vim constraints_top.g
This file contains the timing constraints. Line 1 specifies the clock. The deafult time unit is 1ns. Line 1 thus specifies a clock of 100 MHz with a duty cycle of 50%. We would be synthesizing this design at 100 MHz. Lines 3 to 5 specify the clock transitions and clock uncertainties. We'll keep them at 1% and 10% respectively for this example. Lines 7 to 12 specify the input transition times and line 14 specifies the output transition times. We'll keep these at 10% for this example. The following changes need to be done to this file.
Change line 1 as : create_clock ‐name clk ‐period 10 ‐waveform {0 5} [get_ports "clk"] Change to create_clock ‐name clk ‐period 10 ‐waveform {0 5} [get_ports ""] Modify lines 7 to 12 as (add or delete lines wherever necessary) [get_ports ""] Modify line 14 as (add or delete lines wherever necessary) [get_ports ""]
Close constraints_top.g. Your setup is ready now. Next, we have to initialize a few variables related to cadence tools. Run the following command. source /home/smart/word_cad_65nm/cadence.cshrc
Next, invoke RTL Compiler
rc ‐gui
Minimize the gui and source the following files in the terminal (rc - shell)
rc:/> source setup.g rc:/> source template.tcl
(This is your main synthesis script )
Your design should get synthesized after this step if everything was done right. If you want to view it on the gui, double click on your top module name. You can exit RTL compiler now
rc:/> exit
You'll find that there are a few directories written out in your work directory. One of them, calledreports_, will have your synthesis reports. You can go through the reports to see a few metrics of your design, eg timing characteristics, area, power, gate count. Alternately, you can enter commands in the rc shell after synthesis to view detailed information about your design. The directory called outputs_, would have the output files after synthesis. is the synthesized netlist. You should have a look at this file. This is the netlist that would be taken forward for PnR.
Physical Design The process of converting a netlist into manufacturable geometrical structures having the desired functionality and satisfying the various timing and design rule constraints can broadly be called as the activity of physical design. For the purposes of this lab, we would go through the very basic vanilla flow to convert our netlist to a GDS. We would not be doing any timing or physical verification checks. Physical Design can broadly be divided into the following sub-tasks, which are, in order Partitioning Floorplanning Power Planning Placement Clock Tree Synthesis (CTS) Routing Physical Verification Parasitic Extraction and Back Annotation Timing Analysis & Closure DFM, DFY and Tapeout We would go through the tool flow of each of these steps without getting into theoretical details. Physical Verification, extraction and timing analysis is beyond the scope of this lab.
Initial Setup Again, we'll assume that the design name is counter. Create your work area as :
mkdir ~/counter_pd cd ~/counter_pd
Copy the required setup files and the generated netlist and sdc from your synthesis work area cp ‐rf ~/pd_setup_files/* .
cp ~/counter_synthesis/outputs_/*.v . cp ~/counter_synthesis/outputs_/*.sdc . Please change the above to copy from your synthesis output directory
Your work directory will now have 5 items : design.view, lib, lef, .v, .sdc Open design.view
vim design.view edit line 5 to change top.sdc to .sdc Close the file.
Now we are ready to launch our PnR tool, Cadence SoC Encounter. But before that, source the cadence cshrc file.
source /home/smart/work_cad_65nm/cadence.cshrc
Invoke encounter
encounter
We first need to load the required files
Go to File ‐> Import Design Under the "Verilog" tab, under "Files", enter the name of your netlist, .v (or browse and select the file & click add) Change the "Top Cell" to "Auto assign" Under the "Technology/Physical Libraries" tab, select "LEF Files" Browse to the lef/all.lef file and click add Under "Power", enter VDD as the power net and VSS as the ground net Under "Analysis Configuration", add the design.view file in the MMMC View Definition File section. Click OK
Your Design should get initialized now. Click on the Floorplan View button, next to online help, on the top right corner of the screen. Press f to fit everything on screen.
You should now see your initial setup ready with the standard cells shaded on the left of the estimated floorplan.
Floorplanning Click on Floorplan ‐> Specify floorplan Change the Ratio to 1 Change core utilization to 0.6 Change Core to left, core to right, etc.. (all 4) to 10 Click OK
You should now see the square floorplan with the area assigned for power rings on your screen.
Power Planning Click on Power ‐> Power planning ‐> add ring Under nets, browse and select both VDD and VSS, click add, and click OK. Under "Ring Configuration", change Top and Bottom to Metal5 Horizontal; and Left and Right to Metal6 Vertical Change width and spacing to 2 under each column. Under "offset", click on "centre in channel" Click OK
You should now see the power rings around the core area. Next, we need to add the power stripes.
Click on Power ‐> power planning ‐> add stripe Select both VDD and VSS under nets. Change the layer to Metal6, and direction to Vertical. Change width and spacing to 2 Change set to set distance to 20 Click OK.
You should now see the vertical metal stripes on your screen. We now need to provide power to the standard cell rails by dropping vias.
Click on Route ‐> Special route Select VDD and VSS as nets Click OK
The standard cell rails have now been provided with VDD and VSS
Placement Click on Place ‐> Place standard cell Click OK
After the placement run is complete, click on Physical View button next to "online help" on the top right corner. You sould now see the standard cells placed in your design.
Clock Tree Synthesis Click On Clock ‐> Synthesize clock tree Click on gen spec, and select all the clock buffers and clock inverters available in the library. (ie all cells starting with CLK*) and click ADD and OK Click OK
Your clock tree should get synthesized after this step.
Routing Click on route ‐> nano route ‐> route Click OK, leaving all options as default
This should complete a vanilla detailed route run.
Final Steps Adding filler cells - Any unused area in your floorplan must be f illed up with fillers to ensure well continuity among other things. Do t he f ollowing t o add filler cells
Place ‐> Physical Cell ‐> Add filler Select all available filler cells Click OK
Timing check - Let us see how our setup checks look. Timing ‐> report timing Choose post‐route under design stage Choose "setup" under analysis type. Click OK
Check the reports on the terminal (or detailed reports in your work directory). As we targetted the design for 100 MHz, which is very conservative in the 180nm process, your design should have easily met timing. In your reports, the number of violating paths (FEPs) and the TNS should be zero. To save your post-PnR netlist, do the following
File ‐> Save ‐> Netlist Name your file as _post_pnr.v
To export the GDS, do the follwoing
File ‐> Save ‐> GDS/OASIS Select GDSII as the format Name the file as .gds Click OK
The GDS should get written out in your working directory. You can try out other options/commands with encounter. Finally, close encounter
encounter 1> exit
Acronyms RTL - Register Transfer Logic GDS - Graphical Database System PnR - Place and Route SDC - Synopsys Design Constraints lib - Liberty format RC - Cadence RTL Compiler CTS - Clock Tree Synthesis DFM - Design for Manufacturability DFY - Design for yield LEF - Library Exchange Format FEP - Failing End Points WNS - Worst Negative Slack TNS - Total Negative Slack
Basic vim commands Opening a file
vim
Vim has 2 modes, command mode and insert mode. Command mode is where you enter vim commands and insert mode is where you type. By default, vim enters command mode on launch. To enter insert mode, press i
i
To return to command mode, press ESC
ESC
To save a file, in command mode, type
:w!
To quit without saving, in command mode, type
:q!
To save and quit, in command mode, type :wq!
To view line numbers, in command mode, type
:se nu
Monte Carlo Simulations Here are some basic pointers to running monte carlo simulations - that is usedto study the effect of variations.
ADE XL evironment As ADE L does not support running Monte Carlo simulations, you will have to use ADE XL. First get acquianted with the ADE XL by running a simple transient simulation Launch ADE XL from the schematic editing window Launch --> ADE XL Select "Create New View" and click "OK" Select appropriate options in the next window (default will do) and click "OK" Create --> Test --> setup transient simulation in ADE L as usual "Outputs setup" tab select on notepad+pencil icon to "set up plotting options" Plotting option select Auto to automatically plot outputs Run the transient simulation by hitting green arrow run button
Monte Carlo simulation For Monte Carlo, select "Monte Carlo sampling" in pulldown options - which is "Single Run, Sweep and Corners" by default Go to ADE L and select the new model and add the appropriate section number Setup --> Model Libraries Delete existing lines Add the file "/opt/umc65nmll/G-9FD-LOGIC_MIXED_MODE65N-LL_LOW_K_UMK65FDKLLC00000OA-FDKVer.B10_PB/UMK65FDKLLC00000OA_B10_DESIGNKIT/UMK65FDKLLC00000OA_B10/Models/Spectre/Monte_Carlo/l65ll_v171_mc.lib.scs" with the sections "mc_ll_rvt12", "mc_ll_lvt12", and "mc_ll_hvt12" as demonstrated in lab. So there should now be 3 lines in the list which are enabled (have a tick mark against their line). In Data-view sub-window, select "global variables" -> "click to add variable" -> add a variable called "sigma" with a value of 3 - this is as recommended by our foundry Select simulation options next to pull down menu and set appropriate monte carlo options Tick "Save data to allow family plots" Run using green-arrow button and see the family of curves
A good tut orial with screenshots i s available here
.
Cadence documentation for ADE XL may be found at "/opt/cadence/IC616/doc/adexl/adexl.pdf".
The documentation for all tools is available at "/opt/cadence/IC616/doc/" - explore them to improve your understanding of the tools.
