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http://www.vlsi.wpi.edu/cds/flow.html This site contains a complete on-line tutorial for a typical bottom-up design flow using CADENCE Custom IC Design Tools (version 97A). The examples were generated using the HP 0.6 um CMOS14TB process technology files, prepared at North Carolina State University (NCSU) and made available through MOSIS.
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0- Login and Running Cadence 1. To run Cadence, type in a terminal : cds /usr/local/tools icfb &
It will take a while, until Cadence setup is finished. 2. Two windows will appear on the screen : •
Command Interpreter Window
Command Interpreter Window (CIW) is the main window of the Cadence software environment, which enables you to have control over every part of Cadence. You can perform many tasks using CIW : • • • • •
Open new windows Start tools and quit design sessions View warnings, errors and other informational messages Change the configuration of your working environment Use the Input Line for typing commands
•
Library Manager
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The Library Manager is a tool that you can use to organize your libraries and cells in a design. It has three main boxes (columns) which correspond to Library, Cell, and View, respectively. The following is a list of operations you can do on the libraries and cells using the Library Manager : • • • • • • •
Create Delete Move Copy Rename Edit properties Import/export data
For more information refer to Cadence Design Framework II Help.
Cadence Design Framework II Help The Cadence Design Framework II (DFII) Help manual is a comprehensive document on using Cadence DFII tools that can be accessed from within the Cadence environment. You can access the manual in two ways : • •
Type the following at the command prompt in any shell to open the stand-alone manual. remote> openbook &
The main menu of the manual will pop up as seen below.
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Click on the Help button on any Cadence application
For example, if you click on Help in a schematic editor, the following help page shows up.
NOTE: If you encounter any problems with accessing the main menu of the manual, try typing openbook -quit
at the command prompt.
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1- Design Specifications The bottom-up design flow for a transistor-level circuit layout always starts with a set of design specifications. The "specs" typically describe the expected functionality (Boolean operations) of the designed block, as well as the maximum allowable delay times, the silicon area and other properties such as power dissipation. Usually, the design specifications allow considerable freedom to the circuit designer on issues concerning the choice of a specific circuit topology, individual placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of the final design. Note that the limitations spelled out in the initial design specs typically require certain design trade-offs, such as increasing the dimensions of the transistors in order to reduce the delay times. In a large-scale design, the initial design specifications may also evolve during the design process to accomodate other specs or limitations. This implies that the designer(s) of individual blocks or modules must communicate clearly and frequently about the spec updates, in order to avoid later inconsistencies. As an example, the initial design specs of a one-bit binary full adder circuit are listed below: • • • • •
Technology: 0.8 um twin-well CMOS Propagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case) Transition times of "sum" and "carry_out" signals <1.2 ns (worst case) Circuit area < 1500 um^2 Dynamic power dissipation (at VDD=5 V and fmax=20 MHz) < 1 mW
It can be seen that one can design a number of different adders (with different topologies, different maximum delays, different total silicon areas, etc.), all of which essentially conform to the specs listed above. This indicates that the starting point of a typical bottom-up design process usually leaves the designer a considerable amount of design freedom.
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2- Schematic Capture The traditional method for capturing (i.e. describing) your transistor-level or gate-level design is via the schematic editor. Schematic editors provide simple, intuitive means to draw, to place and to connect individual components that make up your design. The resulting schematic drawing must accurately describe the main electrical properties of all components and their interconnections. Also included in the schematic are the power supply and ground connections, as well as all "pins" for the input and output signals of your circuit. This information is crucial for generating the corresponding netlist, which is used in later stages of the design. The generation of a complete circuit schematic is therefore the first important step of the transistor-level design flow. Usually, some properties of the components (e.g. transistor dimensions) and/or the interconnections between the devices are subsequently modified as a result of iterative optimization steps. These later modifications and improvements on the circuit structure must also be accurately reflected in the most current version of the corresponding schematic.
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A detailed example description of "Schematic Capture" The basic steps to capture a schematic are the following: • • • • • • •
Open a new schematic design Select and place components Pick up supply voltages Wire components Edit component properties Place pins Check&Save
Example : Schematic Capture (CMOS Inverter)
Step 1 : Open a new schematic window Note : Before you begin with going through this example, be sure that you have the Library Manager open. 1. Click File on the menu banner in the Library Manager and hold the left mouse button until you choose New and then Cellview.
A small new window called "Create New File" appears.
2. There are four main fields in the Create New File window : •
Library Name You have to choose your working directory by clicking and holding the left mouse button on the Library field. Since our library name is "tutorial" in this example, we choose the corresponding label, "tutorial".
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Cell Name Enter the name of your cell for which you will draw the schematic. In our example, we will draw the schematic of an inverter, so we type "inverter" in the Cell Name field.
•
View Name The View Name indicates the level of the design hierarchy. You can determine that you are going to draw either a symbol or a schematic or a layout in this field just by typing the corresponding view name. Since we will draw the schematic of an inverter, the correct view name choice is "schematic" for our example.
•
Tool Here, you have to select the design editing tool that you will use to enter your design. The tool depends on the hierarchy level of your design. If you click and hold the left mouse button on the tool field, you will see the available tools. Only three of these tools will be used for all the examples. Composer Schematic Composer Symbol Virtuoso Layout
: Schematic editor : Symbol editor : Layout editor
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Since we will draw a schematic, we choose "Composer Schematic". Choosing Composer Schematic automatically converts the View Name to schematic. Actually, the selected tool converts the View Name to the corresponding one.
3. Now, click on "OK" to close this window and open the new schematic editor window chosen in the "Create New File" window.
Step 2 : Add components Note : At this point, you should have an empty schematic editor window open. 1. The first thing to do is to add and place components which will be used in the schematic. The components we need for a schematic of an inverter are the following : • • • •
PMOS : p-type MOSFET NMOS : n-type MOSFET VDD : Power supply voltage GND : Ground line
To add components, click on Add in the menu banner of the schematic entry window and choose Component, as shown below. ( Add --> Component )
2. Two new pop-up windows appear. One of them is "Add Component Window", where you can enter the Library Name, Cell Name and the View Name of the component to be added to the schematic.
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The other window is the "Component Browser", which enables the designer to browse easily through the available libraries and select the desired components.
Component Browser pops up every time the Browse button on the Add Component window is clicked. 3. We begin picking up the components by selecting the MOS transistors from the Component Browser window. You must be careful to pick up the components from the correct library. You can change the component library simply by clicking and holding the left mouse button on the library field. The correct library is "NCSU_Analog_Parts", so, select this library if it is not selected when you opened the Component Browser. After all, the window should appear like shown above. There are many folders under this library. Each of them is named depending on the components they include. So, to pick up an n-type MOSFET, you have open the "N_Transistors" folder by clicking once on it. The new folder contains many symbols which are also shown in the picture below. Pick up the NMOS transistor by clicking once on "nmos", which is a model for a three terminal n-type MOSFET.
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If you move the mouse cursor on the schematic window, you will see a bright NMOS transistor symbol moving with the mouse pointer showing the gate terminal of the transistor. At this point, you decide where to put this transistor. Click on a location in the schematic window, where you want to put the transistor. Please refer to the images below to see the difference between a "to be placed" transistor (left image) and "a placed transistor" (right image).
The same procedure can be applied to select and to place the PMOS transistor. The only difference is to pick "pmos" from the "P-Transistors" folder in the Component Browser. The "select-and-place" procedure for PMOS is summarized below.
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Note : Always make sure that you are not confusing a PMOS transistor with an NMOS transistor. The differences between the PMOS symbol and the NMOS symbol are: • •
There is a tiny circle at the gate terminal of PMOS transistors. The direction of the arrow which always marks the source terminal of the transistor is different. The arrow points from the source terminal towards the transistor in the PMOS symbol, while it points out towards the source terminal in the NMOS symbol.
Step 3 : Placing supply voltage components 1. Picking up the supply voltage components involves the same steps as in adding transistors to the schematic. • •
Choose Add and then Component on the menu banner if you somehow closed the Component Browser window. Click on the folder "Supply_Nets", so that you will access the components in this folder.
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We will put the components "vdd" and "gnd" in our schematic. You can pick up one of them simply by clicking on the corresponding one. Let's assume that we take "vdd" first, so, click on "vdd", move the mouse on the schematic window and place the component by clicking a location in that window. The individual steps of this procedure are described in the images below.
2. You can follow similar steps for placing the "gnd" component.
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3. At this point, we are finished with selecting and placing the necessary components. Press "ESCAPE" (ESC) key on the keyboard to close the Component Browser and Add Component windows. 1. After all the components are placed, they should be connected according to the function they realize. To connect the components in a schematic, we use wires by choosing Add and then Wire (narrow) on the menu banner. ( Add --> Wire (narrow) )
This command initiates the wiring mode. 2. A new window called Add Wire will pop-up.
In this window you can change the routing method and the draw mode. 3. We begin to wire the components by connecting VDD and the source terminal of the PMOS transistor. Every component has tiny red squares on its terminals where you can do the wiring. Connecting any two nets in the schematic is done by first clicking at one of the nets and then at the other one.
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During these steps, you will always be prompted by the schematic window. The message appears in the bottom most field of the schematic window. If you follow the instructions prompted in that field, you can easily complete your job. In this step, the following phrase will be prompted : Point at the starting point for the router Since we begin with wiring the VDD and the source of PMOS, we click first at the center of the red square which corresponds to the VDD net.
One end of the wire is now fixed, and you will realize that the other end floats and moves according to the mouse pointer. You will also see that the nearest net to the floating end of the wire is automatically highlighted. The new prompt is the following : Point at ending point for the router
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3. Click on the target net which is the source terminal of the PMOS transistor .
This was the final step of connecting the two nodes. The same procedure can be applied for the rest of the nodes; first choose any two nodes which should be connected. Then, wire them together just by clicking first one of them and then the other. As long as you are in the wiring mode, you will be prompted about the next step you have to do, as described above. Press ESC on the keyboard, to leave the wiring mode. You will be in this mode, as long as you don't press ESC or choose another command from the menu. 4. The remaining steps are summarized below. In the wiring mode, •
Click on the drain terminal of PMOS. Click on the drain terminal of NMOS.
•
Click on the gate terminal of PMOS. Click on the gate terminal of NMOS.
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Click on the GND node. Click on the source terminal of NMOS.
5. Your schematic should look like the schematic shown in the image below.
Press ESC key to leave the wiring mode.
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Step 5 : Edit properties of components The components you select and place from the library always come with a set of default parameters or properties. You can (and usually should) modify component properties according to your design specifications. Here are the steps to edit component properties in the schematic window. 1. Select the PMOS transistor by clicking on it . The selected component should be highlighted by a bright rectangle (box) around it.
2. Choose Properties and then Object from the Edit menu.
A larger window with many editable fields appears which is called the Edit Object Properties window. 3. Edit the properties by clicking on the corresponding field. You may change the values for Width or Length depending on your design specifications. Usually, you will change only the Width value, which stands for the channel width, W. The default values for these properties are the smallest available values which are determined by the current technology.
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To edit the channel width of the transistor, click on the Width field. Then enter a new value which is either a result of your calculations or just an initial value to see how the performance changes depending on this variable. While changing a parameter, you have pay attention to the unit you use (click here for the list of units). The channel width is changed to 1200 nm (nanometers) which is equal to 1.2 um (micrometers).
4. Click OK after editing the properties in the Edit Object Properties Window. The most important parameters (type, dimensions) always appear in the schematic window. You can easily observe the changes of these properties that are listed near the corresponding transistor in the schematic.
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Step 6 : Placing the pins You must place I/O pins in your schematic to identify the inputs and the outputs. A pin can be an input or an output or an input-output (bi-directional) or a switch pin. We will only use an input pin and an output pin in our inverter schematic. 1. Click Add on the menu and then select Pin on the pull-down menu.
2. The Add Pins window appears.
3. Enter the name of your input pin in the Pin Names field. The input name in this example is "Inp" (note that the pin names can be completely arbitrary). Also, note that the Direction option is set to Input indicating that the current pin is an input pin. As long as you enter pins of the same direction, you can enter pin names one after the other in the Pin Names field, only putting space between them. In this case, each time you place a pin, the next one will appear until all your pins are placed in the schematic.
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4. Move the mouse cursor on the schematic window to place pin. Now, you have your input pin with the name "Inp" floating in the schematic window. Point to a location to place the input pin. Since the input is the gate terminals of both transistors, it is more convenient to put this pin in front of the common node of these terminals.
4. Go back to the Add Pin window to pick up an output pin. First, you have to change the pin direction to Output. To do this, click the left mouse button on the Direction field and select Output in the pop-up menu. Enter the output pin name, which is "Outp" in our example.
5. Place the output pin by clicking on a lcoation in the schematic window. The procedure is completely analogous to the placement of input pins. Now it is better to put the output pin near the common drain node which is the output of the inverter circuit.
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At this point, you are finished placing the pins. Press ESC on the keyboard to close the Add Pin window. 6. Connect the pins to the corresponding nodes using wires. The wiring procedure is the same as described in the previous steps. Wiring the pins is summarized below : Click on Add on the menu and then select Wire (narrow). You are now in the wiring mode again. •
Click on the input pin. => The other end of the wire is floating. Click on a point on the common wire which connects the gate terminals of both transistors, PMOS and NMOS.
•
Click on the output pin. => The other end of the wire is floating. Click on a point on the common wire which connects the drain terminals of both transistors, PMOS and NMOS.
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Press ESC to close the wiring mode.
At the end of this step, your schematic should look like the following:
Step 7 : Check and Save 1. Click Design on the menu banner and then select Check and Save.
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During this tutorial, you may save your design selecting Save on the Design menu. It is also strongly advised that you save your designs frequently, every time after you make significant changes, so that you don't loose your data because of a computer crash or because of a mistake that can happen in a complicated design environment such as this one. 2. Check the message field in the CIW window to see the error and the warning messages.
You can see the message in the screen-shot above indicating that there is no error in our schematic. If this wasn't the case, the errors would have been listed in this window. Check the message field every time you save a design.
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3- Symbol Creation If a certain circuit design consists of smaller hierarchical components (or modules), it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. This step largely simplifies the schematic representation of the overall system. The "symbol" view of a circuit module is an icon that stands for the collection of all components within the module. A symbol view of the circuit is also required for some of the subsequent simulation steps, thus, the schematic capture of the circuit topology is usually followed by the creation of a symbol to represent the entire circuit. The shape of the icon to be used for the symbol may suggest the function of the module (e.g. logic gates - AND, OR, NAND, NOR), but the default symbol icon is a simple rectangular box with input and output pins. Note that this icon can now be used as the building block of another module, and so on, allowing the circuit designer to create a system-level design consisting of multiple hierarchy levels.
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A detailed example description of "Symbol creation" The basic steps to create a symbol are the following: • • • • •
Open the schematic design Create the cellview Locate the pins Edit shape of the symbol Check&Save
Example : Creating a Symbol
Step 1: Opening an existing schematic Note : You can skip this step if you have your schematic window open. 1. Select your library by clicking on it in the library column of the Library Manager. The cells in the library will appear in the cell column. 2. Select your cell by clicking on it in the cell column of the Library Manager. The existing cellviews of your cell will appear in the view section. At this point, there should be only the "schematic" view appearing in the "view" column.
3. Select your cellview by clicking on it in the view column of the Library Manager.
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The name of the selected view will appear in the small cell window. 4. In the Library Manager Window, select Open from the File menu: ( File --> Open ) The schematic of the design will pop-up.
Step 2 : Creating cellview 1. From the Design menu, select Create Cellview and then From Cellview : ( Design --> Create Cellview --> From Cellview )
The following window will pop up.
2. Check the view names and click OK Before clicking OK, you have to ensure that the target view name is symbol, which is indicated with "To View Name" in the bottom-right corner of the pop-up window. If not, then you can change the target view name to "symbol" by clicking and holding the left mouse button on the corresponding box.
Step 3 : Locating the pins 1. After clicking OK in the Cellview From Cellview, window the following window pops up :
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In this window (Symbol Generation Options) you can edit your pin attributes and locations. In the default case, you will have your input(s) on the left and your output(s) on the right of the symbol.
You can change your pin locations simply by putting the pin name in the corresponding pin location field. 2. If you don't want to change anything or you are finished with editing the pin specifications, then press OK to continue. A new window will appear, showing your new symbol. This is the "black box" or symbol representation of your schematic.
Step 4 : Editing the shape of the symbol icon 1. In the new window, the automatically generated symbol is shown. As seen in the window, the default shape of the symbol icon is a rectangle, with the pins located as defined during the previous step in Symbol Generation Options pop-up window. The small red squares indicate the connection points for each corresponding pin. The red rectangle surrounding the whole symbol determines the clickable area to select the symbol when used in a schematic.
2. If you are not satisfied with the symbol properties, then you can create a new symbol simply by editing the existing one.
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You can do the following operations on your symbol : • • • •
Deleting/replacing some existing parts Adding new geometric shapes Changing the locations for pins and instance name Adding new labels
The following is an example for a manually created inverter symbol, which was obtained by editing the symbol above.
Step 5 : Check and Save 1. To check and save the symbol, choose Check and Save from the Design menu : ( Design --> Check and Save )
While editing the symbol, you can use only Save, which does not check anything. At this point, checking a symbol means comparing the symbol view with the corresponding schematic view, by matching all of the pin names. This occurs only when you click on Check and Save.
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4- Simulation After the transistor-level description of a circuit is completed using the Schematic Editor, the electrical performance and the functionality of the circuit must be verified using a Simulation tool. The detailed transistor-level simulation of your design will be the first in-depth validation of its operation, hence, it is extremely important to complete this step before proceeding with the subsequent design optimization steps. Based on simulation results, the designer usually modifies some of the device properties (such as transistor width-to-length ratio) in order to optimize the performance. The initial simulation phase also serves to detect some of the design errors that may have been created during the schematic entry step. It is quite common to discover errors such as a missing connection or an unintended crossing of two signals in the schematic. The second simulation phase follows the "extraction" of a mask layout (post-layout simulation), to accurately assess the electrical performance of the completed design.
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A detailed description of "Simulation". The basic steps to simulate a design are the following: • • • • • • • • • •
Open a new schematic design Select and place components (circuit symbol to be simulated) Select and place components (test-bench elements) Wire components Define the voltage sources Determine the output load Open the simulator window Edit your simulation parameters Run the simulation Re-run the simulation
Step 1 : Open a new schematic design Note : You should first create the symbol of the circuit schematic which you want to simulate. If you did not have the symbol for the schematic, refer to the "Create Symbol" example. 1. Open a new schematic. Follow the same procedure described in "Open a New Schematic" to create a new schematic where you will put your simulation schematic for the inverter. Give a name to your new schematic which makes it clear that the new schematic is to simulate the inverter. The new schematic is called "invTest" in this example.
Step 2 : Select and place components Note : At this point, you should have an empty schematic editor window open. 1. The first step is to add and to place the components which will be used to simulate the inverter. The components we need for the simulation of the inverter are the following : * inverter
Symbol created for the inverter
* VDD Power supply
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vdc
DC voltage source
Pulse * vpulse waveform generator *
C
Capacitor
Adding and placing components in a schematic was explained previously [click here for the corresponding example]. Here you will see how to pick up a symbol you created from your library, and to place it in your schematic. 2. Click Add and select Component.
Two new pop-up windows appear, Component Browser and Add Component.
Click Browse in the Add Component window to activate the Component Browser.
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3. You should pay attention to the library from which you take the components. The point where you have to take care of is picking up the components from the correct library. You can change the component library simply by clicking and holding the left mouse button on the library field. In this step, we have two source libraries, one is the given component library "NCSU_Analog_Parts", and the other is our design library which contains the components that we designed stored previously. This library's name in our example is "tutorial". This means, to pick up the inverter symbol, we have to change the library of the Component Browser to our library, "tutorial". This can be done, as explained in previous steps [click here for the corresponding example], by clicking and holding the left mouse button until you select the corresponding library in the pop-up library list.
After the library "tutorial" is selected, there will be a new list of components which are included in this library. Every symbol that you created within this library will show up here. So, by clicking on "inverter" in the component list in the Component Browser, you can pick up the symbol you created for the inverter.
You can always check the corresponding fields in the Add Component window to make sure that you selected the desired component. This can be easily seen in the image below.
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You can go to the schematic window and place the symbol of the inverter to a point by clicking on it. These two images below show the symbol before placement and after placement.
We are now finished placing the symbol of the inverter. Placement of the other components will be explained in the next step.
Step 3 : Select and place components Note : You do not have to place the components exactly the same way as seen in the example images. As long as you connect them correctly, you can always move a component to some other location in the same schematic. 1. Pick up and place the rest of the components required for the simulation. The remaining components are in the "NCSU_Analog_Parts" library. Change your library from "tutorial" to "NCSU_Analog_Parts". Refer to the previous example (step 3 :"Changing the library in the Component Browser window") to see how you can change the source library. •
Place the supply nets, "vdd" and "gnd".
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Open the folder "Supply_Nets", select "vdd" and "gnd" and place them anywhere in the schematic window. Your original circuit schematic already does have these supply nets attached to its appropriate nodes, but now you have to define the voltages in the new schematic window.
•
Place the voltage sources, "vdc" and "vpulse". Go up one folder to the main content folder. Open the folder "Voltage Sources", select "vdc" and "vpulse" and place them in the schematic window.
•
Place the capacitance which will be the output load, "cap".
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Go up one folder to the main content folder. Open the folder "R_L_C", select "cap" and place it in the schematic window.
We placed all the necessary components for this schematic. 2. Why did we put these components into this schematic ? You can think of this procedure (creating a new schematic and placing these components into the new schematic) as being analogous to building a "test-bench" for the circuit you designed. As in the real test-bench case, you must build a simple test set-up (consisting of voltage sources, load devices, etc.) around your original circuit to measure its operation and its characteristics.
Step 4 : Wire components Note : Always save your designs if you make any changes on it. If you make a mistake, you can use the undo command under the edit menu. 1. Connect the DC-voltage source "vdc" to "vdd" and "gnd". A DC-voltage source called "vdd" is required as the power supply voltage in all digital circuits. The value of this voltage usually depends on the technology used. The technology we use for this example is HP 0.6u AMOS14TB [click here for further information], which is low-voltage process meaning that the typical VDD voltage value is 3.3 V. N.B.: HP AMOS14TB is no longer available from MOSIS
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http://www.mosis.com/Technical/Processes/proc-hp-amos14tb.html Available Fabrication Processes http://www.mosis.com/Technical/Processes/ To supply the VDD voltage to the circuit, we will use a DC-voltage source with a constant voltage value of 3.3 V. How to configure the voltage value of the source will be explained in the next steps. The connections of the voltage source are shown in the image below. Simply wire the "vdd" with the positive terminal of the DC-voltage source and the "gnd" with the negative terminal of the voltage source.
2. Connect the pulse wavefrom generator "vpulse" to the input of the inverter "Inp". The pulse generator is a voltage source which can produce pulses of any duration, period and voltage levels. This source will be used to generate the input data (stimuli), so that we can observe the output of the inverter and see if the inverter operates correctly. Wire the positive terminal of the pulse generator to the input pin of the inverter "Inp" and then the negative terminal of the pulse generator to "gnd".
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For the sake of simplicity, you can also pick up more "gnd" components and put them into your schematic where it is needed. All nodes connected to the "gnd" symbol will be short circuited throughout the schematic, i.e., all of them will stay at the reference voltage level which is O V (zero volts). The following is an example to describe the case explained in the last paragraph. The connections in the schematic below describe the same circuit as in the schematic shown above.
To add a new component, you can either use the Add Component and the Component Browser window, or copy the component if it exists in the current schematic. For
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example, you may prefer to copy the existing "gnd" instance which is the one we connected with the DC-voltage source, rather than browsing through the libraries and the components. 3. Connect the load capacitance "cap" to the output of the inverter "Outp". In CMOS digital circuits, the output nodes are typically loaded by purely capacitive loads. One of the important specifications of a circuit would usually be its driving capability for a given capacitive load. The larger the capacitive load at the output, the larger the delays to drive this load. Wire the positive node of the capacitance to the output pin of the inverter "Outp" and then the negative node of the capacitance to "gnd".
4. At the end of these steps, your entire schematic looks like the following.
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Step 5 : Define the voltage sources In this step, we will enter the necessary parameters for the voltage source components. 1. Edit the properties of the DC-voltage source. Select the DC-voltage source by clicking on it. The selected component is highlighted by a bright box (rectangle) around it.
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Click Edit on the menu bar and select Properties and Object, respectively.
The Edit Object Properties window appears.
Edit the DC voltage field in the Edit Object Properties window and type the VDD value which is 3.3V in our examples.
Click the "OK" button on the Edit Object Properties window. You can observe the new value entered for the DC-voltage near the DC-voltage source.
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2. Edit the properties of the pulse generator Select the pulse generator instance in the schematic.
The Edit Object Properties window for the pulse generator appears.
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The parameters which are listed in the image above are used to define a pulse which will be repeated periodically. How to use these parameters to define the input pulse waveform is explained in the figure below.
The following image shows the values for the pulse generator parameters which are used to define the input waveform. Click on OK to apply these changes and close the Edit Object Properties window.
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Finally, the new values for the important parameters of the pulse generator appear near the its instance.
Step 6 : Determine the output load 1. Edit the properties of the capacitor which is the output load of the inverter. Select the capacitor by clicking on it.
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Click edit on the menu and select Properties and Object, respectively. The Edit Object Properties window appears. This time, the listed parameters are valid for the selected capacitor.
The only parameter we change is the capacitance. As shown in the previous image above, the default value for the capacitance is 1 pF (picofarads). This value may be too high for a typical inverter load in this technology. Refer to the "Commonly Used Prefixes for Units in Cadence". By editing the corresponding field in the Edit Object Properties window, we change the capacitor value to 25 fF (femtofarads).
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Click on OK in the Edit Object Properties window. The capacitance will be updated to the new value which is 25 fF.
2. Add labels to the nodes you want to observe after the simulation. In Cadence, labeling a node corresponds to adding certain names to the wires. In our example, there are two important nodes (or wires) which we want to observe during our simulations. These are the input and the output nodes of the inverter. You may think that you labeled these nets before while you were drawing the schematic for the inverter by adding the pins. But, those labels are only valid in that schematic which is now in the lower level of hierarchy. So, every time you create a symbol and use this symbol in a new schematic, you have give new labels to the nodes you want to specify. Select Wire Name in the Add command list, as shown below.
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The Add Wire Name window appears. Now, you can type all the label names one after the other in the Names field. You will see that there isn't any information related to the direction of the nodes, because only the pins are defined with a direction.
In the example, we will label the two wires as "in" and "out".
After all the labels are typed, move the mouse cursor on the schematic. Now you will see the first label floating with the mouse cursor. Click on the corresponding net to name the net with this label. As soon as you put the first label, the second label will appear on the mouse cursor. This procedure is repeated until you are finished putting all label names you entered in the Add Label window.
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The schematic with the wires ("in" and "out") labeled is shown in the image below.
Close the Add Label window either by clicking on OK in the window or pressing ESC on keyboard. Save your design by using Check and Save in the Design command list. Be sure that the CIW doesn't report any errors or any warnings.
Step 7 : Open the simulator window Now, we are ready to simulate our design. We will use Analog Artist as the simulator.
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1. Open the Analog Artist window. Click on Tools in the menu banner of the schematic entry window and choose Analog Artist.
The Analog Artist main window will appears, as shown below. As you can see, there are four main fields in this window. • • • •
Design Analyses Design Variables Outputs
Note that the library, the cell and the view names are listed in the Design field, so that you can check that you are simulating the desired cell using the correct view.
Step 9 : Run the Simulation Now, we have to select the nodes that we want to observe as simulation results. 1. Click on Outputs in the menu banner, select To Be Plotted and then Select on Schematic.
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The schematic window becomes active, so that you can select the nodes to be observed in that window. 2. Click on the nets which you want to observe in the schematic window.
The selected nodes are the input of the inverter, "in", and the output of the inverter "out" which drives the capacitive load. Each time you select a node, the corresponding wire name appears in the Outputs list. 3. Press ESC to finish your selections.
4. Start the simulation by clicking Simulation and then selecting Run.
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The waveform window appears after the simulation is completed. It includes the waveforms of the selected nodes plotted between t=0 and the determined Stop Time which is 30 ns in our example.
You will see the two waveforms together, plotted on the same time axis. To separate the waveforms, from the menu Axes select option To Strip. Once seperated you can select the waveforms by clicking on them and draging them on top of each other to group. To return to the initial composite waveforms, from the menu Axes select option To Composite. Notice that this option has replaced the former To Strip option.
Step 10 : Re-run the Simulation
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If you are not satisfied with the simulation results, there are two different aspects that can be modified : •
The simulation environment is not satisfactory. This means that the setup to simulate your design should be modified. You can basically change two things, the properties of the input signal you feed to the circuit and the amount of output load which is capacitive. Also, make sure that the power supply voltages are connected properly. Refer to the step "Define the voltage sources" to setup your input sources. Refer to the step "Determine the output load" to change the capacitance value of the capacitor. Refer to the step "Define the voltage sources" to check the connections of your power supply voltages. These changes are made without descending to a lower level of hierarchy in the design.
•
You have to modify your circuit design. Usually, you will need to change the W/L ratios (the ratio between the channel width and channel length) of the transistors to meet your design specifications. Therefore, you have to edit your design which consists only of a CMOS inverter in our example.
The procedure describing how to re-run the simulation after editing the design is summarized below. 1. Go back to the schematic window and select the symbol of your design. The symbol for the inverter should be selected in this example.
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2. Click on Design in the menu banner, select Hierarchy and then Descend Edit.
3. Click on OK in the Descend window which asks the designer which view of the design is to be edited.
The existing schematic window now displays the schematic view for the inverter, by going one level down through the design hierarchy. 4. Make the appropriate changes in the editable schematic of the design. To change the existing W/L ratio for a specific transistor, you have to edit its object properties. Refer to the "Edit Object Properties" step in the schematic example. 5. Check and save your new schematic. 6. Click on Design in the menu banner, select Hierarchy and then Return.
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Never forget that you are editing the design at a lower level of the hierarchy - you always must return to the original level from which you have descended. 7. Go to the Analog Artist window and run the simulation again, as described in "Run the Simulation" step. As the simulation runs, you can switch to the waveform window, because the waveforms will be updated after the simulation is finished. You can iterate on your design as described in this section of the tutorial. When you want to end the simulation, quit the Analog Artist simulator. This will automatically close the Waveform window, too. Note: Quitting a tool does not mean closing the corresponding window. Please always use the "close" or "quit" commands located in the menu bar of the tool.
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5- Mask Layout The creation of the mask layout is one of the most important steps in the full-custom (bottom-up) design flow, where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication, using a Layout Editor. Physical layout design is very tightly linked to overall circuit performance (area, speed and power dissipation) since the physical structure determines the transconductances of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area which is used to realize a certain function. On the other hand, the detailed mask layout of logic gates requires a very intensive and time-consuming design effort. The physical (mask layout) design of CMOS logic gates is an iterative process which starts with the circuit topology and the initial sizing of the transistors. It is extremely imporant that the layout design must not violate any of the Layout Design Rules (shown on the last pages of this tutorial), in order to ensure a high probability of defect-free fabrication of all features described in the mask layout.
Another alternative of generating the mask layout (other than manually design) is to make use of automated tools for generating a layout from a schematic using the device level placer.
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Note: Two detailed examples description are shown bellow the first is the main procedures in "Mask Layout Manual Design" and the second is a description of generating a layout from a schematic using the device level placer.
1- A detailed example description of the main procedures in "Mask Layout Manual Design". Example: CMOS Inverter Layout
In this tutorial, a simple CMOS inverter layout will be drawn step by step. We will start with a simple design idea and will complete the mask layout using different techniques.
Steps of Layout Design
•
•
Starting up o Design Idea o Create Layout Cellview o Virtuoso and LSW NMOS o o o o
Drawing the N-Diffusion (Active) The Gate Poly Making Active Contacts Covering Contacts with Metal-1
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The N-Select Layer
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PMOS
•
Drawing the P-Diffusion (Active) Transistor Features The P-Select Layer Drawing the N-Well Connecting both transistors
•
Placing the PMOS and NMOS Connecting the Output Connecting the Input Making a Metal-1 connection for the Input Power Rails P Substrate contact N Substrate contact Enclosing the Substrate Contact DRC and Finalizing
o o o o
o o o o o o o o
o o
Design Rule Checking Final Layout
Design Idea To draw the mask layout of a circuit, two main items are necessary at the beginning: 1. A circuit schematic 2. A signal flow diagram 1. Circuit schematic Any physical layout will actually correspond to a circuit schematic. It is important that the schematic of a functionally correct circuit is present and the layout is drawn according to the schematic (and not the other way around). The schematic will the contain exact connection diagram and individual device properties. Two example inverter schematics can be seen below. While both schematics are identical, the one on the right is drawn in a way to resemble the final layout.
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In this example the NMOS transistor and the PMOS transistor have identical dimensions W=1.2u and L=0.6u 2. Signal flow diagram (I think this is the same as stick diagrame) A layout can be drawn in a number of different ways. The most important factor determining the actual layout is the signal flow. The layout will almost in all cases be a part of a larger structure or the basic building element of an array of identical blocks. In modern fabrication technologies, more than one physical layer can be used to transfer signals. For example with the fabrication technology used throughout this manual, a total of 4 layers (poly, Metal-1, Metal-2, Metal-3) can be used. The general flow of the signal connections as well as their layers need to be pre-determined. The following is an sample flow diagram used for the example layout:
In this flow diagram, it has been decided that all signals are on the same layer (blue, Metal-1) and that all signals will travel horizontally. Note that the signal flow diagram is just a concept that you can visualize for a particular circuit, or a simple scetch that you can scribble on the back of an envelope. The actual mask layout will roughly follow this concept.
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Create Layout Cellview We will assume, that you have logged on and started Cadence Design Tools, and that you already have created a design library for yourself. Please refer to Starting Cadence Section if you have not done so. 1. From the Library Manager, choose File then New and then Cellview ( File --> New --> Cellview )
2. Enter cellname and choose layout cellview A dialog box will appear prompting you for the design library, cellname and cellview. Make sure that the library name corresponds to your design library, choose a name for your cell and choose Virtuoso as the design tool. The cellview will be selected as layout.
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Virtuoso and LSW Two design windows will pop-up after you have entered the design name.
LSW The Layer Selection Window (LSW), lets the user select different layers of the mask layout. Virtuoso will always use the layer selected in the LSW for editing. The LSW can also be used to determine which layers will be visible and which layers will be selectable. To select a layer, simply click on the desired layer within the LSW. Virtuoso Virtuoso is the main layout editor of Cadence design tools. There is a small button bar on the left side of the editor. Commonly used functions can be accessed by pressing these buttons. There is an information line at the top of the window. This information line, (from left to right) contains the X and Y coordinates of the cursor, number of selected objects, the travelled distance in X and Y, the total distance and the command currently in use. This information can be very handy while editing. At the bottom of the window, another line shows what function the mouse buttons have at any given moment. Note that these functions will change according tto the command you are currently executing. Most of the commands in Virtuoso will start a mode, the default mode is selection, as long as you do not choose a new mode you will remain in that mode. To quit from any mode and return to the default selection mode, the "ESC" key can be used.
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Drawing the N-Diffusion (Active) Now we will start drawing our first transistor. which will be the NMOS transistor of the CMOS inverter. From the schematic, we know that this transistor has a channel width of 1.2u. The width of the transistor will correspond to the width of the active area. We will select the n-diffusion layer and draw a rectangular active area to define the transistor. 1. Select nactive layer from the LSW
2. From the Create menu in Virtuoso select Rectangle ( Create --> Rectangle )
3. Draw the box You are now in rectangle mode. Select the first corner of rectangle in the layout window (you may select any point within the window but try to select a point close to the origin), click once, and then move the mouse cursor to the opposite corner. Using the information bar, draw a box that is 3.6u horizontal and 1.2u vertical. All units are in micrometers by default. To simplify the drawing, a grid of half a lambda is used, that is the cursor moves in 0.15u increments only.
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The Gate Poly The second step is to draw the gate. We will use a vertical polysilicon rectangle to create the channel. Note that the length of the transistor channel will be determined by the width of this poly rectangle. 1. Select poly layer from the LSW
2. From the menu Misc choose Ruler ( Misc --> Ruler )
The ruler is a very handy function. In our case we need to draw the poly rectangle in the middle of the diffusion region. Furthermore, design rules tell us that poly must extend at least by 0.6u (2 Lambda) from edge of the diffusion (D.R: Poly,Minimum gate extension of active). To pinpoint the location of the poly gate we can use two rulers. One ruler will be used to determine the horizontal distance of the poly gate from the diffusion edge, while a second ruler will show the minimum amount of poly extension outside the diffusion according to the design rules 3. Draw poly rectangle
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The starting point is pinpointed by two rulers. The rectangle function is used to draw a poly rectangle that is 0.6u horizontal and 2.4u vertical.
Making Active Contacts The next step is to make the active contacts. These contacts will provide access to the drain and source regions of the NMOS transistor. 1. Select the ca (Active Contact) layer from the LSW.
2. Use the ruler to pinpoint a location 0.30u from the edges of diffusion (D.R: ActiveContact, Minimum active overlap). 3. Create a square with a width and height of 0.6u within the active area (D.R: Active-Contact, Exact contact size).
4. From the Edit menu choose Copy ( Edit --> Copy )
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You could choose to draw the second contact the same way as you have drawn the first one. However, copying existing features is also a viable alternative. The copy dialog box will pop-up as soon as you select the copying mode. For this operation the default values are appropriate. The Snap Mode is an interesting option. When this is in orthogonal setting the copied objects will move only along one axis. This is a good feature to help you avoid alignment problems.
5. Copy the contact After you enter the copy mode, an object must be selected. Click in the contact, you'll notice that the outline of contact will attach to your cursor. Now move the object, and click when you are satisfied with the location.
Design rules state that the minimum contact to poly spacing must be 0.6u (2 lambda) (D.R: Active-Contact, Minimum spacing to gate of transistor). You can use a ruler to pinpoint the location. Please note that you can interrupt any mode for placing a ruler (and zooming in and out). After you are finished (by hitting "ESC" key) you'll return to the mode you were in.
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Now you have placed an active contact each into the source and drain diffusion regions of the transistor.
Covering Contacts with Metal-1 Active contacts in fact only define holes in the oxide (connection terminals). The actual connection to the corresponding diffusion region is made by the Metal layer. 1. Select layer Metal-1 from the LSW
2. Draw two rectangles 1.2u wide to cover the contacts
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Note that Metal-1 has to extend over the contact in all directions by at least 0.3u (1 lambda) (D.R: Metal-1,Minimum overlap of any contact).
The N-Select Layer Each diffusion area of each transistor must be selected as being of n-type or p-type. This is accomplished by a defining the "window: of n-type (or p-type) doping (implantation), through a special mask layer called n-select (p-select). 1. Select nselect layer from the LSW.
2. Draw a rectangle extending over the active area by 0.6u (2 lambda) in all directions (D.R: Select, Minimum select overlap of active).
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This is it ! Our first transistor is finished, now let us make a few million more of the same :-)
Drawing the P-Diffusion (Active) Now that we have drawn the NMOS transistor, the next step is to draw the PMOS transistor. The basic steps invloved in drawing the PMOS are the same. 1. Select pactive layer from the LSW
2. Draw a rectangle 3.6u by 1.2u You can use the cursor keys and the zoom function to find yourself a place to build the transistor. Make sure you leave enough separation between the NMOS and the PMOS. Note that the PMOS transistor will also be sorrounded by the N-well region.
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Transistor Features These three steps are identical to the ones done for the NMOS. 1. Draw the gate poly
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2. Place the contacts
3. Cover contacts with Metal-1
The P-Select Layer As with the NMOS transistor, the p-type doping (implantation) window over the active area must be defined using the n-pelect layer.
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1. Select pselect layer from the LSW
2. Draw a rectangle that extends over the active area by 0.6u (2 lambda) in all directions.
Drawing the N-Well In this process, the silicon substrate is originally doped with p-type impurities. NMOS transistors can be realized on this p-type substrate simply by creating n-type diffusion areas. For the PMOS transistors however a different approach must be taken: A larger ntype region (n-well) must be created, which acts like a substrate for the PMOS transistors. From the process point of view, the n-well is one of the first structures to be formed on the surface during fabrication. Here we chose to draw the n-well after almost everything else is finished. Note that the drawing sequence of different layers in a mask layout is completely arbitrary, it does not have to follow the actual fabrication sequence. 1. Select the nwell layer from the LSW
2. Draw a large n-well rectangle extending over the P-Diffusion
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The n-well must extend over the PMOS active area by a large margin, at least 1.8u (6 lambda) (D.R: Active, Source/drain active to well edge).
Placing the PMOS and NMOS transistors In this example, we did not pay much attention to the location of the transistors while building them. As long as the design rules are not violated, the transistors can be placed in any arbitrary arrangement. Yet based on our original signal flow diagram, it is more desirable to place the PMOS transistor directly on top of the NMOS transitor- for a more compact layout. 1. Select the PMOS transistor First make sure that you are in selection mode. If you are in any other mode (like rectangle drawing mode) exit the mode by pressing "ESC". Now using the mouse, click and drag a box that covers your PMOS. If you were successful, all the objects within the PMOS would be highlighted as in the figure below:
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2. From the menu Edit select the option Move ( Edit --> Move )
A window will pop-up similar to the copy window. This time we will have to change the Snap Mode option to Anyangle so that we can move the transistor freely.
3. Pick the reference point We will be asked to find a reference point for the object to be moved. The cursor will practically grab the object from that reference point. Since we want an accurate placement, it is advisable to select a point for which alignment is simpler. The corner between the diffusion and the poly is a good place to grab the PMOS. After we have picked the reference point, the outline of the shape will appear attached to the cursor and we will be able to move the shape around. Since the minimum distance from diffusion to the n-well edge is 1.8u (D.R: Active, Source/drain active to well edge,
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the PMOS and NMOS have to be at least 3.6u apart. We can place a ruler to help us aligning the two shapes and to measure the distance.
4. Place the transistor You can drop the selected object (in this case consisting of the n-well, the p-active, poly and contacts) into its final location by clicking once on the left mouse button.
Connecting the Output
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1. Draw a Metal-1 rectangle between NMOS and PMOS drain region contacts Note that the minimum Metal-1 width is 0.9u (3 lambda), thus narrower than the Metal-1 covering the contacts. Also note that the transistors are completely symmetric, the source and drain regions are interchangeable.
Connecting the Input The next step will be to connect the gates of both transistors, which will form the input. To do this, we could use the rectangle command again, but this time we will use a different command, the path command. Throughout this tutorial, you will see that you typically have multiple options, commands or procedures available to create the same features in the layout. Please become familiar with as many of such options as possible. 1. Select poly layer from the LSW
2. From the Create menu select Path ( Create --> Path )
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The path options box will pop up:
In the path mode you can draw lines (or paths) with the selected layer. The width of the drawn line can be adjusted, the default is the minimum width of the selected layer. 3. Start path To start the path, click on the middle of the PMOS poly extension. You'll see a ghost line appear. Move this ghost line to the NMOS poly extension.
4. Double click to finish path A single click will finish a line segment and let you continue drawing, a double click will finish the path.
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Making a Metal-1 connection for the Input We have already decided in our signal flow graph that we want the input in Metal-1. Therefore we have to make a connection from the poly layer to the Metal-1 layer. This connection can be done manually by drawing a poly contact layer between Metal-1 and poly, but we will use the path command to automatically add the contacts. 1. Starting from the poly line connecting the gates, start drawing a horizontal poly path 2. On the Path Options dialog box, click on Change To Layer and switch to Metal1
This will automatically add a contact to the end of the current path, note that this will still be a ghost line. You can place the contact at a certain location by clicking once, thereafter the path will continue using the new layer.
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3. Finish the path You can finish the path by double clicking. Note that you will not be able to see the contact between the metal and poly layers, there will be a red square instead. This is called an instance. An instance is practically a finished layout that is included completely in your circuit. Since it is a complete layout, it is not possible to edit that layout from within your cell, it is said to be on a lower level of hierarchy.
By default, only the current layer of hierarchy is visible. Objects that you include as instances will be shown as boxes corresponding to their size. You can press SHIFT-F to see all levels of hierarchy. CTRL-F will return you to viewing only a single layer of hierarchy.
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Power Rails Now that our transistors are placed and connected, we will have to add Power and Ground rails. Usually a layout consists of a large number of cells, all of which need power and ground connections. Therefore it is common to design cells such that they will have one continous, wide power and ground connection when placed side by side. Our Signal Flow Graph suggests horizontal power and ground lines in Metal-1. 1. Draw the Power Rail in Metal-1 above the PMOS
2. Draw the Ground Rail in Metal-1 below the NMOS
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Make sure to connect the Power Rail and the Ground rail to the source contact of the PMOS and to that of NMOS, respectively.
P-Substrate Contact The substrate on which the transistors are built must be properly biased. The way to do this is to add substrate contacts. The NMOS transistors are build on a p-type substrate, we will have to create a p-type substrate contact. 1. Draw a P-select square next to the NMOS transistor. Since the contact will be made to p-substrate, the contact area will have to be p-type.
2. Draw a P-active square inside the P-select area. This will define the active area of the substrate contact. make sure that you are not violating any design rules associated with active area spacing.
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3. Draw the active contact square inside the p-type active area.
4. Make a metal connection to ground, covering the entire substrate contact.
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Note that the susbtrate contact can also be created and placed as an instance, instead of drawing every item seperately. this alternative approach will be demonstrated in the next step, for the n-well contact.
N-Substrate Contact The PMOS transistor was placed within the n-well, this well also has to be biased with the VDD potential. THis will be done with an n-type substrate contact. We can follow the same steps that we did for the p substrate contact, but we will try to introduce another method. Almost all of the interlayer connections are already available as instances in your design library. We used the metal-poly contact instance while connecting the input. Similar instances also exist for the substrate connections. 1. From the menu Create select option Instance ( Create --> Instance )
This will pop-up the instance options menu.
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You'll have to provide a cell name and library here. It may be the case that you already know the cell name and cell view, but in this case it is better to Browse in your library to find the appropriate cell. This is essentially the same library browser that you access when you start Cadence Design Tools. It lets you choose the library, cell and cell view, your selection will be transferred to the Instance options menu.
The N-substrate contact is named NTAP, and only has a symbolic view. 2. Move the instance to the desired location. Once you have selected the instance, the cursor will show a ghost image representing the instance, and you'll be able to move the instance to the desired location:
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3. Place the instance. Once satisfied, you can click to place the instance. You'll remain in the instance mode after you have placed the instance, press "ESC" to go back to selection mode again. Note that in this example, the n-well contact has been placed right on top of the n-well boundary, which will obviously generate a rul eviolation. the n-well is simply not wide enough to accomodate both the PMOS transistor and rge contact. This will have to be dealt with in the next step.
4. Make the power connection.
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The instance will not automatically connect itself to the power supply rail. This connection has to be made by either a Metal-1 rectangle or path.
Enclosing the substrate contact In the previous step we tried to place the n-type substrate contact in the n-well. Since we had drawn the n-well to cover the P-diffusion at minimum length, the well is not wide enough to accomodate the additional contact. We must enlarge the n-well, so that it also covers the substrate contact. One way to do this would be to simply draw an adjoining rectangle using the n-well layer. Instead, we will try to modify the existing rectangle, so that it covers the contact. 1. Press F4 on the keyboard to toggle selection mode. By default, the selection mode will only select whole objects. Pressing "F4" will change this default to partial selection. The information bar will start displaying "(P) Select" (P for partial) instead of "(F) Select" (F for Full). 2. Move cursor over the left edge of the n-well. You'll notice that as soon as the cursor is close to the edge, only the edge line will be highlighted as a pale dashed line.
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3. Click once to select the edge. 3. Move mouse over the selected edge (without pressing any mouse buttons). You'll notice that the cursor changes shape when you are close to the edge. 4. Press and hold left mouse button when cursor changes above the selected edge. You have grabbed the edge, and as long as you do not release the mouse button you can "stretch" the edge. Move the edge of the n-well so that all the of the substrate contact is covered by n-well.
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Design Rule Checking The layout must be drawn according to strict design rules. After you have finished your design, an automatic program will check each and every feature in your design against these design rules and report violations. This process is called Design Rule Checking. Our design is finished, we must now perform a Design rule Check to see if we have any errors. 1. From the menu Verify select option DRC ( Check --> DRC )
This will pop-up the DRC options dialog box.
2. Start DRC The default options for the DRC are adequate for most situations. DRC results and progress will be displayed in the CIW.
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You'll have to check the results from the CIW. In this example we have two poly-to-poly contact spacing errors. You can also see that the rule number for this is 5.5, and the spacing is supposed to be at least 1.5um The errors are also highlighted on the layout.
As it is mostly the case, one misplacement will cause multiple DRC errors. The error can be corrected by moving the contact further to the left.
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After moving the contact to the left, we will have to perform another DRC.
This is a successful DRC.
Final Layout This is the completed layout of the CMOS inverter. Congratulations.
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2- Example: Automatic Layout Generation Tools (Device Level Placer)
In this tutorial an alternative way of drawing layouts will be introduced. This tutorial assumes that the reader is familiar with the Virtuoso layout tool and has followed the layout manual.
Since the manual creation of the physical layout is labour intensive, significant amount of work has been put into the automation of the physical layout design process. The device level placer is one of the lower-level answers. The device level placer, will read in a schematic and place all the transistors and I/O pins in the layout window. This tool will use parametric instances that will generate appropriately sized transistors.
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Although the device level placer and similar contemporary tools provide some nice features, the quality of the layouts they produce are still far from hand optimized layouts. Steps of Automatic Layout Generation • • • •
Starting the Automatic Layout Tool Placing the Components Making Connections Finishing Touches
Example : Automatic Layout Generation (CMOS Inverter)
Step 1 : Starting the Automatic Layout Tool To start the automatic layout generation, you must have finished your circuit schematic first. Please follow the Schematic Tutorial Example first if you have not done so. 1. Open the schematic view of your design.
In this example, the PMOS transistor has a channel width of W=4.5u and a channel length of L=0.6u, while the NMOS transistor has a channel width of W=3u and a channel length of L=0.6u. 2. From the menu select Tools --> Design Synthesis --> Device-Level Editor.
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Selecting this option will first open up a small dialog box that will let the user select the cell name for the layout. It is a good idea to use the same cell name and specify layout as the cell view name.
Upon the selection of the view name, the user will be prompted another small dialog box. This box will ask for a pin layer, pins in the layout will be placed as connections in the given layer. Choose Metal-1 as the I/O Pin Layer, and all of the pins that you have specified in your schematic will be placed as connections in Metal-1.
In addition to the already open schematic window, a new layout window and the layer selection window will pop up. These three windows define the working environment for the automatic layout generation flow.
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After the I/O pin layer is selected, two rectangles representing the transistors (the nmos and the pmos) and two Metal-1 squares will show up in the bottom half of the layout window. Notice the cyan colored square on the upper half of the layout window: This is the estimated size of the layout, this size is not mandatory, it is calculated roughly from the sizes of the active elements. With the next step, you'll start forming the layout within the box above.
Step 2 : Placing the Components The default behavior of the layout editor is to show only the current hierarchy. You can press shift-f to display all the hierarchy levels, this way you'll be able to see actual transistors instead of the red instance rectangles. The first step is to place all the components within the design area. 1. Select the PMOS transistor by clicking once.
2. Move the selected transistor by dragging it with the mouse.
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Note that in addition to the ghost image of the selected object, lines to other objects will show up. These lines represent the connections of the selected (and dragged) object to other objects of the design. In this example the poly of the PMOS transistor will be shown connected to the poly of the NMOS transistor and the input, and the drain region of the transistor will be shown connected to the output and the drain region of the NMOS. 3. Release the mouse button to place the selected transistor.
4. Move the remaining objects the same way
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Note that the automatic layout tool looks almost identical to the Virtuoso layout editor. All of the commands that were available in the manual layout tool are available in this tool too. You can use rulers to pinpoint the exact location of the devices.
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The I/O pins correspond to the pins drawn in the schematic. Although they just look like an ordinary Metal-1 patch they contain information about the name, type and direction of the connection.
As the last step, move and place the output pin too. 5. Final placement
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Your final working environment should look more or less like this. Note that this placement is not obligatory, you can choose to place the transistors and the I/O pins any way you desire.
Step 3 : Making Connections In the previous step we have placed the components, the next step is to make the connections between individual objects. We will be using the same methods that we used during manually drawing a layout here. The automatic layout tool has an additional menu which provides some useful options to faciliate signal connections. 1. From the menu DLE select option Probe.
The probe option will display a small dialog box:
Now you can go and select connections (nets) devices, and terminals in either layout or the schematic window and the corresponding object will be highlighted in the other window. This is called cross-probing.
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As an example try clicking and selecting the wire connecting the drains of both transistors to the output pin, notice that two drain regions as well as the output I/O pin in the layout window will be highlighted. 2. Connect the drain regions with Metal-1 using the path command.
Notice that the new connection will also be highlighted as it is drawn.
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Connect the gates of both transistors using a poly path and connect this path to the input.
Step 4 : Finishing Touches At this point the design is almost finished. Unfortunately the automatic design creation process for this fabrication technology is unable to add substrate connections. So these will have to be added by the user. 1. Using the Create --> Instance command select a PTAP substrate contact.
Place the instance close to the bottom of the NMOS transistor, close to the source region (which has not been connected to a ground rail yet).
2. Using the Create --> Instance command select a NTAP substrate contact.
This contact will be used as the n-well contact.
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As in the previous manuallayout example, the N-Substrate contact will not fit in a n-well that is drawn according to the minimum distance rules from the transistor. Since the transistor is an instance, it is not possible to stretch the n-well edge as it has been done in the layout example.
To address this problem, we can easily draw an extension to the already existing n-well using the rectangle command. The next step is to draw the ground rail and the power rail. 3. Using the Rectangle command draw the ground rail with Metal-1.
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Make sure to connect the NMOS source and the substrate contact to the ground rail you have just drawn. 4. Draw the power rail with Metal-1. Notice that the power rail and the ground rail are symmetric. So instead of redrawing the power rail you can copy the ground rail.
To select multiple objects press "SHIFT" key while selecting objects. When you are done, use Edit --> Copy command to copy the selected image. You can flip the selected image upsidedown by clicking the "upsidedown" button on the copy dialog box.
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5. Place the pins. The next step is to give connection information to the power rails and ground rails. To do this, first select the Metal-1 layer from the layer selection window and then use the Create --> Pin command.
This will pop-up a dialog box to allow you enter various parameters of the pin.
For the power rail enter the name: "vdd!" (without quotes, watch case and the exclamation mark). The exclamation mark is important, it defines a global signal, that is a signal name that is unique accross your entire design.
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Define a rectangle with the Metal-1 layer on the power rail, as the pin location. The location of the pin and the size are not relevant (at least not in this context), as a good practice try to make it a minimum sized box (0.9u x 0.9u) and make sure it is on the power rail. Place a pin on the ground rail in a similar way. Use the name "gnd!" (without the quotes, watch for the case and exclamation mark) for the pin name.
Place the pin:
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This is the final layout, created by the automatic device level editor.
6- Design Rule Check (DRC) The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design. The detected errors are displayed on the layout editor window as error markers, and the corresponding rule is also displayed in a separate window. The designer must perform DRC (in a large design, DRC is usually performed frequently before the entire design is completed), and make sure that all layout errors are eventually removed from the mask layout, before the final design is saved.
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7- Circuit Extraction Circuit extraction is performed after the mask layout design is completed, in order to create a detailed net-list (or circuit description) for the simulation tool. The circuit extractor is capable of identifying the individual transistors and their interconnections (on various layers), as well as the parasitic resistances and capacitances that are inevitably present between these layers. Thus, the "extracted net-list" can provide a very accurate estimation of the actual device dimensions and device parasitics that ultimately determine the circuit performance. The extracted net-list file and parameters are subsequently used in Layout-versus-Schematic comparison and in detailed transistor-level simulations (postlayout simulation).
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A detailed example description of "Circuit Extraction".
Step 1 : Extracting from the Layout The mask layout only contains physical data. In fact it just contains coordinates of rectangles drawn in different colors (layers). The extraction process identifies the devices and generates a netlist associated with the layout. Make sure you have a layout window with a finished design ready. Make sure that the design does not contain any DRC errors.
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1. From the Verify menu select the option Extract ( verify --> Extract )
A new window with extraction options will appear. The default options will only extract ideal devices. This ideal case would reasult in a list much similar to the schematic. For a more accurate representation, however, we will have to take the parasitic effects into account. To enable the extraction of parasitic devices, a selection parameter called a switch has to be specified. You can type the switch into the designated box, or you can select it from a menu using the Set Switches option.
The switch specified in the example (above) to enable extracting the parasitic capacitances is called Extract_parasitic_caps.
Check the Command Interpreter Window (the main window when you start Cadence) for errors after extraction.
Following a successfull extraction you will see a new cell view called extracted for your cell in the library manager. See the following section for accessing the extracted view.
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Step 2 : The Extracted Cell View Following the extraction step a new cellview is generated in your library. This cell view is called extracted view.
Try loading the cellview. It will open up a layout that looks almost identical to the layout you have extracted. You will notice that only the I/O pins appear as solid blocks and all other shapes appear as outlines.
The red rectangles indicate that there are a number of instances within this hierarchy. Try pressing Shift-F to see all of the hierarchy.
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This will reveal a number of symbols. If you zoom in you will be able to identify individual elements, such as transistors and capacitors. You will notice that the parameters (e.g. channel dimensions) of these devices represent the values they were drawn in the layout view. Apart from your actual devices you will notice a number of elements, mainly capacitors in your extracted cell view. These are not actual devices, they are parasitic capacitances, side effects formed by different layers you used for your layout.
The next step will be to correpond the extracted netlist to that of the schematic. This is called the Layout Versus Schematic checking. This will ensure that the schematic that we have drawn and the layout are identical.
8- Layout versus Schematic Check After the mask layout design of the circuit is completed, the design should be checked against the schematic circuit description created earlier. The design called "Layoutversus-Schematic (LVS) Check" will compare the original network with the one extracted from the mask layout, and prove that the two networks are indeed equivalent. The LVS step provides an additional level of confidence for the integrity of the design, and ensures that the mask layout is a correct realization of the intended circuit topology. Note that the LVS check only guarantees topological match: A successful LVS will not guarantee that the extracted circuit will actually satisfy the performance requirements. Any errors that may show up during LVS (such as unintended connections between transistors, or missing connections/devices, etc.) should be corrected in the mask layout -
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before proceeding to post-layout simulation. Also note that the extraction step must be repeated every time you modify the mask layout.
A detailed example description of "Layout versus Schematic Check".
We are going to compare the schematic and the extracted layout to see if they are identical. 1. From the Verify menu select the option LVS.
If you had previously run a LVS check, this would pop-up a small warning box. Make sure that the option Form Contents is selected in this box.
The top half of the LVS options window is split into two parts. The part on the left corresponds to the schematic cell view and the right part corresponds to the extracted cell view that are to be compared. Make sure that the entries in these boxes represent the values for your circuit. Although there are a number of options for LVS, the default options will be enough for basic operations, select Run to start the comparison.
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The comparison algorithm will run in the background, the result of the LVS run will be displayed in a message box. Be patient, even for a very small design the LVS run can take some time (minutes).
The succeeded message in the above message box, indicates that the LVS program has finished comparing the netlists, NOT THAT THE CIRCUITS MATCH. It might be the case that the LVS was successful in comparing the netlists and came up with the result that both circuits were different. To see the actual result of an LVS run you have to examine the output of the LVS run. The Output option is right next to the Run command
You can take a look at the complete LVS result here. The most important part of the report can be found in the figure above. It states that the netlists did indeed match. If you discover that there is a mismatch, you must go back to the layout view and correct the error(s). Most of the other options on the LVS form, are for finding mismatches between two netlists and to generate netlists that include only parasitic effects relevant to one part of the circuit.
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9- Post-layout Simulation The electrical performance of a full-custom design can be best analyzed by performing a post-layout simulation on the extracted circuit net-list. At this point, the designer should have a complete mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with no violations. The detailed (transistor-level) simulation performed using the extracted net-list will provide a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that may occur due to signal delay mismatches. If the results of post-layout simulation are not satisfactory, the designer should modify some of the transistor dimensions and/or the circuit topology, in order to achieve the desired circuit performance under "realistic" conditions, i.e., taking into account all of the circuit parasitics. This may require multiple iterations on the design, until the post-layout simulation results satisfy the original design requirements. Finally, note that a satisfactory result in post-layout simulation is still no guarantee for a completely successful product; the actual performance of the chip can only be verified by testing the fabricated prototype. Even though the parasitic extraction step is used to identify the realistic circuit conditions to a large degree from the actual mask layout, most of the extraction routines and the simulation models used in modern design tools have inevitable numerical limitations. This should always be one of the main design considerations, from the very beginning. After all, there is no substitute for the "real silicon" ! A detailed example description of "Post-Layout Simulation". This tutorial describes the steps needed for running a post layout simulation. This tutorial assumes that the reader is familiar with the topics covered in Schematics Tutorial and the Simulation Tutorial and that the reader has: • • • • •
Drawn a circuit schematic Created a symbol for the schematic Created a test schematic to simulate the design Simulated the design Generated a physical mask layout of the design either manually as described in Layout Tutorial or using design automation tools as described in Automatic Layout Generation Tutorial
Steps of Postlayout Simulation • • • •
Extracting from the Layout The Extracted Cell View Layout Versus Schematic Summary of the Cell Views
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Simulating the Extracted Cell View
Step 1 : Extracting from the Layout (described before) Step 2 : The Extracted Cell View (described before) Step 3 : Layout Versus Schematic (described before) Step 4 : Summary of the Cell Views. So far you have created a number of cell views corresponding to the same circuit. In this section we want to review all of these cellviews and discuss why they are used. 1. Schematic view For any design, the schematic should be the first cell view to be created. The schematic will be the basic reference of your circuit.
2. Symbol view After you are done with the schematic, you will need to simulate your design. The proper way of doing this is to create a seperate test schematic and include your circuit as a block. Therefore you will need to create a symbol.
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3. Layout view This is the actual layout mask data that will be fabricated. It can be generated by automated tools or manually.
4. Extracted view After the layout has been finalized, it is extracted, devices and parasitic elements are identified and a netlist is formed.
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5. Test Schematic A separate cell is used to as a test bench. This test bench includes sources, loads and the circuit to be tested. The test cell usually consists of a single schematic only.
Step 5 : Simulating the Extracted Cell View After a successful LVS you will have two main cell views for the same circuit. The first one is the schematic, which is your initial (ideal) design, the second is the extracted, that is based on the layout and in addition to the basic circuit includes all the layout associated parasitic effects. Since both of these views refer to the same circuit they can be interchanged. In this example we are going to re-run the simulation example, but we will make the simulator to use the extracted cell view instead of the schematic cell view.
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Make sure that you are in the test schematic, that you used to simulate your design earlier. 1. Start Analog Artist using Tools --> Analog Artist
The Analog Artist window will pop-up.
2. From the Setup menu choose the Environment option.
A new dialog box controlling various parameters of Analog Artist will pop-up.
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The line that we will have to alter is called the Switch View List. This entry is an ordered list of cell views that contain information that can be simulated. The simulator (in fact the netlister) will search until it finds one of these cellviews. The default entry does not contain an extracted cellview. We will simply add an entry for extracted cellview in front of the schematic cellview. As a result of this modification, the simulator will use the extracted cell view of the cell, if one is available.
3. Choose analyses
In the simulation example a transient analysis was used, this time we will use a DC simulation. In a DC simulation the value of any voltage or current source is varied over a specified range. It is used to obtain input/output characteristics of circuits.
The basic options of the DC analysis are not very straight-forward. The first step is to determine what parameter will be swept.
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Choose Component Parameter as the Sweep Variable.
You can select the parameter from the schematic window after you click on Select Component.
As each component has a number of parameters, you will be given a list of parameters associated with the component you select.
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In the example given above we have selected the DC voltage of the voltage source as the sweep variable. After we have selected the variable we can decide, the range where the variable will change.
This example changes the DC voltage source connected to the input from 0 Volts to 3.3 Volts. The last parameter determines how the sweep will be performed. A linear sweep will increment the value of the sweep variable by a fixed amount. The example below uses a step size of 10 millivolts.
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From this point on the simulation will continue just as it has been described in the Simulation Tutorial, except for the fact that the results will now include parasitic effects from the actual layout.
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APPENDIX Scalable Sub-micron Design Rules The following rules are taken from the MOSIS webpage: http://www.mosis.org/New/Technical/Designrules/dr-scmos72.html Please note that the following rules are SUB-MICRON enhanced lambda based rules. Only rules relevant to the HP-CMOS14tb technology are presented here. In addition to the lambda rules, the micron rules for lambda=0.3u are given in an additional column. Please refer to http://www.mosis.org/New/Technical/Designrules/dr-scmos72.html for more accurate and complete information. N.B.: HP AMOS14TB is no longer available from MOSIS http://www.mosis.com/Technical/Processes/proc-hp-amos14tb.html Available Fabrication Processes http://www.mosis.com/Technical/Processes/ Available Design Rules http://www.mosis.com//Technical/Designrules/
Layout Rules • • • • • • • • • • •
1. Well 2. Active 3. Poly 4. Select 5. Poly Contact 6. Active Contact 7. Metal-1 8. Via 9. Metal-2 14. Via2 15. Metal-3
1. Well Rule
Description
Lambda
Microns
1.1
Minimum width
12
3.6u
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1.2
Minimum spacing between wells at different potential
18
5.4u
1.3
Minimum spacing between wells at same potential
6
1.8u
2. Active Rule
Description
Lambda
Microns
2.1
Minimum width
3
0.9u
2.2
Minimum spacing
3
0.9u
2.3
Source/drain active to well edge
6
1.8u
2.4
Substrate/well contact active to well edge
3
0.9u
2.5
Minimum spacing between active of different implant
0 or 4
0 or 1.2u
3. Poly Rule
Description
Lambda
Microns
3.1
Minimum width
2
0.6u
3.2
Minimum spacing
3
0.9u
3.3
Minimum gate extension of active
2
0.6u
3.4
Minimum active extension of poly
3
0.9u
3.5
Minimum field poly to active
1
0.3u
Rule
Description
Lambda
Microns
4. Select
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4.1
Minimum select spacing to channel of transistor
3
0.9u
4.2
Minimum select overlap of active
2
0.6u
4.3
Minimum select overlap of contact
1
0.3u
4.4
Minimum select width and spacing
2
0.6u
5. Poly Contact Rule
Description
Lambda
Microns
5.1
Exact contact size
2x2
0.6u x 0.6u
5.2b
Minimum poly overlap
1
0.3u
5.3
Minumum contact spacing
3
0.9u
5.4
Minimum spacing to gate of transistor
2
0.6u
5.5b
Minimum spacing to other poly
5
1.5u
5.6b
Minimum spacing to active (single contact)
2
0.6u
5.7b
Minimum spacing to active (multiple contacts)
3
0.9u
6. Active Contact Rule
Description
Lambda
Microns
6.1
Exact contact size
2x2
0.6u x 0.6u
6.2b
Minimum active overlap
1
0.3u
6.3
Minimum contact spacing
3
0.9u
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6.4
Minimum spacing to gate of transistor
2
0.6u
6.5b
Minimum spacing to diffusion active
5
1.5u
6.6b
Minimum spacing to field poly (single contact)
2
0.6u
6.7b
Minimum spacing to field poly (multiple contacts)
3
0.9u
6.8b
Minimum spacing to poly contact
4
1.2u
7. Metal-1 Rule
Description
Lambda
Microns
7.1
Minimum width
3
0.9u
7.2a
Minimum spacing
3
0.9u
7.3
Minimum overlap of any contact
1
0.3u
8. Via Rule
Description
Lambda
Microns
8.1
Exact size
2x2
0.6u x 0.6u
8.2
Minimum spacing
3
0.9u
8.3
Minimum overlap by Metal-1
1
0.3u
8.4
Minimum spacing to contact
2
0.6u
9. Metal-2 Rule
Description
Lambda
Microns
9.1
Minimum width
3
0.9u
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9.2b
Minimum spacing
3
0.9u
9.3
Minimum overlap of via1
1
0.3u
14. Via2 Rule
Description
Lambda
Microns
14.1
Exact size
2x2
0.6u x 0.6u
14.2
Minimum spacing
3
0.9u
14.3
Minimum overlap by Metal-2
1
0.3u
14.4
Minimum spacing Via-1
2
0.6u
15. Metal-3 Rule
Description
Lambda
Microns
15.1
Minimum width
5
1.5u
15.2
Minimum spacing
3
0.9u
15.3
Minimum overlap of Via-2
2
0.6u
