Explain various transistor switching times. Ans.1. The time interval between the instant of application input pulse and output (collector) currant to attain 10 percent of its maximum value va lue is termed as the delay time td . 2. Rise time tr, is defined as the time reuired for the output currant !c to "o from 10# to $0# of its maximum value. %. The sum of delay time td, and rise time tr, is called the turn&' time ton,
i.e. . T*R& '++ time is made up of a stora"e time ts, and a fall time tf i.e. . -tora"e time ts, is defined as the time interval between the end of the input pulse (trailin" ed"e) and when the collector current falls to $0# of its maximum value. 'R -tora"e time, is eual to the sum of time taen in removin" excess char"e stored and the time taen by collector transition capacitance to dischar"e to $0# of its maximum but ma/or portion of the time is taen in removin" excess exce ss char"e stora"e. The time duration of the output pulse measured between two 0# levels of risin" and fallin" waveform is nown as the pulse width. +or a fast&switchin" transistor, turn&on time and turn&off time must be of the order of nano seconds.
How is a transistor used as a switch. Ans. transistor can be employed as an electronic switch. 'peratin" a transistor as a switch means it at either saturation or cut&off nowhere else alon" the load line. hen a transistor is saturated it is lie a closed switch from collector to emitter. hen a transistor is cut off it is lie an open switch.
SWITCHING TIES !" A T#ANSIST!# !nstead of a step, if a pulse is applied to the transistor switch, how does the device respond To understand this, we consider the switchin" times of a transistor (see +i". 3.2). 4et the input to the transistor switch be a pulse of duration T . hen a pulse is applied, because of stray capacitances, collector current will not reach the steady&state value instantaneously. To now exactly when the device switches into the ' state and also into the '++ state, we define the followin" switchin" times of the transistor.
The Turn$on Time o% a Transistor Turn&on time of the transistor is the time taen by the transistor from the instant the pulse is applied to the instant the transistor switches into the ' state and is the sum of the delay time and rise time. To find out the turn&on time of the transistor, the delay time and rise time have to be calculated. &ela' Time ( td ). !t is the time taen for the collector current to reach from its initial value to 10 per cent of its final value. !f the rise of the collector current is linear, the time reuired to rise to 10 per cent IC (sat) is 156 the time reuired for the current to rise from 10 p er cent to $0 per cent IC (sat).
!t is "iven as7 where, tr is the rise time. #ise Time. Rise time, tr is the time taen for the collector current to reach from 10 per cent of its final value to $0 per cent of its final value. +rom +i". 3.2 it is seen that the moment input pulse is 8ero, the collector current is expected to fall to 8ero. 9owever, because of the stored char"es, the current remains unaltered for sometime interval ts1 and then be"in to fall. The time taen for this current to fall from its initial value at ts1 to $0 per cent of its initial value is ts2. The sum of these ts1 and ts2 is approximately ts1 : ts and is called the stora"e time. )#EA*&!WN +!,TAGES e have seen that by the application of a si"nal of proper polarity and ma"nitude, a transistor switch can be driven into saturation. s a result, the volta"e at the collector of the device isVCE (sat) (typically 0.1 ; for VCC . This output is connected to operate some other circuits. +or proper operation, it is desirable that VCC be made reasonably lar"e. 9owever, by increasin" the value of VCC , the reverse&bias volta"e on the collector base diode could become so lar"e that an avalanche breadown may occur in the collector diode. The leaa"e current ICO will then become MnICO where, Mn is the avalanche multiplication factor. Mn depends on VCB. n empirical relation for Mn, applicable for many transistor types is "iven as7
9ere, VCBO(max) is a maximum reverse&bias volta"e that can be applied between the collector and base terminals of the transistor when the emitter lead is open&circuited and n is typically in the ran"e of 2 to 10 which controls the sharpness of onset of a breadown. ?alculation of Mnis illustrated in the @xample 3.12. The )rea-down +oltage with )ase Not !pen Circuited ?onsider the fi"ure shown in +i". 3.%1. VCEO(max) is the breadown volta"e between the collector and emitter terminals with the base lead open. ow, if the base lead is not open circuited, but a resistance RB is connected between the base and emitter terminals, the new breadown volta"e may be termed as VCER(max). The expectation is that VCER(max) lies somewhere between VCEO(max) and VCBO(max). 4et us try to calculate the value of VCER(max).
!t is nown that unless a volta"e of Vγ exists between base and emitter terminals, the diode forward current is small and the collector to base leaa"e current will now flow throu"h RB. 'nce the forward&bias volta"e of the base emitter diode is more than Vγ, a lar"e current flows throu"h the collector and the correspondin" breadown volta"e is VCEO(max). Areadown occurs when VCE is "reater than VCEO(max). hen the threshold volta"e Vγ is reached, at that instant the collector current is MnICO. Thus, at breadown the current throu"h RB is MnICO.
"IG#E /.01 ICvs. VCE extended into breadown re"ion for different conditions 1. hen the base is open circuited ( IC : ICEO)
2. hen RB is connected between the base and emitter %. hen RB is connected with a reverse&bias volta"e VBB.
+rom +i". 3.%, it is apparent that breadown occurs at VCEO(max) with base lead open at the point, the current rises abruptly. VCEO(max) is called the sustainin" volta"e. hen RB is connected between the base and emitter, the breadown occurs at a lar"er volta"e VCER(max). fter breadown the volta"e returns to the sustainin" volta"e. !f RB : 0, breadown occurs at a sli"htly lar"er volta"e. +urther, we also see from the characteristics that if the emitter diode is reverse&biased, the breadown occurs at a still lar"er volta"e. The lar"er is the reverse&bias volta"e, the lar"er is the breadown volta"e. These characteristics explain the possible breadown volta"es for different conditions on the emitter diode, so that at these prohibited volta"es the transistor is not operated. The currents for all the possible connections (except for ICEO) "ive two values for the same volta"e. lso, once the breadown occurs current in the transistor increases with decreasin" volta"e, which means that the transistor exhibits ne"ative resistance characteristic. The transistor when used in the breadown re"ion is called an avalanche transistor. +rom @. (3.$) we see that VCEO(max) is dependent on hFE which in turn depends on the collector current IC . B? current "ain is the ratio of IC/IB at an operatin" point and is desi"nated as hFE or βdc. The parameter hFE is useful in determinin" whether a transistor is in saturation or not and it varies with collector current IC (see +i". 3.%0). Typically hFE varies as shown in +i". 3.% which is called current "ain characteristic. THE SAT#ATI!N 2A#AETE#S !" A T#ANSIST!# AN& THEI# +A#IATI!N WITH TE2E#AT#E The output characteristics of n–p–n transistor havin" PT : 20 m at room temperature in the ?@ confi"uration are "iven in +i". 3.%3. The dc load line for RL : 00 C is superimposed on the characteristics. 9owever, from the characteristics in +i". 3.%3 the saturation volta"eVCE (sat) can not be found as its value is typically a fraction of a volt (0.1 ; for
VCE (cut&off) : VCC : 10 ; To be able to read VCE (sat), the characteristics in the volta"e ran"e 0 to 0. ; are expanded and the dc load line for RL : 00 C is a"ain superimposed, as shown in +i". 3.%D(a). The re"ion Esee +i". 3.%D(b)F around IB : 0.1D m is expanded to see the variation in IC for lar"er values of IB as shown as the dotted re"ion in +i". 3.%D(a). !t is seen for IB > 0.1D m, that there is no appreciable chan"e in the collector current for a chan"e in the base current as shown in +i". 3.%D(b), which indicates that the transistor is driven into saturation. "ain from these characteristics we see that for IB : 0.1D m, VCE ( sat) : 20 m; and for IB : 0.% m, VCE (sat): 12 m;. This variation explains that, the lar"er is the value of IB, the smaller is the value of VCE (sat). t a "iven operatin" point, the ratio of VCE (sat) /IC is called the saturation resistance RCS. RCS at the point Q is
"IG#E /.0/ Typical output characteristics of an n= p=n transistor in the ?@ mode
