ThinkPad T440p Schematics

5

4

3

Oasis-1 SHB SOVP LOGIC SCHEMATICS D

C

B

A

2

1

OAS1H-0 VER 1.01 Aug/08/2013

1.TITLE PAGE 36.MEMORY TERMINATION 2.EC HISTORY 37.BLANK 3.CPU(1/8) : DMI/FDI/PEG 38.LCD CONNECTOR 4.CPU(2/8) : MISC/JTAG/CLK 39.BLANK 5.CPU(3/8) 5.CPU(3/8) : DDR3L CHANNEL- A 40.EXT 40.EXT CRT INTERFACE 6.CPU(4/8) 6.CPU(4/8) : DDR3L CHANNEL- B 41.DISPLAY 41.D ISPLAY PORT CONNECTOR 7.CPU(5/8) 7.CPU(5/8) : POWER 42.BLANK 42.B LANK 8.CPU(6/8) 8.CPU(6/8) : GND 43.SATA 43.SATA HDD CONN 9.CPU(7/8) 9.CPU(7/8) : EDP/DDI 44.SATA 44.SATA BAY I/F CONN 10.CPU(8/8) 10.CPU(8/8) : CFG/RESERVED 45.USB 45.U SB CONNECTOR 11.PCH(1/10) 11.PCH(1/10) : RTC/HDA/SATA/JTA RTC/HDA/SATA/JTAG G 46.AOU/USB 46.A OU/USB POWER SWITCH 12.PCH(2/10) 12.PCH(2/10) : LPC/SPI/SMBUS/C-LINK/THERMAL47.GBE 47.GBE LAN CLARKVILLE 13.PCH(3/10) 13.PCH(3/10) : DMI/FDI/PM 48.GBE 48.GBE LAN SWITCH 14.PCH(4/10) 14.PCH(4/10) : LCD/CRT/PCI/DDI CONTROL 49.RJ45 49.R J45 SUB CARD I/F 15.PCH(5/10) 15.PCH(5/10) : GPIO/CPU/MISC/NCTF/RSVD 50.PCIE 50.PCIE NGFF CARD SLOT 16.PCH(6/10) 16.PCH(6/10) : PCIE/USB 51.MEDIA 51.MEDIA CARD CONTROLLER 17.PCH(7/10) 17.PCH(7/10) : CLOCKS 52.MEDIA 52.MEDIA CARD INTERFACE 18.PCH(8/10) 18.PCH(8/10) : POWER 53.SMART 53.SMART CARD/3rd NGFF I/F 19.PCH(9/10) 19.PCH(9/10) : POWER 54.AUDIO 54.A UDIO ALC3232 20.PCH(10/10):GND 20.PCH(10/10):GND 55.AUDIO 55.A UDIO CONNECTOR 21.XDP 21.XDP CONNECTOR 56.AUDIO 56.A UDIO JACK SENSE 22.RTC BATTERY 22.RTC BATTERY 57.AUDIO 57.A UDIO EXT MIC I/F 23.SPI FLASH 23.SPI FLASH 58.AUDIO 58.A UDIO SPEAKER 24.DDR3L SO DIMM CHANNEL-A 59.AUDIO BEEP 25.BLANK 60.DOCKING CONNECTOR 26.DDR3L SO DIMM CHANNEL-B 61.MEC1633L(1/3) 27.DDR3L DECOUPLING 62.MEC1633L(2/3) 28.N14M-GS(1/6) : PEG I/F 63.MEC1633L(3/3) 29.N14M-GS(2/6) : DIGITAL OUT I/F 64.KEYBOARD CONNECTOR 30.N14M-GS(3/6) : VRAM I/F 65.CLICK PAD/NFC/FPR CONNECTOR 31.N14M-GS(4/6) : GPIO 66.BLANK 32.N14M-GS(5/6) : POWER 67.FAN CONNECTOR 33.N14M-GS(6/6) : GND 68.G-SENSOR 34.VRAM CHANNEL-A 69.TPM 35.BLANK 70.EEPROM/SMBUS SW

D

71.THINK ENGINE(1/2) 72.THINK ENGINE(2/2) 73.DC-IN 74.BATTERY INPUT 75.BATTERY CHARGER(BQ24760) 76.CHARGER SELECTOR 77.BATTERY MONITOR 78.DC/DC VCC5M/VCC3M (TPS51220A) 79.DC/DC VCCCPUCORE(TPS51631) 80.DC/DC VCCCPUCORE(CSD97374) 81.BLANK 82.VCCCPUCORE DECOUPLING 83.DC/DC VCCGFXCORE_D (TPS51219) 84.BLANK 85.DC/DC VCC1R05AMT(VT384B) 86.DC/DC VCC1R35A(VT387B) 87.DC/DC VCC0R675B(TPS51200) 88.DC/DC VCC1R5VIDEO(VT382B) 89.DC/DC VCC1R05VIDEO_PLL(TPS74801) 90.BLANK 91.BLANK 92.DC/DC VCC1R5B(BD3551) 93.LOAD SW PCH SUS 94.LOAD SW LAN 95.LOAD SW VIDEO 96.LOAD SW B 97.LOAD SW VCC5MUBAY 98.LOAD SW WWAN & WLAN 99.PTH FOR SCREW HOLES Project Name : OAS-1 SP ASSESS Size :

Title :

Document Number :

TITLE PAGE Rev

C

B

A

5

4

3

2

1

D

D

VCCCPUIO

VCC1R35A

2

VCCCPUIO_PCH

2 R64

R12

62_0201_5%

HaswellrPGAEDS

1K_0201_5%

1

JCPU1B

1

AP32

62,75,79 15

PECI

PECI -PROCHOT -THERMTRIP

-PROCHOT -THERMTRIP

R85

1

MISC

AN32 AR27 CATERR AK31 PECI AM30 FC_AK31 AM35 PROCHOT THERMTRIP

TP936 62

SKTOCC

2 56_0201_5%

T H E R M A L

3 R D D

C

13 15,21 13 15 17 17 17 17

PM_SYNC CPUPWRGD DRAMPWRG -PLTRST_PROC

PM_SYNC CPUPWRGD DRAMPWRG -PLTRST_PROC

R9243 1 R8969 1

2 0_0201_5% 2 0_0201_5%

@

AT28 AL34 PM_SYNC AC10 PWRGOOD AT26 SM_DRAMPWROK PLTRSTIN

-CPURST

G28 H28 F27 E27 D26 E26

-EDP_NS_CLK_135M EDP_NS_CLK_135M -EDP_SS_CLK_135M EDP_SS_CLK_135M -CPU_CLK_100M CPU_CLK_100M

-EDP_NS_CLK_135M EDP_NS_CLK_135M -EDP_SS_CLK_135M EDP_SS_CLK_135M 17 -CPU_CLK_100M 17 CPU_CLK_100M

2 R9239 VCC3M

VCC3M

VCC3M 2K_0201_5% 1

2 C1901 2 2

R9240

2

R9241

R9280

1

2 % 5 7 _ 1 1 R 0 2 0 _ 1 K 0 1

K 6 2 V 3 . 6 0 _ 0 1 9 0 1 2 C 1 0 _ U 1 . 0

@

DPLL_REF_CLKN DPLL_REF_CLKP SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP BCLKN BCLKP

G A T J

P W R

C L O C K

2 OF 9 LOTES_AZIF0012P002B_INTELHASWEL CONN_ASM@

AP3 AR3 AP2 AN3

SM_RCOMP_0 SM_RCOMP_1 SM _RCOMP_2 SM_DRAMRST PRDY PREQ TCK TMS TRST TDI TDO DBR BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7

AR29 AT29 AM34 AN33 AM33 AM31 AL33 AP33

AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28

1 R7 R84 1 R576 1

2 100_0201_1% 2 75_0201_1% 2 100_0201_1% -DRAMRST -XDP_PRDY -XDP_PREQ XDP_TCK XDP_TMS -XDP_TRST XDP_TDI XDP_TDO -XDP_DBR

24,26

-XDP_PRDY 21 -XDP_PREQ 21 X DP _T CK 21 X DP _T MS 21 -XDP_TRST 21 X DP _T DI 21 X DP _T DO 21 -XDP_DBR 13,20,21

C

2 R2 51_0201_5% 1

0.1U_0201_6.3V6K

0_0402_5% 100K_0201_5% 1

100K_0201_5%

1

1 5

86

R9286 1

DDR_VR_PWRGD

2 B

1

C8484 @ 0.01U_0201_6.3V7K

2 0_0201_5%

1

B P

2

Y A G 3 U112

R9244

4

1

2 0_0201_5%

MC74VHC1G09DFT2G_SC70-5 B

R9249 1

@

2 0_0201_5%

A

A

Project Name : OAS-1 SP ASSESS Size :

Title :

Document Number :

CPU(2/8) : MISC/JTAG/CLK Rev

5

4

3

2

1

D

D

1 D

Q1

2 VCCCPUIO

E DP _H PD

G

VCCCPUIO_A S 3

38

LSK3541G1ET2L _VMT3 LSK3541G1ET2L_VMT3 2

2

R8

2 R10

R5

10K_0201_5%

24.9_0201_1%

1

100K_0201_5% 1

1

HaswellrPGA EDS

JCPU1H

C

41 41 41 41 41 41 41 41

DPB_0N DPB_0P DPB_1N DPB_1P DPB_2N DPB_2P DPB_3N DPB_3P

60 60 60 60 60 60 60 60

DPC_0N DPC_0P DPC_1N DPC_1P DPC_2N DPC_2P DPC_3N DPC_3P

T28 U28 T30 U30 U29 V29 U31 V31 T34 U34 U35 V35 U32 T32 U33 V33 P29 R29 N28 P28 P31 R31 N30 P30

DDIB_TXBN_0 DDIB_TXBP_0 DDIB_TXBN_1 DDIB_TXBP_1 DDIB_TXBN_2 DDIB_TXBP_2 DDIB_TXBN_3 DDIB_TXBP_3 DDIC_TXCN_0 DDIC_TXCP_0 DDIC_TXCN_1 DDIC_TXCP_1 DDIC_TXCN_2 DDIC_TXCP_2 DDIC_TXCN_3 DDIC_TXCP_3

eDP

EDP_AUXN EDP_AUXP EDP_HPD EDP_RCOMP EDP_DISP_UT IL

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1

DDID_TXDN_0 DDID_TXDP_0 DDID_TXDN_1 DDID_TXDP_1 DDID_TXDN_2 DDID_TXDP_2 DDID_TXDN_3 DDID_TXDP_3

M27 N27 P27 E24 R27

P35 R35 N34 P34 P33 R33 N32 P32

EDP_AUXN EDP_AUXP

EDP_AUXN EDP_AUXP

38 38

EDP_COMP C

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 FDI_TXN0 FDI_TXP0 FDI_TXN1 FDI_TXP1

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 F D I_ TX N0 F D I_ TX P0 F D I_ TX N1 F D I_ TX P1

38 38 38 38 13 13 13 13

DDI


B

B

A

A


Title :

Document Number :

CPU(7/8) : EDP/DDI Rev

5

4

3

2

1

D

D

HaswellrPGA EDS

JCPU1I

AT1 AT2 AD10 VCCCPUCORE

W29 W28 G26 W33 AL30 AL29 F25

2 R8898 C

A34 A35

C35 B35

49.9_0201_1% 1

AL25 W30 W31 W34

21

CFG3 % 1 _ 1 0 2 0 _ 9 . 9 4 2

1 0 0 9 8 R

% 5 _ 1 0 2 0 _ K 1 2

% 5 _ 1 0 2 0 _ K 1 2

% 5 _ 1 0 2 0 _ K 1 2

1 4 1 R

1 5 6 9 8 R

1 6 6 9 8 R

% 5 _ 1 0 2 0 _ K 1 2

% 5 _ 1 0 2 0 _ K 1 2

% 5 _ 1 0 2 0 _ K 1 2

@

@

@

1 7 6 9 8 R

1 8 6 9 8 R

1 1 3 2 9 R

AT20 AR20 AP20 AP22 AT22 AN22 AT25 AN23 AR24 AT23 AN20 AP24 AP26 AN25 AN26 AP25

RSVD_TP_0 RSVD_TP_1 RSVD_16 RSVD_TP_2 RSVD_TP_3 RSVD_TP_4 RSVD_TP_5 TESTLO_G26 RSVD_17 RSVD_18 RSVD_19 VCC_103 RSVD_TP_6 RSVD_TP_7 RSVD_TP_8 RSVD_TP_9 RSVD_TP_10 TESTLO CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15

RSVD_TP_11 RSVD_TP_12 RSVD_TP_13 RSVD_TP_14

C23 B23 D24 D23

AT31 CFG_RCOMP AR21 CFG_16 AR23 CFG_18 AP21 CFG_17 AP23 CFG_19 AR33 RSVD_29 G6 FC_G6 AM27 RSVD_30 AM26 RSVD_31 F5 RSVD_20 AM2 RSVD_21 K6 RSVD_22 E18 RSVD_23 RSVD_24 RSVD_25 NC RSVD_26 RSVD_TP_15 RSVD_TP_16 RSVD_TP_17

2 C

R8963 49.9_0201_1% 1

U10 P10 B1 A2 AR1 E21 E20

AP27 RSVD_27 AR26 RSVD_28 AL31 VSS_330 AL32 VSS_331


Layout note: Trace length between Pin AP22 to R9231.2 as short as possible. TP940

B

B

Table 10-1 CFG2 : PEG Static Lane Reversal 1 : Normal Operation 0 : Lane Reversal CFG4 : Display Port Presence 1 : Disabled 0 : Enabled CFG[6:5] : PEG Bifurcation 11 : Func 1 Disabled, Func 2 Disabled (x16,---,---) 10 : Func 1 Enabled, Func 2 Disabled (x8,x8,---) 01 : Func 1 Disabled, Func 2 Enabled 00 : Func 1 Enabled, Func 2 Enabled (x8,x4,x4) CFG7 : PEG Defer Training 1 : PEG Train Immediately Following XXRESETB Deassertion 0 : PEG Wait for BIOS for Training

A

A


Title :

Document Number :

CPU(8/8) : CFG/RESERVED Rev

5

4

3

2

1

D

D

VCC3_SUS VCC3B

VCC3LAN_SPI

2

2 2 % 5@ _ 1 0 2 6 5 0 6 6 _ 2 2 9 1 K 9 1 3 R . R 3

R860

@

8.2K_0201_5% 1

61,69,70

% 5 _ 1 0 2 0 _ K 3 . 3

2

LPC_AD0

A20

LPC_AD1

C20

LPC_AD2

A18

LPC_AD3 61,69,70

C18 B21

-LPC_FRAME

61,69,70

INTEGRATED PULL UP

D21

INTEGRATED PULL UP

G20 AL11

IRQSER

SMBALERT#/GPIO11 LAD_0

SMBus

SMBCLK

LAD_1 LAD_2

SMBDATA

L P C

SML0ALERT#/GPIO60

LAD_3 SML0CLK LFRAME# SML0DATA LDRQ0# SML1ALERT#/PCHHOT#/GPIO74 LDRQ1#/GPIO23 SML1CLK/GPIO58 SERIRQ SML1DATA/GPIO75

23 SPI_CLK

SPI2_CLK

R9268 2 23

R9267 1

2 33_0201_5%

1 33_0201_5% -SPI_CS0

23

-SPI_CS1

AJ11 R 9287 2

1 33_0201_5%

AJ7

R 9288 2

1 33_0201_5%

AL7 AJ10

23

SPI_MOSI_IO0

23

SPI_MISO_IO1

23

SPI_IO2

23

SPI_IO3

R9269 2

1 33_0201_5%

AH1

R9270 2

1 33_0201_5%

AH3

R9271 2

1 33_0201_5%

AJ4

R9272 2

1 33_0201_5%

AJ2

CL_CLK SPI_CLK C-Link

CL_DATA

SPI_CS0# CL_RST#

2

2

2

2

R107

R389

R394

R397

499_0201_1%

499_0201_1%

10K_0201_5%

4.7K_0201_5%

4.7K_0201_5%

1

1

1

1

1

1

1

R272 @ 10K_0201_5%

23

SPI2_MOSI_IO0

23

SPI2_MISO_IO1

23

SPI2_IO2

23

SPI2_IO3

R9273 1

2 33_0201_5%

R9274 1

2 33_0201_5%

R9275 1

2 33_0201_5%

R9276 1

2 33_0201_5%

N7 R10

SMB_CLK

U11

SMB_DATA

S MB _C LK

70

SMB_DATA

70

S ML 0_ CL K

47

C

N8 U8

SML0_CLK

R7

SML0_DATA

SML0_DATA

47

H6 K6

EC_SCL2

N11

EC_SDA2

AF11

CL_CLK_WLAN

AF10

CL_DATA_WLAN

AF7

-CL_RST_WLAN

E C_ SC L2

62

E C_ SD A2

62

CL_CLK_WLAN CL_DATA_WLAN -CL_RST_WLAN

50 50 50

SPI_CS1# SPI_CS2#

S P I

TP1

SPI_MOSI Thermal

TP2

SPI_MISO TP4 SPI_IO2 TP3 SPI_IO3 TD_IREF

B

2 R106

10K_0201_5%

LPC_AD[3:0]

C

23

2 R359

10K_0201_5% 1

LPT_PCH_M_EDS

U5D

2 R9282

BA45 BC45 BE43 BE44 AY43

R8971

1

2 8.25K_0201_1%

3 OF 11 DH82QM87-SR17C-C2_FCBGA695

B

Layout note: Put on below resistors near PCH (U5): R9268,R9269,R9270,R9271,R9272 R9267,R9273,R9274,R9275,R9276

A

A


Title : PCH(2/10) : LPC/SPI/SMBUS/C-LINK/THERMAL

Document Number :

Rev

5

4

3

2

1

D

D

VCC3M

3

DMI_RXN[3:0] DMI_RXN0 DMI_RXN1

3

3

3

DMI_RXP[3:0]

DMI_TXN[3:0]

DMI_TXP[3:0]

% 5 _ 1 0 2 0 _ K 0 2 1

% 5 _ 1 0 2 0 _ K 0 2 1

1 7 7 1 9 R

1 1 6 1 R

1 2 0 5 R

AP17 AV20 AY22 AP20

DMI_RXP2 DMI_RXP3

AR17 AW20

DMI_TXN0 DMI_TXN1

BD21 BE20

DMI_TXP2 DMI_TXP3

BE16

AV17 R201 1

2 7.5K_0201_1%

R9059 1

2 0_0201_5%

BPWRG

R21 1

2 0_0201_5%

AD7

CPUCORE_PWRGD

R617 1

2 0_0201_5%

F10

20,21,4

21,79

4

H3

DRAMPWRG R9250 1

-RSMRST -SUSWARN

62 20,71

R6

AB7

MEPWRG

21,71

AY17

AM1

-XDP_DBR

85

2 0_0201_5%

J2 J4

-PWRSW_EC

K1

AC_PRESENT

E6

71

-BATLOW

K7 N4

B

AB10 62

-PCH_SLP_WLAN

FDI_RXN_0 DMI_RXN_2 DMI_RXN_3

FDI_RXN_1

DMI_RXP_0 DMI_RXP_1

FDI_RXP_0 FDI_RXP_1

DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1

TP16 TP5 DMI

FDI

BD17 BE18 DMI_TXN_2 DMI_TXN_3 BB21 BC20 DMI_TXP_0 DMI_TXP_1 BB17 BC18 DMI_TXP_2 DMI_TXP_3

AW17

21,62,70,72

LPT_PCH_M_EDS

U5B

AW22 AR20 DMI_RXN_0 DMI_RXN_1

DMI_RXP0 DMI_RXP1

DMI_TXP0 DMI_TXP1 VCC1R5B

% 5 _ 1 0 2 0 _ K 0 0 2 1

DMI_RXN2 DMI_RXN3

DMI_TXN2 DMI_TXN3

C

VCC3_SUS

D2

TP15 TP10 FDI_CSYNC FDI_INT FDI_IREF

DMI_IREF

TP17

TP12

TP13

TP7

FDI_RCOMP

AJ35

FDI_TXN0

AL35

FDI_TXN1

AJ36

FDI_TXP0

AL36

FDI_TXP1

F D I_ TX N0

9

F D I_ TX N1

9

F D I_ TX P0

9

F D I_ TX P1

9

AV43 AY45 AV45 AW44 AL39

FDI_CSYNC

AL40

FDI_INT

F DI _C SY NC F DI _I NT

3 3

AT45 AU42 AU44 AR44

R 897 01

2 7 .5 K_ 02 01_ 1%

C

VCC1R5B RTCVCC

VCC3B

VCC3M

VCC3M

% 5 _ 1 0 2 0 _ K 0 3 2 3

% 5 _ 1 0 2 0 _ K 2 . 2 8

% 5 _ 1 0 2 0 _ K 0 1 2

% 5 _ 1 0 2 0 _ K 0 1 2

1 4 6 1 R

1 8 2 R

1 2 1 6 R

1 4 1 6 R

@

DMI_RCOMP

SUSACK#

DSWVRMEN

SYS_RESET#

DPWROK

SYS_PWROK PWROK APWROK

WAKE# SystemPower Management

DRAMPWROK

CLKRUN# SUS_STAT#/GPIO61 SUSCLK/GPIO62

RSMRST#

SLP_S5#/GPIO63

SUSWARN#/SUSPWRNACK/GPIO30

SLP_S4#

PWRBTN#

SLP_S3#

ACPRESENT/GPIO31

SLP_A#

BATLOW#/GPIO72

SLP_SUS#

RI#

PMSYNCH

TP21

SLP_LAN#

C8 L13

R203 1

2 0_0201_5%

M PW RG

K3

72

-PCIE_WAKE

AN7 U7 Y6

50,61,71

-CLKRUN

61,6 9,70

-SUS_STAT

61,70

SUSCLK_32K

Y7

61,71

-PCH_SLP_S5

C6

20,71

-PCH_SLP_S4

H1

-PCH_SLP_S3

F3

-PCH_SLP_M

F1

20,62,71 20,62,71,78 20,71

-PCH_SLP_SUS

AY3

P M_ SY NC

G5

62

4

B

-PCH_SLP_LAN

71

SUSCLK_32K_R

50

SLP_WLAN#/GPIO29 4 OF 11 DH82QM87-SR17C-C2_FCBGA695

R 9251 1

@

2 0_0201_5%

Design Note : Put R9251 near PCH (U5) in order to shorten the stub of SUSCLK_32K.

A

A


Title :

Document Number :

PCH(3/10) : DMI/FDI/PM Rev

5

4

3

2

1

D

D

VCC3B

C

VCC3B 40 40 40 2

1

40 40

BLUE GREEN RED

% % % 5 5 5 _ _ _ 1 1 1 0 0 0 2 2 2 0 0 0 _ _ _ K K K 2 2 2 . . . 2 8 2 8 2 8

% % % % % 5 5 5 5 5 _ _ _ _ _ 1 1 1 1 1 0 0 0 0 0 2 2 2 2 2 0 0 0 0 0 _ _ _ _ _ K K K K K 2 2 2 2 2 . . . . . 2 8 2 8 2 8 2 8 2 8

1 3 1 0 1 9 6 6 6 6 1 6 R R R

1 5 1 0 1 6 1 5 1 2 6 5 4 4 4 4 5 5 5 5 R R R R R

@

@

C

@

R38

R513 1

2 150_0201_1%

T45

2.2K_0201_5%

2.2K_0201_5%

R242 1

2 150_0201_1%

U44

R527 1

2 150_0201_1%

V45

1

M43

DDCCLK

M45

DDCDATA 40

HSYNC

40

VSYNC

LPT_PCH_M_EDS

U5E

2 R40

N42 N44 R140

1

2

U40 U39

649_0201_0.5%

VGA_BLUE

R40

DDPB_CTRLCLK

VGA_GREEN VGA_RED

VGA_DDC_DATA

C R T

VGA_VSYNC Y A L P S I D

VGA_IRTN

H45

DDPB_AUXN

K43

DDPC_AUXN

J42

DDPD_AUXN 38 71 72

N36

PANEL_BKLT_CTRL

K36

VGA_BLON

G36

PANEL_POWER_ON 2

B

1

H20

2 R138

R433

L20

100K_0201_5%

100K_0201_5%

K17

1

M20 53 15 65

A12

-SC_DTCT

B13

PLANARID1

C12

NFC_REG_ON

C10 A10 AL6

EDP_BKLTCTL EDP_BKLTEN

% 5 _ 1 0 2 0 _ K 2 . 2 8

% 5 _ 1 0 2 0 _ K 2 . 2 8

1

1

1

K45

DDPC_AUXP

EDP_VDDEN

% 5 _ 1 0 2 0 _ K 2 . 2 8

H43

DDPB_AUXP

L V D S

60

VCC3B

N38

DDPD_CTRLDATA

DAC_IREF

41 60

DOCK_DP_DATA

N40

DDPD_CTRLCLK

VGA_HSYNC

DOCK_DP_CLK

R36

DDPC_CTRLDATA

41

DPB_CTRLDATA

R35

DDPC_CTRLCLK

VGA_DDC_CLK

DPB_CTRLCLK

R39

DDPB_CTRLDATA

J44

DDPD_AUXP

0 3 4 R

K40

DDPB_HPD PIRQA#

2 3 4 R

5 3 4 R DPB_AUXN 41 DOCK_DPC_AUXN DPB_AUXP 41 DOCK_DPC_AUXP D PB _H PD 41

K38

DDPC_HPD PIRQB#

H39

DDPD_HPD PIRQC# PIRQD#

G17

PIRQE#/GPIO2 GPIO50 PCI

GPIO52

PIRQF#/GPIO3

L15

PIRQG#/GPIO4 GPIO54

M15

PIRQH#/GPIO5 GPIO51 PME#

N FC _I NT

F17

AD10

GPIO53 PLTRST#

INTEGRATED PULL UP

-SATA0_DEVSLP

43

-SATA1_DEVSLP

50

-SATA4_DEVSLP

53

VCC5B

GPIO55 G 2

VCC3M

2

3 R438 10K_0201_5%

R991 1

-PLTRST_NEAR

2 33_0201_5%

1

U73

5

VCC

NC IN_A

47,50,70

B

65

Y11


21,51,61,69,70,71

60 60

R993 1

-PLTRST_FAR

2 33_0201_5%

4

OUT_Y

GND

1

D OC K_ HP D

D

S

60

2 Q186 LSK3541G1ET2L_VMT3 R9210

1 100K_0201_5%

2

1

3

TC7SG17FE_SON5

2

A

1

C460 100P_0201_25V8J

2

1

C46 100P_0201_25V8J

A

Table 14-1 Buffer (U73) Toshiba

TC7SG17FE

ONsemi

NL17SZ17XV5T2G Project Name : OAS-1 SP ASSESS Size :

Title :

Document Number :

PCH(4/10) : LCD/CRT/PCI/DDI CONTROL Rev

5

4

3

2

1

TEST PAD FOR METS/APS D

D

U5J

C

AL34 AL38 AL8 AM14 AM24 AM26 AM28 AM30 AM32 AM16 AN36 AN40 AN42 AN8 AP13 AP24 AP31 AP43 AR2 AK16 AT10 AT15 AT17 AT20 AT26 AT29 AT36 AT38 D42 AV13 AV22 AV24 AV31 AV33 BB25 AV40 AV6 AW2 F43 AY10 AY15 AY20 AY26 AY29 AY7 B11 B15

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

LPT_PCH_M_EDS

U5K

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS


K39 L2 L44 M17 M22 N12 N35 N39 N6 P22 P24 P26 P28 P30 P32 R12 R14 R16 R2 R34 R38 R44 R8 T43 U10 U16 U28 U34 U38 U42 U6 V14 V16 V26 V43 W2 W44 Y14 Y16 Y24 Y28 Y34 Y36 Y40 Y8

AA16 AA20 AA22 AA28 AA4 AB12 AB34 AB38 AB8 AC2 AC44 AD14 AD16 AD18 AD30 AD32 AD40 AD6 AD8 AE16 AE28 AF38 AF8 AG16 AG2 AG26 AG28 AG44 AJ16 AJ18 AJ20 AJ22 AJ24 AJ34 AJ38 AJ6 AJ8 AK14 AK24 AK43 AK45 AL12 AL2 BC22 BB42

LPT_PCH_M_EDS



B19 B23 B27 B31 B35 B39 B7 BA40 BD11 BD15 BD19 AY36 AT43 BD31 BD35 BD39 BD7 D25 AV7 F15 F20 F29 F33 BC16 D4 G2 G38 G44 G8 H10 H13 H17 H22 H24 H26 H31 H36 H40 H7 K10 K15 K20 K29 K33 BC28

VCC3_SUS

VCC3M

JAPS1 13,21,4 60,64,70,71 11,22

14 13 12 11 10 9 8 7 6 5 4 3 2 1

-XDP_DBR -PWRSWITCH -RTCRST

13,71 13,62,71 13,71

-PCH_SLP_M -PCH_SLP_S4 -PCH_SLP_S5

13,62,71,78

-PCH_SLP_S3

14 13 12 11 10 9 8 7 6 5 4 3 2 1

16 15

GND2 GND1

ACES_50501-01441-001 CONN_NOASM@

C

TP11

11 OF 11 DH82QM87-SR17C-C2_FCBGA695 13,71

AC_PRESENT

B

B

A

A


Title :

Document Number :

PCH(10/10):GND Rev

5

4

3

2

1

D

D

VCC3_SUS

VCC1R05B

VCC3_SUS

VCC3B VCC1R05B

% 5 2 _ 1 0 2 0 _ K 1 1

4

XDP_TCK

4 4

XDP_TMS XDP_TDI -XDP_TRST XDP_TDO

4 4

13,20,4 -XDP_DBR 14,51,61,69,70,71 -PLTRST_NEAR

C

13,62,70,72 7

BPWRG PWR_DEBUG

15,4

CPUPWRGD 10

4 4

1 9 4 R

% 5 _ 1 0 2 0 _ 2 1 5 @ 5 7 1 4 R

VCCCPUIO

2 % 5 2 _ 1 0 2 0 _ 0 5 1 1

1

6 7 1 9 R

28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

XDP_TCK XDP_TMS XDP_TDI -XDP_TRST XDP_TDO -XDP_DBR -PLTRST_NEAR

@ R588 1

2 1K_0201_5%

BPWRG PWR_DEBUG @ CPUPWRGD

R594 1

2 1K_0201_5%

CFG3

-XDP_PRDY -XDP_PREQ

C8320 @ 0.1U_0201_6.3V6K

-XDP_PRDY -XDP_PREQ

11 11 11 11

13,79

PCH_TCK

% 1 _ 2 0 4 0 _ 0 1 2 2

@

@

@

PCH_TMS PCH_TDI PCH_TDO

CPUCORE_PWRGD

13,71

-RSMRST

28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

PCH_TCK PCH_TMS PCH_TDI PCH_TDO -XDP_DBR CPUCORE_PWRGD R511 1

@

21K_0402_5%

R514 1

@

21K_0402_5%

-RSMRST


2

% 1 _ 2 0 4 0 _ 0 1 2 2

9 1 5 1 0 1 0 1 3 5 5 5 R R R

JXDP1

GND GND 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

% 1 _ 2 0 4 0 _ 0 1 2 2

% 5 _ 2 0 4 0 _ 0 0 2 1

% 5 _ 2 0 4 0 _ 0 0 2 1

% 5 _ 2 0 4 0 _ 0 0 2 1

@

@

@

% 5 _ 1 0 2 0 _ 1 5

JXDP2

GND GND 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

C


2

R471 51_0201_5% 1

3 1 5 1 6 1 4 4 4 9 9 9 R R R

1 1 4 5 R

Table 21-1

B

SIGNAL

REF DES

ENABLE

DISABLE

TDO

R475

ASM

NO ASM

TRST#

R471

ASM

ASM

DBRST#

R491

ASM

ASM

RESET#

R588

ASM

NO ASM

CPUPWRGD

R594

ASM

NO ASM

PWR_DEBUG

R9176

ASM

ASM

C8320 JXDP1

ASM ASM

NO ASM NO ASM

Table 21-2 SIGNAL TDO TMS TDI TCK CPUCORE_PWRGD -RSMRST

REF DES

ENABLE

DISABLE

R509 R943 R530 R946 R515 R945

220 100 220 100 220 100

NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM

R541

51

51

R511

ASM

NO ASM

R514

ASM

NO ASM

JXDP2

ASM

NO ASM

B

LOGIC LOGIC

A

A


Title :

Document Number :

XDP CONNECTOR Rev

5

4

3

2

1

D

D

VCC3SW

RTCVCC

2 2

D6 RB520CS-30GT2RA_VMN2-2

1

D3 2

1

C287 1U_0402_6.3V6K

1

RB520CS-30GT2RA_VMN2-2 2 R4 1K_0201_5% 1 C

C

JRTC1

1 2

1 2

R620 1

DRAPH_WS32020-S0471-HF CONN_ASM@

2 20K_0201_5%

2

-RTCRST

11,2 0

2

JCMOS1 @ 1U_0402_6.3V6K 1 SHORT PADS 1

R250 1

C459

-RTCRST

2 20K_0201_5%

2

1

-SRTCRST

- SR TC R ST

11

2 JCMOS2 @ 1U_0402_6.3V6K 1 SHORT PADS C285

B

B

A

A


Title :

Document Number :

RTC BATTERY Rev

5

4

3

2

1

VCC3LAN

2 D12 1 RB520CS-30GT2RA_VMN2-2

D

D

VCC3LAN_SPI % 5 _ 1 0 2 0 _ K 3 . 3 2

% 5 _ 1 0 2 0 _ K 3 . 3 2

1 3 0 7 R 12 SPI_IO3 12 SPI_CLK 12 SPI_MOSI_IO0

SPI_IO3 SPI_CLK SPI_MOSI_IO0

R 8981 2 R681 1 R674 1

1 33_0201_5% 2 33_0201_5% 2 33_0201_5%

SPI_IO3_R SPI_CLK_R SPI_MOSI_IO0_R

K 6 V 3 . 6 2 9 _ 2 1 4 0 2 C 0 _ U 1 1 . 0

K 6 V 3 . 6 2 9 _ 2 1 6 0 2 C 0 _ U 1 1 . 0

Table 23-1 SPI Configuration Single

Dual

1 U49

8 7 6 5

Layout note: Put on resistors R8981,R681,R674 R694,R8980 near U49.

Winbond@

VCC /CS /HOLD(IO3) DO(IO1) CLK /WP(IO2) DI(IO0) GND

1 2 3 4

6 0 7 R SPI_MISO_IO1_R SPI_IO2_R

R694 2 R8980 1

1 33_0201_5% 2 33_0201_5%

-SPI_CS1 SPI_MISO_IO1 SPI_IO2

- SP I_ CS 1 12 SPI_MISO_IO1 12 S PI _I O2 12

U113 (CS0#)

W25Q32FVSSIQ_SO8

U49

U113 (CS0#)

MXIC@

U49 (CS1#)

Supplier

P/N

16MB Macronix Winbond (Numonyx)

MX25L12875FM2I-10G W25Q128FVSIQ


MX25L6475EM2I-10G W25Q64FVSSIQ


MX25L3275EM2I-10G W25Q32FVSSIQ

C

C

ZZZ5

SPI_1ST@

ZZZ4

MX25L3275EM2I-10G_SO8

SPI_2ND@

BOM note: Virtual symbol for BOM control. Winbond

X7601301003

LOGIC

Macronix

X7601301004

BOM note: Virtual symbol for BOM control.

Design Note: MX25Lxxx73E may be mixed from SIT. Don't mix it from FVT.

VCC3LAN_SPI

U113

B

12 SPI2_IO3 12 SPI2_CLK 12 SPI2_MOSI_IO0

SPI2_IO3 SPI2_CLK SPI2_MOSI_IO0

R 9259 2 R 9261 1 R 9263 1

1 33_0201_5% 2 33_0201_5% 2 33_0201_5%

SPI2_IO3_R SPI2_CLK_R SPI2_MOSI_IO0_R

Layout note: Put on resistors R9259,R9261,R9263 R9260,R9262 near U113.

8 7 6 5

Winbond@

VCC /CS /HOLD(IO3) DO(IO1) CLK /WP(IO2) DI(IO0) GND

1 2 3 4

SPI2_MISO_IO1_R SPI2_IO2_R

R9260 2 R9262 1

1 33_0201_5% 2 33_0201_5%

-SPI_CS0 SPI2_MISO_IO1 SPI2_IO2

- SP I_ CS 0 12 SPI2_MISO_IO1 S PI 2_ IO 2 12

12 B

W25Q64FVSSIQ_SO8

U113

MXIC@

MX25L6475EM2I-10G_SO8


A

A


Title :

Document Number :

SPI FLASH Rev

5

4

3

2

1

D

D

C

C

BLANK B

B

A

A


Title :

Document Number :

BLANK Rev

5

4

3

2

1

D

D

VCC1R35A

2

VCC0R675B

1

C451 10U_0603_6.3V6M

Design note: RF solution.

2

1

C462 10U_0603_6.3V6M

2

1

C477 10U_0603_6.3V6M

2

1

C480 10U_0603_6.3V6M

2

1

C484 10U_0603_6.3V6M

2

1

C486 10U_0603_6.3V6M

2

1

C490 10U_0603_6.3V6M

2

1

C498 10U_0603_6.3V6M

2

1

2

C509 10U_0603_6.3V6M

1

C8461 SWG@ 1000P_0402_25V7-K

2

1

C8461

UMA@

C8460 47P_0402_25V

2200P_0402_25V @ C455 10U_0603_6.3V6M C

2

2@ C463 10U_0603_6.3V6M

1

1

BOM note: Virtual symbol for BOM control. C

Design note: RF solution.

VCC1R35A

C8463

2

1

C479 10U_0603_6.3V6M

2

1

C481 10U_0603_6.3V6M

2

1

C485 10U_0603_6.3V6M

2

1

C489 10U_0603_6.3V6M

2

1

C497 10U_0603_6.3V6M

2

1

C503 10U_0603_6.3V6M

2

1

C517 10U_0603_6.3V6M

2

1

C524 10U_0603_6.3V6M

2

1

C518 10U_0603_6.3V6M

2

1

C8463 SWG@ 1000P_0402_25V7-K

2

1

UMA@

C8462 47P_0402_25V

2200P_0402_25V


B

B

A

A


Title :

Document Number :

DDR3L DECOUPLING Rev

5

4

3

2

1

D

D

C

C

BLANK B

B

A

A


Title :

Document Number :

BLANK Rev

5

4

3

2

1

D

D

VCC1R5VIDEO VCC1R5VIDEO 2 2

R8619 SWG@ 1.33K_0201_1%

R8620 SWG@ 1.33K_0201_1%

1 1 34

FBA_VREF_0

2

2

R8621 SWG@ 1.33K_0201_1% C

1

1

34 C6235 SWG@ 0.01U_0201_6.3V7K

FBA_VREF_1

2 R8622 SWG@ 1.33K_0201_1% 1

2

1

C6234 SWG@ 0.01U_0201_6.3V7K C

B

B

A

A


Title :

Document Number :

MEMORY TERMINATION Rev

5

4

3

2

1

D

D

C

C

BLANK B

B

A

A


Title :

Document Number :

BLANK Rev

5

4

3

2

1

D

D

C

C

BLANK B

B

A

A


Title :

Document Number :

BLANK Rev

5

4

3

2

1

VCC3B D233 RED

1

6

2

5

3

GREEN

4

BLUE

VCC5B

AOZ8904CIL_SOT23-6 D254

NEAR CRT CONN

D

1

2

D

RB521CS-30GT2RA_VMN2-2 D234

50OHM TRACE

14

CRT_HSYNC_R FL15 2 1 BLM15BB220SN1D_2P

RED

RED

1

6

2

5

2

CRT_VSYNC_R

1

C8481 0.1U_0201_6.3V6K

2

2

R55

2

150_0201_1% 1

1

DDCDATA_CONN

C542 @ 33P_0201_25V8J

3

4

DDCCLK_CONN

1

AOZ8904CIL_SOT23-6

C1060 @ 100P_0201_25V8J 2 2

R372 R370

14

GREEN

2.2K_0201_5%

NEAR CRT CONN

FL16

VCC5B

2.2K_0201_5%

2 1 BLM15BB220SN1D_2P

GREEN

1

1

1 R61

2

150_0201_1% 2

1

DDCDATA_CONN

2

C433 @ 33P_0201_25V8J

CRT CONN

F22 1.5A_6V_NANOSMDC150F

75OHM TRACE

1

2

1

C527 @ 100P_0201_25V8J

JCRT1 14

BLUE

CRT_RED_CONN CRT_GREEN_CONN CRT_BLUE_CONN

FL17 2 1 BLM15BB220SN1D_2P BLM 15BB220SN1D_2P

BLUE 2 R72

2

C

150_0201_1% 1

1

C469 @ 33P_0201_25V8J

D 8 V 2 5 2 _ 1 0 2 0 1 _ P 7 8 8 4 C

D 8 V 2 5 2 _ 1 0 2 0 1 _ P 9 8 9 4 C

D 8 V 2 5 2 _ 1 0 2 0 1 _ P 6 8 0 5 C

1 2 3 4 5 6 7 8 16

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

GND1GND2

9 10 11 12 13 14 15

VCC5B_CRT

DDCCLK_CONN

C

17

SINGA_2DS3Y19-015111F CONN_ASM@

C522 0.1U_0201_6.3V6K

2

2

1

1

C528 @ 100P_0201_25V8J

NEAR CRT CONN

VCC5B

U38

1

14

VSYNC

VSYNC

2

G

Vcc

CRT_VSYNC_CONN

K 6 V 2 3 . 6 _ C1293 2 0 4 0 1 _ U 1

5

IN A R154

3

VCC3B

CRT_HSYNC_CONN

GND

OUT Y

4

CRT_VSYNC

1

2

CRT_VSYNC_R

FL18 1 2 BLM15BB220SN1D_2P

G 2

27_0201_5%

B

TC7SET125FUF_SC70-5

2

1

VCC5B

C512 @ 100P_0201_25V8J

14

DDCCLK

14

DDCDATA

DDCCLK

3

DDCDATA

3

Q47 LSK3541G1ET2L_VMT3

1

D

S

B

DDCCLK_CONN

U56

1

14

HSYNC

HSYNC

2

G

Vcc

5

IN A R92

3

GND

OUT Y

4

CRT_HSYNC

1

2

CRT_HSYNC_R

FL19 1 2 BLM15BB220SN1D_2P BLM15BB220SN1D_2P

G 2

27_0201_5% TC7SET125FUF_SC70-5

2

1

C516 @ 100P_0201_25V8J

S

Q48 LSK3541G1ET2L_VMT3

1

D

DDCDATA_CONN

Table 40-1 CRT Sync Buffer table (U38, U56) TOSHIBA

TC7SET125FU

NXP

74AHCT1G125GW

A

A


Title :

Document Number :

EXT CRT INTERFACE Rev

ThinkPad T440p Schematics

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