Test Bench Generation using Perl script

Scripting Languages and Verification Lab (Winter Sem 2014-15) 14MVD0123 14MVD0106

SCRIPTING LANGUAGES AND VERIFICATION LAB LAB REPORT

EXPT 2: WRITE A PERL PROGRAM TO GENERATE A TEST BENCH FOR A GIVEN VERILOG CODE

Aditya Vibhute 14MVD0123

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Scripting Languages and Verification Lab (Winter Sem 2014-15) 14MVD0123 14MVD0106

EXP 2: WRITE A PERL PROGRAM TO GENERATE A TEST BENCH FOR A GIVEN VERILOG CODE

OBJECTIVE: Write a PERL Program to Generate a Test bench for a given Verilog Code.

DESCRIPTION: Keywords and Functions: 1. 2. 3. 4.

print: To print the required data. for: for loop; used for terminating running of the program after a specified limit rand: this function returns random values between user defined range. while: while loop is used to run a piece of code until the condition remains true, as soon as the condition becomes false, program terminates/comes out of the loop. 5. if: program will be executed if the specified condition is true. 6. split: this function is used to split the string of characters. Sometimes a specified delimiter is used to make divisions in between the string. 7. foreach: it is similar to for loop. Foreach helps us to check whether element of the list stored in an array variable is given word.

CODE (Combinational Circuit):

#!usr\bin\perl open OUT,">fulladd_tb.v"; open IN,"fulladd.v"; $test_vector=9; while($a=) { if($a=~/module\s(\w+)\((.*)\)\;/) { $name=$1; $portlist=$2; } if ($a=~/input\s+(.*)\;/) { $input=$1; @b=split/,/,$input; $k=@b; }

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Scripting Languages and Verification Lab (Winter Sem 2014-15) 14MVD0123 14MVD0106

if($a=~/output\s+(.*)\;/) { $output=$1; } } print OUT"module $name\_test()\;\n\n"; print OUT"reg $input\;\n\n"; print OUT"wire $output\;\n\n"; print OUT"$name\ f1($portlist)\;\n\n"; print OUT"initial\n"; print OUT"begin\n"; print"$k\n@b\n"; for($i=0;$i<$test_vector;$i=$i+1) { { %b=0; foreach $j(@b) { $data=int(rand(2)); print OUT"\#205j=$data\;\n"; } print OUT"\n"; } print OUT"\#200\$stop\;\n"; print OUT"end\n\n"; print OUT"endmodule\n"; close IN; close OUT;

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Scripting Languages and Verification Lab (Winter Sem 2014-15) 14MVD0123 14MVD0106

OUTPUT

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Scripting Languages and Verification Lab (Winter Sem 2014-15) 14MVD0123 14MVD0106

CODE (Sequential Circuit) pl script: #! usr/bin/perl open out,">count_tb.v"; open in ,"count.v"; $test_vector=10; while($a=) { if($a=~ /module\s(\w+)\((.*)\)\;/) { $name=$1; $ports=$2; } if($a=~ /output\s+(.*)\;/) { $output=$1; @d=split / /,$output; } if($a=~ /input\s+(.*)\;/) { $input=$1; @b=split/,/,$input; $k=@b; } } print out "module $name\_tb()\;\n"; print out "reg $input\;\n"; print out "wire $output\;\n"; print out "$name $name\_1(@d[1],@b[0],@b[1])\;\n"; print out "initial\n"; print out "begin\n"; print out "@b[0]=1\'b0\;\n"; print out "@b[1]=1\'b1\;\n"; print out "\#20 @b[1]=1\'b0\;\n"; print out "end\n"; print out "always \#5 @b[0]=\~@b[0] \;\n"; print out "initial\n"; print out "begin\n"; print out "\$monitor(\"\%b \%b \%b \",@b[0],@b[1],@d[1])\;\n"; print out "end\n"; print out "endmodule"; close out; close in

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Scripting Languages and Verification Lab (Winter Sem 2014-15) 14MVD0123 14MVD0106

Verilog Code: module count(out,clk,rst); output [3:0] out; input clk,rst; reg [3:0]out; initial begin out=4'b0; end always(@posedge clk) begin out=out+1; end endmodule

OUTPUT:

CONCLUSION:

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Scripting Languages and Verification Lab (Winter Sem 2014-15) 14MVD0123 14MVD0106

Hence we have successfully generated t es t benches for Verilog codes using PERL Interpreter for both combinational and sequential logic.

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