What is the diference between initial and nal block o systemverilog? The basic diference diference between these two are are evident rom the nomenclature, nomenclature, i.e, Initial block starts getting executed during simulation time t=0 while the Final block gets executed when the simulation is completed. eore getting into details, there is one similarit! between these two se"uential block o codes, both o them gets executed onl! once during the simulation #ow getting back to the diference between Initial and Final blocks, Initial blocks can contain some $ dela!s or wait statements or some wait or events, but the Final block should not contains an! such things. Final block should get executed executed with 0 simulation time. Ideall! this is used or test case status reporting or some displa! statements that have to be printed ater the test case execution is completed
System verilog Simulation Environment Phases %s one uses s!stem verilog as a veri&cation language, one needs to understand how to setup and control the simulation environment to get maximum reporting without generating erroneous reports. 'ere are some pointers rom ()!stem verilog or *eri&cation+ *eri&cation+ b! hris )pear that will enhance !our understanding o the simulation phases or s!stem verilog. Build Phase - enerate con&guration / andomi1e the con&guration o the 23T and surrounding
environment - uild environment / %llocate and connect the testbench components based on the con&guration. % testbench component is one that onl! exists in the testbench, as opposed to ph!sical components in the design that are built with T4. - eset the 23T - on&gure the 23T / ased on the generated con&guration rom the &rst step, load the 23T command registers Run Phase - )tart environment / un the testbench components such as F5s and stimulus generators - un the test / )tart the test and then wait or it to complete. It is eas! to tell when a directed test has completed, but doing so can be complex or a random test. 6ou can use the testbench la!ers as a guide. )tarting rom the top, wait or la!er to drain all the inputs rom the previous la!er 7i an!8, wait or the current la!er to become idle, and wait or the next lower la!er. 6ou should use time9out checkers to make sure the 23T or testbench does not lock up. Wra!u Phase - )weep / %ter the lowest la!er completes, !ou need to wait or the &nal transactions to drain out o the 23T. - eport / :nce 23T is idle, sweep the testbench or lost data. )ometimes the scoreboard holds the transactions which never came out, perhaps because the! were dropped b! the 23T. %rmed with this inormation, !ou can create the &nal report on whether the test passed or ailed. I it ailed, be sure to delete an! unctional coverage results, as the! ma! not be correct.
Packed "rray and #nacked "rray )!stem *erilog uses the term packed arra! to reer to the dimensions declared beore the ob;ect name 7what *erilog9<00 reers to as the vector width8. The term unpacked arra! is used to reer to the dimensions declared ater the ob;ect name. >> packed arra! bit ?@/0A packedBarra! = CDh%%E >> unpacked arra! reg unpackedBarra! ?@/0A = D0,0,0,0,0,0,0,GE
$%his $ keyword in systemverilog HthisH is a ke! word in )!stem *erilog used to unambiguousl! reer to class properties or methods o current ob;ect. The HthisH ke!word shall onl! used within a non9static class methods otherwise an error shall occur.
class %)Iwith%nkit E int a E unction new 7int a8E this.a = aE endunction / new endclass / %)Iwith%nkit >>lass instantiation and usage %)Iwith%nkit %w% = new 7<8E Jdispla! 7H%w%.a = Kd,H, %w%.a8E
"lias is s!stem verilog coding techni"ue to model bi9directional mapping or LinoutM ports or wires in a module. In particular, alias mapping is direct connection o one inout port to other. In other wa!, its a short9circuit o wires module tomap 7 inout ?> alias alias = %?0A, %?A, %?
Randomi&ation 6ou &rst create a class to hold a group o related random variables, and then have the random9solver &ll them with random values. In s!stemverilog which arra! t!pe is preerred or memor! declaration and wh! 5odeling memories larger than a ew megab!tes should be done with an associative arra!. #ote that each element in an associative arra! can take several times more memor! than a &xed9si1e or d!namic memor! because o pointer overhead.
'ow to avoid race round condition between (#% and test bench in systemverilog verication % race condition is a Naw in a s!stem or process that is characteri1ed b! an output that exhibits an unexpected dependence on the relative timing or ordering o events.
%s ar as I can tell, a program block b! itsel onl! addresses two race conditions between the testbench and 23T, both o which are covered b! using a clocking block b! itsel. Orroneous use o blocking assignments or se"uential logic. 6ou have a race within !our 23T regardless o the race between !our testbench and 23T. Orroneous use o non9blocking assignments in combinational gated clock logic. 6ou ma! have a race within !our 23T regardless o the race between !our testbench and 23T.
What are the advantages o systemverilog rogram block In a short, incomplete summar!, a program block/ cannot cannot contain alwa!s procedures, primitive instances, module instances, interace instanc es 7virtual interace and port interace is allowed8, or other programinstances. speci&es scheduling in the eactive region. This prevents race conditions. has an extra s!stem task Jexit, which terminates the program instances that calls it. The simulation will terminate when all program instances have exited. is mostl! like a module block except as stated above.
The idea o a program block is to create a clear separation between test and design Toda! the opinion o useulness o a program block is divided. From the last ew conventions I been to, the trend seems to be in avor o abandoning program blocks. This is because the advantages can be achieved b! other methods. )cheduling in the eactive region can be done with clockingblocks. % mailbox, "ueue7?JA8, or associative arra! 7?PA8 can be used or intelligentl! handling simulation terminate running multiple tests. Qersonall!, I still like using program blocks and use initial orever as an alwa!s e"uivalent when needed. I !ou are planning to use 3*5, then a non9program blocks test bench might work better or !ou. In the end, it reall! comes down to a methodolog! preerence. It is best to evaluate and tr! it on !our own.
4et me turn the "uestion around/ Rh! should an!one use a program block or their testbench, i ever!thing works &ne without themS The developers o the %*5 and :*5 do not believe that program block solve timing problems on their own. #umerous methodologies alread! in use b! T4 designers that eliminate races are sucient or testbenches.
What is the diference between logic and bit in systemverilog reg and wire were the original t!pes. Rires are constantl! assigned and regs are evaluated at particular points, the advantage here is or the simulator to make optimisations. % common mistake when learning *erilog is to assume the a reg t!pe implies a register in hardware. The earlier optimisation or the simulator can be done through the context o its usage. This introduces logic which can be used in place o wire and reg. The t!pe bit and b!te have also been created that can onl! hold < states 0 or no x or 1. b!teimplies bit ?@/0A. 3sing these t!pes ofers a small speed improvement but I would recommend not using them in T4 as !our veri&cation ma! miss uninitiali1ed values or critical resets. The usage o bit and b!te would be more common in testbench components, but can lead to issues in case o having to drive xDs to stimulate data corruption and recover!. ) E*lain the diference between data tyes logic and reg and wire + Rire are eg are present in the verilog and s!stem verilog adds one more data t!pe called logic. Rire / Rire data t!pe is used in the continuous assignments or ports list. It is treated as a wire )o it can not hold a value. It can be driven and read. Rires are used or connecting diferent modules. eg / eg is a date storage element in s!stem verilog. Its not a actual hardware register but it can store values. egister retain there value until next assignment statement. 4ogic / )!stem verilog added this additional datat!pe extends the rand eg t!pe so it can be driven b! a single driver such as gate or module. The main diference between logic data!pe and reg>wire is that a logic can be driven b! both continuous assignment or blocking>non blocking assignment.
What is the need o virtual interace ? %n interace encapsulate a group o inter9related wires, along with their directions 7via modports8 and s!nchroni1ation details 7via clocking block8. The ma;or usage o interace is to simpli! the connection between modules. ut Interace canDt be instantiated inside program block, class 7or similar non9 module entit! in )!stem*erilog8. ut the! needed to be driven rom veri&cation environment like class. To solve this issue virtual interace concept was introduced in )*. *irtual interace is a data t!pe 7that implies it can be instantiated in a class8 which hold reerence to an interace 7that implies the class can drive the interace using the virtual interace8. It provides a mechanism or separating abstract models and test programs rom the actual signals that make up the design. %nother big advantage o virtual interace is that class can d!namicall! connect to diferent ph!sical interaces in run time. *irtual interaces provide a mechanism or separating abstract models and test programs rom the actual signals that make up the design. % virtual interace allows the same subprogram to operate on diferent portions o a design and to d!namicall! control the set o signals associated with the subprogram. Instead o reerring to the actual set o signals directl!, users are able to manipulate a set o virtual signals. hanges to the underl!ing design do not re"uire the code using virtual interaces to be rewritten. ! abstracting the connectivit! and unctionalit! o a set o blocks, virtual interaces promote code reuse. *irtual interaces can be declared as class properties, which can be initiali1ed procedurall! or b! an argument to new78. This allows the same virtual interace to be used in diferent classes. % virtual interace is a pointer to an actual interace in )!stem*erilog. It is most oten used in classes to provide a connection point to allow classes to access the signals in the interace through the virtual interace pointer.
What is abstract class in systemverilog 6es, an abstract class in )!stem*erilog is the same as a virtual class. Uava uses the ke!word DabstractD, but other languages like VV do not have a speci&c ke!word. )!stem*erilog re9used the ke!word virtual so as not to reserve another ke!word. %n abstract class is simpl! one where the constructor is protected and !ou cannot construct it directl!, !ou must extend the class &rst and !ou can construct a derived ob;ect. %bstract classes allow another concept with is a pure virtual method. These are methods that must be overridden in in the extended class. ase class libraries like the 3*5 are ull o abstract classes and have methods that !ou must override, like a cop! or print method. %n abstract class that onl! contains pure virtual methods is called an interace class and !ou can de&ne an interace class that implements multiple interace classes.
What is diference between ,random-. and ,urandom-. Jrandom s!stem unction returns a <9bit signed random number each time it is called Jurandom s!stem unction returns a <9bit unsigned random nu mber each time it is called. 7newl! added in )*, not present in verilog8
What is e*ect statements in assertions %n expect statement is ver! similar to an assert statement, but it must occur within a procedural block 7including initial or alwa!s blocks, tasks and unctions8, and is used to block the execution until the propert! succeeds. 3nlike an assert statement, an expect statement starts onl! a single thread o evaluation. It comes out o the blocking mode onl! i the propert! succeeds or ails.
System/erilog (P0 -(irect Programming 0nterace. is an interace which can be used to interace )!stem*erilog with oreign languages. These Foreign languages can be , VV, )!stem as well as others. 2QIs consist o two la!ers/ % )!stem*erilog 4a!er and a Foreign language la!er. oth the la!ers are isolated rom each other. Rhich programming language is actuall! used as the oreign language is transparent and irrelevant or the )!stem9*erilog side o this interace. #either the )!stem*erilog compiler nor the oreign language compiler is re"uired to anal!1e the source code in the otherMs language. 2iferent programming languages can be used and supported with the same intact )!stem*erilog la!er. For now, however, )!stem*erilog de&nes a oreign language la!er onl! or the programming language.
What is the diference between 11 and 111 == tests logical e"ualit! 7tests or and 0, all other will result in x8 === tests W9state logical e"ualit! 7tests or , 0, 1 and x8
System %asks and 2unctions These are tasks and unctions that are used to generate input and output during simulation. Their names begin with a dollar sign 7J8 Jdispla!, Jstrobe, Jmonitor
What is systemverilog assertion binding and advantages o it enerall! !ou create a )*% bind &le and instantiate sva module with T4 module. )*% bind &le re"uires assertions be wrapped in module that includes port declaration, I the assertion module uses the same signal names as the target module, the bind &le port declarations are still re"uired but the bind9instantiation can be done using the )!stem*erilog .P implicit port connections. I signal names are not exactl! matching between target and bind &le module then we need to expand the instantiation with respected port names.
Parameteri&ed 3lasses in System /erilog + )!stem verilog allows prameteri1ed classes. In the s!stem verilog !ou can parameteri1e the t!pes also. Its basicall! like templates in VV. 4ike in classes can be parameteri1ed or si1e, width, and more Rith *erilog parameter notation lass t!pe can also be a parameter 9 Xuali&ed with ke!word t!pe 9 2e&ne operations which can be used with diferent t!pes Oach diferent t!pe parameter creates a diferent class declaration. 9 )eparate static members or each diferent t!pe Qarameteri1ed classes can be extended 7inherited8.
how to generate array without randomisation in systemverilog The new uni"ue constraint lets !ou use one statement to constrain a set o variables or arra! elements to have uni"ue values. Rhen randomi1ed, this class generates a set o ten uni"ue values rom 0 to Y.
6ou can also add other non9random variables to the set o uni"ue values which has the efect o excluding the values o those variables rom the set o uni"ue values.
Rhen randomi1ed, this class generates a set o ten uni"ue values excluding the values 0, @ and Y.
What is the diference between always4comb-. and always5-6. alwa!sBcomb is sensitive to changes within the contents o a unction, whereas alwa!s ZP is onl! sensitive to changes to the arguments o a unction.
What is the diference between overriding and overloading 7verloading Rhen two or more methods 7unctions8 in the same lass have the same name but diferent parameters is called method overloading. 'ere !ou can see the unctions name are same but parameter t!pe and number o parameters are diferent. 7verriding Rhen two or more methods 7unctions8 have the exact same method name, return t!pe, number o parameters, and t!pes o parameters as the method in the parent class is called method :verriding. 'ere !ou can see the method name, parameter and return t!pe are same but one method is in the parent class and another one in the child class.
Shallow 3oy+ )impl! makes a cop! o the reerence to % into . Think about it as a cop! o %Ds %ddress. )o, the addresses o % and will be the same i.e. the! will be pointing to the same memor! location i.e. data contents.
(ee coy+ )impl! makes a cop! o all the members o %, allocates memor! in a diferent location or and then assigns the copied members to to achieve deep cop!. In this wa!, i % becomes non9existant is still valid in the memor!. The correct term to use would be cloning, where !ou know that the! both are totall! the same, but !et diferent 7i.e. stored as two diferent entities in the memor! space8. 6ou can also
provide !our clone wrapper where !ou can decide via inclusion>exclusion list which properties to select during deep cop!.
