Interview questions in Verilog with Answers: 1. What are are the the two differ different ent desig design n methodol methodologie ogies? s? The first one is the top-down design methodology and the other one is the bottom down design methodology. In the top-down design method, we first define the top blocks and then identify the sub-blocks required to build the top block. The sub blocks are further divided into until we come to the leaf cells, which cannot be divided any further. In the bottom up design method, it is the other way round starting from the smallest level to the top-level block. Typically, Typically, a mixture of both these methods is being followed in the industry today. 2.
Defi Define ne a mo modu dule le? ? A module is the basic building block of erilog. erilog. It can be an element or a collection of lower level design blocks. !lements are grouped g rouped into a module to provide common functionality that will be used in various places in the design
3. What are the diffe differen rentt levels levels of abstr abstrati ation? on? The internals of each module in erilog erilog can be described in four different levels of abstraction. Independent of the levels of these abstractions, the module behaves in the same way to the environment. The internals of the module are hidden from the environment The first level of abstraction is the "ehavioral or the algorithmic level. #ere the module is implemented in terms of the desired design algorithms independent of the hardware implementation details The seond level of abstraction is the data flow level. #ere the module is designed by specifying the flow of data !e"t level of abstraction is the gate level modeling. #ere the module is described in terms of the logic gates and interconnections between them The last level of abstraction is the switch level. #ere the internals of the module are designed in terms of switches, storage nodes and interconnections between them #he higher $first% the level of abstration& the more fle"ible and tehnolog' inde(endent is the design . If the switch level of abstraction is being used, then it very much technology dependent. Thus, a small change in the design will cause a significant change in the design. In general, a combination of the behavioral level and the dataflow constructs are being used today and this is called as register transfer level design or the $T% $T% design ). What is instant instantiati iation on and and instan instanes? es? The process of creating ob&ects from a module is called as instantiation and this created ob&ect is called as instances
*. What is a stimulus blo+, test benh? 'nce the design block is completed, the functionality of such a block is tested and checked by applying stimulus to the block. (uch a block is called as the stimulus block or a test bench. -. What is the differene between wire and a reg data t'(e? A wire represents structural interconnections between various components and a register represents variable, which are being used to store data. The net and register are the two different data types in erilog and wire is a net. . What is the differene between /// and //? "oth of these are equality operators. )) *hecks for equality of +ero and one and the result is unknown if an x or + is present. ))) is the case equality function and this checks for equality of the two variables including x and +. 0. What is the differene between ase" and ase statements? "oth these statements are multibranching statements and the difference is that casex treats x and + as dont care in the case item and in the case expression. *ase+ treats all the + values as dont cares in the case and in the case expression but the case statement does not do either of the two. . What is the differene between unar' o(erator and logial o(erator? All logical operators require two operands to perform their function and in the other hand unary operators require only operand to perform their function. 1. What is the funtion of the statement (arameter? arameters are commands which are used in erilog to define particular constants. arameters cannot be used as variables and parameters for each module can be overridden individually at compile time. 11. Wh' is def(aram used? They are used in a module to override the parameters values. The new parameter value will be decided by the defparam command 12. What is the differene between monitor and dis(la' statements? "oth of these are essentially s'stem tas+s . (ystem tasks are commands used in erilog which begin with the sign . display is used to display the values of variables or nets or whatever is present in the parameter list. (uppose the values of the variables inside the display command changes then a new display command has to be invoked to display the new value. The monitor requires to be invoked only once and it displays all the variables and signals in the parameter list even when one of them inside the parameter list changes.
13. What is the differene between sto( and finish statements? These two commands are also essentially system tasks as they begin with the sign. The stop command will stop/pause0 the simulation at that point and go into an interactive mode. This command is used whenever the designer wants to suspend the simulation and examine the values. The finish command on the other hand will completely terminate the simulation. 1). What are +e'words and identifiers? 1eywords are basically special identifiers which are used to define the language constructs and all the keywords are used in lower case letters as erilog differentiates between lower case and upper case letters.
Identifiers on the other hand are names that are given to ob&ects such as to registers, functions, modules etc. so that they can be referenced in design. Identifiers are case sensitive. The identifiers cannot start with a digit or a dollar sign. The dollar sign is reserved for system tasks. 1*. What are esa(ed identifiers? They are a class of identifiers which begin with the backslash and end with the white spaces. 2hite spaces include the new line, tab and the space. All characters between the backslash and the white spaces are processed 1-. What are strings?4 These are essentially a sequence of characters, which are enclosed in double quotes.
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44What are the two om(iler diretives?44
Include and define are the two complier directives in erilog. The define directive is used to define text macros in erilog and the inlude directive is used to include a entire erilog source file into another during compilation 10. What are (orts and what are the different t'(es of (orts? orts essentially provide the interface by which the modules can communicate with the environment. They are also called as terminals. The different types of ports are the input ports, output ports and the inout ports. 1. What is turn off dela'? The turn off delay is associated with gate level modeling and is the delay associated with a gate output transition to the high impedance value from another value. 2. What are the +e' features of behavioral modeling? The key features with behavioral modeling are that they must start with an initial or an always statement. The statements begin and end can be used along with the initial statements to group various blocks. They are equivalent to the 34 in * programming
21. Differentiate between Inter assignment Dela' and Inertial Dela' and intra assignment dela'? The inter assignment delay is the type of delay used in behavioral modeling and it is called as regular delay control. It waits for the appropriate amount of time steps before executing the command. The inertial delay is encountered in data flow modeling and it is the property where if the period of the input pulse is shorter than the delay in the continuous assignment statement, the input is not propagated to the output. The intra assignment delay is also used in behavioral modeling and here the value of the expression on the right hand is evaluated first and after the specified time delay it is assigned to the left hand side variable from a temp register 22. What is the differene between the following lines of ode? reg15/ 61 reg27 reg3 / 6 1 reg)7 The first statement is non-blocking statement and the second statement is block (tatement. 23. What are the differenes between blo+ing and non8blo+ing statements? The blocking statements use the operator ) and the whole statement is completely executed before the control passes on to the next statement. 5on blocking statements on the other hand use6) as the operator and for such statements, the right hand side of the expression is evaluated and assigned to the left hand side after the s(eified time interval . 5on-blocking statements can be used effectively to model concurrent data flow transfers like in shift registers because the result is not dependent on the order of data flow and they can avoid the race conditions, which are possible, if blocking statements are used. "oth these statements are used in behavioral modeling and are the basic procedural assignments statements 2). What is the differene between (roedural assignment statements and ontinuous assignment statements? The first difference between the two is that procedural statements are used in behavioral modeling and continuous statements are used in data flow modeling. In addition, in procedural statements the value placed on the variable will remain unchanged unless another procedural statement updates the variable with a different value. In the continuous one, the value of the right hand side expression would be placed continuously on the left side net. 2*. 9"(lain the different t'(es of ontinuous statements?4 There are three different types of continuous statements7 $egular continuous assignment • 2ire out8
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Assign 9:; out) in: < in=8 Implicit continuous assignment 2ire 9:; out) in: < in=8 Implicit net assignment 2ire 9:;8 Assign out) in: < in=8
2-. What is the differene between inertial dela' and trans(ort dela'? Inertial delay models are simulation models that filter the pulses, which are shorter than the propagation delay of erilog gate primitive or the continuous assignment. They swallow all the glitches. erilog simulates inertial delay by default. Transport delay models on the other hand are simulation models that pass all the pulses, including pulses, which are shorter than the propagation delay of the corresponding erilog statement. They pass glitches, delayed in time. Transport delay models can be modeled in erilog by adding explicit delay values to the $#( of the non-blocking assignment. 2. Wh' is it alled as blo+ing statements? It is called as blocking assignment because, once a blocking assignment is encountered, it will first execute that step and then only proceed to the next step. In the sense, it blocks the execution of other steps unless this step is finished executing. 20. Wh' is it alled as non8blo+ing statements? A non-blocking statement does not block other assignments from being executed between the evaluate and the update steps of a non-blocking assignment 2. What are the various multiwa' branhing statements in Verilog? The different multiway statements in erilog are case, casex, case+. 3. What are the various loo( ommands in Verilog?4 The various loop commands in erilog include for, repeat, forever, while. 31. What is the differene between sequential and (arallel blo+s??? 44 The keywords begin and end are used to group statements into a sequential block and these blocks are processed in the order in which they are mentioned. A statement is executed only after its preceding statement is finished execution. If a delay is specified then it is relative to the time when the previous statement finished execution. arallel blocks on the other hand start with keyword fork and &oin, all statements inside a parallel block are executed concurrently, and if a delay is mentioned then that delay is relative to the time, the block was entered. 32. What are the various +e' features of blo+s?
There are three special features of the blocks, which are nested blo+s& named blo+s and disabling of named blo+s . In nesting of blocks essentially, they can be mixed. "oth sequential and parallel blocks can be mixed with each other. These blocks can be given a name also, it will become a named block, and if we have to disable such a named block, we can use the disable block command to do this. >>. What is the benefit of using ehavior modeling st'le over ;#< modeling? The advantage of "ehavioral modeling is that it is written with higher level of abstraction and the simulation speed is faster. >?. =ow do 'ou im(lement the bi8diretional (orts in Verilog =D
Behavioral Models : Higher level of modeling where behavior of logic is modeled.
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RTL Models : Logic is modeled at register level
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Structural Models : Logic is modeled at both register level and gate level. 3-. What is the differene between a Verilog tas+ and funtion? A function will return a single value and a task will not return any value. A function will also execute itself in one simulation time unit and a task can contain time controlling statements. A function cannot enable task, but task can enable a function or other tasks. Function :
A function is unable to enable a task however functions can enable other functions. A function will carry out its required duty in zero simulation time. ( The program time will not be incremented during the function routine)Within a function, no event, delay or timing control statements are permitted In the invocation of a function their must be at least one argument to be passed.Functions will only return a single value and can not use either output or inout statements. Tasks:
Tasks are capable of enabling a function as well as enabling other versions of a Task Tasks also run with a zero simulation however they can if required be executed in a non zero simulation time. Tasks are allowed to contain any of these statements. A task is allowed to use zero or more arguments which are of type output, input
or inout. A Task is unable to return a value but has the facility to pass multiple values via the output and inout statements .
A Verilog HL function is the same as a tas!" with ver# little differences" li cannot drive more than one out$ut" can not contain dela#s. •
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functions are defined in the module in which the# are used. %t is $ossibl functions in se$arate files and use com$ile directive &include to i function in the file which instantiates the tas!. functions can not include timing delays" li!e $osedge" negedge" ' d means that functions should be e(ecuted in )*ero) time dela#. functions can have an# number of in$uts but onl# one out$ut. The variables declared within the function are local to that function. Th declaration within the function defines how the variables $assed to t b# the caller are used. functions can ta!e" drive" and source global variables" when no local va used. +hen local variables are used" basicall# out$ut is assigned end of function e(ecution. functions can be used for modeling combinational logic. functions can call other functions, but can not call tasks.
3. >iven the following Verilog ode& what value of a is dis(la'ed?
Alwa's @$l+% begin a / 7 a 5/ 17 dis(la'$a%7 9nd
30. >iven the following sni((et of Verilog ode& draw out the waveforms for l+ and a. Alwa's @$l+% begin a / 7 6* a / 17 9nd 3. What is the differene between the following two lines of Verilog ode? 6* a / b7 a / 6* b7 ). What is the differene between: / foo ? a: b7 and if $foo% / a7 else / b7
?:. =ow an 'ou swa( 2 integers a and b& without using a 3rd variable? The two integers can be swapped using erilog non-blocking assignments. This does not require the use of a third variable. If we use blocking assignments statements then we would require the use of a third variable. ?=. Whih one is (referred in design entr'? ;#< oding or hemati? Wh'?44 )3. 9"(lain the Verilog rae ondition? A erilog race condition is said to occur when two or more simulation steps that are schedules to occur in the same simulation time would give rise to different combination of values if the order of the steps were interchanged. )). Bention some the guidelines used for oding in Verilog? @se blocking assignment for expressing combinational logic and use non blocking assignment to express sequential logic. 2e should not use both the types of statements in the same block.
Ce' (oints to have in mind while writing doing ;#< oding for a finite state mahine 1. There are three different ways of coding in $T%. 'ne always block, two always block and the three always block. The two alwa's blo+ and the three always block are the preferred style of coding. 2. After obtaining the state transition diagram, first assign the values to each of the states. This can be done in binary encoding or one-hot encoding. 3. In one-hot encoding the number of bits used is equal to the number of states of the (B, with only of the bits being one for each state representation. In binar' enoding the number of fli(8flo(s required is the logarithmi value of the number of states to the base two. ). These assignments to the states can be made either using the parameter command or using the compiler directive command, define. The parameter is the command, which is preferred because, declaring the state assignments using parameters creates local definitions and hence the same name of the state can be used for a different erilog module where a separate parameter statement would make different assignments to the states. *. In general, CA vendors always recommend the use of one-hot encoding style because flip-flops are plentiful in an CA and the combinational circuits required in one-hot encoding is less that that required in binary encoding. As these combinational circuit elements si+e determine the performance of these CA, the one-hot encoding is preferred. -. (ome of the main goals of (B coding are that the coding style should be easy to code and understand, should be compact, should facilitate easy debugging and should yield efficient synthesis results. . There are essentially two main blocks in the two always and the three always coding style of a (B. They are the combinational always block and the sequential always block. 0. In the sequential always block, we always use non-blocking assignment statements and are used to code clocked or sequential logic. The sensitivity list of a sequential block is an edge based sensitivity list. . The two main reasons why we prefer to use non-blocking statements with intra assignment delays is that it gives the appearance of the clk-q delay in the waveform viewer and it helps avoid hold time problems.
1. The next type of always block is the combinational always block. This block used blocking statements and is used to update the next state value. The sensitivity list of these combinational blocks is not edge based. 11. In the combinational always block, the value of next state is set to a default value. This is essentially a coding trick and is useful in debugging. If a next state assignment has not been made inside the combinational always block then the outputs during simulation will go to default value D at that particular point during simulation and hence can be carefully debugged 12. (uppose we use a two always block method for coding a (B, then we would have one combinational always blocks, which will be used for assigning the states, and the value of the output registers. The sequential always block would be used for checking the asynchronous logic at the beginning. 13. (uppose we use a three always block method of coding a (B, then we will first have the sequential always block for the asynchronous logic and then the combinational always block for making the state assignments and then one more sequential logic for making the output assignment 1). (uppose we want to use an output-encoded style of coding, then a (A" followed by a *A" and then we would have a continuous assignment statement for the output. 1*. In Ceneral, if we have to implement a state machine design having two separate constraints, the we can create two state machine design for each of them and then combine the output of the state machines to get the desired output.
odes for various iruits
:E =-: mutliplexer using gate level modeling. =E =-: mutliplexer using behavioral modeling- using if statement and using case statement >E =-: mutliplexer using data flow modeling ?E ?-: mutliplexer using gate level modeling FE ?-: mutliplexer using data flow modeling GE ?-: mutliplexer using behavioral modeling-using if statement HE ositive/5egative latch JE Asyncronous/(yncronous and T flip flops KE !ncoders/decoders
>ate level modeling for mu"2:
module mux=Lout,i;,i:,s;E8 output out8 input i;,i:,s;8 //internal wires wire sbar,y:,y=8 not g:Lsbar,s;E8 and g=Ly:,i;,sbarE8 and g>Ly=,i:,s;E8 or g?Lout,y:,y=E8 ata low 7 module mux21(q, sel, a, b); input sel, a, b; output q; assign q = sel ? b : a; endmodule
"ehavioral 7 If or case statements AlwaysL0E *ase sel ;7 q6)a8 :7 q6)b8
A ataflow B@D M arameteri+ed 2idth module mu"21n$q& sel& a& b%7 (arameter WID / 1-7 in(ut sel7 in(utEWID81:F a& b7 out(utEWID81:F q7 assign q / sel ? b : a7 endmodule N "y default, this is now a :G-bit wide B@D. N 2hen instantiating, the default value of :G can be overridden7
mu"21n B1$q& sel& a& b%7 ,, Instane a 1-8bit version mu"21n 6$)% B$q& sel& a& b%7 ,, Instane a )8bit version
Rac ec ondi t i ons: Theor derofe x ec ut i oni s n' tal wa ysguar ant eedwi t hi nVer i l og.Thi scanbes t bei l l us t r at edbyac l as si cex ampl e.Cons i dert hec odes ni ppetbel ow: initial a = 0; initial b = a; initial begin #1; $display("Value a=%b Value of b=%b",a,b); end
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