Siemens Simatic S 7 300 - 400 -Function Block Diagram for S7-300 and S7-400

Preface, Contents Product Overview

1

Configuration and Elements of Function Block Diagram

2

Addressing

3

Bit Logic Instructions

4

Timer Instructions

5

Counter Instructions

6

Integer Math Instructions

7

Floating-Point Math Instructions

8

This reference manual is part of the documentation package with the order number:

Comparison Instructions

9

6ES7810-4CA04-8BR0

Move and Conversion Instructions

10

Word Logic Instructions

11

Shift and Rotate Instructions

12

Data Block Instructions

13

Jump Instructions

14

Status Bit Instructions

15

Program Control Instructions

16

SIMATIC S7 Function Block Diagram (FBD) for S7-300 and S7-400 Programming Reference Manual

10/98 C79000-G7076-C566 Release 01

Appendix Glossary, Index

Safety Guidelines

!

!

!

This manual contains notices which you should observe to ensure your own personal safety, as well as to protect the product and connected equipment. These notices are highlighted in the manual by a warning triangle and are marked as follows according to the level of danger:

Danger indicates that death, severe personal injury or substantial property damage will result if proper precautions are not taken.

Warning indicates that death, severe personal injury or substantial property damage can result if proper precautions are not taken.

Caution indicates that minor personal injury or property damage can result if proper precautions are not taken.

Note draws your attention to particularly important information on the product, handling the product, or to a particular part of the documentation.

Correct Usage

!

Trademarks

Note the following:

Warning This device and its components may only be used for the applications described in the catalog or the technical description, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens.

SIMATIC, AG.

SIMATIC HMI

and

SIMATIC NET are registered trademarks of SIEMENS

Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners.

Copyright Siemens AG 1998 All rights reserved

The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved.

We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed.

Siemens AG Bereich Automatisierungs- und Antriebstechnik Geschaeftsgebiet Industrie-Automatisierungssysteme Postfach 4848, D-90327 Nuernberg

Siemens AG 1998 Technical data subject to change.

Siemens Aktiengesellschaft

C79000-G7076-C566

Function Block Diagram (FBD) for S7-300 and S7-400

Preface

Purpose of the Manual

This manual is your guide to creating user programs in the Function Block Diagram (FBD) programming language. This manual also includes a reference section that describes the syntax and functions of the language elements of Function Block Diagram.

Audience

The manual is intended for S7 programmers, operators, and maintenance/service personnel. A working knowledge of automation procedures is essential.

Where is this Manual Valid?

This manual is valid for release 5.0 of the STEP 7 programming software package.

Which Standards Does the Software Comply With?

FBD corresponds to the “Function Block Diagram” language defined in the International Electrotechnical Commission’s standard IEC 1131-3. For further details, refer to the table of standards in the STEP 7 file NORM_TBL.WRI.

Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01

iii

Preface

Requirements

To use this Function Block Diagram manual effectively, you should already be familiar with the theory behind S7 programs which is documented in the online help for STEP 7. The language packages also use the STEP 7 standard software, so you should be familiar with handling this software and have read the accompanying documentation.

Documentation

Purpose

STEP 7 Basic Information with

Basic information for technical Working with STEP 7 V5.0, Getting Started personnel describing the methods of implementing control tasks with Manual STEP 7 and the S7-300/400 Programming with STEP 7 V5.0 programmable controllers. Configuring Hardware and Communication Connections, STEP 7 V5.0

Order Number 6ES7810-4CA04-8BA0

From S5 to S7, Converter Manual STEP 7 Reference with

Ladder Logic (LAD)/Function Block Diagram (FBD)/Statement List (STL) for S7-300/400 manuals

Standard and System Functions for S7-300/400

Online Helps

Provides reference information and describes the programming languages LAD, FBD and STL and standard and system functions extending the scope of the STEP 7 basic information.

Purpose

6ES7810-4CA04-8BA0

Order Number

Help on STEP 7

Basic information on programming and configuring hardware with STEP 7 in the form of an online help.

Part of the STEP 7 Standard software.

Reference helps on STL/LAD/FBD

Context-sensitive reference information.

Part of the STEP 7 Standard software.

Reference help on SFBs/SFCs Reference help on Organization Blocks

Accessing the Online Help

You can display the online help in the following ways:

Context-sensitive help about the selected object with the menu command Help > Context-Sensitive Help, with the F1 function key, or by clicking the question mark symbol in the toolbar.

Help on STEP 7 via the menu command Help > Contents. References

iv

References to other documentation are indicated by reference numbers in slashes /.../. Using these numbers, you can check the exact title in the References section at the end of the manual.


Preface

SIMATIC Customer Support Online Services

The SIMATIC Customer Support team offers you substantial additional information about SIMATIC products via its online services:

General current information can be obtained: – on the Internet under http://www.ad.siemens.de/simatic/html_00/simatic – via the Fax-Polling number 08765-93 02 77 95 00

Current product information leaflets and downloads which you may find useful are available: – on the Internet under http://www.ad.siemens.de/support/html_00/ – via the Bulletin Board System (BBS) in Nuremberg (SIMATIC Customer Support Mailbox) under the number +49 (911) 895-7100. To dial the mailbox, use a modem with up to V.34 (28.8 Kbps) with the following parameter settings: 8, N, 1, ANSI; or dial via ISDN (x.75, 64 Kbps).

Additional Assistance

If you have other questions, please contact the Siemens representative in your area. The addresses are listed, for example, in catalogs and in Compuserve (go autforum). Our SIMATIC Basic Hotline is also ready to help:

in Nuremberg, Germany – Monday to Friday 07:00 to 17:00 (local time): telephone: +49 (911) 895–7000 – or E-mail: [email protected]

in Johnson City (TN), USA – Monday to Friday 08:00 to 17:00 (local time): telephone: +1 423 461–2522 – or E-mail: [email protected]

in Singapore – Monday to Friday 08:30 to 17:30 (local time): telephone: +65 740–7000 – or E-mail: [email protected] The SIMATIC Premium Hotline is available round the clock worldwide with the SIMATIC card (telephone: +49 (911) 895-7777).

Courses for SIMATIC Products

Siemens offers a number of training courses to introduce you to the SIMATIC S7 automation system. Please contact your regional training center or the central training center in Nuremberg, Germany for details: Telephone: +49 (911) 895-3154.


v

Preface

Questionnaires on the Manual and Online Help

vi

To help us to provide the best possible documentation for you and future STEP 7 users, we need your support. If you have any comments or suggestions relating to this manual or the online help, please complete the questionnaire at the end of the manual and send it to the address shown. Please include your own personal rating of the documentation.


Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

1

Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

2

Configuration and Elements of Function Block Diagram . . . . . . . . . . . . . . . . . . .

2-1

2.1

Elements and Box Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2

2.2

Boolean Logic and Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-6

2.3

Significance of the CPU Registers in Statements . . . . . . . . . . . . . . . . . . . .

2-9

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2

3.2

Types of Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-4

Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

4.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-2

4.2

AND Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3

4.3

OR Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-4

4.4

AND-before-OR Logic Operation and OR-before-AND Logic Operation .

4-5

4.5

Exclusive OR Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-6

4.6

Insert Binary Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-7

4.7

Negate Binary Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-8

4.8

Assign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-9

4.9

Midline Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-10

4.10

Save RLO to BR Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-11

4.11

Set Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-12

4.12

Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13

4.13

Set Counter Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-14

4.14

Up Counter Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-16

4.15

Down Counter Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-17

4.16

Pulse Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-18

4.17

Extended Pulse Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-20

3

4


vii

Contents

5

6

7

viii

4.18

On-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-22

4.19

Retentive On-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-24

4.20

Off-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-26

4.21

Positive RLO Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-28

4.22

Negative RLO Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-29

4.23

Address Positive Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-30

4.24

Address Negative Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-31

4.25

Set_Reset Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-32

4.26

Reset_Set Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-33

Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1

5.1

Memory Areas and Components of a Timer . . . . . . . . . . . . . . . . . . . . . . . . .

5-2

5.2

Choosing the Right Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-4

5.3

Pulse S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-5

5.4

Extended Pulse S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-7

5.5

On-Delay S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-9

5.6

Retentive On-Delay S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-11

5.7

Off-Delay S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-13

Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-1

6.1

Memory Address and Components of a Counter . . . . . . . . . . . . . . . . . . . . .

6-2

6.2

Up-Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-3

6.3

Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-5

6.4

Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-7

Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-1

7.1

Add Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-2

7.2

Add Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-3

7.3

Subtract Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-4

7.4

Subtract Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-5

7.5

Multiply Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-6

7.6

Multiply Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-7

7.7

Divide Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-8

7.8

Divide Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-9

7.9

Return Fraction Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-10

7.10

Evaluating the Bits of the Status Word with Integer Math Instructions . . .

7-11


Contents

8

9

10

Floating-Point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-1

8.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-2

8.2

Add Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-3

8.3

Subtract Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-4

8.4

Multiply Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-5

8.5

Divide Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-6

8.6

Evaluating the Bits of the Status Word with Floating-Point Instructions . .

8-7

8.7

Forming the Absolute Value of a Floating-Point Number . . . . . . . . . . . . . .

8-8

8.8

Forming the Square (SQR) of a Floating-Point Number . . . . . . . . . . . . . . .

8-9

8.9

Forming the Square Root (SQRT) of a Floating-Point Number . . . . . . . . .

8-10

8.10

Forming the Natural Logarithm of a Floating-Point Number . . . . . . . . . . . .

8-11

8.11

Forming the Exponential Value of a Floating-Point Number . . . . . . . . . . . .

8-12

8.12

Forming Trigonometric Functions of Angles as Floating-Point Numbers .

8-13

Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-1

9.1

Compare Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-2

9.2

Compare Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-3

9.3

Compare Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-4

Move and Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-1

10.1

Assign Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-2

10.2

BCD to Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-3

10.3

Integer to BCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-4

10.4

Integer to Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-5

10.5

BCD to Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-6

10.6

Double Integer to BCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-7

10.7

Double Integer to Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-8

10.8

Ones Complement Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-9

10.9

Ones Complement Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

10.10

Twos Complement Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

10.11

Twos Complement Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

10.12

Negate Real Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13

10.13

Round to Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14

10.14

Truncate Double Integer Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.15

Ceiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

10.16

Floor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17


ix

Contents

11

12

13

14

15

16

A

x

Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-1

11.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-2

11.2

(Word) AND Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-3

11.3

(Word) AND Double Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-4

11.4

(Word) OR Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-5

11.5

(Word) OR Double Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-6

11.6

(Word) Exclusive OR Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-7

11.7

(Word) Exclusive OR Double Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-8

Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12-1

12.1

Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12-2

12.2

Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

Data Block Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13-1

13.1

Open Data Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13-2

Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-1

14.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-2

14.2

Unconditional Jump in a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-3

14.3

Conditional Jump in a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-4

14.4

Jump-If-Not . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-5

14.5

Jump Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-6

Status Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15-1

15.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15-2

15.2

Exception Bit Binary Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15-3

15.3

Result Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15-4

15.4

Exception Bit Unordered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15-6

15.5

Exception Bit Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15-7

15.6

Exception Bit Overflow Stored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15-8

Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16-1

16.1

Calling an FC/SFC without Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16-2

16.2

Calling an FB, FC, SFB, SFC, and Multiple Instances . . . . . . . . . . . . . . . .

16-4

16.3

Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16-7

16.4

Master Control Relay Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16-8

16.5

Master Control Relay Activate/Deactivate . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

16.6

Master Control Relay On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13

Alphabetical Lists of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-1

A.1

A-2

List of Instructions with International Names . . . . . . . . . . . . . . . . . . . . . . . .


Contents

A.2

B

C

List of Instructions with International (English) Names and German Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-6

A.3

List of Instructions with German SIMATIC Names . . . . . . . . . . . . . . . . . . . .

A-10

A.4

List of Instructions with German Names and International (English) Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-14

Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-1

B.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-2

B.2

Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-3

B.3

Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-7

B.4

Counter and Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-11

B.5

Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-13

B.6

Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B-14

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C-1

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Glossary-1

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Index-1


xi

Contents

xii


Product Overview

1

What is FBD?

FBD stands for Function Block Diagram. FBD is a graphic programming language and uses logic boxes familiar from Boolean algebra to represent logic. Complex functions (for example math functions) can also be represented directly connected to the logic boxes.

The FBD Programming Language

The Function Block Diagram programming language has all the elements necessary for creating a complete user program. It contains a wide range of instructions. These include the various basic instructions and a wide range of addresses and address types. Functions and function blocks allow you to structure your FBD program clearly.

The Programming Package

The FBD programming package is an integral part of the STEP 7 Standard Software. This means that following the installation of your STEP 7 software, all the editor functions, compiler functions, and test/debug functions for FBD are available to you. Using FBD, you can create your own user program. With the Incremental Editor, the input of the local data structure is made easier with the help of table editors. There are three programming languages in the standard software, STL, FBD, and LAD. You can switch from one language to the other almost without restriction and choose the most suitable language for the particular block you are programming. If you write programs in LAD or FBD, you can always switch over to the STL representation. If you convert LAD programs into FBD programs and vice versa, program elements that cannot be represented in the destination language are displayed in STL.


1-1

1-2



2

Chapter Overview

Page

Section

Description

2.1

Elements and Box Structure

2-2

2.2

Boolean Logic and Truth Tables

2-6

2.3

Significance of the CPU Registers in Statements

2-9


2-1


2.1

Elements and Box Structure

FBD Instructions

FBD instructions consist of elements and boxes that are connected graphically to form networks. The elements and boxes can be classified in the following groups:

Instructions as Elements

STEP 7 represents some of the FBD instructions as individual elements that do not require addresses or parameters (see Table 2-1). Table 2-1

FBD Instruction as an Element without Address or Parameters Element

Instruction as a Box with Address

Section in this Manual

Negate binary input

4.7

STEP 7 represents some of the FBD instructions as boxes for which you must specify an address (see Table 2-2). For more detailed information about addressing, refer to Chapter 3. Table 2-2

FBD Instruction as Box with Address Element

=

Instruction as a Box with Address and Value

Description

Description


Assign

4.8

STEP 7 represents some of the FBD instructions as boxes for which you specify an address and a value (for example a timer or counter value, see Table 2-3). For more detailed information about addressing, refer to Chapter 3. Table 2-3

FBD Instruction as a Box with Address and Value Element

Description


Retentive on-delay timer

4.19

> SS

2-2

TV



Instruction as Box with Parameters

STEP 7 represents some of the FBD instructions as boxes with inputs and outputs (see Table 2-4). The inputs are on the left of the box and the outputs on the right. You specify the input parameters and some of the output parameters. Most outputs are provided by the STEP 7 software. To assign parameters, you must use the specific notation of the data types. The parameters of the Enable input (EN) and the Enable output (ENO) are described below. For further information about input and output parameters, refer to the descriptions of the individual instructions in this manual. Table 2-4

FBD Operation as a Box with Inputs and Outputs Box

Description


Divide real

8.5

DIV_R EN

Enable Input and Enable Output Parameters

IN1

OUT

IN2

ENO

If the Enable input (EN) of an FBD box is activated, the box carries out a specific function. If the function is executed by the box without errors, the Enable output (ENO) is activated. The parameters EN and ENO of an FBD box are of the BOOL data type and can be located in the I, Q, M, D, or L memory areas (see Table 2-5 and 2-6). How EN and ENO function is described below:

If EN is not activated (its signal state is 0), the box does not execute its function and ENO is not activated (its signal state is also 0).

If EN is activated (its signal state is 1) and if the box executes its function without errors, ENO is also activated (its signal state is also 1).

If EN is activated (its signal state is 1) and if an error occurs during the execution of the function, ENO is not activated (its signal state remains 0).

Memory Areas and Functions

The majority of the addresses in FBD refer to memory areas. The following table shows the types and their functions.


2-3


Table 2-5

Memory Areas and Their Functions Access to Area

Name of Area

Function of Area

Process input image

At the beginning of the scan cycle, the operating system reads the inputs from the process and records the values in this area. The program uses these values when it is running cyclically.

Using Units of the Following Size:

Process output During the scan cycle, the program calculates output values and image enters them in this area. At the end of the scan cycle, the operating system reads the calculated output values from this area and sends them to the process outputs.

Abbr.

Input bit Input byte Input word Input double word

I IB IW ID

Output bit Output byte Output word Output double word

Q QB QW QD

Bit memory

This area provides memory space for interim results calculated Memory bit in the program. Memory byte Memory word Memory double word

M MB MW MD

I/Os

Using this area, your program has direct access to input and output modules (peripheral inputs and outputs).

Peripheral input byte Peripheral input word Peripheral input double word

PIB PIW PID

Peripheral output byte Peripheral output word Peripheral output double word

PQB PQW PQD

Timer (T)

T

Ext. inputs I/Os: Ext. outputs Timers

Timers are function elements in FBD. This area provides memory space for timer cells. In this area, the clock timing accesses the timer cells and updates them by decrementing the timer value. Timer operations access these timer cells.

Counters

Counters are function elements in FBD. This area provides Counter (C) memory space for counters. Count instructions access the cells in this area.

Data block

This area contains data that can be accessed from within any block. If it is necessary to open two data blocks at the same time, you can open one with the “OPN DB” instruction and the other with the “OPN DI” instruction. The notation of the addresses, for example L DBWi and L DIWi identifies the data block to be accessed. Although you can access any data block with the “OPN DI” i instruction, i this hi iinstruction i iis mainly i l used d to open iinstance ddata blocks that are assigned to function blocks (FBs) and system function blocks (SFBs). For more detailed information about FBs and SFBs, refer to the STEP 7 Online Help.

Data block opened with the “OPN DB” instruction: Data bit Data byte Data word Data double word

DBX DBB DBW DBD

Data block opened with the “OPN DI” instruction: Data bit Data byte Data word Data double word

DIX DIB DIW DID

This area contains temporary local data belonging to a logic block (FB or FC). This type of data is also called dynamic local data. This area is used as a buffer. When the logic block is closed, the data are lost. These data are located in the local data stack (L stack).

Temporary local data bit Temporary local data byte Temporary local data word Temporary local data double word

Local data

2-4

C

L LB LW LD



Table 2-6 lists the maximum address ranges for the various memory areas. For more detailed information about the address ranges on your CPU, refer to the corresponding manual /70/ or /101/. Table 2-6

Memory Areas and Their Address Ranges Access Using

Name of Area

Units of the Following Sizes:

Abbr.

M i Maximum Address Add Range R

Process input image Input bit Input byte Input word Input double word

I IB IW ID

0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532

Process output image

Output bit Output byte Output word Output double word

Q QB QW QD

0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532

Bit memory

Memory bit Memory byte Memory word Memory double word

M MB MW MD

0.0 to 255.7 0 to 255 0 to 254 0 to 252

I/Os: External inputs

Peripheral input byte Peripheral input word Peripheral input double word

PIB PIW PID

0 to 65 535 0 to 65 534 0 to 65 532

I/Os: External outputs

Peripheral output byte Peripheral output word Peripheral output double word

PQB PQW PQD

0 to 65 535 0 to 65 534 0 to 65 532

Timers

Timer

T

0 to 255

Counters

Counter

C

0 to 255

Data block

Data block opened with the DB [OPN] instruction DBX DBB DBW DBD

0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532

Data bit in the instance DB Data byte Data word Data double word

DIX DIB DIW DID

0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532

Temporary local data bit Temporary local data byte Temporary local data word Temporary local data double word

L LB LW LD

0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532

Data bit in the data block Data byte Data word Data double word Data block opened with the DI [OPN] instruction

Local data 1)

1)

With FBD instructions, you can only use an address in the L memory area when you declare it as VAR_TEMP in the variable declaration table.


2-5


2.2

Boolean Logic and Truth Tables

Boolean Logic

The FBD programming language is based on the binary logic of Boolean algebra in which variables can adopt the values “true” (1) or “false” (0). Each logic instruction checks the signal state of a variable for 1 (true, satisfied) or 0 (false, not satisfied) and then produces a result. The instruction then either saves the result or uses it to perform a Boolean logic operation. The result of the logic operation is known as the RLO. To represent the logic, the logic boxes known from Boolean algebra are used. The results of the logic instructions for all possible combinations of logical variables are listed in truth tables. The rules of Boolean logic are illustrated below based on the AND, OR, and exclusive OR logic operations.

AND Logic Operation

In an AND logic operation, the signal states of two or more specified addresses are checked. If the signal state of the address is 1 the condition is satisfied and the instruction produces the result 1. If the signal state of the address is 0, the condition is not satisfied and the operation produces the result 0. Figure 2-1 illustrates an AND logic operation in the FBD programming language.

The condition is satisfied when the signal state is 1 at inputs I1.0 AND I1.1.

& I1.0 I1.1 Figure 2-1

Q4.0 = AND Logic Operation in FBD

The possible results of an AND logic operation can be represented in a truth table. Here, 1 means “satisfied” and 0 means “not satisfied”. The possible logic instructions and their results are shown in Table 2-7. Table 2-7

AND Truth Table

If the result of the signal and the result of the signal the result of the logic instruction is as follows: state check at address I1.0 state check at address I1.1 is as below is as below

2-6

1

1

1

0

1

0

1

0

0

0

0

0



OR Logic Operation

In an OR logic operation, the signal states of two or more specified addresses are checked. If the signal state of one of the addresses is 1, the condition is satisfied and the instruction provides the result 1. If the signal state of all addresses is 0, the condition is not satisfied and the instruction produces the result 0. Figure 2-2 shows an OR logic operation in the FBD programming language.

>=1 Q4.0 =

I1.0 I1.1

Figure 2-2

The condition is satisfied when the signal state is 1 at inputs I1.0 OR I1.1.

OR Logic Operation in FBD

The possible results of an OR logic operation can be shown in a truth table. Here, 1 means “satisfied” and 0 means “not satisfied”. The possible logic operations and their results are shown in Table 2-8. Table 2-8

Exclusive OR Logic Operation

OR Truth Table

If the result of the signal state check at address I1.0 is as below

and the result of the the result of the logic instruction is as follows: signal state check at address I1.1 is as below

1

0

1

0

1

1

1

1

1

0

0

0

In an exclusive OR logic operation, the signal states of two or more specified addresses are checked. If the signal state of one of the addresses is 1 the condition is satisfied and the instruction provides the result 1. If the signal state of all addresses is 0 or 1, the condition is not satisfied and the instruction produces the result 0. Figure 2-3 shows an exclusive OR logic operation in the FBD programming language.

XOR Q4.0 =

I1.0 I1.1

Figure 2-3

The condition is satisfied when the signal state is 1 at input I1.0 OR at input I1.1 exclusively (i.e. not at both).

Exclusive OR Logic Operation in FBD


2-7


The possible results of an exclusive OR logic operation can be represented in a truth table. Here, 1 means “satisfied” and 0 means “not satisfied”. The possible logic operations and their results are shown in Table 2-9. Table 2-9

Exclusive OR Truth Table

and the result of the the result of the logic instruction If the result of the signal state check at is as follows: signal state check at address I1.0 is as below address I1.1 is as below

2-8

1

0

1

0

1

1

1

1

0

0

0

0



2.3

Significance of the CPU Registers in Statements

Explanation

Registers help the CPU perform logic, math, shift, or conversion instructions. These registers are described below.

Accumulators

The accumulators are general-purpose registers that you use to process bytes, words, and double-words. The accumulators are 32-bits wide.

31

24

23

High byte

16

8 7

Low byte

High word Figure 2-4

15 High byte

0 Low byte

Low word

Accumulator (1 or 2)

Areas of an Accumulator

Status Word

The status word contains bits that you can reference in the address of bit logic instructions. The following sections explain the significance of bits 0 through 8. 215...

Figure 2-5

Changes in the Bits of the Status Word

...29

28

27

26

25

BR

CC1

CC0

OV

24 OS

23

22

21

20

OR

STA

RLO FC

Structure of the Status Word

Value

Meaning

0

Sets the signal state to 0

1

Sets the signal state to 1

x

Changes the state

–

State remains unchanged


2-9


First Check

Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-5). At the start of an FBD network, the signal state of the FC bit is always 0, unless the previous network ended with the SAVE box Each logic instruction checks the signal state of the FC bit as well as the signal state of the contact that the instruction addresses. The signal state of the FC bit determines the sequence of a logic string. If the FC bit is 0 (at the start of an FBD network), the instruction stores the result in the result of logic operation bit (RLO) of the status word and sets the FC bit to 1. This is known as the first check. The 1 or 0 that is set in the RLO bit after the first check is then referred to as the result of first check. If the signal state of the FC bit is 1, an instruction then combines the result of its signal state check at the addressed contact with the RLO formed at the addressed contact after the first check, and sets the result in the RLO bit. A logic string made up of FBD instructions always ends with an output instruction (for example set output, reset output, assign) or with a jump instruction dependent on the result of the logic operation (RLO). These instructions reset the FC bit to 0.

Result of Logic Operation

Bit 1 of the status word is called the result of logic operation bit (RLO bit, see Figure 2-5). This bit stores the result of a string of logic instructions or compare instructions. The signal state of the RLO bit provides information about signal flow. The first instruction in an FBD network checks the signal state of an address and produces a result of 1 or 0. The instruction enters the result of this signal state in the RLO bit. The second instruction in a string of logic operations also checks the signal state of an address and produces a result. The instruction now combines this result with the value of the RLO bit of the status word according to the rules of Boolean logic (see First Check above). The result of the logic operation is entered in the RLO bit of the status word and replaces the previous value in the RLO bit. Each subsequent instruction in the string of logic operations combines two values: the result of the signal check at the specified address and the current RLO. You can, for example, assign the state of a bit memory location to the RLO during a first check using a Boolean logic operation or trigger a jump instruction.

2-10



Status Bit

Bit 2 of the status word is called the status bit (STA bit, see Figure 2-5). The status bit stores the value of a bit that is referenced. The status of a logic instruction that reads memory is always the same as the value of the bit that this instruction checks (the bit on which it performs its logic operation). The status of a bit instruction that writes to memory (Set Output, Reset Output, or Assign) is the same as the value of the bit to which the instruction writes. If no writing takes place, the value is the same as the value of the bit that the instruction references. The status bit has no significance for bit instructions that do not access memory. These instructions set the status bit to 1 (STA=1). The status bit is not checked by an instruction. It is interpreted during program test (program status) only.

OR Bit

Bit 3 of the status word is called the OR bit (see Figure 2-5). The OR bit is required to execute an AND before OR logic operation. An AND logic operation can contain the instructions AND input and AND NOT input. The OR bit indicates to the instructions that a previously executed AND logic operation produced the value 1 so that the result of the OR logic operation has already been determined. Any other bit-processing instruction resets the OR bit.

Overflow Bit

Bit 5 of the status word is called the overflow bit (OV bit, see Figure 2-5). The OV bit indicates an error. It is set by a math instruction or a compare floating-point numbers instruction after an error has occurred (overflow, illegal instruction, illegal floating-point number). The bit is set or reset according to the result of the math or compare instruction (error).

Stored Overflow Bit

Bit 4 of the status word is called the store overflow bit (OS bit, see Figure 2-5). The OS bit is set together with the OV bit when an error occurs. Since the OS bit is unchanged when math instructions are executed without errors (in contrast to the OV bit), this indicates whether or not an error occurred in one of the previously executed instructions. The following instructions reset the OS bit: JOS (jump if stored overflow bit = 1, must be programmed in STL), block calls and block end statements.

CC1 and CC0

Bits 7 and 6 of the status word are called condition code 1 and condition code 0 (CC1 and CC0, see Figure 2-5). The CC1 and CC0 bits provide information about the following results or bits:

Result of a math instruction Result of a compare instruction Result of a digital instruction Bits that have been shifted out of the address by a shift or rotate instruction. Tables 2-10 to 2-15 list the meaning of CC1 and CC0 after your program has executed certain instructions.


2-11


Table 2-10

CC1 and CC0 after Math Instructions, without Overflow

CC1

CC0

Explanation

0

0

Result = 0

0

1

Result < 0

1

0

Result > 0

Table 2-11

CC1 and CC0 after Integer Math Instructions, with Overflow

CC1

CC0

Explanation

0

0

Negative range overflow in Add Integer and Add Double Integer

1

Negative range overflow in Multiply Integer and Multiply Double Integer Positive range overflow in Add Integer, Subtract Integer, Add Double Integer, Subtract Double Integer, Twos Complement Integer, and Twos Complement Double Integer

1

0

Positive range overflow in Multiply Integer and Multiply Double Integer, Divide Integer, and Divide Double Integer Negative range overflow in Add Integer, Subtract Integer, Add Double Integer, and Subtract Double Integer

1

1

Division by 0 in Divide Integer, Divide Double Integer, and Return Fraction Double Integer

0

Table 2-12

2-12

CC1 and CC0 after Floating-Point Math Instructions, with Overflow

CC1

CC0

0

0

Gradual underflow

0

1

Negative range overflow

1

0

Positive range overflow

1

1

Not a valid floating-point number

Explanation



Table 2-13

CC1 and CC0 after Comparison Instructions

CC1

CC0

0

0

IN2 = IN1

0

1

IN2 < IN1

1

0

IN2 > IN1

1

1

IN1 or IN2 is not a valid floating-point number

Table 2-14

CC1 and CC0 after Shift and Rotate Instructions

CC1

CC0

0

0

Bit shifted out last = 0

1

0

Bit shifted out last = 1

Table 2-15

Binary Result Bit

Explanation

Explanation

CC1 and CC0 after Word Logic Instructions

CC1

CC0

0

0

Explanation Result = 0

1

0

Result <> 0

Bit 8 of the status word is called the binary result bit (BR bit, see Figure 2-5). The BR bit forms a link between the processing of bits and words. This bit is an efficient method with which you can interpret the result of a word instruction as a binary result and include this result in a binary string of logic operations. The BR bit represents an internal memory bit in which the RLO can be saved prior to a word instruction that changes the RLO so that the old RLO is available again after the operation when the interrupted series of bit instructions is resumed. With the BR bit, you can, for example, program a function block (FB) or a function (FC) in Statement List (STL) and call the FB or FC in FBD. If you write a function block or a function that you want to call in FBD, regardless of whether you write the FB or FC in STL or FBD, you must take into account the BR bit. The BR bit corresponds to the Enable output (ENO) of an FBD box. You save the RLO in the BR bit using the SAVE instruction (in STL) or with the SAVE FBD box according to the following criteria:

Save an RLO of 1 in the BR bit when the FB or FC is processed without errors.

Save an RLO of 0 in the BR bit if an error occurs during the processing of an FB or FC. Program these instructions at the end of the FB or FC so that they are the last instructions executed in the block.


2-13


!

Meaning of EN/ENO

Warning The BR bit can be reset to 0 unintentionally. When you write FBs or FCs in FBD and do not handle the BR bit as described above, an FB or FC might overwrite the BR bit of another FB or FC. To avoid this problem, save the RLO at the end of each FB or FC as described above.

The Enable input (EN) and Enable output (ENO) parameters of an FBD box function as explained below:

If EN is not activated (its signal state is 0), the box does not execute its function and ENO is not activated (it also has a signal state of 0).

If EN is activated (its signal state is 1) and the box executes its function without errors, ENO is also activated (its signal state is also 1).

If EN is activated (its signal state is 1) and an error occurs while the function is being executed, ENO is not activated (its signal state is 0). When you call a system function block (SFB) or a system function (SFC) in your program, the SFB or SFC indicates whether or not the CPU executed the function without errors by setting the signal state of the BR bit:

If an error occurred during execution, the BR bit is set to 0. If the function was executed without errors, the BR bit is 1.

2-14


3

Addressing Chapter Overview

Section

Description

Page

3.1

Overview

3-2

3.2

Types of Addresses

3-4


3-1

Addressing

3.1

Overview

What is Addressing?

Many FBD instructions operate with one or more addresses. The address specifies a constant or a location at which the instruction finds a variable which it uses to perform a logic operation. This location can be a bit, byte, word, or double word. Examples of possible addresses are as follows:

A constant, the value of a timer or counter, or an ASCII character string A bit in the status word of the programmable controller A data block and a location within the data block area Immediate and Direct Addressing

The following types of addressing are available:

Immediate addressing (specifying a constant as the address) Direct addressing (specifying a variable as the address) Figure 3-1 shows an example of immediate and direct addressing. The function of the box is to compare two input parameters (in this case, two 16-bit integers) to see if the first input is less than or equal to the second. The constant 50 is entered as input parameter IN1. Memory word MW200, a location in memory, is entered as input parameter IN2. Because the constant 50 in the example is the actual value with which IN1 of the box will work, 50 is an immediate address of the instruction box. Because MW200 points to a location in memory where there is another value with which IN2 of the box will work, MW200 is a direct address. MW200 is a location, not the actual value itself.

CMP <= I

Figure 3-1

3-2

50

IN1

MW200

IN2

Immediate and Direct Addressing


Addressing

Table 3-1

Constant Formats for Immediate Addressing Using Addresses of Elementary Data Types

Size in Format Options Type and Description Bits

Range and Number Notation (Lowest Value to Highest Value)

Example

BOOL (Bit)

1

Boolean Text

TRUE/FALSE

TRUE

BYTE (Byte)

8

Hexadecimal

B#16#0 to B#16#FF

B#16#10 byte#16#10

WORD (Word)

16

Binary

2#0001_0000_0000_0000

Hexadecimal

2#0 to 2#1111_1111_1111_1111 W#16#0 to W#16#FFFF

BCD Unsigned decimal

C#0 to C#999 B#(0,0) to B#(255,255)

Binary

2#0 to 2#1111_1111_1111_1111_ 1111_1111_1111_1111 DW#16#0000_0000 to DW#16#FFFF_FFFF B#(0,0,0,0) to B#(255,255,255,255)

2#1000_0001_0001_1000_ 1011_1011_0111_1111

DWORD (Double word)

32

Hexadecimal Unsigned decimal

W#16#1000 word16#1000 C#998 B#(10,20) byte#(10,20)

DW#16#00A2_1234 dword#16#00A2_1234 B#(1,14,100,120) byte#(1,14,100,120)

INT (Integer)

16

Signed decimal

-32768 to 32767

1

DINT (Double integer)

32

Signed decimal

L#-2147483648 to L#2147483647

L#1

REAL (Floating point)

32

IEEE floating point

Upper limit: ±3.402823e+38 Lower limit: ±1.175495e-38 )

1.234567e+13

S5TIME (SIMATIC time)

16

S5 Time in 10-ms units (as default value)

S5T#0H_0M_0S_10MS to S5T#2H_46M_30S_0MS and S5T#0H_0M_0S_0MS

S5T#0H_1M_0S_0MS S5TIME#0H_1M_0S_0MS

TIME (IEC time)

32

IEC time in 1-ms units, signed integer

T#-24D_20H_31M_23S_648MS to T#24D_20H_31M_23S_647MS

T#0D_1H_1M_0S_0MS TIME#0D_1H_1M_0S_0MS

DATE (IEC date)

16

IEC date in 1-day units

D#1990-1-1 to D#2168-12-31

D#1994-3-15 DATE#1994-3-15

TIME_OF_ DAY (Time of day)

32

Time of day in 1-ms units

TOD#0:0:0.0 to TOD#23:59:59.999

TOD#1:10:3.3 TIME_OF_DAY#1:10:3.3

CHAR (Character)

8

Character

’A’,’B’, etc.

’E’


3-3

Addressing

3.2

Types of Addresses

Possible Addresses

One of the following elements can be used as the address of an FBD instruction:

A bit whose signal state will be checked A bit to which the signal state of the logic operation string will be assigned

A bit to which the result of logic operation (RLO) will be assigned A bit that will be set or reset A number that indicates a counter that will be incremented or decremented

A number that indicates a timer to be used An edge memory bit that saves the previous RLO An edge memory bit that saves the previous signal state of a different address

A byte, word, or double word containing a value with which the FBD element or box will work

The number of a data block (DB or DI) that will be opened or created The number of a function (FC), system function (SFC), a function block (FB), or system function block (SFB) that will be called

A label as the destination for a jump Address Identifiers

Variables as addresses consist of an address identifier and an address within the memory area indicated by the address identifier. An address identifier can be one of the following two basic types:

An address identifier that indicates the following two data objects: – The memory area in which the instruction finds a value (data object) with which it can perform a logic operation (for example “I” for process input image, see Table 2-5). – The size of a value (data object) with which the instruction will perform a logic operation (for example B for “Byte”, W for “Word” and D for “Double Word”, see Table 2-5).

An address identifier that indicates a memory area but not the size of the data object in the area (for example an identifier for the T area (timers), C (counters), or DB or DI (data block) and the number of the timer, counter, or data block, see Table 2-5).

3-4


Addressing

Pointers

A pointer identifies the location of a variable. A pointer contains an address instead of a value. When assigning an actual parameter for the parameter type “Pointer”, you provide the memory address. With STEP 7, you can enter the pointer either in the pointer format or simply as an address (for example M 50.0). The following example illustrates the pointer format for accessing data starting at M 50.0. P#M50.0

Working with Words or Double Words as the Data Object

If you are working with an instruction whose address identifier indicates a memory area of your programmable controller and a data object that is either a word or double word in size, remember that the memory location is always referenced as a byte address. This byte address is the smallest byte number or the number of the high byte within the word or double word. The address in the instruction shown in Figure 3-2, for example, references four successive bytes in the memory area M starting at byte 10 (MB10) through to byte 13 (MB13).

Instruction: L MD10 Address identifier

Figure 3-2

Byte address

Example of a Memory Location Referenced as a Byte Address

Figure 3-3 shows data objects with the following sizes:

Double word: memory double word MD10 Word: memory word MW10, MW11 and MW12 Byte: memory bytes MB10, MB11, MB12 and MB13 If you use absolute addresses that are a word or double word long, make sure that you avoid any overlapping byte assignments.

MW10 MB10

MW12 MB11

MB12

MB13

MW11 MD10 Figure 3-3

Referencing a Memory Location as a Byte Address


3-5

Addressing

3-6


4

Bit Logic Instructions Chapter Overview

Section

Description

Page

4.1

Overview

4-2

4.2

AND Logic Operation

4-3

4.3

OR Logic Operation

4-4

4.4

AND-before-OR Logic Operation and OR-before-AND Logic Operation

4-5

4.5


4-6

4.6

Insert Binary Input

4-7

4.7

Negate Binary Input

4-8

4.8

Assign

4-9

4.9

Midline Output

4-10

4.10

Save RLO to BR Memory

4-11

4.11

Set Output

4-12

4.12

Reset Output

4-13

4.13

Set Counter Value

4-14

4.14

Up Counter Instruction

4-16

4.15

Down Counter Instruction

4-17

4.16

Pulse Timer Instruction

4-18

4.17

Extended Pulse Timer Instruction

4-20

4.18

On-Delay Timer Instruction

4-22

4.19

Retentive On-Delay Timer Instruction

4-24

4.20

Off-Delay Timer Instruction

4-26

4.21

Positive RLO Edge Detection

4-28

4.22

Negative RLO Edge Detection

4-29

4.23

Address Positive Edge Detection

4-30

4.24

Address Negative Edge Detection

4-31

4.25

Set_Reset Flip Flop

4-32

4.26

Reset_Set Flip Flop

4-33


4-1


4.1

Overview

Explanation

Bit logic instructions work with two digits, 1 and 0. These two digits form the base of a number system called the binary system. The two digits 1 and 0 are called binary digits or simply bits. In conjunction with AND, OR, XOR and outputs, a 1 stands for logical YES and a 0 for logical NO. The bit logic instructions interpret the signal states 1 and 0 and combine them according to the rules of Boolean logic. These combinations produce a result of 1 or 0 known as the result of logic operation (RLO, see Section 2.2). The logic operations triggered by the bit logic instructions execute a variety of functions.

Functions

Bit logic instructions are available for the following functions:

AND, OR, and XOR: these instructions check the signal state and produce a result that is either copied to the RLO bit or combined with it. With AND logic operations, the result of the signal state check is combined according to the AND truth table (see Table 2-7). With OR logic operations, the result of the signal state check is combined according to the OR truth table (see Table 2-8), with exclusive OR logic operations, according to the exclusive OR truth table (see Table 2-9).

Assign and Midline Output: these instructions assign the RLO or store it temporarily.

The following instructions react to an RLO of 1: – Set Output and Reset Output – Set_Reset Flip Flop and Reset_Set Flip Flop

Some instructions react to a rising or falling edge so that you can execute the following functions: – Increment or decrement the value of a counter – Start a timer – Produce an output of 1

The remaining instructions affect the RLO directly in the following ways: – Negate the RLO – Save the RLO in the binary result bit of the status word In this chapter, the counter and timer instructions are shown in the international and SIMATIC forms.

4-2



4.2

AND Logic Operation

Description

With the AND instruction, you can check the signal states of two or more specified addresses at the inputs of an AND box. If the signal state of all addresses is 1, the condition is satisfied and the instruction provides the result 1. If the signal state of an address is 0, the condition is not satisfied and the instruction produces the result 0. If the AND instruction is the first instruction in a string of logic operations, it saves the result of its signal state check in the RLO bit. Every AND instruction that is not the first instruction in the string of logic operations, combines the result of its signal state check with the value stored in the RLO bit. These values are combined according to the AND truth table.

Table 4-1

AND Box and Parameters Parameters

FBD Box

Data Type

BOOL TIMER COUNTER

&

Memory Area

Description

I, Q, M, T, C, D, L

The address indicates the bit whose signal state will be checked.

&

I0.0

Q4.0 =

I0.1

Output Q4.0 is set when the signal state is 1 at input I0.0 AND I0.1.

Status Word Bits

writes Figure 4-1

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

x

x

x

1

AND Logic Operation


4-3


4.3

OR Logic Operation

Description

With the OR instruction, you can check the signal states of two or more specified addresses at the inputs of an OR box. If the signal state of one of the addresses is 1, the condition is satisfied and the instruction produces the result 1. If the signal state of all addresses is 0, the condition is not satisfied and the instruction produces the result 0. If the OR instruction is the first instruction in a string of logic operations, it saves the result of its signal state check in the RLO bit. Each OR instruction that is not the first instruction in the string of logic operations combines the result of its signal state check with the value stored in the RLO bit. These values are combined according to the OR truth table.

Table 4-2

OR Box and Parameters Parameters

FBD Box

Data Type

BOOL TIMER COUNTER

>=1

Memory Area

Description

I, Q, M, T, C, D, L

The address specifies the bit whose signal state will be checked

>=1

I0.0

Q4.0 =

I0.1

Output Q4.0 is set when the signal state is 1 at input I0.0 OR at input I0.1.

Status Word Bits

writes Figure 4-2

4-4

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

x

x

x

1

OR Logic Operation



4.4

AND-before-OR Logic Operation and OR-before-AND Logic Operation

Description

With the AND-before-OR instruction, you can check the result of a signal state according to the OR truth table. With an AND-before-OR logic operation the signal state is 1 when at least one AND logic operation is satisfied.

&

I0.0 I0.1

The signal state is 1 at output Q3.1 when at least one AND logic operation is satisfied.

>=1

The signal state is 0 at output Q3.1 when no AND logic operation is satisfied.

&

I0.2

Q3.1 =

I0.3

Status Word Bits

writes Figure 4-3

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

x

x

x

1

AND-before-OR Logic Operation

Description

With the OR-before-AND instruction, you can check the result of a signal state check according to the AND truth table. With an OR-before-AND logic operation the signal state is 1 when all OR logic operations are satisfied.

I1.0

>=1

I1.1

The signal state is 1 at output Q3.1 when both OR logic operations are satisfied.

&

The signal state is 0 at output Q3.1 when at least one OR logic operation is not satisfied.

>=1

I1.2

Q3.1 =

I1.3

Status Word Bits

writes Figure 4-4

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

x

x

x

1

OR-before-AND Logic Operation


4-5


4.5


Description

With the Exclusive OR instruction, you can check the result of a signal state check according to the Exclusive OR truth table. With an Exclusive OR logic operation, the signal state is 1 when the signal state of one of the two specified addresses is 1.

Table 4-3

Exclusive OR Box and Parameters

FBD Box

Parameters

Data Type

BOOL TIMER COUNTER

XOR

Q3.1 =

I0.2

Description

I, Q, M, T, C, D, L

The address specifies the bit whose signal state will be checked.

The signal state is 1 at output Q3.1 when the signal state is 1 at either input I0.0 OR at input I0.2 (exclusively, in other words not at both).

XOR I0.0

Memory Area

Status Word Bits

writes

Figure 4-5

4-6

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

x

x

x

1




4.6

Insert Binary Input

Description

Table 4-4

The Insert Binary Input instruction inserts a further binary input to an AND, OR, or XOR box. Binary Input Element and Parameters Parameters

FBD Element

I1.0 I1.1 I1.2

Data Type BOOL TIMER COUNTER

Memory Area

Description

I, Q, M, T, C, D, L

The address specifies the bit whose signal state will be checked

Output Q4.0 is 1 when the signal state at I1.0 AND I1.1 AND I1.2 is 1.

& Q4.0 =

Status Word Bits

writes Figure 4-6

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

–

1

x

–

Insert Binary Input


4-7


4.7

Negate Binary Input

Description

The Negate Binary Input instruction negates the RLO. When you negate the result of logic operation, you must remember certain rules:

If the result of logic operation at the first input of an AND or OR box is negated, there is no nesting.

If the result of logic operation is negated but not at the first input of an OR box, the entire binary logic operation before the input is included in the OR logic operation.

If the result of logic operation is negated but not at the first input of a AND box, the entire binary logic operation before the input is included in the AND logic operation. Table 4-5

Negate Binary Input Element

FBD Element

Parameters

Data Type

None

I1.0 I1.1

I1.2 I1.3

–

Memory Area –

Description –

Output Q4.0 is 1 when:

&

the signal state at I1.0 AND I1.1 is NOT 1 &

AND the signal state at I1.2 AND I1.3 is NOT 1 OR the signal state at I1.4 is NOT 1.

& >=1 Q4.0 =

I1.4

Status Word Bits

writes Figure 4-7

4-8

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

–

1

x

–

Negate Binary Input



4.8

Assign

Description

The Assign instruction produces the result of logic operation. The box at the end of a logic operation has the signal 1 or 0 according to the following criteria:

The output has the signal 1 when the conditions of the logic operation before the output box are satisfied

The output has the signal 0 when the conditions of the logic operation before the output box are not satisfied. The FBD logic operation assigns the signal state to the output that is addressed by the instruction (to achieve the same effect, the signal state of the RLO bit could also be assigned to the address). If the conditions of the FBD logic operations are satisfied, the signal state at the output box is 1. Otherwise the signal state is 0. The Assign instruction is influenced by the Master Control Relay (MCR). For more detailed information about the functions of the MCR, refer to Section 16.4. You can only place the Assign box at the right-hand end of the string of logic operations. You can, however, use several Assign boxes. You can create a negated assignment with the Negate Input instruction. Table 4-6

Assign Box and Parameters Parameters

FBD Box
=

I0.0

Data Type BOOL

&

I0.1

Memory Area I, Q, M, D, L

Description The address specifies the bit to which the signal state of the string of logic operations is assigned.

The signal state at output Q4.0 is 1 when the signal state is 1 at inputs I0.0 AND I0.1, OR I0.2 is 0. >=1

I0.2

Q4.0 = Status Word Bits

writes Figure 4-8

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

x

–

0

Assign


4-9


4.9

Midline Output

Description

The Midline Output instruction is an intermediate element that buffers the RLO. More precisely, this element buffers the bit logic operation of the last branch to be opened before the Midline Output. The Midline Output instruction is influenced by the Master Control Relay (MCR). For more information about the MCR functions, see Section 16.4. You can create a negated Midline Output by negating the input of the Midline Output.

Table 4-7

Midline Output Box and Parameters Parameters

FBD Box
#

1

Data Type BOOL

Memory Area I, Q, M, D,

Description

L1

The address specifies the bit to which the RLO will be assigned.

With the Connector instruction you can only use an address in the L memory area if you declare the address in VAR_TEMP; you cannot use the L memory area for absolute addresses.

I1.0 I1.1 I1.2 I1.3

M0.0 #

&

M1.1 #

&

&

>=1 DB5.DBX3.2 #

M2.2 #

I1.4

Q4.0 =

The Midline Outputs buffer the following results of the logic operations: M0.0 buffers the negated

&

RLO of

I1.0 I1.1

M2.2 the RLO of

I1.4

#

M1.1 the negated

I1.2 I1.3

RLO of

&

DB5.DBX3.2 the negated RLO of the entire bit logic operation in bit 2 of the 3rd bytes in DB 5.

Status Word Bits

writes Figure 4-9

4-10

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

x

–

1

Midline Output



4.10 Save RLO to BR Memory

Description

The Save RLO to BR Memory instruction saves the RLO in the BR bit of the status word. The first check bit FC is not reset. For this reason, if there is an AND logic operation in the next network, the state of the BR bit is included in the logic operation. Using the “Save RLO to BR Memory” instruction in conjunction with checking the BR bit in the same block or on subordinate blocks is not recommended, because the BR bit can be modified by many instructions occurring inbetween. It is advisable to use the SAVE instruction before exiting a block, since the ENO output (=BR bit) is then set to the value of the RLO bit and you can then check for errors in the block. With the “Save RLO to BR Memory” instruction, the RLO of a network can form part of a logic operation in a subordinate block. The CALL instruction in the calling block resets the first check bit.

Table 4-8

Save RLO to BR Memory Box and Parameters

FBD Box

Parameters

Data Type

None

SAVE

I1.2 I1.3

–

Memory Area –

Description –

The result of logic operation (RLO) is written to the BR bit.

&

SAVE

Status Word Bits

writes Figure 4-10

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

x

–

–

–

–

–

–

–

–



4-11


4.11 Set Output

Description

The Set Output instruction is only executed when the RLO is 1. If the RLO is 1, this instruction sets the specified address to 1. If the RLO is 0, the instruction does not affect the specified address which remains unchanged. The Set Output instruction is influenced by the Master Control Relay (MCR). For more detailed information about the MCR, refer to Section 16.4.

Table 4-9

Set Output Box and Parameters

FBD Box

Parameters

Data Type BOOL


S

Description The address specifies which bit will be set.

The signal state at output Q4.0 is set to 1 only when: I0.0 I0.1

The signal state is 1 at inputs I0.0 AND I0.1

& >=1

OR the signal state at input I0.2 is 0.

Q4.0 S

I0.2

If the RLO of the branch is 0, the signal state of Q4.0 is not changed.

Status Word Bits

writes

Figure 4-11

4-12

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

x

–

0

Set Output



4.12 Reset Output

Description

The Reset Output instruction is only executed when the RLO is 1. If the RLO is 1, this instruction resets the specified address to 0. If the RLO is 0, the instruction does not affect the specified address which remains unchanged. The Reset Output instruction is influenced by the Master Control Relay (MCR). For more detailed information about the MCR, refer to Section 16.4.

Table 4-10

Reset Output Box and Parameters

FBD Box

Parameters

Data Type BOOL

Memory Area I, Q, M, T, C, D, L

TIMER

R

Description The address specifies which bit will be reset.

COUNTER

The signal state at output Q4.0 is reset to 0 only when: I0.0 I0.1

The signal state is 1 at inputs I0.0 AND I0.1

& >=1

OR the signal state at input I0.2 is 0.

Q4.0 R

I0.2

If the RLO of the branch is 0, the signal state at output Q4.0 is unchanged.

Status Word Bits

writes

Figure 4-12

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

x

–

0

Reset Output


4-13


4.13 Set Counter Value

Description

With the Set Counter Value instruction, you assign a default value to the counter you have specified. This instruction is executed only when there is a rising edge at the RLO (change from 0 to 1 in the RLO). You can only place the Set Counter Value box at the right-hand end of the string of logic operations. You can, however, use several Set Counter Value boxes.

Table 4-11

Set Counter Value Box and Parameters, with SIMATIC Mnemonics

FBD Box

SZ

Table 4-12

Memory Area

Counter number

COUNTER Z

Address1 specifies the number of the counter that will be assigned a preset value.

ZW

WORD

The value that is preset (address2) can be in the range between 0 and 999. If you enter a constant, the characters, C# must precede the value indicating the BCD format, for example C#100.

E, A, M, D, L or constant

Description

Set Counter Value Box and Parameters with International Mnemonics

SC

4-14

Data Type

ZW

FBD Box

Parameters

CV

Parameters

Data Type

Memory Area

Counter number

COUNTER C

Address1 specifies the number of the counter that will be assigned a preset value.

CV

WORD

The value that is preset (address2) can be in the range between 0 and 999. If you enter a constant, the characters, C# must precede the value indicating the BCD format, for example C#100.

I, Q, M, D, L or constant

Description



C5 SC

The counter C5 has the value 100 preset when the signal state of I0.0 changes from 0 to 1 (rising edge in the RLO). C# specifies that you are entering a value in BCD format.

I0.0 C#100

If there is no rising edge, the value of counter C5 is not changed.

CV

Status Word Bits

writes Figure 4-13

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

–

–

0

Set Counter Value


4-15


4.14 Up Counter Instruction

Description

The Up Counter instruction increments the value of a specified counter by 1 when there is a rising edge at the RLO (change from 0 to 1) and the value of the counter is less than 999. If there is no rising edge at the RLO, or the counter has already reached the value 999, it is not incremented. The Set Counter Value instruction sets the value of the counter (see Section 4.13). You can only place the Up Counter box at the right-hand end of the string of logic operations. You can, however, use several Up Counter boxes.

Table 4-13

Up Counter Boxes and Parameters with SIMATIC and International Mnemonics Parameters

FBD Boxes
ZV

Counter number

Data Type COUNTER

CU

Memory Area Z

Description The address specifies the number of the counter that will be incremented.

C

If the signal state of I0.0 changes from 0 to 1 (rising edge in the RLO), the value of the counter C10 is incremented by 1 (unless the value of C10 is 999).

C10 CU I0.0

If there is no rising edge, the value of C10 remains unchanged.

Status Word Bits

writes Figure 4-14

4-16

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

–

–

0

Up Counter



4.15 Down Counter Instruction

Description

The Down Counter instruction decrements the value of a specified counter by 1 when there is a rising edge at the RLO (change from 0 to 1) and the value of the counter is higher than 0. If there is no rising edge at the RLO, or if the counter has already reached the value 0, the value of the counter is not decremented. The Set Counter Value instruction sets the value of the counter (see Section 4.13). You can only place the Down Counter box at the right-hand end of the string of logic operations. You can, however, use more than one Down Counter boxes.

Table 4-14

Down Counter Boxes and Parameters with SIMATIC and International Mnemonics

FBD Boxes

Parameters

ZR

Data Type

Counter number

COUNTER

CD

Memory Area Z

Description The address specifies the number of the counter to be decremented.

C

If the signal state of input I0.0 changes from 0 to 1 (rising edge at the RLO), the value of counter C10 is decremented by 1 (unless the value of C10 is already 0).

C10 CD

If there is no rising edge, the value of C10 is not changed.

I0.0

Status Word Bits

writes Figure 4-15

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

–

–

0

Down Counter


4-17


4.16 Pulse Timer Instruction

Description

The Pulse Timer instruction starts a timer with a specified value when there is a rising edge at the RLO (change from 0 to 1). As long as the RLO is positive, the timer continues to run for the specified time. A signal state check for 1 produces 1 as long as the timer is running. If the RLO changes from 1 to 0 before the time has expired, the timer is stopped. In this case, a signal state check for 1 produces a result of 0. The time units used for timers are d (days), h (hours), m (minutes), s (seconds) and ms (milliseconds). For more detailed information about the memory area and the components of a timer, refer to Section 5.1. You can only place the Pulse Timer box at the right-hand end of the string of logic operations. You can, however, use more than one Pulse Timer box.

Table 4-15

Pulse Timer Box and Parameters with SIMATIC Mnemonics

FBD Box
SI

Table 4-16

Memory Area

Description

Timer number

TIMER

T

The address specifies the number of the timer to be started.

TW

S5TIME


Time value (S5TIME format)

Pulse Timer Box and Parameters with International Mnemonics

SP

4-18

Data Type

TW

FBD Box

Parameters

TV

Parameters

Data Type

Timer number

TIMER

T

Memory Area


Description

TV

S5TIME





If the signal state of input I0.0 changes from 0 to 1 (rising edge at the RLO), timer T5 is started. As long as the signal state is 1, the timer continues to run for the specified time of 2 seconds. If the signal state at I0.0 changes from 1 to 0 before this time has expired, the timer is stopped. As long as the timer is running, the signal state at output Q4.0 is 1.

Network 1: T5 SP I0.0 S5T#2s

TV

Examples of timer values: S5T#2s = 2 seconds

Network 2:

S5T#12m_18s = 12 minutes and 18 seconds

Q4.0 =

T5

Status Word Bits

writes Figure 4-16

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

–

–

0

Pulse Timer


4-19


4.17 Extended Pulse Timer Instruction

Description

The Extended Pulse Timer instruction starts a timer with a specified value if there is a rising edge at the RLO (change from 0 to 1). The timer continues to run for the specified time even if the RLO changes to 0 before this time has expired. A signal state check for 1 produces 1 as long as the timer is running. The timer is restarted with the specified time if the RLO changes from 0 to 1 while the timer is running. For more detailed information about the memory area and the components of a timer, refer to Section 5.1. You can only place the Extended Pulse Timer box at the right-hand end of the string of logic operations. You can, however, use more than one Extended Pulse Timer box.

Table 4-17

Extended Pulse Timer Box and Parameters with SIMATIC Mnemonics Parameters

FBD Box
SV

Table 4-18

Description

TIMER

T


TW

S5TIME



Extended Pulse Timer Box and Parameters with International Mnemonics Parameters
SE

4-20

Memory Area

Timer number

TW

FBD Box

Data Type

TV

Data Type

Memory Area

Description

Timer number

TIMER

T


TV

S5TIME





Network 1:

If the signal state of input I0.0 changes from 0 to 1 (rising edge at the RLO), timer T5 is started. The timer continues to run without being influenced by a falling edge at the RLO. If the signal state of input I0.0 changes from 0 to 1 before the specified time has expired, the timer is retriggered.

T5 SE I0.0 TV

S5T#2s

As long as the timer is running, the signal state at output Q4.0 is 1. Network 2: Q4.0 =

T5

Status Word Bits

writes Figure 4-17

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

–

–

0

Extended Pulse Timer


4-21


4.18 On-Delay Timer Instruction

Description

The On-Delay Timer instruction starts a specified timer when there is a rising edge at the RLO (change from 0 to 1). A signal state check for 1 produces 1 when the specified time has expired without an error occurring and the RLO is still 1. If the RLO changes from 1 to 0 while the timer is running, the timer is stopped. In this case, a signal state check for 1 always produces the result 0. For more detailed information about the address of a timer in memory and the components of a timer, refer to Section 5.1. You can only place the On-Delay Timer box at the right-hand end of the string of logic operations. You can, however, use more than one On-Delay Timer box.

Table 4-19

On-Delay Timer Box and Parameters with SIMATIC Mnemonics

FBD Box
SE

Table 4-20

TW

SD

4-22

Data Type

Memory Area

Description

Timer number

TIMER

T


TW

S5TIME



On-Delay Timer Box and Parameters with International Mnemonics

FBD Box

Parameters

TV

Parameters

Data Type

Memory Area

Description

Timer number

TIMER

T


TV

S5TIME





Network 1: If the signal state of input I0.0 changes from 0 to 1 (rising edge at the RLO), timer T5 is started. When the time expires, and the signal state is still 1, output Q4.0 has the value 1. If the signal state changes from 1 to 0, the timer is stopped.

T5 SD I0.0 S5T#2s

TV

Network 2: Q4.0 =

T5

Status Word Bits

writes

Figure 4-18

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

–

–

0

On-Delay Timer


4-23


4.19 Retentive On-Delay Timer Instruction

Description

The Retentive On-Delay Timer instruction starts the specified timer when there is a rising edge at the RLO (change from 0 to 1). The timer continues to run for the specified time if the RLO changes to 0 before the time has expired. A signal state check for 1 produces the result 1 regardless of the RLO if the time has expired. If the RLO changes from 0 to 1 while the timer is running, the timer is restarted with the specified value. Fore more detailed information about the address of a timer in memory and the components of a timer, refer to Section 5.1. You can only place the Retentive On-Delay Timer box at the right-hand end of the string of logic operations. You can, however, use more than one Retentive On-Delay Timer box.

Table 4-21

Retentive On-Delay Timer Box and Parameters with SIMATIC Mnemonics Parameters

FBD Box
SS

Table 4-22

Description

TIMER

T


TW

S5TIME



On-Delay Timer Box and Parameters with International Mnemonics Parameters

SS

4-24

Memory Area

Timer number

TW

FBD Box

Data Type

TV

Data Type

Memory Area

Description

Timer number

TIMER

T


TV

S5TIME





Network 1: If the signal state of input I0.0 changes from 0 to 1 (rising edge at the RLO), timer T5 is started. The timer continues to run regardless of whether the signal state at I0.0 changes from 1 to 0. If the signal state changes from 0 to 1 before the time has expired, the timer is retriggered. Output Q4.0 has the value 1 when the time has expired.

T5 SS I0.0 TV

S5T#2s Network 2:

Q4.0 =

T5

Status Word Bits

writes Figure 4-19

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

–

–

0

Retentive On-Delay Timer


4-25


4.20 Off-Delay Timer Instruction

Description

The Off-Delay Timer instruction starts the specified timer when the RLO has a falling edge (change from 1 to 0). A signal state check for 1 produces 1 when the RLO is 1 or when the timer is running. The timer is reset when the RLO changes from 0 to 1 while the timer is running. The time is only restarted when the RLO changes from 1 to 0. For more detailed information about the address of a timer in memory and the components of a timer, refer to Section 5.1. You can only place the Off-Delay Timer box at the right-hand end of the string of logic operations. You can, however, use more than one Off-Delay Timer box.

Table 4-23

Off-Delay Timer Box and Parameters with SIMATIC Mnemonics

FBD Box

Parameters

SA

Table 4-24

Description

TIMER

T


TW

S5TIME



Off-Delay Timer Box and Parameters with International Mnemonics Parameters

SF

4-26

Memory Area

Timer number

TW

FBD Box

Data Type

TV

Data Type

Memory Area

Description

Timer number

TIMER

T


TV

S5TIME





Network 1:

T5 SF

The timer is started when the signal state at I0.0 changes from 1 to 0.

I0.0 S5T#2s

If the signal state changes from 0 to 1, the timer is reset.

TV

The signal state at output Q4.0 is 1, when the signal state at input I0.0 is 1 or the timer is running.

Network 2: Q4.0 =

T5

Status Word Bits

writes

Figure 4-20

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

–

–

0

Off-Delay Timer


4-27


4.21 Positive RLO Edge Detection

Description

Table 4-25

The Positive RLO Edge Detection instruction detects a change from 0 to 1 (rising edge) at the specified address and indicates this with an RLO of 1 after the instruction. The current signal state at the RLO is compared with the signal state of the address (the edge memory bit). If the signal state of the address is 0 and the RLO is 1 before the instruction, the RLO will be 1 (pulse) after the instruction, in all other cases the RLO is 0. The RLO prior to the instruction is stored in the address. Positive RLO Edge Detection Box and Parameter Parameters

FBD Box

Data Type BOOL


The address specifies which edge memory bit will store the previous RLO.

P

I1.0 I1.1 I1.2 I1.3

&

&

I1.4

&

M0.0 P

M1.1 N

Description

The edge memory bit M3.3 stores the signal state of the previous RLO.

&

>=1

M2.2 P

M3.3 N

Q4.0 =

Status Word Bits

writes

Figure 4-21

4-28

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

x

x

1




4.22 Negative RLO Edge Detection

Description

Table 4-26

The Negative RLO Edge Detection instruction detects a change from 1 to 0 (falling edge) at the specified address and indicates this by setting the RLO to 1 after the instruction. The current signal state of the RLO is compared with the signal state of the address (the edge memory bit). If the signal state of the address is 1 and the RLO prior to the instruction was 0, the RLO is 1 (pulse) after the instruction, in all other cases it is 0. The RLO prior to the instruction is stored in the address. Negative RLO Edge Detection Box and Parameter Parameters

FBD Box

Data Type

Memory Area

BOOL

I, Q, M, D, L

The address specifies which edge memory bit will store the previous RLO.

N

I1.0 I1.1 I1.2 I1.3

&

&

I1.4

&

M0.0 P

M1.1 N

Description

The edge memory bit M3.3 stores the signal state of the previous RLO.

&

>=1

M2.2 P

M3.3 N

Q4.0 =

Status Word Bits

writes Figure 4-22

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

0

x

x

1



4-29


4.23 Address Positive Edge Detection

Description

Table 4-27

The Address Positive Edge Detection instruction compares the signal state of with the signal state of the previous signal check that is stored in the parameter M_BIT. If there has been a change from 0 to 1, output Q has the value 1, in all other cases it has the value 0. Address Positive Edge Detection Box and Parameters Parameters

FBD Box POS

Data Type

Memory Area

BOOL

I, Q, M, D, L

Signal to be checked for a positive (rising) edge.

M_BIT

BOOL

Q, M, D

The M_BIT address specifies the edge memory bit used to store the previous signal state of POS. You should only use the process image input area I for the M_BIT when no input module is already using this address.

Q

BOOL

I, Q, M, D, L

One-shot output.

M_BIT Q

I0.3

Output Q4.0 is 1 when:

POS

M0.0

Description

M_BIT

there is a rising edge at input I0.3 AND the signal state is 1 at input I0.4. &

Q

Q4.0 =

I0.4

Status Word Bits

writes Figure 4-23

4-30

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

x

–

–

–

–

0

1

x

1




4.24 Address Negative Edge Detection

Description

Table 4-28

The Address Negative Edge Detection instruction compares the signal state of with the signal state of the previous check that is stored in the M_BIT parameter. If a change from 1 to 0 occurred, output Q has the value 1, in all other situations it has the value 0. Address Negative Edge Detection Box and Parameters Parameters

FBD Box NEG

M_BIT

Data Type

Memory Area

Description

BOOL

I, Q, M, D, L

Signal to be checked for a negative (falling) edge change.

M_BIT

BOOL

Q, M, D

The M_BIT address specifies the edge memory bit in which the previous signal state of NEG is stored. Only use the process input image I memory area for the M_BIT when no input module is already using this address.

Q

BOOL

I, Q, M, D, L

One-shot output.

Q

I0.3 Output Q4.0 is 1 when:

NEG

there is a falling edge at input I0.3 AND the signal state at input I0.4 is 1. M0.0

M_BIT

&

Q

Q4.0 =

I0.4

Status Word Bits

writes

Figure 4-24

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

x

–

–

–

–

0

1

x

1



4-31


4.25 Set_Reset Flip Flop

Description

The Set_Reset Flip Flop instruction executes Set (S) or Reset (R) instructions only when the RLO is 1. An RLO of 0 has no effect on these instructions, the address specified in the instruction remains unchanged. Set_Reset Flip Flop is set when the signal state at input S is 1 and the signal state at input R is 0. If input S is 0 and input R is 1, the flip flop is reset. If the RLO at both inputs is 1 the flip flop is reset. The Set_Reset Flip Flop instruction is influenced by the Master Control Relay (MCR). For more detailed information about how the MCR functions, refer to Section 16.4.

Table 4-29

Set_Reset Flip Flop Box and Parameters

FBD Box

Parameters

SR

BOOL

I, Q, M, D, L

The address specifies which bit will be set or reset.

S

S

BOOL

I, Q, M, D, L, T, C

Set instruction enabled

R

BOOL

I, Q, M, D, L, T, C

Reset instruction enabled

Q

BOOL

I, Q, M, D, L

Signal state of

R

Q

Memory Area

SR S

&

I0.0 I0.1

Description

If I0.0 is 1 and I0.1 is 0, memory bit M0.0 is set and Q4.0 is 1. If I0.0 is 0 and I0.1 is 1, the memory bit M0.0 is reset and Q4.0 is 0.

M0.0

&

I0.0 I0.1

Data Type

R

If both signal state are 0, there is no change. If both signal states are 1, the reset instruction dominates due to the order of the instructions. M0.0 is reset and Q 4.0 is 0.

Q4.0 =

Q

Status Word Bits

writes Figure 4-25

4-32

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

x

x

x

1

Set_Reset Flip Flop



4.26 Reset_Set Flip Flop

Description

The Reset_Set Flip Flop instruction executes instructions such as Set (S) or Reset (R) only when the RLO is 1. An RLO of 0 does not affect these instructions, the address specified in the instruction is not changed. Reset_Set Flip Flop is reset when the signal state at input R is 1 and the signal state at input S is 0. If input R is 0 and input S is 1, the flip flop is set. If the RLO at both inputs is 1, the flip flop is set. The Reset_Set Flip Flop instruction is affected by the Master Control Relay (MCR). For more detailed information about the way in which the MCR functions, refer to Section 16.4.

Table 4-30

Reset_Set Flip Flop Box and Parameters

FBD Box

Parameters

Data Type

Memory Area

BOOL

I, Q, M, D, L

The address specifies which bit will be set or reset.

S

BOOL

I, Q, M, D, L, T, C

Reset instruction enabled

R

BOOL

I, Q, M, D, L, T, C

Set instruction enabled

Q

BOOL

I, Q, M, D, L

Signal state of

RS R S

Q

If I0.0 is 1 and I0.1 is 0, the memory bit M0.0 is reset and output Q4.0 is 0. If I0.0 is 0 and I0.1 is 1, the memory bit M0.0 is set and output Q4.0 is 1.

M0.0

&

I0.0 I0.1

Description

RS R

&

I0.0 I0.1

S

Q

If both signal states are 0, there is no change. If both signal states are 1, the Set instruction dominates due to the order of the instructions. M 0.0 is set and Q4.0 is 1.

Q4.0 =

Status Word Bits

writes Figure 4-26

BR

CC1

CC0

OV

OS

OR

STA

RLO

FC

–

–

–

–

–

x

x

x

1

Reset_Set Flip Flop


4-33


4-34


5

Timer Instructions Chapter Overview

Section

Description

Page

5.1

Memory Areas and Components of a Timer

5-2

5.2

Choosing the Right Timer

5-4

5.3

Pulse S5 Timer

5-5

5.4

Extended Pulse S5 Timer

5-7

5.5

On-Delay S5 Timer

5-9

5.6

Retentive On-Delay S5 Timer

5-11

5.7

Off-Delay S5 Timer

5-13


5-1

Timer Instructions

5.1

Memory Areas and Components of a Timer

Memory Area

Timers have an area reserved for them in the memory of your CPU. This memory area reserves one 16-bit word for each timer address. When you program in FBD, 256 timers are supported. Please refer to your CPU’s technical information to check the number of timer words available. The following functions access the timer memory area: Timer instructions Updating of timer words by the clock timing. In the RUN mode, this CPU function decrements a given time value by one unit at the interval specified by the time base until the time value is zero.

Time Value

Bits 0 through 9 of the timer word contain the time value in binary code. The time value specifies a number of units. When the timer is updated, the time value is decremented by one unit at intervals specified by the time base. The time value is decremented until it is equal to zero. You can load a predefined time value with the following syntax.

S5T#aH_bbM_ccS_dddMS – where: a = hours, bb = minutes, cc = seconds and ddd = milliseconds – The time base is selected automatically, and the value is rounded down to the next lower number with that time base. The maximum time value you can enter is 9,990 seconds, or 2H_46M_30S.

Time Base

Bits 12 and 13 of the timer word contain the time base in binary code. The time base defines the interval at which the time value is decremented by one unit (see Table 5-1 and Figure 5-1). The smallest time base is 10 ms; the largest is 10 s. Table 5-1

Time Base and Binary Code Time Base

5-2

Binary Code for the Time Base

10 ms

00

100 ms

01

1s

10

10 s

11


Timer Instructions

Because time values are saved at only one time interval, values that are not exact multiples of a time interval are truncated. Values with a resolution too high for the required range are rounded down to within the required range but not to the desired resolution. The following table shows the possible resolutions and the corresponding ranges. Table 5-2

Resolution and Ranges of the Time Base Resolution

Bit Configuration in the Timer Cell

Time Base

0.01 seconds

10MS to 9S_990MS

0.1 seconds

100MS to 1M_39S_900MS

1 second

1S to 16M_39S

10 seconds

10S to 2HR_46M_30S

When a timer is started, the contents of the timer cell are used as the time value. Bits 0 through 11 of the timer cell contain the time value in binary coded decimal format (BCD format: each group of four bits contains the binary code for one decimal value). Bits 12 and 13 contain the time base in binary code (see Table 5-2). Figure 5-1 shows the contents of the timer cell loaded with timer value 127 with a time base of 1 second.

15... x

...8 x

1

0

0

0

0 1

1

7... 0

...0 0

1

0

0

1

2

1

1

7

Time value in BCD (0 to 999) Time base 1 second Irrelevant: These bits are ignored when the timer is started. Figure 5-1

Reading the Time and the Time Base

Contents of the Timer Cell for Timer Value 127, Time Base 1 Second

Each timer box provides two outputs, BI and BCD, for which you can specify a word location. The BI output provides the time value in binary format, the time base is not displayed. The BCD output provides the time base and the time value in binary coded decimal (BCD) format.


5-3

Timer Instructions

5.2

Choosing the Right Timer The following figure provides an overview of the five types of timers described in this chapter. This overview is intended to help you choose the right timer for your timing job.

Input signal

I0.0

Output signal (Pulse timer)

Q4.0 S_PULSE t The maximum time that the output signal remains at 1 is the same as the programmed time value t. The output signal stays at 1 for a shorter period if the input signal changes to 0.

Output signal (Extended pulse timer)

Q4.0 S_PEXT

Output signal (On-delay timer)

Q4.0 S_ODT

t The output signal remains at 1 for the programmed length of time, regardless of how long the input signal stays at 1.

t The output signal changes to 1 only when the programmed time has elapsed and the input signal is still 1.

Output signal (Retentive on-delay timer)

Q4.0 S_ODTS

Output signal (Off-delay timer)

Q4.0 S_OFFDT

t The output signal changes from 0 to 1 only when the programmed time has elapsed, regardless of how long the input signal stays at 1.

t The output signal changes to 1 when the input signal changes to 1 or while the timer is running. The time is started when the input signal changes from 1 to 0.

Figure 5-2

5-4

Choosing the Right Timer


Timer Instructions

5.3

Pulse S5 Timer

Description

The Pulse S5 Timer instruction starts a specified timer if there is a rising edge (a change in signal state from 0 to 1) at the Start (S) input. A signal change is always necessary to start a timer. The timer continues to run for the time specified at the Time Value (TV) input until the programmed time elapses, as long as the signal state at input TV is 1. While the timer is running, a signal state check for 1 at output Q produces a result of 1. If there is a change from 1 to 0 at the S input before the time has elapsed, the timer is stopped. Then a signal state check for 1 at output Q produces a result of 0. While the timer is running, a change from 0 to 1 at the Reset (R) input of the timer resets the timer. This change also resets the time and the time base to zero. A signal state of 1 at the R input of the timer has no effect if the timer is not running. The current time value can be scanned at outputs BI and BCD. The time value at BI is in binary format; at BCD it is in binary coded decimal format.

Table 5-3

Pulse S5 Timer Box and Parameters with SIMATIC Mnemonics

FBD Box

Parameters

Data Type

Memory Area

Nr.

TIMER

T

Timer identification number. The range depends on the CPU.

S

BOOL

E, A, M, D, L, T, Z

Start input

TW

S5TIME


Preset time value (range 0 to 9999)

R

BOOL

E, A, M, D, L, T, Z

Reset input

DUAL

WORD

E, A, M, D, L

Time remaining (value in integer format)

DEZ

WORD

E, A, M, D, L

Time remaining (value in BCD format)

Q

BOOL

E, A, M, D, L

Status of the timer

T–Nr. T Nr. S IMPULS S_IMPULS S

DUAL

TW

DEZ

R

Q

Table 5-4

Pulse S5 Timer Box and Parameters with International Mnemonics

FBD Box

Parameters

Data Type

Memory Area

no.

TIMER

T


S

BOOL

I, Q, M, D, L, T, C

Start input

TV

S5TIME



R

BOOL

I, Q, M, D, L, T, C

Reset input

BI

WORD

I, Q, M, D, L


BCD

WORD

I, Q, M, D, L


Q

BOOL

I, Q, M, D, L

Status of the timer

T no. S PULSE S_PULSE S TV R

Description

BI BCD Q


Description

5-5

Timer Instructions

Example

Figure 5-3 illustrates the Pulse S5 Timer instruction, describes the status word bits, and shows the characteristics of the instruction.

If the signal state of input I0.0 changes from 0 to 1 (if there is a rising edge in the RLO), timer T5 is started. The timer continues to run with the specified time of two seconds (2s) as long as input I0.0 is 1. If the signal state of input I0.0 changes from 1 to 0 before the time elapses, the timer is stopped. If the signal state of input I0.1 changes from 0 to 1 while the timer is running, the timer is reset. The signal state of output Q4.0 is 1 as long as the timer is running.

T5 S_PULSE I0.0

S

S5T# 2s

TV

I0.1

R

BI BCD Q

Q4.0 =

Examples of other preset time values: Available units: h (hours), m (minutes), s (seconds), ms (milliseconds) S5T#4s ––> 4 seconds S5T#1h_15m ––> 1 hour and 15 minutes S5T#2h_46m_30s––>2 hours, 46 minutes, and 30 seconds

Status Word Bits

writes

BR –

CC1 –

CC0 –

OV –

OS –

OR x

STA x

RLO x

FC 1

Timing Diagram –– t ––

–– t ––

–– t ––

RLO at input S RLO at input R Timer running RLO at output Q Negated RLO at output Q

Figure 5-3

5-6

t = programmed time

Pulse S5 Timer


Timer Instructions

5.4


Description

The Extended Pulse S5 Timer instruction starts a specified timer if there is a rising edge (change in signal state from 0 to 1) at the Start (S) input. A signal change is always necessary to start a timer. The timer continues to run for the time specified at the Time Value (TV) input, even if the signal state at the S input changes to 0 before the time has elapsed. A signal state check for 1 at output Q produces a result of 1 as long as the timer is running. The timer is restarted with the specified time if the signal state at input S changes from 0 to 1 while the timer is running. A change from 0 to 1 at the Reset (R) input of the timer while the timer is running resets the timer. This change also resets the time and the time base to zero. The current time value can be scanned at the outputs BI and BCD. The time value at BI is in binary format; at BCD it is in binary coded decimal format.

Table 5-5

Extended Pulse S5 Timer Box and Parameters with SIMATIC Mnemonics

FBD Box

Parameters

Data Type

Memory Area

Nr.

TIMER

T


S

BOOL

E, A, M, D, L, T, Z

Start input

TW

S5TIME



R

BOOL

E, A, M, D, L, T, Z

Reset input

DUAL

WORD

E, A, M, D, L


DEZ

WORD

E, A, M, D, L


Q

BOOL

E, A, M, D, L

Status of the timer

T Nr. S_VIMP _ S

DUAL

TW

DEZ

R

Q

Table 5-6

Extended Pulse S5 Timer Box and Parameters with International Mnemonics

FBD Box T no. S_PEXT S TV R

Description

BI BCD Q

Parameters

Data Type

no.

TIMER

T


S

BOOL

I, Q, M, D, L, T, C

Start input

TV

S5TIME



R

BOOL

I, Q, M, D, L, T, C

Reset input

BI

WORD

I, Q, M, D, L


BCD

WORD

I, Q, M, D, L


Q

BOOL

I, Q, M, D, L

Status of the timer


Memory Area

Description

5-7

Timer Instructions

Example

Figure 5-4 illustrates the Extended Pulse S5 Timer instruction, describes the status word bits, and shows the characteristics of the instruction.

If the signal state of input I0.0 changes from 0 to 1 (rising edge in the RLO), timer T5 is started. The timer continues to run for the specified time of two seconds (2s) regardless of a falling edge at input S. If the signal state of input I0.0 changes from 0 to 1 before the time has elapsed, the timer is restarted. If the signal state of input I0.1 changes from 0 to 1 while the timer is running, the timer is reset. The signal state of output Q4.0 is 1 as long as the timer is running.

T5 S_PEXT I0.0

S

S5T# 2s

TV

I0.1

R

BI BCD Q

Q4.0 =

Status Word Bits

writes

BR –

CC1 –

CC0 –

OV –

OS –

OR x

STA x

RLO x

FC 1

Timing Diagram

–– t ––

–– t ––

–– t ––

–– t ––

RLO at input S RLO at input R Timer running RLO at output Q Negated RLO at output Q t = programmed time

Figure 5-4

5-8



Timer Instructions

5.5

On-Delay S5 Timer

Description

The On-Delay S5 Timer instruction starts a specified timer if there is a rising edge (change in signal state from 0 to 1) at the Start (S) input. A signal change is always necessary to start a timer. The timer continues to run for the time specified at the Time Value (TV) input as long as the signal state at input S is 1. A signal state check for 1 at output Q produces a result of 1 when the time has elapsed without error and when the signal state at input S is still 1. When the signal state at input S changes from 1 to 0 while the timer is running, the timer is stopped. In this case, a signal state check for 1 at output Q always produces the result 0. A change from 0 to 1 at the Reset (R) input of the timer while the timer is running resets the timer. This change also resets the time and the time base to zero. The timer is also reset if the signal state is 1 at the R input while the timer is not running. The current time value can be scanned at the outputs BI and BCD. The time value at BI is in binary format; at BCD it is in binary coded decimal format.

Table 5-7

On-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics

FBD Box

Parameters

Data Type

Memory Area

Nr.

TIMER

T


S

BOOL

E, A, M, D, L, T, Z

Start input

TW

S5TIME


Preset time value (range 0 – 9999)

R

BOOL

E, A, M, D, L, T, Z

Reset input

DUAL

WORD

E, A, M, D, L


DEZ

WORD

E, A, M, D, L


Q

BOOL

E, A, M, D, L

Status of the timer

T–Nr. S_EVERZ DUAL

S TW

DEZ Q

R

Table 5-8

On-Delay S5 Timer Box and Parameters with International Mnemonics

FBD Box

Parameters

Data Type

Memory Area

no.

TIMER

T


S

BOOL

I, Q, M, D, L, T, C

Start input

TV

S5TIME



R

BOOL

I, Q, M, D, L, T, C

Reset input

BI

WORD

I, Q, M, D, L


BCD

WORD

I, Q, M, D, L


Q

BOOL

I, Q, M, D, L

Status of the timer

T no. S_ODT S TV R

Description

BI BCD Q


Description

5-9

Timer Instructions

Example

Figure 5-5 illustrates the On-Delay S5 Timer instruction, describes the bits in the status word and shows the characteristics of the instruction.

If the signal state of input I0.0 changes from 0 to 1 (rising edge in the RLO), timer T5 is started. If the specified time of two seconds (2s) elapses and the signal state of input I0.0 is still 1, the signal state of output Q4.0 is 1. If the signal state of input I0.0 changes from 1 to 0, the timer is stopped and output Q4.0 is 0. If the signal state of input I0.1 changes from 0 to 1 while the timer is running, the timer is restarted.

T5 S_ODT I0.0

S

S5T# 2s

TV

I0.1

R

BI BCD Q

Q4.0 =

Status Word Bits

writes

BR –

CC1 –

CC0 –

OV –

OS –

OR x

STA x

RLO x

FC 1


–– t ––

–– t ––

RLO at input S RLO at input R Timer running RLO at output Q Negated RLO at output Q t = programmed time Figure 5-5

5-10

On-Delay S5 Timer


Timer Instructions

5.6


Description

The Retentive On-Delay S5 Timer instruction starts a specified timer if there is a rising edge (change in signal state from 0 to 1) at the Start (S) input. A signal change is always necessary to start a timer. The timer continues to run for the time specified at the Time Value (TV) input, even if the signal state at input S changes to 0 before the timer has expired. A signal state check for 1 at output Q produces a result of 1 when the time has elapsed, regardless of the signal state at input S when the reset input (R) remains at 0. The timer is restarted with the specified time if the signal state at input S changes from 0 to 1 while the timer is running. A change from 0 to 1 at the Reset (R) input of the timer resets the timer regardless of the RLO at the S input. The current time value can be scanned at the outputs BI and BCD. The time value at BI is in binary format; at BCD it is in binary coded decimal format.

Table 5-9

Retentive On-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics

FBD Box T–Nr. S SEVERZ S_SEVERZ S

DUAL

TW

DEZ Q

R

Table 5-10

T no. S ODTS S_ODTS

TV R

Data Type

Memory Area

Description

Nr.

TIMER

T


S

BOOL

E, A, M, D, L, T, Z

Start input

TW

S5TIME



R

BOOL

E, A, M, D, L, T, Z

Reset input

DUAL

WORD

E, A, M, D, L


DEZ

WORD

E, A, M, D, L


Q

BOOL

E, A, M, D, L

Status of the timer

Retentive On-Delay S5 Timer Box and Parameters with International Mnemonics

FBD Box

S

Parameters

BI BCD Q

Parameters

Data Type

no.

TIMER

T


S

BOOL

I, Q, M, D, L, T, C

Start input

TV

S5TIME



R

BOOL

I, Q, M, D, L, T, C

Reset input

BI

WORD

I, Q, M, D, L


BCD

WORD

I, Q, M, D, L


Q

BOOL

I, Q, M, D, L

Status of the timer


Memory Area

Description

5-11

Timer Instructions

Example

Figure 5-6 illustrates the Retentive On-Delay S5 Timer instruction, describes the status word bits, and shows the characteristics of the instruction.

If the signal state of input I0.0 changes from 0 to 1 (rising edge in the RLO), timer T5 is started. The timer continues to run regardless of a signal change at input I0.0 from1 to 0. If the signal state of input I0.0 changes from 0 to 1 before the time has elapsed, the timer is restarted. If the signal state of input I0.1 changes from 0 to 1 while the timer is running, the timer is restarted. The signal state of output Q4.0 is 1 if the time has elapsed and the signal state at I 0.1 remains 0.

T5 S_ODTS BI

I0.0

S

S5T# 2s

TV

I0.1

R

BCD Q

Q4.0 =

Status Word Bits

writes

BR –

CC1 –

CC0 –

OV –

OS –

OR x

STA x

RLO x

FC 1

Timing Diagram

–– t ––

–– t ––

–– t ––

–t–


5-12



Timer Instructions

5.7

Off-Delay S5 Timer

Description

The Off-Delay S5 Timer instruction starts a specified timer if there is a falling edge (change in signal state from 1 to 0) at the Start (S) input. A signal change is always necessary to start a timer. The result of a signal state check for 1 at output Q is 1 when the signal state at the S input is 1 or when the timer is running. The timer is reset when the signal state at input S changes from 0 to 1 while the timer is running. The timer is not restarted until the signal state at input S changes again from 1 to 0. A change from 0 to 1 at the Reset (R) input of the timer while the timer is running resets the timer. The actual time value can be scanned at the outputs BI and BCD. The time value at BI is in binary format; at BCD it is in binary coded decimal format.

Table 5-11

Off-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics

FBD Box

Parameters

Data Type

Memory Area

Nr.

TIMER

T


S

BOOL

E, A, M, D, L, T, Z

Start input

TW

S5TIME



R

BOOL

E, A, M, D, L, T, Z

Reset input

DUAL

WORD

E, A, M, D, L


DEZ

WORD

E, A, M, D, L


Q

BOOL

E, A, M, D, L

Status of the timer

T–Nr. S_AVERZ DUAL

S TW

DEZ Q

R

Table 5-12

Off-Delay S5 Timer Box and Parameters with International Mnemonics

FBD Box

Parameters

Data Type

Memory Area

no.

TIMER

T


S

BOOL

I, Q, M, D, L, T, C

Start input

TV

S5TIME



R

BOOL

I, Q, M, D, L, T, C

Reset input

BI

WORD

I, Q, M, D, L


BCD

WORD

I, Q, M, D, L


Q

BOOL

I, Q, M, D, L

Status of the timer

T no. S_OFFDT S TV R

Description

BI BCD Q


Description

5-13

Timer Instructions

Example

Figure 5-7 illustrates the Off-Delay S5 Timer instruction, describes the status word bits, and shows the characteristics of the instruction.

T5 S_OFFDT I0.0

S

S5T# 2s

TV

I0.1

R

If the signal state at input I0.0 changes from 1 to 0, the timer is started. Output Q4.0 is 1 when I0.0 is 1 or the timer is running. If the signal state at I0.1 changes from 0 to 1, while the timer is running, the timer is reset.

BI BCD Q

Q4.0 =

Status Word Bits

writes

BR –

CC1 –

CC0 –

OV –

OS –

OR x

STA x

RLO x

FC 1


–– t ––

–– t ––

–– t ––


5-14

Off-Delay S5 Timer


6

Counter Instructions Chapter Overview

Section

Description

Page

6.1

Memory Address and Components of a Counter

6-2

6.2

Up-Down Counter

6-3

6.3

Up Counter

6-5

6.4

Down Counter

6-7


6-1


6.1

Memory Address and Components of a Counter

Memory Area

Counters have an area reserved for them in the memory of your CPU. This memory area reserves one 16-bit word for each counter address. When you program in FBD, 256 counters are supported. The counter instructions are the only functions that can access the counter memory area.

Count Value

Bits 0 through 9 of the counter word contain the count value in binary code. The count value is taken from the accumulator and entered in the counter word when a counter is set. The range of the count value is 0 to 999. You can increment/decrement the count value within this range using the Up-Down Counter, Up Counter, and Down Counter instructions.

Bit Configuration in the Counter

A counter is set to a required value by loading a number between 0 and 999 as the count value, for example 127, in the following format: C# 127 The C# stands for binary coded decimal format (BCD format: each group of four bits contains the binary code for one decimal value). Bits 0 through 11 of the counter contain the count value in binary coded decimal format . Figure 6-1 shows the contents of the counter after you have loaded the count value 127 and the contents of the counter cell after the counter has been set. 15 14 13 12

11 10 9

8

7

6

5

4

3

2

1

0

0

1

0

0

1

0

0

1

1

1

0

0 1

irrelevant

2

7

Count value in BCD (0 to 999) 15 14 13 12

11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

1

1

1

1

1

1

1

irrelevant

Figure 6-1

6-2

Binary count value

Contents of the Counter Cell after the Counter has been Set with Count Value 127



6.2

Up-Down Counter

Description

A rising edge (change in signal state from 0 to 1) at input S of the Up-Down Counter instruction sets the counter with the value at the Preset Value (PV) input. The counter is incremented by 1 if the signal state at input CU changes from 0 to 1 (rising edge) and the value of the counter is less than 999. The counter is decremented by 1 if the signal state at input CD changes from 0 to 1 (rising edge) and the value of the counter is higher than 0. If there is a rising edge at both count inputs, both operations are executed and the count remains the same. The counter is reset if there is a rising edge at input R. Resetting the counter sets the count value to 0. A signal state check for 1 at output Q produces a result of 1 when the count is greater than 0; the check produces a result of 0 when the count is equal to 0.

Table 6-1

Up-Down Counter Box and Parameters with SIMATIC Mnemonics

FBD Box

Parameters

Data Type

Memory Area

Description

Nr.

COUNTER

Z

Counter identification number. The range depends on the CPU.

ZV

BOOL

E, A, M, D, L

ZV input: Up Counter

ZV

ZR

BOOL

E, A, M, D, L

ZR input: Down Counter

ZR

S

BOOL

E, A, M, D, L, T, Z Input for presetting the counter

ZW

WORD

E, A, M, D, L

Z-Nr Z-Nr. ZAEHLER

S ZW R

DUAL DEZ Q

or constant

Count value in the range between 0 and 999 or Count value entered as C# in BCD format

R

BOOL

E, A, M, D, L, T, Z Reset input

DUAL

WORD

E, A, M, D, L

Current count value (integer format)

DEZ

WORD

E, A, M, D, L

Current count value (BCD format)

Q

BOOL

E, A, M, D, L

Status of the counter


6-3


Table 6-2

Up-Down Counter Box and Parameters with International Mnemonics Parameters

FBD Box

Data Type

Memory Area

Description

no.

COUNTER

C


CU

BOOL

I, Q, M, D, L

CU input: Up Counter

CD

BOOL

I, Q, M, D, L

CD input: Down Counter

CU

S

BOOL

I, Q, M, D, L, C

Input for presetting the counter

CD

PV

WORD

I, Q, M, D, L or

Count value in the range between 0 and 999

constant

or

C no. S CUD S_CUD

CV S PV CV_BCD R Q

Count value entered as C# in BCD format R

BOOL

I, Q, M, D, L, C

Reset input

CV

WORD

I, Q, M, D, L


CV_BCD

WORD

I, Q, M, D, L


Q

BOOL

I, Q, M, D, L


C10 S_CUD I0.0

CU

I0.1

CD

I0.2

S

C#55

PV CV_BCD

I0.3

R

A change in signal state from 0 to 1 at input I0.2 sets counter C10 with the value 55. If the signal state of input I0.0 changes from 0 to 1, the value of counter C10 is incremented by 1, except when the value of counter C10 is already 999. If input I0.1 changes from 0 to 1, counter C10 is decremented by 1, except when the value of counter C10 is already 0. If I0.3 changes from 0 to 1, the value of C10 is set to 0. Q4.0 is 1, when C 10 is not equal to 0.

CV

Q4.0 =

Q

Status Word Bits

writes

Figure 6-2

6-4

BR –

CC1 –

CC0 –

OV –

OS –

OR x

STA x

RLO x

FC 1

Up-Down Counter



6.3

Up Counter

Description

A rising edge (change in signal state from 0 to 1) at input S of the Up Counter instruction sets the counter with the value at the Preset Value (PV) input. With a rising edge at input CU, the count value is incremented by 1 when the count value is less than 999. The counter is reset by a rising edge at input R. Resetting the counter sets the count value to 0. A signal state check for 1 at output Q produces a result of 1 when the count is greater than 0. The check produces a result of 0 when the count is equal to 0.

Table 6-3

Up Counter Box and Parameters with SIMATIC Mnemonics Parameter

FBD Box

Z-Nr. Z Nr Z VORW Z_VORW ZV

ZW

Q

Table 6-4

Z


ZV

BOOL

E, A, M, D, L

ZV input: Up Counter

S

BOOL


ZW

WORD

E, A, M, D, L


or

or

constant

Count value entered as C# in BCD format

R

BOOL


DUAL

WORD

E, A, M, D, L


DEZ

WORD

E, A, M, D, L


Q

BOOL

E, A, M, D, L


Up Counter Box and Parameters with International Mnemonics Parameters

FBD Box C no. S_CU S CU CU CV

Data Type

Memory Area

Description

no.

COUNTER

C


CU

BOOL

I, Q, M, D, L

CU input: Up Counter

S

BOOL

I, Q, M, D, L, T, C Input for presetting the counter

PV

WORD

I, Q, M, D, L


or

or

constant


PV CV_BCD R

Description

COUNTER

DEZ

R

Memory Area

Nr.

DUAL

S

S

Data Type

Q R

BOOL

I, Q, M, D, L, T, C Reset input

CV

WORD

I, Q, M, D, L


CV_BCD

WORD

I, Q, M, D, L


Q

BOOL

I, Q, M, D, L



6-5


C10 S_CU I0.0

CU

I0.2

S

C#901

PV CV_BCD

I0.3

R

A change in signal state from 0 to 1 at input I0.2 sets counter C10 with the value 901. If the signal state of I0.0 changes from 0 to 1, the value of counter C10 is incremented by 1, unless the value of C10 is equal to 999. If I0.3 changes from 0 to 1, the value of C 10 is set to 0. The signal state of output Q 4.0 is 1 if C10 is not equal to 0.

CV

Q

Q4.0 =

Status Word Bits

writes

Figure 6-3

6-6

BR –

CC1 –

CC0 –

OV –

OS –

OR x

STA x

RLO x

FC 1

Up Counter



6.4

Down Counter

Description

A rising edge (change in signal state from 0 to 1) at input S of the Down Counter instruction sets the counter with the value at the Preset Value input (PV). With a rising edge at input CD, the counter is decremented by 1 when the count value is greater than 0. The counter is reset by rising edge at input R. A signal state check for 1 at output Q produces a result of 1 when the count is greater than 0; the check produces a result of 0 when the count is equal to 0.

Table 6-5

Down Counter Box and Parameters with SIMATIC Mnemonics Parameter

FBD Box Z-Nr. Z RUECK Z_RUECK ZR DUAL

S ZW

Z


ZR

BOOL

E, A, M, D, L

ZR input: Down Counter

S

BOOL


ZW

WORD

E, A, M, D, L


or

or

constant


R

BOOL


DUAL

WORD

E, A, M, D, L


DEZ

WORD

E, A, M, D, L


Q

BOOL

E, A, M, D, L


Down Counter Box and Parameters with International Mnemonics Parameter

FBD Box C no. S_CD S CD CD CV

Data Type

Memory Area

Description

no.

COUNTER

C


CD

BOOL

I, Q, M, D, L

CD input: Down Counter

S

BOOL

I, Q, M, D, L, T, C Input for presetting the counter

PV

WORD

I, Q, M, D, L


or

or

constant


PV CV_BCD R

Description

COUNTER

Q

Table 6-6

Memory Area

Nr.

DEZ

R

S

Data Type

Q R

BOOL

I, Q, M, D, L, T, C Reset input

CV

WORD

I, Q, M, D, L


CV_BCD

WORD

I, Q, M, D, L


Q

BOOL

I, Q, M, D, L



6-7


Z10 S_CD I0.0

CD

I0.2

S

C#901

PV

I0.3

R

A change in signal state from 0 to 1 at input I0.2 sets counter C10 with the value 89. If the signal state of input I0.0 changes from 0 to 1, the value of counter C10 is decreased by 1, unless the value of counter C 10 is equal to 0. The signal state of output Q 4.0 is 1 if counter C10 is not equal to 0. If I0.3 changes from 0 to 1, the value of C 10 is set to 0.

CV BCD Q

Q4.0 =

Status Word Bits

writes

Figure 6-4

6-8

BR –

CC1 –

CC0 –

OV –

OS –

OR x

STA x

RLO x

FC 1

Down Counter


7

Integer Math Instructions Chapter Overview

Section

Description

Page

7.1

Add Integer

7-2

7.2

Add Double Integer

7-3

7.3

Subtract Integer

7-4

7.4

Subtract Double Integer

7-5

7.5

Multiply Integer

7-6

7.6

Multiply Double Integer

7-7

7.7

Divide Integer

7-8

7.8

Divide Double Integer

7-9

7.9

Return Fraction Double Integer

7-10

7.10

Evaluating the Bits of the Status Word with Integer Math Instructions

7-11


7-1


7.1

Add Integer

Description

Table 7-1

A signal state of 1 at the Enable (EN) input activates the Add Integer instruction. This instruction adds inputs IN1 and IN2. The result can be scanned at O. If the result is outside the permissible range for an integer, the OV and OS bit of the status word are 1 and the ENO is 0. Add Integer Box and Parameters Parameters

FBD Box

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

ADD_II ADD EN

IN1

INT


First value for addition

IN1

OUT

IN2

INT

Second value for addition

IN2

ENO


OUT

INT

I, Q, M, D, L

Result of addition

ENO

BOOL

I, Q, M, D, L

Enable output

I 0.0

ADD_I EN

MW0

IN1

OUT

MW2

IN2

ENO

A signal state of 1 at input I 0.0 activates the ADD_I box. The result of the addition MW0 + MW2 is entered in memory word MW10. If the result is outside the permitted range for an integer or the signal state of input I 0.0 is 0, output Q 4.0 is set to 0 and the instruction is not executed.

MW10 Q 4.0 =

Status Word Bits Instruction is executed (EN = 1): BR CC1 CC0 writes x x x

Figure 7-1

7-2

OV x

OS x

OR 0

STA x

RLO x

FC 1

Add Integer



7.2

Add Double Integer

Description

Table 7-2

A signal state of 1 at the Enable (EN) input activates the Add Double Integer instruction. This instruction adds inputs IN1 and IN2. The result can be scanned at O. If the result is outside the permissible range for a double integer, the OV and the OS bit of the status word are 1 and the ENO is 0. Add Double Integer Box and Parameters Parameters

FBD Box

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

ADD_DI ADD DI EN

IN1

DINT


First value for addition

IN1

OUT

IN2

DINT

Second value for addition

IN2

ENO


OUT

DINT

I, Q, M, D, L

Result of addition

ENO

BOOL

I, Q, M, D, L

Enable output

ADD_DI EN

I 0.0 MD0

IN1

OUT

MD4

IN2

ENO

MD10 Q 4.0 =

A signal state of 1 at input I 0.0 activates the ADD_DI box. The result of the addition MD0 + MD4 is entered in memory double word MD10. If the result is outside the permitted range for a double integer or the signal state of input I 0.0 is 0, output Q 4.0 is set to 0 and the instruction is not executed.

Status Word Bits Instruction is executed (EN = 1): writes

Figure 7-2

BR x

CC1 x

CC0 x

OV x

OS x

OR 0

STA x

RLO x

FC 1

Add Double Integer


7-3


7.3

Subtract Integer

Description

Table 7-3

A signal state of 1 at the Enable (EN) input activates the Subtract Integer instruction. This instruction subtracts input IN2 from IN1. The result can be scanned at O. If the result is outside the permitted range for an integer, the OV and the OS bit of the status word are 1 and the ENO is 0. Subtract Integer Box and Parameters

FBD Box

Parameters

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

SUB_II SUB EN

IN1

INT


Minuend (value from which second value is subtracted)

IN1

OUT

IN2

INT

IN2

ENO


Subtrahend (value subtracted from the first value)

OUT

INT

I, Q, M, D, L

Result of subtraction

ENO

BOOL

I, Q, M, D, L

Enable output

I 0.0

SUB_I EN

MW0

IN1

OUT

MW2

IN2

ENO

MW10 Q 4.0 =

A signal state of 1 at input I 0.0 activates the SUB_I box. The result of the subtraction MW0 – MW2 is entered in memory word MW10. If the result is outside the permitted range for an integer or the signal state of input I 0.0 is 0, output Q 4.0 is set to 0 and the instruction is not executed.


Figure 7-3

7-4

OV x

OS x

OR 0

STA x

RLO x

FC 1

Subtract Integer



7.4


Description

Table 7-4

A signal state of 1 at the Enable (EN) input activates the Subtract Double Integer instruction. This instruction subtracts input IN2 from IN1. The result can be scanned at O. If the result is outside the permitted range for a double integer, the OV and the OS bit of the status word are 1 and the ENO is 0. Subtract Double Integer Box and Parameters Parameters

FBD Box

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

SUB_DI SUB DI EN

IN1

DINT


Minuend (value from which second value is subtracted)

IN1

OUT

IN2

DINT

IN2

ENO


Subtrahend (value subtracted from the first value)

OUT

DINT

I, Q, M, D, L


ENO

BOOL

I, Q, M, D, L

Enable output

I 0.0

SUB_DI EN

MD0

IN1

OUT

MD4

IN2

ENO

MD10 Q 4.0 =

A signal state of 1 at input I 0.0 activates the SUB_DI box. The result of the subtraction MD0 – MD4 is entered in memory double word MD10. If the result is outside the permitted range for a double integer or the signal state of input I 0.0 is 0, output Q 4.0 is set to 0 and the instruction is not executed.


Figure 7-4

BR x

CC1 x

CC0 x

OV x

OS x

OR 0

STA x

RLO x

FC 1



7-5


7.5

Multiply Integer

Description

Table 7-5

A signal state of 1 at the Enable (EN) input activates the Multiply Integer instruction. This instruction multiplies input IN1 by IN2. The result is a 32-bit integer that can be scanned at O. If the result is outside the permitted range for a 16-bit integer, the OV and the OS bit of the status word are 1 and the ENO is 0. Multiply Integer Box and Parameters Parameters

FBD Box

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

MUL_II MUL EN

IN1

INT


Multiplicand (value that is multiplied by the second value)

IN1

OUT

IN2

INT

IN2

ENO


Multiplier (value by which the first value is multiplied)

OUT

DINT

I, Q, M, D, L

Result of the multiplication

ENO

BOOL

I, Q, M, D, L

Enable output

I 0.0

MUL_I EN

MW0

IN1

OUT

MW2

IN2

ENO

MD10 Q 4.0 =

A signal state of 1 at input I 0.0 activates the MUL_I box. The result of the multiplication MW0 x MW2 is entered in memory double word MD10. If the result is outside the permitted range for a 16-bit integer or the signal state of input I 0.0 is 0, output Q 4.0 is set to 0 and the instruction is not executed.


Figure 7-5

7-6

BR x

CC1 x

CC0 x

OV x

OS x

OR 0

STA x

RLO x

FC 1

Multiply Integer



7.6


Description

Table 7-6

A signal state of 1 at the Enable (EN) input activates the Multiply Double Integer instruction. This instruction multiplies inputs IN1 and IN2. The result can be scanned at O. If the result is outside the permitted range for a double integer, the OV and the OS bit of the status word are 1 and the ENO is 0. Multiply Double Integer Box and Parameters Parameters

FBD Box

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

MUL_DI MUL DI EN

IN1

DINT


Multiplicand (value that is multiplied by the second value)

IN1

OUT

IN2

DINT

IN2

ENO


Multiplier (value by which the first value is multiplied)

OUT

DINT

I, Q, M, D, L

Result of the multiplication

ENO

BOOL

I, Q, M, D, L

Enable output

I 0.0

MUL_DI EN

MD0

IN1

OUT

MD4

IN2

ENO

MD10 Q 4.0 =

A signal state of 1 at input I 0.0 activates the MUL_DI box. The result of the multiplication MD0 x MD4 is entered in memory double word MD10. If the result is outside the permitted range for a double integer or the signal state of input I 0.0 is 0, output Q 4.0 is set to 0 and the instruction is not executed.


Figure 7-6

BR x

CC1 x

CC0 x

OV x

OS x

OR 0

STA x

RLO x

FC 1



7-7


7.7

Divide Integer

Description

Table 7-7

A signal state of 1 at the Enable (EN) input activates the Divide Integer instruction. This instruction divides input IN1 by IN2. The integer quotient (truncated result) can be scanned at O. The remainder cannot be scanned. If the quotient is outside the permitted range for an integer, the OV and the OS bit of the status word are 1 and the ENO is 0. Divide Integer Box and Parameters

FBD Box

Parameters

DIV I DIV_I

Data Type

OUT

IN2

ENO

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN1

INT


Dividend

IN2

INT


Divisor

OUT

INT

I, Q, M, D, L

Result of division

ENO

BOOL

I, Q, M, D, L

Enable output

EN IN1

Memory Area

I 0.0

DIV_I EN

MW0

IN1

OUT

MW2

IN2

ENO

MW10 Q 4.0 =

A signal state of 1 at input I 0.0 activates the DIV_I box. The quotient of dividing MW0 by MW2 is entered in memory word MW10. If the quotient is outside the permitted range for an integer or the signal state of input I 0.0 is 0, output Q 4.0 is set to 0 and the instruction is not executed.


Figure 7-7

7-8

OV x

OS x

OR 0

STA x

RLO x

FC 1

Divide Integer



7.8


Description

Table 7-8

A signal state of 1 at the Enable (EN) input activates the Divide Double Integer instruction. This instruction divides input IN1 by IN2. The quotient (truncated result) can be scanned at O. The Divide Double Integer instruction stores the quotient as a single 32-bit value in DINT format. This instruction does not produce a remainder. If the quotient is outside the permitted range for a double integer, the OV and the OS bit of the status word are 1 and the ENO is 0. Divide Double Integer Box and Parameters Parameters

FBD Box

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

DIV_DI DIV DI EN

IN1

DINT


Dividend

IN1

OUT

IN2

DINT

ENO


Divisor

IN2

OUT

DINT

I, Q, M, D, L

Result of division

ENO

BOOL

I, Q, M, D, L

Enable output

I 0.0

DIV_DI EN

MD0

IN1

OUT

MD4

IN2

ENO

MD10 Q 4.0 =

A signal state of 1 at input I 0.0 activates the DIV_DI box. The quotient of dividing MD0 by MD4 is entered in memory double word MD10. If the quotient is outside the permitted range for a double integer or the signal state of input I 0.0 is 0, output Q 4.0 is set to 0 and the instruction is not executed.


Figure 7-8

BR x

CC1 x

CC0 x

OV x

OS x

OR 0

STA x

RLO x

FC 1



7-9


7.9


Description

Table 7-9

A signal state of 1 at the Enable (EN) input activates the Return Fraction Double Integer instruction. This instruction divides input IN1 by IN2. The remainder (fraction) can be scanned at O. If the result is outside the permitted range for a double integer, the OV and the OS bit of the status word are 1 and the ENO is 0. Return Fraction Double Integer Box and Parameters

FBD Box

Parameters

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

MOD EN

IN1

DINT


Dividend

IN1

OUT

IN2

DINT

ENO


Divisor

IN2

OUT

DINT

I, Q, M, D, L

Remainder

ENO

BOOL

I, Q, M, D, L

Enable output

I 0.0

MOD EN

MD0

IN1

OUT

MD4

IN2

ENO

MD10 Q 4.0 =

A signal state of 1 at input I 0.0 activates the MOD box. The remainder (fraction) of dividing MD0 by MD4 is stored in memory double word MD10. If the result is outside the permitted range for a double integer or the signal state of input I 0.0 is 0, output Q 4.0 is set to 0 and the instruction is not executed.


Figure 7-9

7-10

BR x

CC1 x

CC0 x

OV x

OS x

OR 0

STA x

RLO x

FC 1




7.10 Evaluating the Bits of the Status Word with Integer Math Instructions

Description

The integer math instructions influence the following bits in the status word:

CC1 and CC0 OV OS A dash (-) in the table means that the bit is not affected by the result of the instruction. Table 7-10

Signal State of the Status Word Bits (Result in Valid Range) Status Word Bits

Valid Range of the Result Integers (16 and 32 bits)

CC1

CC0

OV

OS

0 (zero)

0

0

0

-

16 bits: -32 768 result 0 (negative number) 32 bits: -2 147 483 648 result 0 (negative number)

0

1

0

-

16 bits: 32 767 result 0 (positive number) 32 bits: 2 147 483 647 result 0 (positive number)

1

0

0

-

Table 7-11

Signal State of the Status Word Bits (Result not in Valid Range) Invalid Range for the Result

Status Word Bits

Integers (16 and 32 bits)

CC1

CC0

OV

OS

32 767 (positive number) 2 147 483 647 (positive number)

1

0

1

1

16 bits: result -32 768 (negative number) 32 bits: result -2 147 483 648 (negative number)

0

1

1

1

16 bits: result 32 bits: result

Table 7-12

Signal State of the Status Word Bits (Math Instructions with Integers (32 Bits) +D, /D and MOD) Operation

Status Word Bits CC1

CC0

OV

OS

+D: result = -4 294 967 296

0

0

1

1

/D or MOD: division by 0

1

1

1

1


7-11


7-12


Floating-Point Math Instructions Chapter Overview

Section

Description

8 Page

8.1

Overview

8-2

8.2

Add Real

8-3

8.3

Subtract Real

8-4

8.4

Multiply Real

8-5

8.5

Divide Real

8-6

8.6

Evaluating the Bits of the Status Word with Floating-Point Instructions

8-7

8.7

Forming the Absolute Value of a Floating-Point Number

8-8

8.8

Forming the Square (SQR) of a Floating-Point Number

8-9

8.9

Forming the Square Root (SQRT) of a Floating-Point Number

8.10

Forming the Natural Logarithm of a Floating-Point Number

8-11

8.11

Forming the Exponential Value of a Floating-Point Number

8-12

8.12

Forming Trigonometric Functions of Angles as Floating-Point Numbers

8-13


8-10

8-1


8.1

Overview You can use the floating-point math instructions to perform the following math operations using two 32-bit IEEE floating-point numbers:

Add Subtract Multiply Divide The IEEE 32-bit floating-point numbers belong to the data type known as REAL. Using floating-point math, you can carry out the following operations with one 32-bit IEEE floating-point number:

Form the absolute value (ABS) of a floating-point number Form the square (SQR) or square root (SQRT) of a floating-point number Form the natural logarithm (LN) of a floating-point number Form the exponential value of a floating-point number (EXP) to base e (= 2.71828...)

Form the following trigonometric functions of an angle, represented as a 32-bit floating-point number: – Form the sine of a floating-point number (SIN) and form the arc sine of a floating-point number (ASIN) – Form the cosine of a floating-point number (COS) and form the arc cosine of a floating-point number (ACOS) – Form the tangent of a floating-point number (TAN) and form the arc tangent of a floating-point number (ATAN)

8-2



8.2

Add Real

Description

A signal state of 1 at the Enable input (EN) activates the Add Real instruction. This instruction adds inputs IN1 and IN2. The result can be scanned at output OUT. If either of the inputs or the result is not a floating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0. For more detailed information about evaluating the bits in the status word, refer to Section 8.6.

Table 8-1

Add Real Box and Parameters

FBD Box

Parameters

ADD_R ADD R EN IN1

OUT

IN2

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN1

REAL


First number to be added

IN2

REAL

I, Q, M, D,or constant L

Second number to be added

OUT

REAL

I, Q, M, D, L

Result of addition

ENO

BOOL

I, Q, M, D, L

Enable output

I0.0

ADD_R EN

MD0

IN1

OUT

MD4

IN2

ENO

A signal state of 1 at input I0.0 activates the ADD_R box. The result of the addition MD0 + MD4 is entered in memory double word MD10. If either of the inputs or the result is not a floating-point number and if the signal state of I0.0 is 0, output Q4.0 is set to 0 and the instruction is not executed.

MD10 Q4.0 =


Figure 8-1

OV x

OS x

OR 0

STA x

RLO x

FC 1

Add Real


8-3


8.3

Subtract Real

Description

A signal state of 1 at the Enable input (EN) activates the Subtract Real instruction. This instruction subtracts input IN2 from IN1. The result can be scanned at output OUT. If either of the inputs or the result is not a floating-point number, the OV bit and the OS bit are set to 1 and ENO is set to 0. For more detailed information about evaluating the bits in the status word, refer to Section 8.6.

Table 8-2

Subtract Real Box and Parameters Parameters

FBD Box SUB_R SUB R EN IN1

OUT

IN2

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN1

REAL


Minuend (from which the second value is subtracted)

IN2

REAL


Subtrahend (that is subtracted from the first value)

OUT

REAL

I, Q, M, D, L


ENO

BOOL

I, Q, M, D, L

Enable output

I0.0

SUB_R EN

MD0

IN1

OUT

MD4

IN2

ENO

A signal state of 1 at input I0.0 activates the SUB_R box. The result of the subtraction MD0 – MD4 is entered in memory double word MD10. If either of the inputs or the result is not a floating-point number and if the signal state of I0.0 is 0, output Q4.0 is set to 0 and the instruction is not executed.

MD10 Q4.0 =

Status Word Bits Instruction is executed (EN = 1): BR CC1 CC0 writes x x x Figure 8-2

8-4

OV x

OS x

OR 0

STA x

RLO x

FC 1

Subtract Real



8.4

Multiply Real

Description

A signal state of 1 at the Enable input (EN) activates the Multiply Real instruction. This instruction multiplies input IN1 by IN2. The result can be scanned at output OUT. If either of the inputs or the result is not a floating-point number, the OV bit and the OS bit are set to 1 and ENO is set to 0. For more detailed information about evaluating the bits in the status word, refer to Section 8.6.

Table 8-3

Multiply Real Box and Parameters Parameters

FBD Box MUL_R MUL R EN IN1

OUT

IN2

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN1

REAL


Multiplicand (value to be multiplied)

IN2

REAL


Multiplier (value by which first value is multiplied)

OUT

REAL

I, Q, M, D, L

Result of multiplication

ENO

BOOL

I, Q, M, D, L

Enable output

I0.0

MUL_R EN

MD0

IN1

OUT

MD4

IN2

ENO

A signal state of 1 at input I0.0 activates the MUL_R box. The result of the multiplication MD0 x MD4 is entered in memory double word MD10. If either of the inputs or the result is not a floating-point number and if the signal state of I0.0 is 0, output Q4.0 is set to 0 and the instruction is not executed.

MD10 Q4.0 =


Figure 8-3

OV x

OS x

OR 0

STA x

RLO x

FC 1

Multiply Real


8-5


8.5

Divide Real

Description

A signal state of 1 at the Enable input (EN) activates the Divide Real instruction. This instruction divides input IN1 by IN2. The result can be scanned at output OUT. If either of the inputs or the result is not a floating-point number, the OV bit and the OS bit are set to 1 and ENO is set to 0. For more detailed information about evaluating the bits in the status word, refer to Section 8.6.

Table 8-4

Divide Real Box and Parameters

FBD Box

Parameters

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

DIV_R DIV R EN

IN1

REAL


Dividend (value to be divided by second value)

IN1

OUT

IN2

REAL

IN2

ENO


Divisor (value by which first value is divided)

OUT

REAL

I, Q, M, D, L

Result of division

ENO

BOOL

I, Q, M, D, L

Enable output

I0.0

DIV_R EN

MD0

IN1

OUT

MD4

IN2

ENO

A signal state of 1 at input I0.0 activates the DIV_R box. The result of dividing MD0 by MD4 is entered in memory double word MD10. If either of the inputs or the result is not a floating-point number and if the signal state of I0.0 is 0, output Q4.0 is set to 0 and the instruction is not executed.

MD10 Q4.0 = Status Word Bits

Instruction is executed (EN = 1): writes

Figure 8-4

8-6

BR x

CC1 x

CC0 x

OV x

OS x

OR 0

STA x

RLO x

FC 1

Divide Real



8.6

Evaluating the Bits of the Status Word with Floating-Point Instructions

Description

Floating-point instructions affect the following bits in the status word:

CC1 and CC0 OV OS A dash (–) in the table means that the bit is not affected by the result of the instruction. Table 8-5

Signal State of the Status Word Bits for Results of Instructions with Floating-Point Numbers (Result in the Valid Range) Valid Range for Result

Instruction with Floating-Point Numbers (32 Bits)


CC0

OV

OS

+0, –0 (zero)

0

0

0

–

–3.402823E+38 < result < –1.175494E–38 (negative number)

0

1

0

–

+1.175494E–38 < result < 3.402823E+38 (positive number)

1

0

0

–

Table 8-6

Signal State of the Status Word Bits for Results of Instructions with Floating-Point Numbers (Result outside the Valid Range) Invalid Range for Result

Instruction with Floating-Point Numbers (32 Bits)


CC0

OV

OS

–1.175494E–38 < result < – 1.401298E–45 (negative number) below minimum

0

0

1

1

+1.401298E–45 < result < +1.175494E–38 (positive number) below minimum

0

0

1

1

result < –3.402823E+38 (negative number) above maximum

0

1

1

1

result > 3.402823E+38 (positive number) above maximum

1

0

1

1

result < –3.402823E+38 or result > +3.402823E+38 not a floating-point number

1

1

1

1


8-7


8.7


Description

Table 8-7

With the Form the Absolute Value of a Floating-Point Number instruction, you can form the absolute value of floating-point number. ABS Box and Parameters Parameters

FBD Box

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

ABS EN OUT

IN

REAL


Input value: floating-point number

IN

OUT

REAL

I, Q, M, D, L

Output value: absolute value of the floating-point number

ENO

BOOL

I, Q, M, D, L

Enable output

ENO

If I0.0 = 1, the absolute value of MD8 is output at MD12.

ABS I0.0

EN

OUT

MD8

IN

ENO

MD8 = +6.234 x 10–3 results in MD12 = 6.234 x 10–3.

MD12 Q4.0 =

Output Q4.0 is 0 if the conversion is not executed (ENO = EN = 0).

Status Word Bits Instruction is executed (EN = 1): writes Figure 8-5

8-8

BR X

CC1 –

CC0 –

OV –

OS –

OR 0

STA X

RLO X

FC 1




8.8

Forming the Square (SQR) of a Floating-Point Number

Description

With the Form the Square of a Floating-Point Number instruction, you can square a floating-point number. If either of the inputs or the result is not a floating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0.

Parameter

Table 8-8 shows the SQR box and describes the parameters. Table 8-8

SQR Box and Parameters

FBD Box

Parameters

SQR EN OUT IN

MD0

EN

OUT

IN

ENO

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Square of the number

ENO

BOOL

I, Q, M, D, L

Enable output

ENO

A signal state of 1 at input I0.0 activates the SQR box. The result of SQR (MD0) is entered in the memory double word MD10. If MD0 is less than 0 or if either of the inputs or the result is not a floating-point number and if the signal state of I0.0 is 0, output Q4.0 is set to 0.

SQR I0.0

Data Type

MD10 Q4.0 =


Figure 8-6

OV x

OS x

OR 0

STA x

RLO x

FC 1

Forming the Square of a Floating-Point Number


8-9


8.9

Forming the Square Root (SQRT) of a Floating-Point Number

Description

With the Form the Square Root of a Floating-Point Number instruction, you can extract the square root of a floating-point number. This instruction returns a positive result, if the value at the address is greater than “0”. If either of the inputs or the result is not a floating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0.

Parameter

Table 8-9 shows the SQRT box and describes the parameters.

Table 8-9

SQRT Box and Parameters

FBD Box

SQRT OUT EN IN

Parameters

MD0

EN

OUT

IN

ENO

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Square root of the number

ENO

BOOL

I, Q, M, D, L

Enable output

ENO

A signal state of 1 at input I0.0 activates the SQRT box. The result of SQRT (MD0) is entered in memory double word MD10. If MD0 is less than 0 or if either of the inputs or the result is not a floating-point number and if the signal state of I0.0 is 0, output Q4.0 is set to 0.

SQRT I0.0

Data Type

MD10 Q4.0 =


Figure 8-7

8-10

OV x

OS x

OR 0

STA x

RLO x

FC 1

Forming the Square Root of a Floating-Point Number



8.10 Forming the Natural Logarithm of a Floating-Point Number

Description

With the Form the Natural Logarithm of a Floating-Point Number instruction, you can form the natural logarithm of a floating-point number. If either of the inputs or the result is not a floating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0. Table 8-10

LN Box and Parameters Parameters

FBD Box

LN OUT EN IN

EN

OUT

MD0

IN

ENO

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Natural logarithm of the number

ENO

BOOL

I, Q, M, D, L

Enable output

ENO

A signal state of 1 at input I0.0 activates the LN box. The result of LN (MD0) is entered in memory double word MD10. If MD0 is less than 0 or if either of the inputs or the result is not a floating-point number and if the signal state of I0.0 is 0, output Q4.0 is set to 0.

LN I0.0

Data Type

MD10 Q4.0 =


Figure 8-8

OV x

OS x

OR 0

STA x

RLO x

FC 1

Forming the Natural Logarithm of a Floating-Point Number


8-11


8.11 Forming the Exponential Value of a Floating-Point Number

Description

With the Form the Exponential Value of a Floating-Point Number instruction, you can form the exponential value of a floating-point number to base e (= 2.71828...). If either of the inputs or the result is not a floating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0. Table 8-11

EXP Box and Parameters Parameters

FBD Box

EXP EN OUT IN

ENO

EN

OUT

MD0

IN

ENO

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Exponent of the number

ENO

BOOL

I, Q, M, D, L

Enable output

A signal state of 1 at input I0.0 activates the EXP box. The result of EXP (MD0) is entered in memory double word MD10. If either of the inputs or the result is not a floating-point number and if the signal state of E 0.0 is 0, output Q4.0 is set to 0.

EXP I0.0

Data Type

MD10 Q4.0 =


Figure 8-9

8-12

OV x

OS x

OR 0

STA x

RLO x

FC 1

Forming the Exponential Value of a Floating-Point Number



8.12 Forming Trigonometric Functions of Angles as Floating-Point Numbers

Description

With the following instructions, you can form trigonometric functions of angles represented as 32-bit IEEE floating-point numbers. Instruction

Meaning

SIN

Form the sine of a floating-point number of an angle specified in radians.

ASIN

Form the arc sine of a floating-point number . The result is an angle specified in radians. The value is in the following range: / 2 arc sine + / 2, where = 3.14...

COS

Form the cosine of a floating-point number of an angle specified in radians.

ACOS

Form the arc cosine of a floating-point number . The result is an angle specified in radians. The value is in the following range: 0 arc cosine + , where = 3.14...

TAN

Form the tangent of a floating-point number of an angle specified in radians.

ATAN

Form the arc tangent of a floating-point number . The result is an angle specified in radians. The value is in the following range: / 2 arc tangent + / 2, where = 3.14...

Parameter

Tables 8-12 through 8-17 show the SIN, ASIN, COS, ACOS, TAN and ATAN boxes and describe the parameters. Table 8-12

SIN Box and Parameters

FBD Box

SIN EN OUT IN

ENO


Parameters

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Sine of the number

ENO

BOOL

I, Q, M, D, L

Enable output

8-13


Table 8-13

ASIN Box and Parameters

FBD Box

ASIN EN OUT IN

Table 8-14

ENO

COS EN OUT

Table 8-15

ENO

ACOS EN OUT

Table 8-16

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Arc sine of the number

ENO

BOOL

I, Q, M, D, L

Enable output

Parameters

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Cosine of the number

ENO

BOOL

I, Q, M, D, L

Enable output

Parameters

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Arc cosine of the number

ENO

BOOL

I, Q, M, D, L

Enable output

TAN Box and Parameters

TAN OUT EN

8-14

Description

EN

ENO

FBD Box

IN

Memory Area

ACOS Box and Parameters

FBD Box

IN

Data Type

COS Box and Parameters

FBD Box

IN

Parameters

Parameters

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Tangent of the number

ENO

BOOL

I, Q, M, D, L

Enable output

ENO



Table 8-17

ATAN Box and Parameters Parameters

FBD Box

ATAN EN OUT IN

ENO

MD0

EN IN

OUT

Description

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Number

OUT

REAL

I, Q, M, D, L

Arc tangent of the number

ENO

BOOL

I, Q, M, D, L

Enable output

A signal state of 1 at input I0.0 activates the SIN box. The result of SIN (MD0) is entered in memory double word MD10. If either of the inputs or the result is not a floating-point number and if the signal state of I0.0 is 0, output Q4.0 is set to 0.

MD10 Q4.0 =

ENO

Memory Area

EN

SIN I0.0

Data Type


Figure 8-10

OV x

OS x

OR 0

STA x

RLO x

FC 1

Forming the Sine of a Floating-Point Number


8-15


8-16


9

Comparison Instructions Chapter Overview

Section

Description

Page

9.1

Compare Integer

9-2

9.2

Compare Double Integer

9-3

9.3

Compare Real

9-4


9-1


9.1

Compare Integer

Description

The Compare Integer instruction compares two values on the basis of 16-bit floating-point numbers. This instruction compares inputs IN1 and IN2 according to the type of comparison you select from the list box. The following table lists the available types of comparison. If the comparison is true, the result of logic operation (RLO) of the comparison is 1. Otherwise, it is 0. You cannot negate the comparison result itself, but you can achieve the same effect as negation by using the opposite compare function. Table 9-1

Types of Comparison for Integers Relational Operator

Type of Comparison

Table 9-2

IN1 is equal to IN2.

==

IN1 is not equal to IN2.

<>

IN1 is greater than IN2.

>

IN1 is less than IN2.

<

IN1 is greater than or equal to IN2.

>=

IN1 is less than or equal to IN2.

<=

Compare Integer Box and Parameters (Example using Equal) Parameters

FBD Box CMP == I IN1

Data Type

Memory Area

Description

IN1

INT


First value to compare

IN2

INT


Second value to compare

Box output

BOOL

I, Q, M, D, L

Result of comparison

IN2

Q4.0 is set when:

MW0

CMP == I IN1

MW2

IN2

MW0 is equal to MW2 AND the signal state is 1 at input I0.0

& I0.0

Q4.0 S Status Word Bits

Comparison is true: writes Figure 9-1

9-2

BR x

CC1 x

CC0 x

OV 0

OS –

OR 0

STA 1

RLO x

FC 1

Compare Integer



9.2


Description

The Compare Double Integer instruction compares two values on the basis of 32-bit floating-point numbers. This instruction compares inputs IN1 and IN2 according to the type of comparison you select from the list box. The following table lists the available types of comparison. If the comparison is true, the result of logic operation (RLO) of the comparison is 1. Otherwise, it is 0. You cannot negate the comparison result itself, but you can achieve the same effect as negation by using the opposite compare function. Table 9-3

Types of Comparison for Double Integers Relational Operator

Type of Comparison

Table 9-4


==


<>


>


<


>=


<=

Compare Double Integer Box and Parameters (Example using Not Equal)

FBD Box CMP <> D IN1 IN2

Parameters

Data Type

IN1

MD4

IN2

Description

IN1

DINT



IN2

DINT



Box output

BOOL

I, Q, M, D, L


Q4.0 is set when:

CMP <> D MD0

Memory Area

&

MD0 is not equal to MD4

I0.0

AND the signal state at

Q4.0 S

at input I0.0 is 1

Status Word Bits Comparison is true: BR writes – Figure 9-2

CC1 x

CC0 x

OV 0

OS –

OR 0

STA x

RLO x

FC 1



9-3


9.3

Compare Real

Description

The Compare Real instruction compares two values on the basis of floating-point numbers. This instruction compares inputs IN1 and IN2 according to the type of comparison you select from the list box. The following table lists the available types of comparison. If the comparison is true, the result of logic operation (RLO) of the comparison is 1. Otherwise, it is 0. You cannot negate the comparison result itself, but you can achieve the same effect as negation by using the opposite compare function. Table 9-5

Types of Comparison for Floating-Point Numbers Relational Operator

Type of Comparison

Table 9-6


==


<>


>


<


>=


<=

Compare Real Box and Parameters (Example using Less Than)

FBD Box CMP
Parameters

Data Type

IN1

REAL



IN2

REAL



Box output

BOOL

I, Q, M, D, L


IN1

MD4

IN2

Description

Q4.0 is set when:

CMP
Memory Area

&

MD0 is less than MD4

I0.0

AND the signal state at

Q4.0

input I0.0 is 1

S

Status Word Bits Comparison is true: BR CC1 writes Figure 9-3

9-4

–

x

CC0

OV

OS

OR

STA

RLO

FC

x

x

x

0

x

x

1

Compare Real Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01

Move and Conversion Instructions Chapter Overview

Section

Description

10 Page

10.1

Assign Value

10-2

10.2

BCD to Integer

10-3

10.3

Integer to BCD

10-4

10.4

Integer to Double Integer

10-5

10.5

BCD to Double Integer

10-6

10.6

Double Integer to BCD

10-7

10.7

Double Integer to Real

10-8

10.8

Ones Complement Integer

10-9

10.9

Ones Complement Double Integer

10-10

10.10

Twos Complement Integer

10-11

10.11

Twos Complement Double Integer

10-12

10.12

Negate Real Number

10-13

10.13

Round to Double Integer

10-14

10.14

Truncate Double Integer Part

10-15

10.15

Ceiling

10-16

10.16

Floor

10-17


10-1


10.1 Assign Value

Description

With the Assign Value instruction, you can assign specific values to variables. The value specified at the IN input is copied to the address specified at the OUT output. ENO has the same signal state as EN. With the MOVE box, the Assign Value instruction can copy all data types with lengths of 8, 16, or 32 bits. User-defined data types such as arrays or structures must be be copied with the system function SFC20 “BLKMOV” (see the Reference Manual /235/). The Assign Value instruction is affected by the Master Control Relay (MCR). For more information on how the MCR functions, see Section 16.5.

Table 10-1

Assign Value Box and Parameters Parameters

FBD Box

MOVE EN

OUT

IN

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

All data types with a length of 8, 16 or 32 bits


Source value

OUT

All data types with a length of 8, 16 or 32 bits

I, Q, M, D, L

Destination address

ENO

BOOL

I, Q, M, D, L

Enable output

The instruction is executed, when input I0.0 is 1. The content of MW10 is copied to data word 12 of the open DB.

MOVE I0.0

EN

OUT

MW10

IN

ENO

DBW12 Q4.0 =

If the instruction is executed, Q4.0 is set to 1.


BR 1

CC0 –

OV –

OS –

OR 0

STA 1

RLO 1

FC 1

Assign Value

Assigning Values to Variables

10-2

CC1 –

For information about integrated system functions that can be used as move instructions and that can assign a specific value to a variable or can copy variables of varying types, refer to the Reference Manual /235/.



10.2 BCD to Integer

Description

The BCD to Integer instruction reads the content of the input parameter IN as a three-digit number in binary coded decimal format (BCD, 999) and converts this number to an integer value. The output parameter OUT contains the result. ENO always has the same signal state as EN. If any of the individual decimal numbers in the BCD number is in the invalid range between 10 and 15, a BCD error occurs when the conversion is attempted, causing the following reaction:

The CPU changes to the STOP mode. “BCD conversion error” is entered in the diagnostic buffer with event ID number 2521.

If OB121 is programmed, it is called. For more detailed information about programming OB121, refer to the Reference Manual /235/. Table 10-2

BCD to Integer Box and Parameters Parameters

FBD Box BCD I BCD_I EN

OUT

IN

ENO

Data Type

Memory Area

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

WORD


Number in BCD format

OUT

INT

I, Q, M, D, L

Integer value of the BCD number

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The content of memory word MW10 is read as a three-digit number in BCD format and converted to an integer. The result is stored in memory word MW12. If the conversion is executed, the signal state of output Q4.0 is 1 (ENO = EN).

BCD_I I0.0

EN

MW10

IN

Description

OUT

MW12 Q4.0 =

ENO


Figure 10-2

BR 1

CC1 –

CC0 –

OV –

OS –

OR 0

STA 1

RLO 1

FC 1

BCD to Integer


10-3


10.3 Integer to BCD

Description

Table 10-3

The Integer to BCD instruction reads the content of the input parameter IN as an integer value and converts this value to a three-digit number in binary coded decimal format (BCD, 999). The output parameter OUT contains the result. If an overflow occurs, ENO is set to 0. Integer to BCD Box and Parameters Parameters

FBD Box I BCD I_BCD EN

OUT

IN

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

INT


Integer

OUT

WORD

I, Q, M, D, L

BCD value of the integer

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The content of memory word MW10 is read as an integer and converted to a three-digit number in BCD format. The result is stored in memory word MW12. If an overflow occurs, the signal state of output Q4.0 is 0. If the signal state at input EN is 0 (meaning that the conversion is not executed), the signal state of output Q4.0 is also 0.

I_BCD I0.0

EN

OUT

MW10

IN

ENO

MW12 Q4.0 =


Figure 10-3

10-4

BR x

CC1 –

CC0 –

OV x

OS x

OR 0

STA x

RLO x

FC 1

Integer to BCD



10.4 Integer to Double Integer

Description

Table 10-4

The Integer to Double Integer instruction reads the content of the input parameter IN as an integer and converts the integer to a double integer. The output parameter OUT contains the result. ENO always has the same signal state as EN. Integer to Double Integer Box and Parameters Parameters

FBD Box II_DI DI EN OUT IN

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

INT


Value to be converted

OUT

DINT

I, Q, M, D, L

Result

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The content of memory word MW10 is read as an integer and converted to a double integer. The result is stored in memory double word MD12. If the conversion is executed, the signal state of output Q4.0 is 1 (ENO = EN).

I_DI I0.0

EN

OUT

MW10

IN

ENO

MD12 Q4.0 =


Figure 10-4

BR 1

CC1 –

CC0 –

OV –

OS –

OR 0

STA 1

RLO 1

FC 1



10-5


10.5 BCD to Double Integer

Description

The BCD to Double Integer instruction reads the content of the input parameter IN as a seven-digit number in binary coded decimal format (BCD, 9,999,999) and converts this number to a double integer value. The output parameter OUT contains the result. ENO always has the same signal state as EN. If any of the individual decimal numbers in the BCD number is in the invalid range between 10 and 15, a BCD error occurs when the conversion is attempted, causing the following reaction:

The CPU changes to the STOP mode. “BCD conversion error” is entered in the diagnostic buffer with event ID number 2521.

If OB121 is programmed, it is called. For more detailed information about programming OB121, refer to the Reference Manual /235/. Table 10-5

BCD to Double Integer Box and Parameters Parameters

FBD Box BCD DI BCD_DI EN

OUT

IN

ENO

Data Type

Memory Area

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

DWORD


Number in BCD format

OUT

DINT

I, Q, M, D, L

Double integer value of the BCD number

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The content of memory double word MD8 is read as a seven-digit number in BCD format and converted to a double integer. The result is stored in MD12. If the conversion is executed, the signal state of output Q4.0 is 1 (ENO = EN).

BCD_DI I0.0 MD8

Description

EN

OUT

IN

ENO

MD12 Q4.0 =


Figure 10-5

10-6

BR 1

CC1 –

CC0 –

OV –

OS –

OR 0

STA 1

RLO 1

FC 1




10.6 Double Integer to BCD

Description

Table 10-6

The Double Integer to BCD instruction instruction reads the content of the input parameter IN as a double integer value and converts this value to a seven-digit number in BCD format ( 9 999 999). The output parameter OUT contains the result. If an overflow occurs, ENO is set to 0. Double Integer to BCD Box and Parameters Parameters

FBD Box DI BCD DI_BCD EN

OUT

IN

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

DINT


Double integer

OUT

DWORD

I, Q, M, D, L

BCD value of the double integer

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The content of memory double word MD8 is read as a double integer and converted to a seven-digit number in BCD format. The result is stored in MD12. If an overflow occurs, the signal state of output Q4.0 is 0. If the signal state at input EN is 0 (meaning that the conversion is not executed), the signal state of output Q4.0 is also 0.

DI_BCD I0.0

EN

OUT

MD8

IN

ENO

MD12 Q4.0 =


BR x

CC1 –

CC0 –

OV x

OS x

OR 0

STA x

RLO x

FC 1



10-7


10.7 Double Integer to Real

Description

Table 10-7

The Double Integer to Real instruction reads the content of the input parameter IN as a double integer value and converts this value to a real number. The output parameter OUT contains the result. ENO always has the same signal state as EN. Double Integer to Real Box and Parameters Parameters

FBD Box DI R DI_R EN IN

OUT ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

DINT



OUT

REAL

I, Q, M, D, L

Result

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The contents of memory double word MD8 is read as an integer and converted to a real number. The result is stored in memory double word MD12. If the conversion is not executed, the signal state of output Q4.0 is 0 (ENO=EN).

DI_R I0.0

EN

OUT

MD8

IN

ENO

MD12

Q4.0 =


Figure 10-7

10-8

BR 1

CC1 –

CC0 –

OV –

OS –

OR 0

STA 1

RLO 1

FC 1




10.8 Ones Complement Integer

Description

Table 10-8

The Ones Complement Integer instruction reads the content of the input parameter IN and performs the Boolean word logic instruction Exclusive Or Word (see Section 11.6) masked by FFFFH, so that the value of every bit is inverted. The output parameter OUT contains the result. ENO always has the same signal state as EN. Ones Complement Integer Box and Parameters Parameters

FBD Box INV I INV_I EN

OUT

IN

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

INT


Input value

OUT

INT

I, Q, M, D, L

Ones complement of the integer

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The value of every bit in MW8 is inverted. MW8 = 01000001 10000001 → MW10 = 10111110 01111110 The conversion is not executed when the signal state of I0.0 is 0 and Q4.0 is 0 (ENO = EN).

INV_I I0.0

EN

OUT

MW8

IN

ENO

MW10 Q4.0 =


Figure 10-8

BR 1

CC1 –

CC0 –

OV –

OS –

OR 0

STA 1

RLO 1

FC 1



10-9


10.9 Ones Complement Double Integer

Description

Table 10-9

The Ones Complement Double Integer instruction reads the content of the input parameter IN and performs the Boolean word logic operation Exclusive Or Word (see Section 11.6) masked by FFFF FFFFH, so that the value of every bit is inverted. The output parameter OUT contains the result. ENO always has the same signal state as EN. Ones Complement Double Integer Box and Parameters Parameters

FBD Box INV DI INV_DI EN

OUT

IN

ENO

Data Type

EN

MD8

IN

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

DINT


Input value

OUT

DINT

I, Q, M, D, L

Ones complement of the double integer

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The value of every bit of memory double word MD8 is inverted:

INV_DI I0.0

Memory Area

OUT

MD12

MD8 = F0FF FFF0 → MD12 = 0F00 000F

Q4.0 =

ENO

The conversion is not executed when I0.0 is 0 and Q4.0 is 0 (ENO = EN).

Status Word Bits

Instruction is executed (EN = 1): writes

Figure 10-9

10-10

BR 1

CC1 –

CC0 –

OV –

OS –

OR 0

STA 1

RLO 1

FC 1




10.10 Twos Complement Integer

Description

Table 10-10

The Twos Complement Integer instruction reads the content of the input parameter IN and changes the sign (for example, from a positive value to a negative value). The output parameter OUT contains the result. The signal state of EN is and ENO is always the same except when the signal state of EN is 1 and an overflow occurs. In this case, the signal state of ENO is 0. Twos Complement Integer Box and Parameters Parameters

FBD Box NEG I NEG_I EN

OUT

IN

ENO

Data Type

Memory Area

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

INT


Input value

OUT

INT

I, Q, M, D, L

Twos complement of the integer

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The value of memory word MW8 is output at OUT to memory word MW10 with the opposite sign:

NEG_I I0.0

EN

MW8

IN

Description

OUT

MW10

Example:MW8 = +10 → MW10 = – 10

Q4.0 =

ENO

If the signal state of EN is 1 and an overflow occurs, ENO is 0 and the signal state of Q4.0 is 0. If the conversion is not executed, Q4.0 is 0 (ENO = EN).


Figure 10-10

BR x

CC1 x

CC0 x

OV x

OS x

OR 0

STA x

RLO x

FC 1



10-11


10.11 Twos Complement Double Integer

Description

Table 10-11

The Twos Complement Double Integer instruction reads the content of the input parameter IN and changes the sign (for example, from a positive value to a negative value). The output parameter OUT contains the result. The signal state of EN is and ENO is always the same except when the signal state of EN is 1 and an overflow occurs. In this case, the signal state of ENO is 0. Twos Complement Double Integer Box and Parameters

FBD Box

Parameter

NEG DI NEG_DI EN

OUT

IN

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

DINT


Input value

OUT

DINT

I, Q, M, D, L

Twos complement of the double integer

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The value of memory double word MD8 is output at OUT to memory double word MD10 with the opposite sign:

NEG_DI I0.0

EN

OUT

MD8

IN

ENO

MD12 Example:MD8 = +60 000 → MW10 = – 60 000

Q4.0 =

If the signal state of EN is 1 and an overflow occurs, ENO is 0 and the signal state of Q4.0 is 0. If the conversion is not executed, Q4.0 is 0 (ENO = EN). Status Word Bits Instruction is executed (EN = 1): BR CC1 CC0 writes x x x

Figure 10-11

10-12

OV x

OS x

OR 0

STA x

RLO x

FC 1




10.12 Negate Real Number

Description

Table 10-12

The Negate Real Number instruction reads the content of the input parameter IN and inverts the sign bit (the instruction changes the sign of the number. for example, from 0 for plus to 1 for minus). The bits of the exponent and mantissa remain the same. The output parameter OUT provides the result. ENO always has the same signal state as EN except when the signal state of EN is 1 and an overflow occurs. In this case, the signal state of ENO is 0. Negate Real Number Box and Parameters

FBD Box

Parameters

NEG R NEG_R EN

OUT

IN

ENO

Data Type

EN

OUT

MD8

IN

ENO

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Input value

OUT

REAL

I, Q, M, D, L

The result is the negated input value.

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The value of memory double word MD8 is output at OUT to memory double word MD12 with the opposite sign as shown in the following example:

NEG_R I0.0

Memory Area

MD12 Q4.0 =

MD8 = + 6.234 x 10–3 → MD12 = – 6.234 x 10–3 If the conversion is not executed, the signal state of output Q4.0 is 0 (ENO = EN).


Figure 10-12

BR x

CC1 –

CC0 –

OV –

OS –

OR 0

STA x

RLO x

FC 1

Negate Real Number


10-13


10.13 Round to Double Integer

Description

Table 10-13

The Round to Double Integer instruction reads the content of the input parameter IN as a real number and converts this number to a double integer. The result is the nearest integer and is contained in output parameter OUT. If the fraction is x.5, the number is rounded to the even number (for example: 2.5 –> 2, 1.5 –> 2). If an overflow occurs, ENO is set to 0. If the input value is not a real number, the OV bit and the OS bit have the value 1 and ENO has the value 0. Round to Double Integer Box and Parameters

FBD Box

Parameters

ROUND EN

OUT

IN

ENO

Data Type

EN

OUT

MD8

IN

ENO

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Value to be rounded

OUT

DINT

I, Q, M, D, L

IN rounded to the next double integer

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if I0.0 is 1. The content of memory double word MD8 is read as a real number and converted to a double integer. The result of this round-to-nearest function is stored in memory double word MD12. If an overflow occurs, the signal state of output Q4.0 is 0. If the signal state at input EN is 0 (meaning that the conversion is not executed), the signal state of output Q4.0 is also 0.

ROUND I0.0

Memory Area

MD12 Q4.0 =


Figure 10-13

10-14

BR x

CC1 –

CC0 –

OV x

OS x

OR 0

STA x

RLO x

FC 1




10.14 Truncate Double Integer Part

Description

Table 10-14

The Truncate Double Integer Part instruction reads the content of the input parameter IN as a real number and converts this number to a double integer (for example 1.5 becomes 1). The result is the integer component of the real number). The output parameter OUT contains the result. If an overflow occurs, ENO is set to 0. If the input value is not a real number, the OV bit and the OS bit have the value 1 and ENO has the value 0. Truncate Double Integer Part Box and Parameters

FBD Box

Parameters

TRUNC EN

OUT

IN

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL


Value to be truncated

OUT

DINT

I, Q, M, D, L

Integer component of IN

ENO

BOOL

I, Q, M, D, L

Enable output

The conversion is executed if the signal state of I0.0 is 1. The content of memory double word MD8 is read as a real number and converted to a double integer according to the “round to zero principle”. The integer component is the result and is stored in memory double word MD12. If an overflow occurs, the signal state of output Q4.0 is 0. If the signal state at input EN is 0 (meaning that the conversion is not executed), the signal state of output Q4.0 is also 0.

TRUNC I0.0

EN

OUT

MD8

IN

ENO

MD12 Q4.0 =


Figure 10-14

BR x

CC1 –

CC0 –

OV x

OS x

OR 0

STA x

RLO x

FC 1



10-15


10.15 Ceiling

Description

Table 10-15

The Ceiling instruction reads the content of the input parameter IN as a real number and converts this number to a double integer (for example: +1.2 –> +2; –1.5 –> –1). The result is the lowest integer which is greater than or equal to the specified real number. The output parameter OUT contains the result. If an overflow occurs, ENO is 0. If the input value is not a real number, the OV bit and the OS bit have the value 1 and ENO has the value 0. Ceiling Box and Parameters

FBD Box

Parameters

CEIL EN

OUT

IN

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL



OUT

DINT

I, Q, M, D, L

Result

ENO

BOOL

I, Q, M, D, L

Enable output

CEIL I0.0

EN

OUT

MD8

IN

ENO

MD12 Q4.0 =

The conversion is executed if I0.0 is 1.The content of memory double word MD8 is read as a real number and converted to a double integer by rounding to the next higher (or equal) whole number. The result is stored in memory double word MD12. If an overflow occurs, the signal state of output Q4.0 is 0. If the signal state at input EN is 0 (meaning that the conversion is not executed), the signal state of output Q4.0 is also 0.


Figure 10-15

10-16

BR x

CC1 –

CC0 –

OV x

OS x

OR 0

STA x

RLO x

FC 1

Ceiling



10.16 Floor

Description

Table 10-16

The Floor instruction reads the content of the input parameter IN as a real number and converts this number to a double integer. The result is the highest integer which is lower than or equal to the specified real number. The output parameter OUT contains the result. If an overflow occurs, ENO is set to 0. If the input value is not a real number, the OV bit and the OS bit have the value 1 and ENO has the value 0. Floor Box and Parameters

FBD Box

Parameters

FLOOR EN

OUT

IN

ENO

Data Type

MD8

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN

REAL



OUT

DINT

I, Q, M, D, L

Result

ENO

BOOL

I, Q, M, D, L

Enable output

FLOOR I0.0

Memory Area

EN

OUT

IN

ENO

MD12 Q4.0 =

The conversion is executed if I0.0 is 1. The content of memory double word MD8 is read as a real number and converted to a double integer by rounding to the next lower (or equal) whole number. The result is stored in memory double word MD12. If an overflow occurs, the signal state of output Q4.0 is 0. If the signal state at input EN is 0 (meaning that the conversion is not executed), the signal state of output Q4.0 is also 0.


Figure 10-16

BR x

CC1 –

CC0 –

OV x

OS x

OR 0

STA x

RLO x

FC 1

Floor


10-17


10-18


11

Word Logic Instructions Chapter Overview

Section

Description

Page

11.1

Overview

11-2

11.2

(Word) AND Word

11-3

11.3

(Word) AND Double Word

11-4

11.4

(Word) OR Word

11-5

11.5

(Word) OR Double Word

11-6

11.6

(Word) Exclusive OR Word

11-7

11.7

(Word) Exclusive OR Double Word

11-8


11-1


11.1 Overview

What Are Word Logic Instructions?

Word logic instructions compare pairs of words (16 bits) and double words (32 bits) bit by bit, according to Boolean logic. The following instructions are available for performing word logic operations:

(Word) AND Word: This instruction combines two words bit by bit, according to the AND truth table.

(Word) AND Double Word: This instruction combines two double words bit by bit, according to the AND truth table.

(Word) OR Word: This instruction combines two words bit by bit, according to the OR truth table.

(Word) OR Double Word: This instruction combines two double words bit by bit, according to the OR truth table.

(Word) Exclusive OR Word: This instruction combines two words bit by bit, according to the Exclusive OR truth table.

(Word) Exclusive OR Double Word: This instruction combines two double words bit by bit, according to the Exclusive OR truth table.

11-2



11.2 (Word) AND Word

Description

The (Word) AND Word instruction is activated by signal state 1 at the Enable input (EN) and combines the two digital values at inputs IN1 and IN2 bit by bit according to the AND truth table. The values are interpreted as pure bit patterns. The result can be scanned at output OUT. ENO has the same signal state as EN. The value of the result at output OUT relative to 0 affects the CC1 bit of the status word as follows:

If the result at output OUT is not equal to 0, the CC1 bit of the status word is set to 1 .

If the result at output OUT is 0, the CC1 bit of the status word is set to 0. Table 11-1

(Word) AND Word Box and Parameters Parameters

FBD Box WAND W WAND_W

Data Type

OUT

IN2

ENO

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN1

WORD


First value of the logic operation

IN2

WORD


Second value of the logic operation

OUT

WORD

I, Q, M, D, L

Result of the logic operation

ENO

BOOL

I, Q, M, D, L

Enable output

EN IN1

Memory Area

I0.0

WAND_W EN

MW0

IN1

OUT

2# 0000000000001111

IN2

ENO

MW2

Q4.0 =

The instruction is activated when the signal state of I0.0 is 1. Only bits 0 to 3 are relevant, all other bits of MW0 are masked. IN1 = 0101010101010101 IN2 = 0000000000001111 OUT = 0000000000000101 Q4.0 is 1 if the instruction is executed.


Figure 11-1

BR 1

CC1 x

CC0 0

OV 0

OS –

OR x

STA 1

RLO 1

FC 1

(Word) AND Word


11-3


11.3 (Word) AND Double Word

Description

The (Word) AND Double Word instruction is activated by signal state 1 at the Enable input (EN) and combines the two digital values at inputs IN1 and IN2 bit by bit according to the AND truth table. The values are interpreted as pure bit patterns. The result can be scanned at output OUT. ENO has the same signal state as EN. The value of the result at output OUT relative to 0 affects the CC1 bit of the status word as follows:



(Word) AND Double Word Box and Parameters Parameter

FBD Box

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

WAND_DW WAND DW EN

IN1

DWORD



IN1

OUT

IN2

DWORD


IN2

ENO


OUT

DWORD

I, Q, M, D, L


ENO

BOOL

I, Q, M, D, L

Enable output

The instruction is activated when I0.0 is 1. Only bits 0 to 11 are relevant, all other bits of MD4 are masked. IN1 = 0101010101010101 0101010101010101 IN2 = 0000000000000000 0000111111111111 OUT = 0000000000000000 0000010101010101

WAND_DW I0.0

EN

MD0

IN1

OUT

DW#16#FFF

IN2

ENO

MD4 Q4.0 =

Q4.0 is 1 if the instruction is executed.


Figure 11-2

11-4

BR 1

CC1 x

CC0 0

OV 0

OS –

OR x

STA 1

RLO 1

FC 1




11.4 (Word) OR Word

Description

The (Word) OR Word instruction is activated by signal state 1 at the Enable input (EN) and combines the two digital values at inputs IN1 and IN2 bit by bit according to the OR truth table. The values are interpreted as pure bit patterns. The result can be scanned at output OUT. ENO has the same signal state as EN. The value of the result at output OUT relative to 0 affects the CC1 bit of the status word as follows:



(Word) OR Word Box and Parameters Parameters

FBD Box WOR W WOR_W

Data Type

OUT

IN2

ENO

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN1

WORD



IN2

WORD



OUT

WORD

I, Q, M, D, L


ENO

BOOL

I, Q, M, D, L

Enable output

EN IN1

Memory Area

The instruction is activated when I0.0 is 1. The bits in MW0 and in the constant are ORed and bits 0 to 3 set to 1, all other bits of MW0 are entered unchanged in MW2

WOR_W I0.0

EN

MW0

IN1

OUT

2#0000000000001111

IN2

ENO

MW2

Q4.0 =

IN1 = IN2 = OUT =

0101010101010101 0000000000001111 0101010101011111



BR 1

CC1 x

CC0 0

OV 0

OS –

OR x

STA 1

RLO 1

FC 1

(Word) OR Word


11-5


11.5 (Word) OR Double Word

Description

The (Word) OR Double Word instruction is activated by signal state 1 at the Enable input (EN) and combines the two digital values at inputs IN1 and IN2 bit by bit according to the OR truth table. The values are interpreted as pure bit patterns. The result can be scanned at output OUT. ENO has the same signal state as EN. The value of the result at output OUT relative to 0 affects the CC1 bit of the status word as follows:



(Word) OR Double Word Box and Parameters Parameters

FBD Box WOR DW WOR_DW

Data Type

OUT

IN2

ENO

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN1

DWORD



IN2

DWORD



OUT

DWORD

I, Q, M, D, L


ENO

BOOL

I, Q, M, D, L

Enable output

EN IN1

Memory Area

WOR_DW I0.0

EN

MD0

IN1

OUT

DW#16#FFF

IN2

ENO

MD4

Q4.0 =

The instruction is activated when I0.0 is 1. The bits in MD0 and in the constant are ORed and bits 0 to 11 set to 1, all other bits of MD0 are entered unchanged in MD4 IN1 = 0101010101010101 0101010101010101 IN2 = 0000000000000000 0000111111111111 OUT = 0101010101010101 0101111111111111 Q4.0 is 1 if the instruction is executed.


11-6

BR 1

CC1 x

CC0 0

OV 0

OS –

OR x

STA 1

RLO 1

FC 1




11.6 (Word) Exclusive OR Word

Description

The (Word) Exclusive OR Word instruction is activated by signal state 1 at the Enable input (EN) and combines the two digital values at inputs IN1 and IN2 bit by bit according to the EXCLUSIVE OR truth table. The values are interpreted as pure bit patterns. The result can be scanned at output OUT. ENO has the same signal state as EN. The value of the result at output OUT relative to 0 affects the CC1 bit in the status word as follows:

If the result at output OUT is not equal to 0, the CC1 bit in the status word is set to 1.

If the result at output OUT is 0, the CC1 bit in the status word is set to 0. Table 11-5

(Word) Exclusive OR Word Box and Parameters Parameters

FBD Box

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

WXOR_W WXOR W EN

IN1

WORD



IN1

OUT

IN2

WORD

ENO



IN2

OUT

WORD

I, Q, M, D, L


ENO

BOOL

I, Q, M, D, L

Enable output

I0.0

WXOR_W EN

MW0

IN1

OUT

2#0000000000001111

IN2

ENO

The instruction is activated when input I0.0 is 1.

MW2

Q4.0 =

IN1 = IN2 = OUT =

0101010101010101 0000000000001111 0101010101011010



Figure 11-5

BR 1

CC1 x

CC0 0

OV 0

OS –

OR x

STA 1

RLO 1

FC 1



11-7


11.7 (Word) Exclusive OR Double Word

Description

The (Word) Exclusive OR Double Word instruction is activated by signal state 1 at the Enable input (EN) and combines the two digital values at inputs IN1 and IN2 bit by bit according to the EXCLUSIVE OR truth table. The values are interpreted as pure bit patterns. The result can be scanned at output OUT. ENO has the same signal state as EN. The value of the result at output OUT relative to 0 affects the CC1 bit in the status word as follows:

If the result at output OUT is not equal to 0, the CC1 bit in the status word is set to 1.

If the result at output OUT is 0, the CC1 bit in the status word is set to 0. Table 11-6

(Word) Exclusive OR Double Word Box and Parameters Parameters

FBD Box WXOR DW WXOR_DW

Data Type

OUT

IN2

ENO

Description

EN

BOOL

I, Q, M, D, L, T, C

Enable input

IN1

DWORD



IN2

DWORD



OUT

DWORD

I, Q, M, D, L


ENO

BOOL

I, Q, M, D, L

Enable output

EN IN1

Memory Area

The instruction is activated when input I0.0 is 1. WXOR_DW EN

I0.0 MD0

IN1

OUT

DW#16#FFF

IN2

ENO

MD4

Q4.0 =

IN1 = 0101010101010101 0101010101010101 IN2 = 0000000000000000 0000111111111111 OUT = 0101010101010101 0101101010101010 Q4.0 is 1 if the instruction is executed.


Figure 11-6

11-8

BR 1

CC1 x

CC0 0

OV 0

OS –

OR x

STA 1

RLO 1

FC 1



12

Shift and Rotate Instructions Chapter Overview

Section

Description

12.1

Shift Instructions

12.2

Rotate Instructions


Page 12-2 12-10

12-1


12.1 Shift Instructions

Description

You can use the Shift instructions to move the contents of input IN bit by bit to the left or the right (see Section 2.3). Shifting n bits to the left multiplies the contents of input IN by 2 to the power n (2n); shifting n bits to the right divides the contents of input IN by 2 to the power n (2n). For example, if you shift the binary equivalent of the decimal value 3 to the left by 3 bits, you obtain the binary equivalent of the decimal value 24. If you shift the binary equivalent of the decimal value 16 to the right by 2 bits, you obtain the binary equivalent of the decimal value 4. The number that you supply for input parameter N indicates the number of bits by which the value is shifted. The bit places that are vacated by the Shift instruction are either padded with zeros or with the signal state of the sign bit (0 stands for positive and 1 stands for negative). The signal state of the bit that is shifted last is loaded into the CC1 bit of the status word (see Section 2.3). The CC0 and OV bits of the status word are reset to 0. You can use jump instructions to evaluate the CC1 bit. The following Shift instructions are available:

Shift Left Word, Shift Left Double Word Shift Right Word, Shift Right Double Word Shift Right Integer, Shift Right Double Integer Shift Left Word

A signal state of 1 at the Enable input (EN) activates the Shift Left Word instruction. This instruction shifts bits 0 to 15 of input IN bit by bit to the left. Input N specifies the number of bits by which to shift the value. If N is higher than 16, the command writes 0 to output OUT and sets the CC0 and OV bits of the status word to 0. The bit positions at the right are padded with zeros. The result of the shift operation can be scanned at output OUT. The operation triggered by this instruction always resets the CC0 and OV bits of the status word to 0 if the value of N is not equal to 0. ENO has the same signal state as EN.

12-2



Parameters:

15...

IN

...8

0 0 0 0

1 1 1 1

N

7...

...0

0 1 0 1

0 1 0 1

0 1 0 0

0 0 0 0

6 places 0 0 0 0 1

OUT

1

1 1 0 1

0 1 0 1

These six bits are lost.

The vacated places are padded with zeros.

Figure 12-1

Shifting the Bits of Input IN Six Bits to the Left

Table 12-1

Shift Left Word Box and Parameters

FBD Box

Parameters

SHL_W EN IN

OUT

N

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, L, D, T, C

Enable input

IN

WORD

I, Q, M, L, D

Value to be shifted

N

WORD

I, Q, M, L, D

Number of bit positions by which the value will be shifted

OUT

WORD

I, Q, M, L, D

Result of the shift instruction

ENO

BOOL

I, Q, M, L, D

Enable output

I0.0

SHL_W EN

MW0

IN

OUT

MW2

N

ENO

The instruction is activated if the signal state of I0.0 is 1.

MW4

Memory word MW0 is shifted to the left by the number of bits specified in memory word MW2.

Q4.0 S

The result is entered in memory word MW4.


Figure 12-2

BR x

CC1 x

CC0 x

OV x

OS –

OR x

STA x

RLO x

FC 1

Shift Left Word


12-3


Shift Left Double Word

A signal state of 1 at the Enable input (EN) activates the Shift Left Double Word instruction. This instruction shifts bits 0 to 31 of input IN bit by bit to the left. Input N specifies the number of bits by which the value will be shifted. If N is greater than 32, the command writes 0 to output OUT and sets the CC0 and OV bits of the status word to 0. The vacated bit positions at the right are padded with zeros. The result of the shift operation can be scanned at output OUT. The operation triggered by this instruction always resets the CC0 and OV bits of the status word to 0 if the value of N is not equal to 0. ENO has the same signal state as EN.

Table 12-2

Shift Left Double Word Box and Parameters Parameters

FBD Box SHL_DW SHL DW EN IN

OUT

N

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, L, D, T, C

Enable input

IN

DWORD

I, Q, M, L, D

Value to be shifted

N

WORD

I, Q, M, L, D


OUT

DWORD

I, Q, M, L, D


ENO

BOOL

I, Q, M, L, D

Enable output

The instruction is activated if the signal state of I0.0 is 1. SHL_DW I0.0

EN

MD0

IN

OUT

MW4

N

ENO

MD10

Memory double word MD0 is shifted to the left by the number of bits specified in memory word MW4. Q4.0 S

The result is entered in memory double word MD10.


12-4

BR x

CC1 x

CC0 x

OV x

OS –

OR x

STA x

RLO x

FC 1




Shift Right Word

A signal state of 1 at the Enable input (EN) activates the Shift Right Word instruction. This instruction shifts bits 0 to 15 of input IN bit by bit to the right. Bits 16 to 31 are not affected. Input N specifies the number of bits by which the value will be shifted. If N is greater than 16, the command writes 0 to output OUT and resets the CC0 and OV bits of the status word to 0. The vacated bit positions at the left are padded with zeros. The result of the shift operation can be scanned at output OUT. The operation triggered by this instruction always resets the CC0 and OV bits of the status word to 0 if N is not equal to zero. ENO has the same signal state as EN.

Table 12-3

Shift Right Word Box and Parameters Parameters

FBD Box SHR_W SHR W EN IN

OUT

N

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, L, D, T, C

Enable input

IN

WORD

I, Q, M, L, D

Value to be shifted

N

WORD

I, Q, M, L, D


OUT

WORD

I, Q, M, L, D


ENO

BOOL

I, Q, M, L, D

Enable output

The instruction is activated if the signal state of I0.0 is 1.

SHR_W I0.0

EN

MW0

IN

OUT

MW2

N

ENO

MW4

Memory word MW0 is shifted to the right by the number of bits specified in memory word MW2.

Q4.0 S



Figure 12-4

BR x

CC1 x

CC0 x

OV x

OS –

OR x

STA x

RLO x

FC 1

Shift Right Word


12-5


Shift Right Double Word

A signal state of 1 at the Enable input (EN) activates the Shift Right Double Word instruction. This instruction shifts bits 0 to 31 of input IN bit by bit to the right. Input N specifies the number of bits by which the value will be shifted. If N is higher than 32, the command writes 0 to output OUT and resets the CC0 and OV bits of the status word to 0. The vacated bit positions at the left are padded with zeros. The result of the shift operation can be scanned at output OUT. The operation triggered by this instruction always resets the CC1 and OV bits of the status word to 0 if N is not equal to zero. ENO has the same signal state as EN.

Parameters:

31...

...16 15...

...0

1111 1111 0101 0101 1010 1010 1111 1111

IN N

3 places

OUT

0001 1111 1110 1010 1011 0101 0101 1111 111 The vacated bit positions are padded with zeros.

These three bits are lost.

Figure 12-5

Shifting Bits of Input IN Three Bits to the Right

Table 12-4

Shift Right Double Word Box and Parameters

FBD Box SHR_DW SHR DW EN

12-6

IN

OUT

N

ENO

Parameters

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, L, D, T, C

Enable input

IN

DWORD

I, Q, M, L, D

Value to be shifted

N

WORD

I, Q, M, L, D


OUT

DWORD

I, Q, M, L, D


ENO

BOOL

I, Q, M, L, D

Enable output



The instruction is activated if the signal state of I0.0 is 1. SHR_DW I0.0

EN

MD0

IN

OUT

MW4

N

ENO

Memory double word MD0 is shifted to the right by the number of bits specified in memory word MW4.

MD10

Q4.0 S

The result is entered in MD10.


Figure 12-6

BR x

CC1 x

CC0 x

OV x

OS –

OR x

STA x

RLO x

FC 1


Shift Right Integer

A signal state of 1 at the Enable input (EN) activates the Shift Right Integer instruction. This instruction shifts bits 0 to 15 of input IN bit by bit to the right. Input N specifies the number of bits by which the value will be shifted. If N is higher than 16, the command behaves as if N were 16. The bit positions at the left are padded according to the signal state of bit 15 (the sign of an integer number). They are filled with zeros if the number is positive, and with ones if it is negative. The result of the shift operation can be scanned at output OUT. The operation triggered by this instruction always resets the CC0 and OV bits of the status word to 0 if N is not equal to zero. ENO has the same signal state as EN.

Parameters:

15...

IN

1

N

Sign bit

OUT

1

0

1

1 0

1

1

...8

7...

1

0

1

...0 0

0

0

1

0

1

0

1

1

1

0

0

0

0

4 places 1

1

1

0

1

0

1

The vacated bit positions are padded with the signal state of the sign bit.

Figure 12-7

1

0

1

0

These four bits are lost.

Shifting Bits of Input IN Four Bits to the Right with Sign


12-7


Table 12-5

Shift Right Integer Box and Parameters Parameters

FBD Box SHR_II SHR EN IN

OUT

N

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, L, D, T, C

Enable input

IN

INT

I, Q, M, L, D

Value to be shifted

N

WORD

I, Q, M, L, D


OUT

INT

I, Q, M, L, D


ENO

BOOL

I, Q, M, L, D

Enable output

The instruction is activated if the signal state of I0.0 is 1. SHR_I I0.0

EN

MW0

IN

OUT

MW2

N

ENO

MW4

Memory word MW0 is shifted to the right by the number of bits specified in memory word MW2. Q4.0 S



Figure 12-8

12-8

BR x

CC1 x

CC0 x

OV x

OS –

OR x

STA x

RLO x

FC 1

Shift Right Integer



Shift Right Double Integer

A signal state of 1 at the Enable input (EN) activates the Shift Right Double Integer instruction. This instruction shifts the entire contents of input IN bit by bit to the right. Input N specifies the number of bits by which the value will be shifted. If N is higher than 32, the command behaves as if N were 32. The bit positions at the left are padded according to the signal state of bit 31 (the sign of a double integer number). They are filled with zeros if the number is positive, and with ones if it is negative. The result of the shift operation can be scanned at output OUT. The operation triggered by this instruction always resets the CC0 and OV bits of the status word to 0 if N is not equal to zero. ENO has the same signal state as EN.

Table 12-6

Shift Right Double Integer Box and Parameters

FBD Box

Parameters

SHR_DI EN IN

OUT

N

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, L, D, T, C

Enable input

IN

DINT

I, Q, M, L, D

Value to be shifted

N

WORD

I, Q, M, L, D


OUT

DINT

I, Q, M, L, D


ENO

BOOL

I, Q, M, L, D

Enable output

The instruction is activated if the signal state of I0.0 is 1. SHR_DI I0.0

EN

MD0

IN

OUT

MW4

N

ENO

Memory double word MD0 is shifted to the right by the number of bits specified in memory word MW4. MD10

Q4.0 S



BR x

CC1 x

CC0 x

OV x

OS –

OR x

STA x

RLO x

FC 1



12-9


12.2 Rotate Instructions

Description

You can use the Rotate instructions to rotate the entire contents of input IN bit by bit to the left or to the right. The vacated bit positions are filled with the signal states of the bits that are shifted out of input IN. The number that you specify for input parameter N is the number of bits by which the value will be rotated. Depending on the instruction, rotation uses the CC1 bit of the status word (see Section 2.3). The CC0 bit of the status word is reset to 0. The following Rotate instructions are available:

Rotate Left Double Word Rotate Right Double Word Rotate Left Double Word

A signal state of 1 at the Enable input (EN) activates the Rotate Left Double Word instruction. This instruction rotates the entire contents of input IN bit by bit to the left. Input N specifies the number of bits by which to rotate. If N is higher than 32, the double word is rotated ((N–1) modulo 32) +1) places. The bit positions at the right are filled with the signal states of the bits rotated. The result of the rotate operation can be scanned at output OUT. The operation triggered by this instruction always resets the CC0 and OV bits of the status word to 0 if N is not equal to zero. ENO has the same signal state as EN.

31...

Parameters:

...16 15...

1111 0000 1010 1010 0000 1111 0000 1111

IN

3 places

N

OUT

111

1000 0101 0101 0000 0111 1000 0111 1111

The signal states of the three bits that are shifted out are inserted in the vacated positions.

Figure 12-10

12-10

...0

These three bits are lost.

Rotating Bits of Input IN Three Bits to the Left



Table 12-7

Rotate Left Double Word Box and Parameters Parameters

FBD Box ROL_DW ROL DW EN IN

OUT

N

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, L, D, T, C

Enable input

IN

DWORD

I, Q, M, L, D

Value to be rotated

N

WORD

I, Q, M, L, D

Number of bit positions by which the value will be rotated

OUT

DWORD

I, Q, M, L, D

Result of the rotate instruction

ENO

BOOL

I, Q, M, L, D

Enable output

The instruction is activated if the signal state of I0.0 is 1. ROL_DW I0.0

EN

MD0

IN

OUT

MW4

N

ENO

MD10

Memory double word MD0 is rotated to the left by the number of bits specified in memory word MW4. Q4.0 S



BR x

CC1 x

CC0 x

OV x

OS –

OR x

STA x

RLO x

FC 1

Rotate Left Double Word

Rotate Right Double Word

A signal state of 1 at the Enable input (EN) activates the Rotate Right Double Word instruction. This instruction rotates the entire contents of input IN bit by bit to the right. Input N specifies the number of bits by which the value will be rotated. The value of N can be between 0 and 31. If N is higher than 32, the double word is rotated ((N–1) modulo 32) +1) places. The bit positions at the left are filled with the signal states of the bits rotated. The result of the rotate operation can be scanned at output OUT. The operation triggered by this instruction always resets the CC0 and OV bits of the status word to 0 if N is not equal to zero. ENO has the same signal state as EN.


12-11


Parameters:

31...

...16 15...

...0

1010 1010 0000 1111 0000 1111 0101 0101

IN

3 places

N

1011 0101 0100 0001 1110 0001 1110 1010 101

OUT

The signal states of the three bits that are shifted out are inserted in the vacated places.

Figure 12-12

Rotating Bits of Input IN Three Bits to the Right

Table 12-8

Rotate Right Double Word Box and Parameters Parameters

FBD Box ROR_DW ROR DW EN IN

OUT

N

ENO

Data Type

Memory Area

Description

EN

BOOL

I, Q, M, L, D, T, C

Enable input

IN

DWORD

I, Q, M, L, D

Value to be rotated

N

WORD

I, Q, M, L, D

Number of bit positions by which the value will be rotated

OUT

DWORD

I, Q, M, L, D

Result of the rotate instruction

ENO

BOOL

I, Q, M, L, D

Enable output

The instruction is activated if the signal state of I0.0 is 1. ROR_DW I0.0

EN

MD0

IN

OUT

MW4

N

ENO

MD10

Memory double word MD0 is rotated to the right by the number of bits specified in memory word MW4. Q4.0 S



Figure 12-13

12-12

BR x

CC1 x

CC0 x

OV x

OS –

OR x

STA x

RLO x

FC 1



13

Data Block Instructions Chapter Overview

Section 13.1

Description Open Data Block


Page 13-2

13-1

Data Block Instructions

13.1 Open Data Block

Description

Table 13-1

You can use the Open Data Block instruction to open an existing data block as a shared data block (DB) or instance data block (DI). The number of the data block is transferred to the DB or DI register. The subsequent DB and DI commands access the corresponding blocks depending on the register contents.

Open Data Block Box and Parameters with SIMATIC Mnemonics

FBD Box

Parameters

Data Type

or

Number of the DB or DI

BLOCK_DB

Memory Area DB, DI

AUF

Table 13-2

Description Number of the DB or DI; Range depends on the CPU.

Open Data Block Box and Parameters with International Mnemonics

FBD Box

Parameter

or

Number of the DB or DI

Data Type

Memory Area

BLOCK_DB

DB, DI

Description Number of the DB or DI; Range depends on the CPU.

OPN

Network 1 DB10 is the currently opened data block. The scan at DBX0.0 therefore refers to bit 0 of data byte 0 of data block DB10. The signal state of this bit is assigned to output Q 4.0.

DB10 OPN Network 2 Q 4.0 DBX 0.0

= Status Word Bits

writes

BR –

CC1 –

CC0 –

OV –

OS –

OR –

STA –

RLO –

FC –

The instruction does not change the bits in the status word. Figure 13-1

13-2

Open Data Block


14

Jump Instructions Chapter Overview

Section

Description

Page

14.1

Overview

14-2

14.2

Unconditional Jump in a Block

14-3

14.3

Conditional Jump in a Block

14-4

14.4

Jump-If-Not

14-5

14.5

Jump Label

14-6


14-1

Jump Instructions

14.1 Overview

Jump Label as Address

The address of a Jump instruction is a label. A label consists of a maximum of four characters. The first character must be a letter; the other characters can be letters or numbers (for example, SEG3). The jump label indicates the destination to which you want the program to jump. You enter the label above the jump box (see Figure 14-1).

Jump Label as Destination

The destination label must be at the beginning of a network. You enter the destination label at the beginning of the network by selecting LABEL from the FBD list box. An empty box appears. In the box, you type the name of the label (see Figure 14-1).

Network1 SEG3 JMP

Network 2 Q4.0 I0.1

=

. . . Network X SEG3

I0.4

Figure 14-1

14-2

Q4.1 R

Jump Label as Address and Destination


Jump Instructions

14.2 Unconditional Jump in a Block

Description

The Unconditional Jump in a Block instruction corresponds to a “go to label” instruction. None of the instructions between the jump operation and the label is executed. You can use this instruction in all logic blocks, for example in organization blocks (OBs), function blocks (FBs) and functions (FCs). There must not be any logic operation before the Unconditional Jump in a Block box.

Table 14-1

Unconditional Jump in a Block Box and Parameters

FBD Box

Parameters

Data Type

Name of a jump – label

Memory Area –

Description The address specifies the label to which the program will jump unconditionally.

JMP

Network 1 CAS1 JMP

??.?

The jump is always executed. None of the instructions between the jump instruction and the label is executed.

. . . Network X CAS1 Q4.1 R

I0.4

Status Word Bits

writes

BR –

CC1 –

CC0 –

OV –

OS –

OR –

STA –

RLO –

FC –

The instruction does not change the bits in the status word. Figure 14-2

Unconditional Jump: Jump to Label


14-3

Jump Instructions

14.3 Conditional Jump in a Block

Description

The Conditional Jump in a Block instruction corresponds to a “go to label” instruction if the RLO is 1. The FBD element “Unconditional Jump” is also used for this operation, however it is made conditional by the preceding logic operation. The conditional jump is only executed when the result of this logic operation is 1. None of the instructions between the jump operation and the label is executed. You can use this instruction in all logic blocks, for example in organization blocks (OBs), function blocks (FBs) and functions (FCs).

Table 14-2

Conditional Jump in a Block Box and Parameters Parameters

Data Type

Name of a jump label

–

FBD Box
JMP

Memory Area –

Description The address specifies the label to which the program will jump if the RLO is 1.

Network 1 CAS1 JMP

I0.0

If the signal state of input I0.0 is 1, the jump to label CAS1 is executed. The instruction to reset output Q4.0 is not executed, even if the signal state of input I0.3 is 1.

Network 2 Q4.0 R

I0.3

Network 3 CAS1 Q4.1 R

I0.4

Status Word Bits

writes

Figure 14-3

14-4

BR –

CC1 –

CC0 –

OV –

OS –

OR 0

STA 1

RLO 1

FC 0

Conditional Jump: Jump in the Block If 1


Jump Instructions

14.4 Jump-If-Not

Description

The Jump-If-Not instruction corresponds to a “go to label” instruction that is executed if the RLO is 0. You can use this instruction in all logic blocks, for example in organization blocks (OBs), function blocks (FBs) and functions (FCs).

Table 14-3

Jump-If-Not Box and Parameters

FBD Box

Parameters

Data Type

Name of a jump – label

JMPN

Memory Area –

Description The address specifies the label to which the program will jump if the RLO is 0.

Network 1 CAS1 JMPN

I0.0

If the signal state of input I0.0 is 0, the jump to label CAS1 is executed. The instruction to reset output Q4.0 is not executed, even if the signal state of input I0.3 is 1.

Network 2 None of the instructions between the jump operation and the label is executed.

Q4.0 R

I0.3

Network 3 CAS1 Q4.1 R

I0.4

Status Word Bits

writes

Figure 14-4

BR –

CC1 –

CC0 –

OV –

OS –

OR 0

STA 1

RLO 1

FC 0

Jump-If-Not


14-5

Jump Instructions

14.5 Jump Label

Description

The jump label is the identifier for the destination of a jump instruction. A jump label must exist for every jump or jump-if-not instruction (JMP or JMPN).

Format

Description 4 characters:

LABEL

first character must be a letter remaining characters can be letters or numbers

Network 1 CAS1 JMP

I0.0

If I0.0 = 1, the jump to label CAS1 is executed. Due to the jump, the operation “Reset output” at Q 4.0 is not executed even if I0.3 = 1.

Network 2 Q4.0 R

I0.3

Network 3 CAS1

I0.4

Figure 14-5

14-6

Q4.1 R

Jump Label


15

Status Bit Instructions Chapter Overview

Section

Description

Page

15.1

Overview

15-2

15.2

Exception Bit Binary Result

15-3

15.3

Result Bits

15-4

15.4

Exception Bit Unordered

15-6

15.5

Exception Bit Overflow

15-7

15.6

Exception Bit Overflow Stored

15-8


15-1


15.1 Overview

Description

The status bit instructions are bit logic instructions (see Chapter 4) that work with the bits of the status word (see Section 2.3). Each of these instructions reacts to one of the following conditions that is indicated by one or more bits of the status word:

The binary result bit is set (has a signal state of 1). The result of a math function is relative to 0 in one of the following ways: – Greater than 0 (>0) – Less than 0 (<0) – Greater than or equal to 0 (>=0) – Less than or equal to 0 (<=0) – Equal to 0 (==0) – Not equal to 0 (<>0)

The result of a math function is unordered (invalid). A math function produced an overflow. In an AND operation, the status bit instructions combine the result of their signal state checks with the previous result of logic operation according to the And truth table (see Section 2.2 and Table 2-7). In an OR operation, the OR truth table is used (see Section 2.2 and Table 2-8). In this section, the Exception Bit Binary Result element, which checks the signal state of the BR (Binary Result) bit of the status word, is shown in its international and SIMATIC form.

Status Word

The status word is a register in the memory of your CPU that contains bits that you can reference in the address of bit and word logic instructions. Figure 15-1 shows the structure of the status word. For more information on the individual bits of the status word, see Section 2.3. 215...

Figure 15-1

Parameters

15-2

...29

28

27

26

25

BR

CC1

CC0

OV

24 OS

23

22

21

20

OR

STA

RLO FC

Structure of the Status Word

The FBD elements described in the following sections do not have any selectable parameters.



15.2 Exception Bit Binary Result

Description

You can use the Exception Bit Binary Result instruction to check the signal state of the BR bit (Binary Result) of the status word (see Section 2.3). In an AND operation, the result of the check is combined with the previous RLO according to the AND truth table (see Section 2.2 and Table 2-7). In an OR operation, the OR truth table is used (see Section 2.2 and Table 2-8).

FBD Box

Figure 15-2 shows the Exception Bit Binary Result box with SIMATIC and international short names.

SIMATIC element

International element

BIE

Figure 15-2

I0.0

& BR

Figure 15-3

Exception Bit Binary Result Box

>=1

I0.2

BR

Q4.0 S

Output Q4.0 is set if the signal state at input I0.0 is 1 OR the signal state at input I0.2 is 0, and, in addition to this RLO, the signal state of the BR bit is 1.



15-3


15.3 Result Bits

Description

You can use the Result Bit instructions to determine the relationship of the result of a math function to zero, in other words, whether the result is >0, <0, >=0, <=0, ==0, or <>0 (see Table 15-1). The condition code bits of the status word (CC 1 and CC 0, see Section 2.3) are evaluated. If the comparison condition indicated in the address is fulfilled, the result of this signal state check is 1. In an AND operation, this instruction combines the result of its check with the previous result of logic operation (RLO) according to the AND truth table (see Section 2.2 and Table 2-7). In an OR operation, this instruction combines the result of its check with the previous RLO according to the OR truth table (see Section 2.2 and Table 2-8).

Table 15-1

Result Bits Boxes

FBD Element

Description

>0

The Result Bit instruction for greater than 0 determines whether or not the result of a math instruction is greater than 0. It checks the combination in the condition code bits CC1 and CC0 in the status word to determine the relationship of a result to 0.

<0

The Result Bit instruction for less than 0 determines whether or not the result of a math instruction is less than 0. It checks the combination in the condition code bits CC1 and CC0 in the status word to determine the relationship of a result to 0.

>=0

The Result Bit instruction for greater than or equal to 0 determines whether or not the result of a math instruction greater than or equal to 0. It checks the combination in the condition code bits CC1 and CC0 in the status word to determine the relationship of a result to 0.

<=0

The Result Bit instruction for less than or equal to 0 determines whether or not the result of a math instruction is less than or equal to 0. It checks the combination in the condition code bits CC1 and CC0 in the status word to determine the relationship of a result to 0.

== 0

The Result Bit instruction for equal to 0 determines whether or not the result of a math instruction is equal to 0. It checks the combination in the condition code bits CC1 and CC0 in the status word to determine the relationship of a result to 0.

<>0

The Result Bit instruction for not equal to 0 determines whether or not the result of a math instruction is not equal to 0. It checks the combination in the condition code bits CC1 and CC0 in the status word to determine the relationship of a result to 0.

15-4



1)

If the signal state at input I0.0 is 1, the SUB_I box is activated. If the value of input word IW0 is greater than the value of input word IW2, the result of the math function IW0 – IW2 is greater than 0.

SUB_I I0.0

EN

IW0

IN1

OUT

IW2

IN2

ENO

MW10 & Q4.0 S

>0

1) Output Q4.0 is set if the function is executed correctly and the result is less than or equal to 0. If the signal state of input I0.0 is 0 (not activated), the signal state of both EN and ENO is 0.

2) SUB_I I0.0

EN

IW0

IN1

OUT

IW2

IN2

ENO

If the signal state of EN is 1 (activated) and an error occurs while the instruction is being executed, the signal state of ENO is 0.

2) Output Q4.0 is set if the function is executed correctly and the result is less than or equal to 0. If the signal state of input I0.0 is 0 (not activated), the signal state of both EN and ENO is 0.

MW10 & Q4.0 S

≤0

Status Word Bits

writes Figure 15-4

BR –

CC1 –

CC0 –

OV –

OS –

OR x

STA x

RLO x

FC 1

Result Bit for Greater than 0 and Negated Result Bit for Greater than 0


15-5


15.4 Exception Bit Unordered

Description

You can use the Exception Bit Unordered instruction to check whether or not the result of a floating-point math function is unordered (in other words, whether one of the values in the math function is not a valid floating-point number). The condition code bits of the status word (CC 1 and CC 0, see Section 2.3) are evaluated. If the result of the math function is unordered (UO) the signal state check produces a result of 1. If the combination in CC 1 and CC 0 does not indicate unordered, the result of the signal state check is 0. In an AND operation, this instruction combines the result of its check with the previous result of logic operation (RLO, see Section 2.3) according to the AND truth table (see Section 2.2 and Table 2-7). In an OR operation, the OR truth table is used (see Section 2.2 and Table 2-8).

FBD Box UO

Figure 15-5

Exception Bit Unordered Box

Network 1:

I0.0

DIV_R EN

ID0

IN1

OUT

ID4

IN2

ENO

MD10

Network 2: UO

Figure 15-6

15-6

Q4.0 S

Q4.1 S

If the signal state at input I0.0 is 1, the DIV_R box is activated. If the value of either input double word ID0 or ID4 is not a valid floating-point number, the floating-point math function is unordered. If the signal state of EN is 1 (activated) and an error occurs while the instruction is being executed, the signal state of ENO is 0. Output Q4.0 is set if the function DIV_R is executed, but one of the values in the math function is not a valid floating-point number. If the signal state of input I0.0 is 0 (not activated), the signal state of both EN and ENO is 0.




15.5 Exception Bit Overflow

Description

You can use the Exception Bit Overflow instruction to detect an overflow (OV) in the last math function. If, after the system executes a math function, the result is outside the permitted negative range or outside the permitted positive range, the OV bit in the status word (see Section 2.3) is set. The instruction checks the signal state of this bit. This bit is reset if the math functions were free of errors In an AND operation, this instruction combines the result of its check with the previous result of logic operation according to the AND truth table (see Section 2.2 and Table 2-7). In an OR operation, the OR truth table is used (see Section 2.2 and Table 2-8).

FBD Box OV

Figure 15-7

If the signal state at input I0.0 is 1, the SUB_I box is activated. If the result of the math function input word IW0 minus input word IW2 is outside the permitted range for an integer, the OV bit in the status word is set.

Network 1: SUB_I I0.0

EN

IW0

IN1

OUT

IW2

IN2

ENO

Exception Bit Overflow Box

MW10

The result of a signal state check at OV is 1. Output Q4.0 is set if the check at OV is 1 and the RLO of network 2 is 1 (if the RLO prior to output Q4.0 is 1). If the signal state of input I0.0 is 0 (not activated), the signal state of both EN and ENO is 0. If the signal state of EN is 1 (activated) and the result of the math function is out of range, the signal state of ENO is 0.

Network 2: &

I0.1 I0.2

>=1 I0.3

M 3.3

Network 3: OV

Figure 15-8

Q4.0 S



15-7


15.6 Exception Bit Overflow Stored

Description

You can use the Exception Bit Overflow Stored instruction to recognize a previous overflow (overflow stored, OS) in a math function. If, after the system executes a math function, the result is outside the permitted negative range or outside the permitted positive range, the OS bit in the status word (see Section 2.3) is set. The instruction checks the signal state of this bit. Unlike the OV (overflow) bit, the OS bit remains set even if later math functions were executed free of errors (see Section 15.5). In an AND operation, this instruction combines the result of its check with the previous result of logic operation according to the AND truth table (see Section 2.2 and Table 2-7). In an OR operation, the OR truth table is used (see Section 2.2 and Table 2-8).

FBD Box OS

Figure 15-9

15-8

Exception Bit Overflow Stored Box



Network 1: MUL_I I0.0

EN

IW0

IN1

OUT

IW2

IN2

ENO

MD8

If the signal state at input I0.0 is 1, the MUL_I box is activated. If the signal state at input I0.1 is 1, the ADD_I box is activated. If the result of one of the math functions is outside the permissible range for an integer, the OS bit in the status word is set. The result of a signal state check at OS is 1 and output Q4.0 is set. Network 1: if the signal state of input I0.0 is 0 (not activated), the signal state of both EN and ENO is 0. If the signal state of EN is 1 (activated) and the result of the math function is out of range, the signal state of ENO is 0.

Network 2: ADD_I I0.1

EN

IW0

IN1

OUT

IW2

IN2

ENO

MW12

Network 2: if the signal state of input I0.1 is 0 (not activated), the signal state of both EN and ENO is 0. If the signal state of EN is 1 (activated) and the result of the math function is out of range, the signal state of ENO is 0.

Network 3: OS

Figure 15-10

Q4.0 S



15-9


15-10


Program Control Instructions Chapter Overview

Section

Description

16 Page

16.1

Calling an FC/SFC without Parameters

16-2

16.2

Calling an FB, FC, SFB, SFC, and Multiple Instances

16-4

16.3

Return

16-7

16.4

Master Control Relay Instructions

16-8

16.5

Master Control Relay Activate/Deactivate

16-10

16.6

Master Control Relay On/Off

16-13


16-1


16.1 Calling an FC/SFC without Parameters

Description

With the Call FC/SFC without Parameters instruction, you can call a function (FC) or a system function (SFC) that has no parameters. The call is conditional or unconditional depending on the preceding logic operation (see the example). In the code section of a function (FC), you cannot specify any parameter of the type BLOCK_FC as the address for a conditional call. You can, however, specify a parameter of the type BLOCK_FC as the address in a function block (FB). A conditional call is executed only if the RLO is 1. If a conditional call is not executed, the RLO after the call instruction is 0. If the instruction is executed, the following functions are performed:

The address required to return to the calling block is saved. The data block registers are saved (data block and instance data block). The previous local data area is replaced by the current local data area. The MA bit (active MCR bit) is written to the block stack (BSTACK). The new local data area is created for the called FC or SFC. Program execution is then continued in the called block. For more detailed information about transferring parameters, refer to the STEP 7 Online Help. Table 16-1

Calling an FC/SFC without Parameters Box

FBD Box Parameters

Data Type

Memory Area

CALL

16-2

Number

BLOCK_FC

–

Description Number of the FC or SFC (for example FC10 or SFC59). The SFCs that are available depend on your CPU. A conditional call with a parameter of the data type BLOCK_FC as the address is only possible in an FB and not in an FC.



DB10 OPN MCRA FC10 CALL

I0.0

Q4.0 = MCRD

I0.1

FC11 CALL

If the unconditional call for FC10 is executed, the CALL instruction performs the following functions:

Saves the address required to return to the current FB. Saves the selectors for DB10 and for the instance data block of the FB. Pushes the MA bit, set to 1 in the MCRA instruction, to the block stack (BSTACK) and resets this bit to 0 for the called FC10 Program execution continues in FC10. If you want to use the MCR function in FC10, you must reactivate it there. When FC10 is completed, program execution returns to the calling FB. The MA bit is restored. DB10 and the instance data block of the user-defined FB are the current DBs again, regardless of which DBs were used by FC10. After the return jump from FC10, the signal state of input I0.0 is assigned to output Q4.0. The call for FC11 is a conditional call. It is executed only if the signal state of input I0.1 is 1. If the call is executed, the function is the same as for calling FC10.

Status Word Bits Unconditional call writes

Conditional call writes

Figure 16-1

BR –

CC1 –

CC0 –

OV –

OS 0

OR 0

STA 1

RLO –

FC 0

BR –

CC1 –

CC0 –

OV –

OS 0

OR 0

STA 1

RLO 1

FC 0

Calling an FC/SFC without Parameters


16-3


16.2 Calling an FB, FC, SFB, SFC, and Multiple Instances

Description

You can call function blocks (FBs), functions (FCs), system function blocks (SFBs), and system functions (SFCs), and multiple instances by selecting them from the “Program Elements” list box. They are at the end of the list of instruction families under the following names:

FB Blocks FC Blocks SFB Blocks SFC Blocks Multiple Instances Libraries When you select one of these blocks, a box appears on your screen with the number or symbolic name of the function or function block and the parameters that belong to it. The block that you call must have been compiled and must already exist in your program file, in the library, or on the CPU. If the call FB, FC, SFB, SFC, and multiple instances instruction is executed, it performs the following functions:

It saves the address required to return to the calling block. It saves both data block registers (data block and instance data block). It replaces the previous local data area with the current local data area. It shifts the MA bit (active MCR bit) to the block stack (BSTACK). It creates the new local data area for the called FC or SFC. Note When the DB and DI registers are saved, it is possible that they do not point to the data blocks that you opened. Because of the copy mechanisms for transferring parameters, especially where function blocks are concerned, the compiler sometimes overwrites the DB register. See the STEP 7 Online Help for more details.

Execution of the program then continues in the called block.

16-4



Enable Output

The Enable output (ENO) of an FBD box corresponds to the BR bit of the status word (see Section 2.3). When you write a function block or function that you want to call from FBD regardless of whether you write the FB or FC in STL, LAD or FBD, keep in mind the BR bit. You save the RLO in the BR bit with the SAVE instruction according to the following criteria:

Save an RLO of 1 in the BR bit when the FB or FC is executed without error.

Save an RLO of 0 in the BR bit when an error occurs in the execution of the FB or FC. You should program these instructions at the end of the FB or FC so that these are the last instructions that are executed in the block.

!

Warning Unintentionally resetting the BR bit to 0 When writing FBs and FCs in FBD, if you do not handle the BR bit as described above, one FB or FC may overwrite the BR bit of another FB or FC. To avoid this problem, store the RLO at the end of each FB or FC as described above.

Effect of the Call on the Bits of the Status Word

Conditional: writes Unconditional: writes

Figure 16-2

Figure 16-2 shows the effects of a conditional and an unconditional call of a block on the bits of the status word (see Section 2.3).

BR x –

CC1 – –

CC0 – –

OV – –

OS 0 0

OR 0 0

STA 1 x

RLO x x

FC x x

Effect of a Block Call on the Bits of the Status Word


16-5


Parameters

The parameters that have been defined in the VAR section of the block will be displayed in the FBD box. Supplying parameters differs depending on the type of block as follows:

For a function (FC), you must supply actual parameters for all of the formal parameters.

The entry of actual parameters is optional with function blocks (FBs). You must, however, attach an instance data block (instance DB) to the FB. If an actual parameter has not been attached to a formal parameter, the FB works with the values that exist in its instance DB.

With multiple instances, you do not need to specify the instance DB since the box that is called has already been assigned the DB number (for more information about declaring multiple instances, refer to STEP 7 Online Help For structured IN/OUT parameters and parameters of the types “Pointer” and “Array”, you must make an actual parameter available (at least during the first call). Every actual parameter that you make available when calling a function block must have the same data type as its formal parameter. For information on how to program a function or how to work with its parameters, see the STEP 7 Online Help. Table 16-2 shows a box for calling FBs, FCs, SFBs, SFCs and describes the parameters common to the box for all these blocks. The block number appears automatically at the top of the block (number of the FB, FC, SFB, or SFC, for example, FC10). Table 16-2

Box and Parameters for Calling FBs, FCs, SFBs, SFCs

FBD Box DB no. Block no. EN IN OUT IN/OUT ENO

Parameters

Data Type

Memory Area

Description

DB no.

BLOCK_DB

–

Data block number. This information is only necessary for calling FBs.

EN

BOOL

I, Q, M, D, L, T, C

Enable input

ENO

BOOL

I, Q, M, D, L

Enable output

DB13 Calls FB10 (using instance DB13)

FB10 Actual addresses, the values of which are copied into instance data block DB13 before processing FB10.

I 1.0

EN Start

I 1.1

Stop

MW20

Length

ENO Run

M2.1

The value of this parameter is copied from DB13 into M 2.1 after processing FB10.

Formal parameters of the FB Figure 16-3

16-6

Call FB as Box



16.3 Return

Description

Table 16-3

You can use the Return instruction to exit blocks. You can exit a block conditionally. Box Return Parameters

FBD Box RET

None

I0.0

Data Type –

Memory Area –

RET

Description –

If the signal state of input I0.0 is 1, the block is exited.

Status Word Bits Conditional Return (Return if RLO = 1) writes

Figure 16-4

BR –

CC1 –

CC0 –

OV –

OS 0

OR 0

STA 1

RLO 1

FC 0

Return


16-7


16.4 Master Control Relay Instructions

Definition of the Master Control Relay

The Master Control Relay (MCR, see also Section 16.5) is used to activate and deactivate signal flow. A deactivated signal flow corresponds to an instruction sequence that writes a zero value instead of the calculated value, or to an instruction sequence that leaves the existing memory value unchanged. Operations triggered by the instructions shown in Table 16-4 are dependent on the MCR. The Assign and Midline Output instructions write a 0 to the memory if the MCR is 0. The Set Output and Reset Output instructions leave the existing value unchanged (see Table 16-5).

Table 16-4

Instructions Influenced by an MCR Zone FBD Box

Description

#

Midline Output

4.9

=

Assign

4.8

S

Set Output

4.11

R

Reset Output

4.12

Set_Reset Flip Flop

4.25

Set_Reset Flip Flop

4.26

Assign a Value

10.1

SR RS MOVE

Table 16-5

Instructions Dependent on MCR and How They React to Its Signal State

Signal State of MCR

Assign, Midline Output = #

0

1

16-8

Section in This Manual

Writes 0

Set or Reset Output S

R

SR

RS

Does not write

Assign a Value

MOVE

Writes 0

(Imitates a relay that falls to its (Imitates a latching relay that quiet state when power is remains in its current state turned off) when power is turned off)

(Imitates a component that produces a value of 0 when power is turned off)

Normal execution

Normal execution

Normal execution



Important Notes on Using MCR Functions Take care with blocks in which the Master Control Relay was activated with MCRA:

If the MCR is deactivated, the value 0 is written by all assignments in program segments between (MCR<) and (MCR>)!

The MCR is deactivated if the RLO was =0 before an MCR< instruction.

!

Danger PLC in STOP or undefined runtime characteristics! The compiler also uses write access to local data behind the temporary variables defined in VAR_TEMP for calculating addresses. This means the following command sequences will set the PLC to STOP or lead to undefined runtime characteristics: Formal parameter access Access to components of complex FC parameters of the type STRUCT, UDT, ARRAY, STRING Access to components of complex FB parameters of the type STRUCT, UDT, ARRAY, STRING from the IN_OUT area in a version 2 block. Access to parameters of a version 2 function block if its address is greater than 8180.0. Access in a version 2 function block to a parameter of the type BLOCK_DB opens DB0. Any subsequent data access sets the CPU to STOP. T 0, C 0, FC0, or FB0 are also always used for TIMER, COUNTER, BLOCK_FC, and BLOCK_FB. Parameter passing

Calls in which parameters are transferred. KOP/FUP T branches and midline outputs in Ladder or FBD starting with RLO = 0.

Remedy Free the above commands from their dependence on the MCR: 1. Deactivate the Master Control Relay using the Master Control Relay Deactivate instruction before the statement or network in question. 2. Activate the Master Control Relay again using the Master Control Relay Activate instruction after the statement or network in question.


16-9


16.5 Master Control Relay Activate/Deactivate

MCR Activate

Table 16-6

Master Control Relay Activate Box

FBD Box MCRA

MCR Deactivate

Table 16-7

With the Activate Master Control Relay, instruction, you make subsequent commands dependent on the MCR. After entering this command, you can program the MCR zones with these instructions (see Section 16.6). When your program activates an MCR area, all MCR actions depend on the content of the MCR stack (see Figure B-4).

Parameters None

Data Type –

Memory Area –

Description Activates the MCR function

With the Deactivate Master Control Relay instruction, subsequent commands are no longer dependent on the MCR. After this instruction, you cannot program any more MCR zones. When your program deactivates an MCR area, the MCR is always energized irrespective of the entries in the MCR stack.

Master Control Relay Deactivate Box

FBD Box MCRD

Parameters None

Data Type –

Memory Area –

Description Deactivates the MCR function

The MCR stack and the bit that controls its dependency (the MA bit) relate to individual levels and must be saved and fetched every time you change the sequence level. They are preset at the beginning of every sequence level (MCR input bits 1 to 8 are set to 1, the MCR stack pointer is set to 0 and the MA bit is set to 0). The MCR stack is transferred from block to block and the MA bit is saved and set to 0 every time a block is called. It is fetched back at the end of the block. The MCR can be implemented in such a way that it optimizes the run time of code-generating CPUs. The reason for this is that the dependency of the MCR is not passed on by the block; it must be explicitly activated by an MCR instruction. A code-generating CPU recognizes this instruction and generates the additional code necessary for the evaluation of the MCR stack until it recognizes an MCR instruction or reaches the end of the block. With instructions outside the MCRA/MCRD range, there is no increase of the run time. The instructions MCRA and MCRD must always be used in pairs within your program.

16-10



ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ OB1

MCRA

ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ FBx

ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ ÀÀÀÀÀÀ FCy

MCRA

ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ MCRD

MCRA

Call FCy

Call FBx

MCRD

BEU

MCRA

BEU

Operations not dependent on the MCR bit Operations dependent on the MCR bit BEU

Figure 16-5

BEU is an STL instruction. You will find more details in the STL Manual /232/ Activating and Deactivating an MCR Area

The operations programmed between MCRA and MCRD depend on the signal state of the MCR bit. Operations programmed outside an MCRA-MCRD sequence do not depend on the signal state of the MCR bit. If an MCRD instruction is missing, the operations programmed between the instructions MCRA and BEU depend on the MCR bit.


16-11


MCRA I0.0

MCR<

I0.3

Q4.0 S

I0.4

Q4.1 = MCR> MCRD

The MCRA instruction activates the MCR function until the next MCRD. The instructions between MCR< and MCR> are processed dependent on the MA bit (here I0.0):

If the signal state of input I0.0 is 1: – – –

Output Q4.0 is set to 1 if the signal state of input I0.3 is 1. Output Q4.0 remains unchanged if the signal state of input I0.3 is 0. The signal state of input I0.4 is assigned to output Q4.1.

If the signal state of input I0.0 is 0: – –

Output Q4.0 remains unchanged regardless of the signal state of input I0.3. Output Q4.1 is 0 regardless of the signal state of input I0.4. Status Word Bits

writes Figure 16-6

BR –

CC1 –

CC0 –

OV –

OS –

OR –

STA –

RLO –

FC –

Master Control Relay (Activate and Deactivate)

You must program the dependency of the functions (FCs) and function blocks (FBs) in the blocks yourself. If this function or function block is called from an MCRA/MCRD sequence, not all instructions within this sequence are automatically dependent on the MCR bit. To achieve this, use the instruction MCRA of the block called.

!

Warning Risk of personal injury and damage to equipment: Never use the instruction MCR as an EMERGENCY OFF or safety device for personnel. MCR is not a substitute for a hardwired master control relay.

16-12



16.6 Master Control Relay On/Off

MCR On

Table 16-8

The Master Control Relay On (MCR<) instruction triggers an operation that saves the RLO in the MCR stack and opens an MCR zone. The instructions shown in Table 16-4 are influenced by this RLO saved in the MCR stack when the MCR zone is opened. The MCR stack works like a LIFO (Last In, First Out) buffer. Only eight entries are possible. If the stack is already full, the Master Control Relay On instruction produces an MCR stack error (MCRF). Master Control Relay On Box

FBD Box MCR<

MCR Off

Table 16-9

Parameters None

Data Type –

Memory Area –

Description Opens an MCR zone

The Master Control Relay Off (MCR>) instruction closes the MCR zone that was opened last. The instruction does this by removing the RLO entry from the MCR stack. The RLO was saved there by the Master Control Relay On instruction. The entry released at the other end of the LIFO (Last In, First Out) MCR stack is set to 1. If the stack is already empty, the Master Control Relay Off instruction produces an MCR stack error (MCRF). Master Control Relay Off

FBD Box MCR>

Parameters None

Data Type –

Memory Area –

Description Closes the MCR zone that was opened last

The MCR is controlled by a stack which is one bit wide and eight entries deep (see Figure 16-7). The MCR is activated as long as all eight entries in the stack are equal to 1. The MCR< instruction copies the RLO to the MCR stack. The MCR> instruction removes the last entry from the stack and sets the released stack address to 1. If an error occurs, for example, if there are more than eight MCR> instructions in succession, or you attempt to execute the instruction MCR> when the stack is empty, the MCRF error message is activated. The monitoring of the MCR stack is based on the stack pointer (MSP: 0 = empty, 1 = one entry, 2 = two entries, ..., 8 = eight entries).


16-13


RLO Shifted bit # "

MSP !

RLO RLO

1

RLO

3

2 4 5 6 7

Shifted bit

8 "

# 1 MA "

MCRA 1

" 0 MCRD

MSP = MCR stack pointer MA = Bit controlling MCR dependency Figure 16-7

Master Control Relay Stack

The instructions MCR< and MCR> must always be used in pairs within your program. The MCR< instruction adopts the signal state of the RLO and copies it to the MCR bit. The MCR> instruction sets the MCR bit to 1 unconditionally. Because of this characteristic, every other instruction between the instructions MCRA and MCRD operates independent of the MCR bit (for information about MCRA and MCRD, see above).

Nesting the Instructions MCR< and MCR>

You can nest the instructions MCR< and MCR>. The maximum nesting depth is eight, in other words, you can write a maximum of eight MCR< instructions in succession before inserting an MCR> instruction. You must program an equal number of MCR< and MCR> instructions. If the MCR< instructions are nested, the MCR bit of the lower nesting level is formed. The MCR< instruction then combines the current RLO with the current MCR bit according to the AND truth table. When an MCR> instruction completes a nesting level, it fetches the MCR bit from the next highest level.

16-14



MCRA I0.0

MCR<

I0.1

MCR< Q4.0 S

I0.3

MCR> Q4.1 =

I0.4

MCR> MCRD

When the MCRA instruction activates the MCR function, you can create up to eight nested MCR zones. In the example, there are two MCR zones. The first MCR> instruction works together with the second MCR< instruction. All instructions between the second set of MCR brackets (MCR) belong to the second MCR zone. The operations are executed as follows: If I0.0 = 1: the signal state of input I0.4 is assigned to output Q4.1. If I0.0 = 0: the signal state of output Q4.1 is 0 regardless of the signal state of input I0.4. Output Q4.0 remains unchanged regardless of the signal state of input I0.3. If I0.0 and I0.1 = 1: output Q4.0 is set to 1 if I0.3 = 1 and Q4.1 = I0.4. If I0.1 = 0: output Q4.0 remains unchanged regardless of the signal state of input I0.3 and input I0.0.

Status Word Bits

writes Figure 16-8

BR –

CC1 –

CC0 –

OV –

OS –

OR 0

STA 1

RLO –

FC 0

Master Control Relay Off


16-15


16-16


Appendix

Alphabetical Lists of Instructions

A

Programming Examples

B

References

C

P-18


Alphabetical Lists of Instructions Chapter Overview

Section

Description

A Page

A.1

List of Instructions with International Names

A-2

A.2

List of Instructions with International (English) Names and German Equivalents

A-6

A.3

List of Instructions with German SIMATIC Names

A-10

A.4

List of Instructions with German Names and International (English) Equivalents

A-14


A-1

Alphabetical List of Instructions

A.1

List of Instructions with International Names Table A-1 contains an alphabetical list of FBD instructions with international (English) full names, the corresponding short name or mnemonic, and the reference to the page on which the instruction is described.

Table A-1

FBD Instructions Arranged Alphabetically by International (English) Full Names with Short Names Short Name

Full Name

Page

Add Double Integer

ADD_DI

7-3

Add Integer

ADD_I

7-2

Add Real

ADD_R

8-3


NEG

4-31


POS

4-30

AND

&

4-3

Assign

=

4-9

Assign a Value

MOVE

10-2


BCD_DI

10-6

BCD to Integer

BCD_I

10-3

Call FB from Box

CALL_FB

16-4

Call FC from Box

CALL_FC

16-4

Call FC SFC (without parameters)

CALL

16-2

Call System FB from Box

CALL_SFB

16-4

Call System FC from Box

CALL_SFC

16-4

Ceiling

CEIL

10-16

Compare Double Integer (>, <, ==, <>, <=, >=)

CMP >=D

9-3

Compare Integer (>, <, ==, <>, <=, >=)

CMP >=I

9-2

Compare Real (>, <, ==, <>, <=, >=)

CMP >=R

9-4


DIV_DI

7-9

Divide Integer

DIV_I

7-8

Divide Real

DIV_R

8-6


DI_BCD

10-7


DI_R

10-8

Down Counter (counter instruction)

S_CD

6-7

Down Counter (bit logic instruction)

CD

4-17


BR

15-3


OV

15-7


OS

15-8


UO

15-6

Exclusive OR

XOR

4-6

Extended Pulse S5 Timer (timer instruction)

S_PEXT

5-7

A-2



Table A-1

FBD Instructions Arranged Alphabetically by International (English) Full Names with Short Names, cont. Full Name

Short Name

Page

Extended Pulse Timer (bit logic instruction)

SE

4-20

Floor

FLOOR

10-17

Form the Absolute Value of a Floating-Point Number

ABS

8-8

Form the Arc Cosine of a Floating-Point Number

ACOS

8-13

Form the Arc Sine of a Floating-Point Number

ASIN

8-13

Form the Arc Tangent of a Floating-Point Number

ATAN

8-13

Form the Cosine of a Floating-Point Number

COS

8-13

Form the Exponential Value of a Floating-Point Number

EXP

8-12

Form the Natural Logarithm of a Floating-Point Number

LN

8-11

Form the Sine of a Floating-Point Number

SIN

8-13

Form the Square of a Floating-Point Number

SQR

8-9

Form the Square Root of a Floating-Point Number

SQRT

8-10

Form the Tangent of a Floating-Point Number

TAN

8-13

Insert Binary Input

–––|

4-7

Integer to BCD

I_BCD

10-4


I_DI

10-5

Jump

JMP

14-3

Jump-If-Not

JMPN

14-5

Master Control Relay Activate

MCRA

16-10

Master Control Relay Deactivate

MCRD

16-10


MCR>

16-13

Master Control Relay On

MCR<

16-13

Midline Output

#

4-10


MUL_DI

7-7

Multiply Integer

MUL_I

7-6

Multiply Real

MUL_R

8-5

Negate Binary Input

–––o|

4-8

Negate Real Number

NEG_R

10-13


N

4-29

Off-Delay S5 Timer (timer instruction)

S_OFFDT

5-13

Off-Delay Timer (bit logic instruction)

SF

4-26

On-Delay S5 Timer (timer instruction)

S_ODT

5-9

On-Delay Timer (bit logic instruction)

SD

4-22


INV_DI

10-10


INV_I

10-9

Open Data Block: DB or DI

OPN

13-2

OR

>=1

4-4


A-3


Table A-1


Short Name

Page


P

4-28

Pulse S5 Timer (timer instruction)

S_PULSE

5-5

Pulse Timer (bit logic instruction)

SP

4-18

Reset Output

R

4-13

Reset_Set Flip Flop

RS

4-33

Result Bit Equal 0

==0

1-6

Result Bit Greater Equal 0

>=0

15-4

Result Bit Greater Than 0

>0

15-4

Result Bit Less Equal 0

<=0

15-4

Result Bit Less Than 0

<0

15-4

Result Bit Not Equal 0

<>0

15-4

Retentive On-Delay S5 Timer (timer instruction)

S_ODTS

5-11

Retentive On-Delay Timer (bit logic instruction)

SS

4-24

Return

RET

16-7


MOD

7-10


ROL_DW

12-11


ROR_DW

12-12


ROUND

10-14


SAVE

4-11

Set Output

S

4-12

Set Counter Value

SC

4-14

Set_Reset Flip Flop

SR

4-32


SHL_DW

12-4

Shift Left Word

SHL_W

12-3


SHR_DI

12-9


SHR_DW

12-6

Shift Right Integer

SHR_I

12-8

Shift Right Word

SHR_W

12-5


SUB_DI

7-5

Subtract Integer

SUB_I

7-4

Subtract Real

SUB_R

8-4


TRUNC

10-15


NEG_DI

10-12


NEG_I

10-11

Up Counter (counter instruction)

S_CU

6-5

Up Counter (bit logic instruction)

CU

4-16

Up-Down Counter

S_CUD

6-3

A-4



Table A-1


Short Name

Page


WAND_DW

11-4

(Word) AND Word

WAND_W

11-3


WXOR_DW

11-8


WXOR_W

11-7


WOR_DW

11-6

(Word) OR Word

WOR_W

11-5


A-5


A.2

List of Instructions with International (English) Names and German Equivalents Table A-4 contains an alphabetical list of FBD instructions with international (English) full names, the German SIMATIC equivalents, and the reference to the page on which the instruction is described.

Table A-2

FBD Instructions Arranged Alphabetically by International (English) Full Names with German Equivalents Full Name

German SIMATIC Equivalent

Page

Add Double Integer

Ganze Zahlen addieren (32 Bit)

7-3

Add Integer


7-2

Add Real

Gleitpunktzahlen addieren

8-3


Signalflanke 1 → 0 abfragen

4-31



4-30

AND

UND-Verknüpfung

4-3

Assign

Zuweisung

4-9

Assign a Value

Wert übertragen

10-2


BCD-Zahl in Ganzzahl (32 Bit) wandeln

10-6

BCD to Integer


10-3

Call FB from Box

FB aufrufen

16-4

Call FC from Box

FC aufrufen

16-4


FC/SFC aufrufen ohne Parameter

16-2


System FB aufrufen

16-4


System FC Box aufrufen

16-4

Ceiling

Aus Gleitpunktzahl nächsthöhere Ganzzahl erzeugen

10-16


Ganze Zahlen vergleichen (32 Bit)

9-3

Compare Integer (>, <, ==, <>, <=, >=)


9-2

Compare Real (>, <, ==, <>, <=, >=)

Gleitpunktzahlen vergleichen

9-4


Ganze Zahlen dividieren (32 Bit)

7-9

Divide Integer


7-8

Divide Real

Gleitpunktzahlen dividieren

8-6


Ganzzahl (32 Bit) in BCD-Zahl wandeln

10-7


Ganzzahl (32 Bit) in Gleitpunktzahl wandeln

10-8


Rückwärtszählen

6-7


Rückwärtszählen

4-17


Störungsbit BIE-Register

15-3


Störungsbit Überlauf

15-7


Störungsbit Überlauf gespeichert

15-8


Störungsbit Ungültige Operation

15-6

A-6



Table A-2

FBD Instructions Arranged Alphabetically by International (English) Full Names with German Equivalents, cont. Full Name


Page

Exclusive OR

EXKLUSIV-ODER-Verknüpfung

4-6


Zeit als verlängerten Impuls starten (SV)

5-7


Zeit als verlängerten Impuls starten (SV)

4-20

Floor

Aus Gleitpunktzahl nächstniedere Ganzzahl erzeugen

10-17


Absolutwert einer Gleitpunktzahl bilden

8-8


Arcuscosinus einer Gleitpunktzahl bilden

8-13


Arcussinus einer Gleitpunktzahl bilden

8-13


Arcustangens einer Gleitpunktzahl bilden

8-13


Cosinus einer Gleitpunktzahl bilden

8-13


Exponentialwert einer Gleitpunktzahl bilden

8-12

Form the Natural Algorithm of a Floating-Point Natürlichen Logarithmus einer Gleitpunktzahl Number bilden

8-11


Sinus einer Gleitpunktzahl bilden

8-13


Quadrat einer Gleitpunktzahl bilden

8-9


Quadratwurzel einer Gleitpunktzahl bilden

8-10


Tangens einer Gleitpunktzahl bilden

8-13

Insert Binary Input

Binären Eingang einfügen

4-7

Integer to BCD


10-4


Ganzzahl (16 Bit) in Ganzzahl (32 Bit) wandeln

10-5

Jump

Springe wenn 1

14-3

Jump-If-Not

Springe wenn 0

14-5


Master Control Relay Anfang

16-10


Master Control Relay Ende

16-10


Master Control Relay ausschalten

16-13


Master Control Relay einschalten

16-13

Midline Output

Konnektor

4-10


Ganze Zahlen multiplizieren (32 Bit)

7-7

Multiply Integer


7-6

Multiply Real

Gleitpunktzahlen multiplizieren

8-5

Negate Binary Input

Binären Eingang negieren

4-8

Negate Real Number

Vorzeichen einer Gleitpunktzahl wechseln

10-13


Flanke 1 → 0 abfragen

4-29

OR

ODER-Verknüpfung

4-4


Zeit als Ausschaltverzögerung starten (SA)

5-13


A-7


Table A-2



Page


Zeit als Ausschaltverzögerung starten (SA)

4-26


Zeit als Einschaltverzögerung starten (SE)

5-9


Zeit als Einschaltverzögerung starten (SE)

4-22


1er Komplement zu Ganzzahl (32 Bit) erzeugen

10-10



10-9


Datenbaustein öffnen

13-2



4-28


Zeit als Impuls starten (SI)

5-5


Zeit als Impuls starten (SI)

4-18

Reset Output

Ausgang rücksetzen

4-13

Reset_Set Flip Flop

Flipflop rücksetzen setzen

4-33

Result Bit Equal 0

Ergebnisbit bei gleich 0

15-4


Ergebnisbit bei größer gleich 0

15-4


Ergebnisbit bei größer als 0

15-4


Ergebnisbit bei kleiner gleich 0

15-4


Ergebnisbit bei kleiner 0

15-4


Ergebnisbit bei ungleich 0

15-4

Retentive On-Delay S5 Timer (timer instruction) Zeit als speich. Einschaltverzögerung starten (SS)

5-11

Retentive On-Delay Timer (Bitverknüpfungsperation)

Zeit als speich. Einschaltverzögerung starten (SS)

4-24

Return

Springe zurück

16-7


Divisionsrest gewinnen (32 Bit)

7-10


32 Bit links rotieren

12-11


32 Bit rechts rotieren

12-12


Zahl runden

10-14


Verknüpfungsergebnis ins BIE-Register laden

4-11

Set Output

Ausgang setzen

4-12

Set Counter Value

Zähleranfangswert setzen

4-14

Set_Reset Flip Flop

Flipflop setzen rücksetzen

4-32


32 Bit links schieben

12-4

Shift Left Word


12-3


Ganzzahl (32 Bit) rechts schieben

12-9


32 Bit rechts schieben

12-6

Shift Right Integer


12-8

Shift Right Word


12-5


Ganze Zahlen subtrahieren (32 Bit)

7-5

Subtract Integer


7-4

Subtract Real

Gleitpunktzahlen subtrahieren

8-4

A-8



Table A-2



Page


Ganze Zahl erzeugen

10-15



10-12



10-11


Vorwärtszählen

6-5


Vorwärtszählen

4-16

Up-Down Counter

Vorwärts-/Rückwärtszählen

6-3


32 Bit UND verknüpfen

11-4

(Word) AND Word


11-3


32 Bit EXKLUSIV ODER verknüpfen

11-8



11-7


32 Bit ODER verknüpfen

11-6

(Word) OR Word


11-5


A-9


A.3

List of Instructions with German SIMATIC Names Table A-3 contains an alphabetical list of FBD instructions with the German full names, the corresponding short name or mnemonic, and the reference to the page on which the instruction is described.

Table A-3

FBD Instructions Arranged Alphabetically by German Full Names, with Short Names SIMATIC Short Name

Page


INV_I

10-9


INV_DI

10-10


NEG_I

10-11


NEG_DI

10-12


WXOR_W

11-7


SHL_W

12-2


WOR_W

11-5


SHR_W

12-5


WAND_W

11-3


WXOR_DW

11-8


ROL_DW

12-11


SHL_DW

12-4


WOR_DW

11-6


ROR_DW

12-12


SHR_DW

12-6


WAND_DW

11-4


ABS

8-8


ACOS

8-13


ASIN

8-13


ATAN

8-13

Ausgang rücksetzen

R

4-13

Ausgang setzen

S

4-12


CEIL

10-16


FLOOR

10-17


BCD_I

10-3


BCD_DI

10-6


–––|

4-7


–––o|

4-8


COS

8-13


AUF

13-2


MOD

7-10


==0

15-4


>0

15-4

Full Name

A-10



Table A-3

FBD Instructions Arranged Alphabetically by German Full Names, with Short Names, cont. Full Name

SIMATIC Short Name

Page


>=0

15-4


<0

15-4


<=0

15-4


<>0

15-4


XOR

4-6


EXP

8-12

FB aufrufen

CALL_FB

16-4

FC aufrufen

CALL_FC

16-4


CALL

16-2


P

4-28


N

4-29


RS

4-33


SR

4-32


ADD_I

7-2


ADD_DI

7-3


DIV_I

7-8


DIV_DI

7-9


MUL_I

7-6


MUL_DI

7-7


SUB_I

7-4


SUB_DI

7-5


CMP >=I

9-2


CMP >=D

9-3

Ganze Zahl erzeugen

TRUNC

10-15


I_DI

10-5


I_BCD

10-4


SHR_I

12-8


DI_BCD

10-7


DI_R

10-8


SHR_DI

12-9


ADD_R

8-3


DIV_R

8-6


MUL_R

8-5


SUB_R

8-4


CMP >=R

9-4

Konnektor

#

4-10


MCRA

16-10


MCR>

16-13


A-11


Table A-3


SIMATIC Short Name

Page


MCR<

16-13


MCRD

16-10

Natürlichen Logarithmus einer Gleitpunktzahl bilden

LN

8-11

ODER-Verknüpfung

>=1

4-4


SQR

8-9


SQRT

8-10

Rückwärtszählen (Zähloperation)

Z_RUECK

6-7

Rückwärtszählen (Bitverknüpfungsoperation)

ZR

4-17


POS

4-30


NEG

4-31


SIN

8-13

Springe wenn 0

JMPN

14-5

Springe wenn 1

JMP

14-3

Springe zurück

RET

16-7


BIE

15-3


OV

15-7


OS

15-8


UO

15-6

System FB aufrufen

CALL_SFB

16-4

System FC aufrufen

CALL_SFC

16-4


TAN

8-13

UND-Verknüpfung

&

4-3


SAVE

4-11


ZAEHLER

6-3

Vorwärtszählen (Zähloperation)

Z_VORW

6-5

Vorwärtszählen (Bitverknüpfungsoperation)

ZV

4-16


NEG_R

10-13

Wert übertragen

MOVE

10-2

Zahl runden

ROUND

10-14


SZ

4-14

Zeit als Ausschaltverzögerung starten (SA) (Zeitoperation)

S_AVERZ

5-13

Zeit als Ausschaltverzögerung starten (SA) (Bitverknüpfungsoperation)

SA

4-26

Zeit als Einschaltverzögerung starten (SE) (Zeitoperation)

S_EVERZ

5-9

Zeit als Einschaltverzögerung starten (SE) (Bitverknüpfungsoperation)

SE

4-22

Zeit als Impuls starten (SI) (Zeitoperation)

S_IMPULS

Zeit als Impuls starten (SI) (Bitverknüpfungsoperation)

SI

4-18

Zeit als speich. Einschaltverzögerung starten (SS) (Zeitoperation)

S_SEVERZ

5-11

A-12



Table A-3


SIMATIC Short Name

Page

Zeit als speich. Einschaltverzögerung starten (SS) (Bitverknüpfungsoperation)

SS

4-24

Zeit als verlängerten Impuls starten (SV) (Zeitoperation)

S_VIMP

5-7

Zeit als verlängerten Impuls starten (SV) (Bitverknüpfungsoperation)

SV

4-20

Zuweisung

=

4-9


A-13


A.4

List of Instructions with German Names and International (English) Equivalents Table A-4 contains an alphabetical list of FBD instructions with German SIMATIC full names, the international (English) equivalents, and the reference to the page on which the instruction is described.

Table A-4

FBD Instructions Arranged Alphabetically by German Full Names with International (English) Equivalents International (English) Equivalent

SIMATIC Full Name

Page



10-9



10-10



10-11



10-12



11-7


Shift Left Word

12-2


(Word) OR Word

11-5


Shift Right Word

12-5


(Word) AND Word

11-3



11-8



12-11



12-4



11-6



12-12



12-6



11-4



8-8



8-13



8-13



8-13

Ausgang rücksetzen

Reset Output

4-13

Ausgang setzen

Set Output

4-12


Ceiling

10-16


Floor

10-17


BCD to Integer

10-3



10-6


Insert Binary Input

4-7


Negate Binary Input

4-8



8-13



13-2

A-14



Table A-4

FBD Instructions Arranged Alphabetically by German Full Names with International (English) Equivalents, cont. SIMATIC Full Name

International (English) Equivalent

Page



7-10


Result Bit Equal 0

15-4



15-4



15-4



15-4



15-4



15-4


Exclusive OR

4-6



8-12

FB aufrufen

Call FB from Box

16-4

FC aufrufen

Call FC from Box

16-4



16-2



4-28



4-29


Reset_Set Flip Flop

4-33


Set_Reset Flip Flop

4-32


Add Integer

7-2


Add Double Integer

7-3


Divide Integer

7-8



7-9


Multiply Integer

7-6

Ganze Zahlen multiplizieren [32 Bit)


7-7


Subtract Integer

7-4



7-5


Compare Integer (>, <, ==, <>, <=, >=)

9-2



9-3

Ganze Zahl erzeugen


10-15



10-5


Integer to BCD

10-4


Shift Right Integer

12-8



10-7



10-8



12-9


Add Real

8-3


Divide Real

8-6


Multiply Real

8-5


Subtract Real

8-4


A-15


Table A-4



Page


Compare Real (>, <, ==, <>, <=, >=)

9-4

Konnektor

Midline Output

4-10



16-10



16-13



16-13



16-10

Natürlichen Logarithmus einer Gleitpunktzahl bilden

Form the Natural Algorithm of a Floating-Point Number

8-11



8-9



8-10

ODER-Verknüpfung

OR

4-4

Rückwärtszählen (Zähloperation)

Down Counter

6-7

Rückwärtszählen (Bitverknüpfungsoperation)

Down Counter

4-17

Signalflanke 0→1 abfragen


4-30

Signalflanke 1→0 abfragen


4-31



8-13

Springe wenn 0

Jump-If-Not

14-5

Springe wenn 1

Jump

14-3

Springe zurück

Return

16-7



15-3



15-7



15-8



15-6

System FB aufrufen


16-4

System FC aufrufen


16-4



8-13

UND-Verknüpfung

AND

4-3



4-11


Up-Down Counter

6-3

Vorwärtszählen (Zähloperation)

Up Counter

6-5

Vorwärtszählen (Bitverknüpfungsoperation)

Up Counter

4-16


Negate Real Number

10-13

Wert übertragen

Assign a Value

10-2

Zahl runden


10-14


Set Counter Value

4-14

Zeit als Ausschaltverzögerung starten (SA) (Zeitoperation)

Off-Delay S5 Timer

5-13

A-16



Table A-4



Page

Zeit als Ausschaltverzögerung starten (SA) (Bitverknüpfungsoperation)

Off-Delay Timer

4-26

Zeit als Einschaltverzögerung starten (SE) (Zeitoperation)

On-Delay S5 Timer

5-9

Zeit als Einschaltverzögerung starten (SE) (Bitverknüpfungsoperation)

On-Delay Timer

4-22

Zeit als Impuls starten (SI) (Zeitoperation)

Pulse S5 Timer

5-5

Zeit als Impuls starten (SI) (Bitverknüpfungsoperation) Pulse Timer

4-18

Zeit als speich. Einschaltverzögerung starten (SS) (Zeitoperation)


5-11

Zeit als speich. Einschaltverzögerung starten (SS) (Bitverknüpfungsoperation)

Retentive On-Delay Timer

4-22

Zeit als verlängerten Impuls starten (SV) (Zeitoperation)


5-7

Zeit als verlängerten Impuls starten (SV) (Bitverknüpfungsoperation)

Extended Pulse Timer

4-20

Zuweisung

Assign

4-9

Table A-5

FBD Instructions Listed in this Manual with their International Full and Short Names and their SIMATIC Short Names SIMATIC Full Name

International Short Name

SIMATIC Short Name

Page


S_CD

Z_RUECK

6-7


CD

ZR

4-17


BR

BIE

15-3


S_PEXT

S_VIMP

5-7


SE

SV

11-5


S_OFFDT

S_AVERZ

5-13


SF

SA

4-26


S_ODT

S_EVERZ

5-9


SD

SE

4-22


OPN

AUF

13-2


S_PULSE

S_IMPULS

5-5


SP

SI

4-18

Retentive On-Delay S5 Timer (timer instruction)

S_ODTS

S_SEVERZ

5-11

Retentive On-Delay Timer (bit logic instruction)

SS

SS

4-24

Set Counter Value

SC

SZ

4-14


S_CU

Z_VORW

6-5


A-17


Table A-5

FBD Instructions Listed in this Manual with their International Full and Short Names and their SIMATIC Short Names, continued SIMATIC Full Name

International Short Name

SIMATIC Short Name

Page


CU

ZV

4-16

Up-Down Counter

S_CUD

ZAEHLER

6-3

A-18


B

Programming Examples Chapter Overview

Section

Description

Page

B.1

Overview

B-2

B.2


B-3

B.3

Timer Instructions

B.4

Counter and Comparison Instructions

B-11

B.5


B-13

B.6


B-14


B-7

B-1


B.1

Overview

Practical Applications

Each FBD instruction described in this manual executes a specific function. When you combine these instructions into a program, you can accomplish a wide variety of automation tasks. This chapter provides the following examples of practical applications of the FBD instructions:

Controlling a conveyor belt using bit logic instructions Detecting direction of movement on a conveyor belt using bit logic instructions

Generating a clock pulse using timer instructions Keeping track of storage space using counter and comparison instructions Solving a problem using integer math instructions Setting the length of time for heating an oven Instructions Used

The examples in this chapter use the following instructions:

Add Integer (ADD_I) AND Assign (=) Assign a Value (MOVE) Compare Integer (CMP_I>=) Compare Integer (CMP_I<=) Divide Integer (DIV_I) Down Counter (S_CD) Extended Pulse Timer (SE) Jump-If-Not (JMPN) Multiply Integer (MUL_I) OR Positive RLO Edge Detection (P) Reset Output (R) Return (RET) Set Output (S) Up Counter (S_CU) (Word) AND Word (WAND_W) (Word) OR Word (WOR_W)

B-2



B.2


Controlling a Conveyor Belt

Figure B-1 shows a conveyor belt that can be activated electrically. There are two push button switches at the beginning of the belt: S1 for START and S2 for STOP. There are also two push button switches at the end of the belt: S3 for START and S4 for STOP. It it possible to start or stop the belt from either end. Sensor S5 stops the belt when an item on the belt reaches the end.

Symbolic Programming

You can write a program to control the conveyor belt shown in Figure B-1 using symbols that represent the various components of the conveyor system. If you choose this method, you need to make a symbol table to correlate the symbols you choose with absolute values (see Table B-1). You define the symbols in the symbol table (see the STEP 7 Online Help). Table B-1

Elements of Symbolic Programming for Conveyor Belt System Absolute Address

Symbol

Start button

I1.1

S1

I1.1

S1

Stop button

I1.2

S2

I1.2

S2

Start button

I1.3

S3

I1.3

S3

Stop button

I1.4

S4

I1.4

S4

Sensor

I1.5

S5

I1.5

S5

Motor

Q4.0

MOTOR_ON

Q4.0

MOTOR_ON

System Component

Symbol Table

Sensor S5

MOTOR_ON Figure B-1

S1 S2

` Start ` Stop

S3 S4

` Start ` Stop

Conveyor Belt System


B-3


Absolute Programming

You can write a program to control the conveyor belt shown in Figure B-1 using absolute values that represent the different components of the conveyor system (see Table B-2). Figure B-2 shows an FBD program to control the conveyor belt. Table B-2

Elements of Absolute Programming for Conveyor Belt System Absolute Address

System Component Start button

I1.1

Stop button

I1.2

Start button

I1.3

Stop button

I1.4

Sensor

I1.5

Motor

Q4.0

Network 1: Pressing either start button turns the motor on.

I1.1

>=1 Q4.0 S

I1.3

Network 2: Pressing either stop button or the sensor at the end of the belt responding turns the motor off.

I1.2 I1.4 E1.5

Figure B-2

B-4

>=1 Q4.0 R

Function Block Diagram to Control a Conveyor Belt



Detecting the Direction of a Conveyor Belt

Figure B-3 shows a conveyor belt that is equipped with two photoelectric barriers (PEB1 and PEB2) that are designed to detect the direction in which a package is moving on the belt.

Symbolic Programming

You can write a program to activate a direction display for the conveyor belt system shown in Figure B-3 using symbols that represent the various components of the conveyor system, including the photoelectric barriers that detect direction. If you choose this method, you need to make a symbol table to correlate the symbols you choose with absolute values (see Table B-3). You define the symbols in the symbol table (see the STEP 7 Online Help). Table B-3

Elements of Symbolic Programming for Detecting Direction Absolute Address

System Component Photoelectric barrier 1

Absolute Programming

Q4.0

Figure B-3

Symbol

Symbol Table

I0.0

PEB1

I0.0

PEB1

Photoelectric barrier 2

I0.1

PEB2

I0.1

PEB2

Display for movement to right

Q4.0

RIGHT

Q4.0

RIGHT

Display for movement to left

Q4.1

LEFT

Q4.1

LEFT

Clock memory bit 1

M0.0

PM1

M0.0

PM1

Clock memory bit 2

M0.1

PM2

M0.1

PM2

You can write a program to activate the direction display for the conveyor belt shown in Figure B-3 using absolute values that represent the photoelectric barriers that detect direction (see Table B-4). Figure B-4 shows an FBD program to control the direction display for the conveyor belt.

PEB2

PEB1

Q4.1

Conveyor Belt System with Photoelectric Light Barriers for Detecting Direction


B-5


Table B-4

Elements of Absolute Programming for Detecting Direction Absolute Address

System Component Photoelectric barrier 1

I0.0


I0.1

Display for movement to right

Q4.0

Display for movement to left

Q4.1

Clock memory bit 1

M0.0

Clock memory bit 2

M0.1

Network 1: If there is a transition in signal state from 0 to 1 (rising edge) at input I0.0 and, at the same time, the signal state at input I0.1 is 0, then the package on the belt is moving to the left.

M 0.0 I0.0

P

& Q4.1 S

I0.1

Network 2: If there is a transition in signal state from 0 to 1 (rising edge) at input I0.1 and, at the same time, the signal state at input I0.0 is 0, then the package on the belt is moving to the right. M 0.1 I0.1

P I0.0

& Q4.0 S

If one of the photoelectric light barriers is interrupted, this means that there is a package between the barriers. & I0.0 I0.1

Q4.0 R Q4.1 R

Figure B-4

B-6

Function Block Diagram for Detecting the Direction of a Conveyor Belt



B.3

Timer Instructions

Clock Pulse Generator

You can use a clock pulse generator or flasher relay when you want to produce a signal that is repeated periodically. Clock pulse generators are commonly found in signaling systems that control flashing indicator lamps. When you use the S7-300, you can implement the clock pulse generator function by using time-driven program execution in special organization blocks. The example shown in the following FBD program illustrates the use of timer functions to generate a clock pulse. The following example shows how to implement a freewheeling clock pulse generator by using a timer (pulse duty factor 1:1). The frequency is divided into the values listed in Table B-5.


B-7


Network 1: If the signal state of timer T1 is 0, load the time value 250 ms into T1 and start T1 as an extended-pulse timer. T1 SE

&

M0.2

TV

S5T#250MS

Network 2: The state of the timer is saved temporarily in an auxiliary memory bit. M0.2 =

&

T1

Network 3: If the signal state of timer T1 is 1, jump to jump label N001. N001 JMP

&

M0.2

Network 4: When the timer T1 expires, the memory word 100 is incremented by 1.

??.?

ADD_I EN

MW100

IN1

OUT

1

IN2

ENO

MW100

Network 5: The MOVE instruction allows you to output the different clock frequencies at outputs Q12.0 through Q13.7.

N001

??.? MW100

Figure B-5

B-8

MOVE EN OUT IN

QW12

ENO

Function Block Diagram to Generate a Clock Pulse



A signal check of timer T1 produces the result of logic operation (RLO, see Section 2.3) shown in Figure B-6.

1 0 250 ms

Figure B-6

RLO for the Negated Input Parameter AN T1 in the Clock Pulse Timer Example

As soon as the time runs out, the timer is restarted. Because of this, the signal check made by AN M0.2 produces signal state 1 only briefly. Figure B-7 shows the negated (inverted) RLO bit.

1 0 250 ms

Figure B-7

Negated RLO Bit of Timer T1 in the Clock Pulse Timer Example

Every 250 ms the RLO bit is 0. The jump is ignored and the content of memory word MW100 is incremented by 1.

Achieving a Specific Frequency

Table B-5 lists the frequencies that you can achieve from the individual bits of memory bytes MB101 and MB100. Network 5 in the FBD diagram shown in Figure B-5 illustrates how the MOVE instruction allows you to see the different clock frequencies at outputs Q12.0 through Q13.7. Table B-5

Frequencies for Clock Pulse Timer Example

Bits in MB101/MB100

Frequency in Hz

Duration

M101.0 M101.1

2.0 1.0

0.5 s (250 ms on/250 ms off) 1 s (0.5 s on/0.5 s off)

M101.2 M101.3

0.5 0.25

2 s (1 s on/1 s off) 4 s (2 s on/2 s off)

M101.4 M101.5

0.125 0.0625

8 s (4 s on/4 s off) 16 s (8 s on/8 s off)

M101.6

0.03125

32 s (16 s on/16 s off)

M101.7

0.015625

64 s (32 s on/32 s off)

M100.0

0.0078125

128 s (64 s on/64 s off)

M100.1

0.0039062

256 s (128 s on/128 s off)

M100.2

0.0019531

512 s (256 s on/256 s off)


B-9


Table B-5

Frequencies for Clock Pulse Timer Example

Bits in MB101/MB100

Frequency in Hz

Duration

M100.3

0.0009765

1024 s (512 s on/512 s off)

M100.4

0.0004882

2048 s (1024 s on/1024 s off)

M100.5

0.0002441

4096 s (2048 s on/2048 s off)

M100.6

0.000122

8192 s (4096 s on/4096 s off)

M100.7

0.000061

16384 s (8192 s on/8192 s off)

Table B-6 lists the signal states of the bits of memory byte MB101. Figure B-8 shows the signal state of memory bit M101.1. Table B-6

Signal States of the Bits of Memory Byte MB101

Scan Cycle

7

6

5

4

3

2

1

0

Time Value in ms

0

0

0

0

0

0

0

0

0

250

1

0

0

0

0

0

0

0

1

250

2

0

0

0

0

0

0

1

0

250

3

0

0

0

0

0

0

1

1

250

4

0

0

0

0

0

1

0

0

250

5

0

0

0

0

0

1

0

1

250

6

0

0

0

0

0

1

1

0

250

7

0

0

0

0

0

1

1

1

250

8

0

0

0

0

1

0

0

0

250

9

0

0

0

0

1

0

0

1

250

10

0

0

0

0

1

0

1

0

250

11

0

0

0

0

1

0

1

1

250

12

0

0

0

0

1

1

0

0

250

Signal State of Bits of Memory Byte MB101

T M101.1

1 0 Time 0

250 ms 0.5 s 0.75 s 1 s

1.25 s 1.5 s

Frequency 1 1 1Hz 1 s T Figure B-8

B-10

Signal State of Bit 1 of MB101 (M101.1)



B.4

Counter and Comparison Instructions

Storage Area with Counter and Comparator

Figure B-9 shows a system with two conveyor belts and a temporary storage area in between them. Conveyor belt 1 delivers packages to the storage area. A photoelectric barrier at the end of conveyor belt 1 near the storage area detects how many packages are delivered to the storage area. Conveyor belt 2 transports packages from the temporary storage area to a loading dock where trucks take the packages away for delivery to customers. A photoelectric barrier at the end of conveyor belt 2 near the storage area detects how many packages leave the storage area to go to the loading dock. A display panel with five lamps indicates the fill level of the temporary storage area. Figure B-10 shows the FBD program that activates the indicator lamps on the display panel.

Display panel

Storage area empty (Q12.0)

Storage area not empty (Q12.1)

I0.0 Packages in

Storage area 50% full (Q15.2)

Temporary storage for 100 packages

Conveyor belt 1

(Q15.3)

Storage area filled to capacity (Q15.4)

I0.1 Packages out

Conveyor belt 2 Photoelectric barrier 1

Figure B-9

Storage area 90% full


Storage Area with Counter and Comparator


B-11


Network 1: Counter C1 counts up at each signal change from 0 to 1 at input CU and counts down at each signal change from 0 to 1 at input CD. With a signal change from 0 to ”1” at input S, the counter value is set to the value PV. A signal change from 0 to 1 at input R resets the counter value to 0. MW200 contains the current counter value of C1. Q12.1 indicates “storage area not empty”.

C1 S_CUD I12.0

CU

I12.1

CD

I12.2

S

CV

MW210

C#10

PV CV_BCD

MW200

I12.3

R

Q12.1 =

Q

Network 2: Q12.0 indicates ”storage area not empty”. Q12.0 Q12.1

&

=

Network 3: If 50 is less than or equal to the counter value (in other words if the current counter value is greater than or equal to 50), the indicator lamp for “storage area 50% full” is lit. CMP <= I 50

IN1

MW200

IN2

Q15.2 =

Network 4: If the counter value is greater than or equal to 90, the indicator lamp for “storage area 90% full” is lit.

MW200

CMP >= I IN1 IN2

90

Q15.3 =

Network 5: If the counter value is greater than or equal to 100, the indicator lamp for “storage area full” is lit. Use output Q4.4 to interlock conveyor belt 1. CMP >= I MW200

IN1

100

IN2

Figure B-10

B-12

Q15.4 =

Function Block Diagram for Activating Indicator Lamps on a Display Panel



B.5


Solving a Math Problem

The following sample program shows you how to use three integer math instructions and the L and T instructions to produce the same result as the following equation: MW4 +

(IW0 ) DBW3) MW0

15

Network 1: Open Data Block DB1 DB1 OPN

Network 2: Input word IW0 is added to shared data word DBW3 (data block must be defined and opened) and the sum is loaded into memory word MW100. MW100 is then multiplied by 15 and the answer stored in memory word MW102. MW102 is divided by MW0 with the result stored in MW4. As long as all results are in the permitted range of each instruction, the ENO passes a signal state of 1 to the next box.

??.?

ADD_I EN

IW0

IN1

DBW3

IN2

OUT

MW100 MUL_I EN

ENO MW100

IN1

OUT

IN2

ENO

MW102 DIV_I

15

Figure B-11

EN MW102

IN1

OUT

MW0

IN2

ENO

MW4

Function Block Diagram for Integer Math Instructions


B-13


B.6


Heating an Oven

The operator of the oven shown in Figure B-12 starts the oven heating by pushing the start push button. The operator can set the length of time for heating by using the thumbwheel switches shown in the figure. The value that the operator sets indicates seconds in binary coded decimal (BCD) format. Table B-7 lists the components of the heating system and their corresponding absolute addresses used in the sample program shown in Figure B-12. Table B-7

Heating System Components and Corresponding Absolute Addresses Absolute Address in FBD Program

System Component Start button

I0.7

Thumbwheel for ones

I1.0 to I1.3

Thumbwheel for tens

I1.4 to I1.7

Thumbwheel for hundreds

I0.0 to I0.3

Start heating

Q4.0

Thumbwheels for setting BCD digits

ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ

Oven

4

Heat Q4.0

7....

...0

XXXX

4

7...

0001

1001

IB0

IB1

4 ...0

Bits

0001

IW0 Bytes

Start button I0.7

Figure B-12

B-14

Using the Inputs and Outputs for a Time-Limited Heating Process



Network 1: If the timer is running, then turn on the heater. If the timer is running, the Return instruction ends the processing here.

&

T1

Q4.0 =

Network 2: If the timer is running, the Return instruction ends the processing here. T1

&

RET

Network 3: Mask input bits I0.4 through I0.7 (that is, reset them to 0). These bits of the thumbwheel inputs are not used. The 16 bits of the thumbwheel inputs are combined with W#16#0FFF according to the (Word) And Word instruction. The result is loaded into memory word MW1. In order to set the time base of seconds, the preset value is combined with W#16#2000 according to the (Word) Or Word instruction, setting bit 13 to 1 and resetting bit 12 to 0.

??.?

WAND_W EN

IW0

IN1

OUT

IN2

ENO

W#16#FFF

MW1 WOR_W EN MW1

IN1

OUT

W#16#2000

IN2

ENO

MW2

Network 4: Start timer T1 as an extended pulse timer if the start push button is pressed, loading as a preset value memory word MW2 (derived from the logic above). T1 I0.7

SE

& MW2

Figure B-13

TV

Function Block Diagram for Heating an Oven


B-15


B-16


C

References /30/

Getting Started: Working with STEP 7 V5.0

/70/

Manual: S7-300 Programmable Controller, Hardware and Installation

/71/

Reference Manual: S7-300, M7-300 Programmable Controllers Module Specifications

/72/

Instruction List: S7-300 Programmable Controller

/100/ Manual: S7-400/M7-400 Programmable Controllers, Hardware and Installation /101/ Reference Manual: S7-400/M7-400 Programmable Controllers Module Specifications /102/ Instruction List: S7-400 Programmable Controller /231/ Manual: Configuring Hardware and Communication Connections, STEP 7 V5.0 /232/ Reference Manual: Statement List (STL) for S7-300 and S7-400 Programming /233/ Reference Manual: Ladder Logic (LAD)for S7-300and S7-400, Programming /234/ Manual: Programming with STEP 7 V5.0 /235/ Reference Manual: System Software for S7-300 and S7-400 System and Standard Functions /250/ Manual: Structured Control Language (SCL) for S7-300/S7-400, Programming /251/ Manual: S7-GRAPH for S7-300 and S7-400, Programming Sequential Control Systems /252/ Manual: S7-HiGraph for S7-300 and S7-400, Programming State Graphs /253/ Manual: C Programming for S7-300 and S7-400, Writing C Programs /254/ Manual: Continuous Function Charts (CFC) for S7 and M7, Programming Continuous Function Charts /270/ Manual: S7-PDIAG for S7-300 and S7-400 “Configuring Process Diagnostics for LAD, STL, and FBD” /271/ Manual: NETPRO, “Configuring Networks” Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01

C-1

References

/800/ DOCPRO Creating Wiring Diagrams (CD only) /801/ TeleService for S7, C7 and M7 Remote Maintenance for Automation Systems (CD only) /802/ PLC Simulation for S7-300 and S7-400 (CD only) /803/ Reference Manual: Standard Software for S7-300 and S7-400, STEP 7 Standard Functions, Part 2

C-2


Glossary

A Absolute Addressing

In absolute addressing, the memory location of the address to be processed is given.

Accumulator

Accumulators are registers in the CPU which act as intermediate buffers for load, transfer, comparison, math, and conversion operations.

Actual Parameter

Actual parameters replace the formal parameters when function blocks (FBs) and functions (FCs) are called. Example: The formal parameter “Start” is replaced by the actual parameter “I3.6”.

Address

An address is part of a STEP 7 statement and specifies what the processor should execute the instruction on. Addresses can be absolute or symbolic.

Address Identifier

An address identifier is the part of the address which contains various data. The data can include elements such as a value itself (data object) or the size of a value with which the instruction can, for example, perform a logic operation. In the instruction statement “L IB10” IB is the address identifier (“I” indicates the memory input area and “B” indicates a byte in that area).

Array

An array is a complex data type which consists of data elements of the same type. These data elements can be elementary or complex.

B Bit Result (BR)

The bit result is the link between bit and word-oriented processing. This is an efficient method to allow the binary interpretation of the result of a word instruction and to include it in a series of logic operations.


Glossary-1

Glossary

C Call Hierarchy

All blocks must be called first before they can be processed. The sequence and nesting of these calls within an organized block is called the call hierarchy.

Condition Codes CC 1 and CC 0

The CC 1 and CC 0 bits (condition codes) provide information on the following results or bits:

Result of a math operation Result of a comparison Result of a digital operation Bits that have been shifted out by a shift or rotate command Current Path

Characteristic of the Ladder Logic programming language. Current paths contain contacts and coils. Complex elements (for example, math functions) can also be inserted into current paths in the form of “boxes.” Current paths are connected to power rails.

D Data Block (DB)

Data blocks (DBs) are areas in a user program which store user data. There are shared data blocks which can be accessed by all logic blocks and there are instance data blocks which are associated with a certain function block (FB) call. In contrast to all other blocks, data blocks do not contain instructions.

Data, Static

Static data are local data of a function block which are stored in the instance data block and, therefore, remain intact until the function block is processed again.

Data Type

A data type defines how the value of a variable or a constant should be used in the user program. In SIMATIC STEP 7 two data types are available to the user (IEC 1131–3):

Elementary data types Complex data types Data Type, Complex

Glossary-2

Complex data types are created by the user with the data type declaration. They do not have their own name and cannot, therefore, be used again. They can either be arrays or structures. The data types STRING and DATE AND TIME are classed as complex data types.


Glossary

Data Type, Elementary

Elementary data types are preset data types according to IEC 1131–3. Examples:

Data type “BOOL” defines a binary variable (“Bit”) Data type “INT” defines a 16-bit fixed-point variable.

Declaration

The declaration section is used for the declaration of the local data of a logic block when programming in the Text Editor.

Direct Addressing

In direct addressing, the address contains the memory location of a value which is to be used by the instruction. Example: The location Q4.0 defines bit 0 in byte 4 of the process-image output table.

F First Check Bit

First check of the result of logic operation.

Folder

Directory of the user interface of the SIMATIC Manager which can be opened and can hold other directories or objects.

Formal Parameter

A formal parameter is a placeholder for the actual parameter in logic blocks. In function blocks (FBs) and functions (FCs) the formal parameters are declared by the user, in system function blocks (SFBs) and system functions (SFCs) they are already available. When a block is called, formal parameters are assigned actual parameters, so the called block works with the current values. The formal parameters are classed as local data. They can be input, output, or in/out parameters.

Function (FC)

According to the International Electrotechnical Commission’s IEC 1131–3 standard, functions are logic blocks without a ‘memory’ (meaning they do not have static data). A function allows you to transfer parameters in the user program, which means they are suitable for programming frequently recurring, complex functions, such as calculations. Important: As a function has no memory, you must continue processing the calculated values directly after the function has been called.


Glossary-3

Glossary

Function Block (FB)

According to the International Electrotechnical Commission’s IEC 1131–3 standard, function blocks are logic blocks with a ‘memory’ (meaning they have static data). A function block allows you to transfer parameters in the user program, which means they are suitable for programming frequently recurring, complex functions, such as closed-loop control and operating mode selection. As a function block has a memory (instance data block), you can access its parameters (for example, outputs) at any time and at any point in the user program.

Function Block Diagram (FBD)

Function Block Diagram (FBD) is one of the programming languages in STEP 5 and STEP 7. FBD represents logic in the boxes familiar from Boolean algebra. In addition, complex functions (for example, math functions) can be represented in direct connection with the logic box. Programs created with FBD can also be translated into other programming languages (for example, Ladder Logic).

I Immediate Addressing

In immediate addressing, the address contains the value with which the instruction works. Example: L.27 means load constant 27 into accumulator.

Input, Incremental

When a block is input incrementally, each line or element is checked immediately for errors (for example, syntax errors). If an error is detected, it is marked and must be corrected before programming is completed. Incremental input is possible in STL (Statement List), LAD (Ladder Logic), and FBD (Function Block Diagram).

Instance

An “instance” is the call of a function block. An instance data block is assigned to each call.

Instance Data Block (DB)

An instance data block stores the formal parameters and the static data of function blocks. An instance data block can be assigned to one function block call or a call hierarchy of function blocks.

Instruction

An instruction is part of a STEP 7 statement; it specifies what the processor should do.

Glossary-4


Glossary

K Keyword

Keywords are used when programming with source files to identify the start and end of a block and to select sections in the declaration section of blocks, the start of block comments and the start of titles.

L Ladder Logic (LAD)

Ladder Logic is a graphic programming language in STEP 5 and STEP 7. Its representation is standardized in compliance with DIN 19239 (international standard IEC 1131-1). Ladder Logic representation corresponds to the representation of relay ladder logic diagrams. In contrast to Statement List (STL), LAD has a restricted set of instructions.

Logic Block

Logic blocks are blocks within SIMATIC S7 that contain a part of the STEP 7 user program. In contrast, data blocks (DBs) only contain data. There are the following types of logic blocks: organization blocks (OBs), function blocks (FBs), functions (FCs), system function blocks (SFBs), and system functions (SFCs). Blocks are stored in the “Blocks” folder under the “S7 Program” folder.

Logic String

A logic string is that portion of a user program which begins with an FC bit that has a signal state of 0 and which ends when an instruction or event resets the FC bit to 0. When the CPU executes the first instruction in a logic string, the FC bit is set to 1. Certain instructions such as output instructions (for example, Set, Reset, or Assign) reset the FC bit to 0. See First Check Bit above.

M Master Control Relay

The Master Control Relay (MCR) is an American relay ladder logic master switch for energizing and de-energizing power flow (current path). A de-energized current path corresponds to an instruction sequence that writes a zero value instead of the calculated value, or, to an instruction sequence that leaves the existing memory value unchanged.

Memory Area

In SIMATIC S7 a CPU has three memory areas:

Load memory Work memory System memory


Glossary-5

Glossary

Mnemonic Representation

Mnemonic representation is an abbreviated form for displaying the names of addresses and programming instructions in the program (for example, “I” stands for “input”). STEP 7 supports the international representation (based on the English language), and the SIMATIC representation (based on the German abbreviations of the instruction set and the SIMATIC addressing conventions).

N Network

Networks subdivide LAD and FBD blocks into complete current paths and Statement List (STL) blocks into clear units.

O Overflow Bit

The status bit OV stands for overflow. An overflow can occur, for example, after a math operation.

P Pointer

You can use a pointer to identify the address of a variable. A pointer contains an identifier instead of a value. If you allocate an actual parameter type, you provide the memory address. With STEP 7 you can either enter the pointer in pointer format or simply as an identifier (for example, M 50.0). In the following example, the pointer format is shown with which data from M 50.0 is accessed: P#M50.0

Project

A project is a folder for all objects in an automation task, irrespective of the number of stations, modules, and how they are connected in networks.

R Reference Data

Glossary-6

Reference data are used to check your S7 program and include the cross-reference list, the assignment lists, the program structure, the list of unused addresses, and the list of addresses without symbols.


Glossary

Result of Logic Operation (RLO)

The result of logic operation (RLO) is the result of the logic string which is used to process other binary signals. The execution of certain instructions depends entirely on their preceding RLO.

S S7 Program

A folder for blocks, source files, and charts for S7 programmable controllers. The S7 program also includes the symbol table.

Shared Data Block (DB)

A shared data block is a DB whose address is loaded in the DB address register when it is opened. It provides storage and data for all logic blocks (FCs, FBs, or OBs) that are being executed. In contrast, an instance DB is designed to be used as specific storage and data for the FB with which it has been associated.

Source File

A source file (text file) is part of a program created either with a graphic or a text-oriented editor and is compiled into an executable S7 user program or the machine code for M7. An S7 source file is stored in the “Sources” folder under the “S7 program” folder.

Statement List (STL)

Statement List (STL) is a textual representation of the STEP 7 programming language, similar to machine code. STL is the assembler language of STEP 5 and STEP 7. If you program in STL, the individual statements represent the actual steps in which the CPU executes the program.

Station

A station is a device which can be connected to one or more subnets; for example, the programmable controller, programming device, and operator station.

Status Bit

The status bit stores the value of a bit that is referenced. The status of a bit instruction that has read access to the memory (A, AN, O, ON, X, XN) is always the same as the value of the bit that this instruction checks (the bit on which it performs its logic operation). The status of a bit instruction that has write access to the memory (S, R, =) is the same as the value of the bit to which the instruction writes or, if no writing takes place, the same as the value of the bit that the instruction references. The status bit has no significance for bit instructions that do not access the memory. Such instructions set the status bit to 1 (STA=1). The status bit is not checked by an instruction. It is interpreted during program test (program status) only.


Glossary-7

Glossary

Status Word

The status word is part of the register of the CPU. It contains status information and error information which is displayed when specific STEP 7 commands are executed. The status bits can be read and written on by the user, the error bits can only be read.

Stored Overflow Bit

The status bit OS stands for “stored overflow bit of the status word”. An overflow can take place, for example, after a math operation.

Symbol

A symbol is a name which can be defined by the user subject to syntax guidelines. After it has been declared (for example, as a variable, data type, jump label, block etc) the symbol can be used for programming and for operator interface functions. Example: Address: I 5.0, data type: BOOL, Symbol: momentary contact switch / emergency stop.

Symbol Table

A table in which the symbols of addresses for shared data and blocks are allocated. Examples: Emergency Stop (symbol) -I 1.7 (address) or closed-loop control (symbol) - SFB24 (block).

Symbolic Addressing

In symbolic addressing, the address being processed is designated with a symbol (as opposed to an absolute address).

System Function (SFC)

A system function is a function (without a memory) that is integrated in the S7 operating system and can, if necessary, be called from the STEP 7 user program like a function (FC).

System Function Block (SFB)

A system function block (SFB) is a function (with a memory) that is integrated in the S7 operating system and can, if necessary, be called from the STEP 7 user program like a function block (FB).

U User Data Types (UDTs)

User data types are special data structures which you can create yourself and use in the entire user program after they have been defined. They can be used like elementary or complex data types in the variable declaration of logic blocks (FCs, FBs, OBs) or as a template for creating data blocks with the same data structure.

User Program

The user program contains all the statements and declarations and all the data for signal processing which can be used to control a device or a process. It is part of a programmable module (CPU, FM) and can be structured with smaller units (blocks).

Glossary-8


Glossary

User Program Structure

The user program structure describes the call hierarchy of the blocks within an S7 program and provides an overview of the blocks used and their dependency.

V Variable Declaration Table

The variable declaration table is used for declaring the local data of a logic block, when programming takes place in the Incremental Editor.

Variable Table (VAT)

The variable table is used to collect together the variables that you want to monitor and modify and set their relevant formats.


Glossary-9

Glossary

Glossary-10


Index Symbols (Word) AND Double Word (WAND_DW) instruction, 11-4–11-5 (Word) AND Word (WAND_W) instruction, 11-3–11-4 (Word) Exclusive OR Double Word (WXOR_DW) instruction, 11-8–11-9 (Word) Exclusive OR Word (WXOR_W) instruction, 11-7–11-8 (Word) OR Double Word (WOR_DW) instruction, 11-6–11-7 (Word) OR Word (WOR_W) instruction, 11-5–11-6 #. See Connector =. See Assign

A Absolute addressing, practical application, B-4 Accumulators count value, 6-2 description, 2-9 function, 2-9 ACOS. See Arc Cosine Add Double Integer (ADD_DI), 7-3 Add Integer (ADD_I), 7-2 Add Real (ADD_R), 8-3 ADD_DI. See Add Double Integer ADD_I. See Add Integer ADD_R. See Add Real Address box with address, 2-2 box with address and value, 2-2 description, 3-4 element, 3-2 label of a jump instruction, 14-2 types, 3-4 Address identifier, 3-4 Address Negative Edge Detection (NEG), 4-31 Address Positive Edge Detection (POS), 4-30


Address types, 3-4 Addressing absolute, B-4 definition, 3-2 direct, 3-2 immediate, 3-2 symbolic, B-3 AND, 4-3 truth table, 2-6 AND-before-OR, 4-5 Arc Cosine (ACOS), 8-13–8-15 Arc Sine (ASIN), 8-13–8-14 Arc Tangent (ATAN), 8-13 ASIN. See Arc Sine Assign Value (MOVE), 10-2 Assignment, 4-9 ATAN. See Arc Tangent AUF. See Open Data Block, SIMATIC mnemonic

B BCD Conversion Error (BCDF), 10-3, 10-6 BCD to Double Integer (BCD_DI), 10-6 BCD to Integer (BCD_I), 10-3 BCD_DI. See BCD to Double Integer BCD_I. See BCD to Integer BCDF. See BCD Conversion Error Beginning of a logic string, 2-10 BIE. See Exception Bit Binary Result, SIMATIC mnemonic Binary input inserting, 4-7 negating, 4-8 Binary Result bit (BR), status bit, 2-13 Binary result bit (BR) Exception Bit Binary Result (BR), 15-3 Exception Bit Unordered (UO), 15-6 save RLO to BR memory, 4-11 Bit logic, practical applications, B-3–B-6

Index-1

Index

Bit logic instruction Address Negative Edge Detection (NEG), 4-31 Address Positive Edge Detection (POS), 4-30 assignment (=), 4-9 connector, 4-10 down counter (CD), 4-17 Extended Pulse Timer (SE), 4-20 insert binary input, 4-7 negate binary input, 4-8 Negative RLO Edge Detection (N), 4-29 Off-Delay Timer (SF), 4-26 On-Delay Timer (SD), 4-22 Positive RLO Edge Detection, 4-28 Pulse Timer (SP), 4-18 Reset output (R), 4-13 Reset_Set Flip Flop, 4-33 Retentive On-Delay Timer (SS), 4-24 save RLO to BR memory, 4-11 set counter value (SC), 4-14 set output (S), 4-12 Set_Reset Flip Flop, 4-32 up counter (CU), 4-16 Bit logic instructions, 4-2 See also Status bit instructions practical application, B-3–B-6 Bit logic operation AND, 4-3 AND-before-OR, 4-5 EXCLUSIVE OR logic operation, 4-6 OR, 4-4 OR-before-AND, 4-5 Bits of the status word, changing, 2-9 Blocks calling, 16-2–16-3 exiting, 16-7 Boolean (BOOL), range, 3-3 Boolean logic, 2-6–2-8 Box, instruction as box, 2-2 BR. See Exception Bit Binary Result, international mnemonic Byte, range, 3-3

C CALL. See Call FC/SFC without Parameters

Index-2

Call FC/SFC without Parameters (CALL), 16-2–16-3 Calling function blocks as a box, 16-4–16-6 effects of a call on the status bits, 16-4 supplying parameters, 16-6 Calling functions as a box, 16-4–16-6 effects of a call on the status bits, 16-4 supplying parameters, 16-6 with the Call FC/SFC without Parameters instruction, 16-2 Calling system function blocks as a box, 16-4–16-6 effects of the call on the status bits, 16-4 supplying parameters, 16-6 Calling system functions effects of the call on the status bits, 16-4 supplying parameters, 16-6 with the Call FC/SFC without Parameters instruction, 16-2 CC1 and CC0. See Condition code bits (CC1 and CC0) CD. See Down Counter, international mnemonic CEIL. See Ceiling Ceiling (CEIL), 10-16 Character (CHAR), range, 3-3 Checking the condition code bits (CC1 and CC0), 2-11 CMP_D. See Compare Double Integer CMP_I. See Compare Integer CMP_R. See Compare Real Compare Double Integer (CMP_D), 9-3 Compare Integer (CMP_I), 9-2 Compare Real (CMP_R), 9-4 Comparing the result of math instruction with zero, 15-4 Comparison instructions Compare Double Integer, 9-3 Compare Integer, 9-2 Compare Real, 9-4 practical applications, B-11–B-12 Condition code bits (CC1 and CC0), 2-11 and Exception Bit Unordered, 15-6 effects of math instructions, 7-11, 8-7 relative to the result bit, 15-4–15-5 status bits, 2-11


Index

Conditional Jump (JMP), 14-4 Connector, 4-10 Conversion instructions BCD to Integer (BCD_I), 10-3 BCD to Integer (BDC_I), 10-3 Ceiling (CEIL), 10-16 Double Integer to BCD (DI_BCD), 10-7 Double Integer to Real (DI_R), 10-8 Floor (FLOOR), 10-17 Integer to BCD (I_BCD), 10-4 Integer to Double Integer (I_DI), 10-5 Negate Real Number (NEG_R), 10-13 Ones Complement Double Integer (INV_DI), 10-10 Ones Complement Integer (INV_I), 10-9 Round to Double Integer (ROUND), 10-14 Truncate Double Integer Part (TRUNC), 10-15 Twos Complement Double Integer (NEG_DI), 10-12 Twos Complement Integer (NEG_I), 10-11 Count, up/down, 6-3 Count value format, 6-2 range, 6-2 Counter, instructions with counters down counter (CD), 4-17 set counter value (SC), 4-14 up counter (CU), 4-16 Counters address range, 2-4, 2-5 count instructions, Up Counter/Down Counter (S_CUD), 6-3 count value format, 6-2 range, 6-2 instructions used with counters, practical applications, B-11–B-12 memory area, 6-2 supported counters, 6-2 Counting down, 4-17, 6-7–6-8 up, 4-16, 6-5–6-6 CPU register, 2-9 count value in a counter, 6-2 status word, 2-9 time value in timer cell, 5-3 CPU registers, function, 2-9 CU. See Up Counter, international mnemonic


D Data block (DB) instance, 16-6 memory areas, 2-5 Data block instructions, Open Data Block (OPN), 13-2 Data types, 3-3 Boolean (BOOL), 3-3 BYTE, 3-3 character (CHAR), 3-3 date (D), 3-3 double integer (DINT), 3-3 double word (DWORD), 3-3 integer (INT), 3-3 REAL, 3-3 S5 TIME, 3-3 time (T), 3-3 time of day (TOD), 3-3 WORD, 3-3 DI_BCD. See Double Integer to BCD DI_R. See Double Integer to Real DIV_DI. See Divide Double Integer DIV_I. See Divide Integer DIV_R. See Divide Real Divide Double Integer (DIV_DI), 7-9 Divide Integer (DIV_I), 7-8 Divide Real (DIV_R), 8-6 Double integer (DINT), range, 3-3 Double Integer to BCD (DI_BCD), 10-7 Double Integer to Real (DI_R), 10-8 Double word, as data object, 3-5 Double word (DWORD), range, 3-3 Down counter (CD), 4-17 Down Counter (S_CD), 6-7–6-8

E Edge detection, 4-28 Element, instruction as, 2-2 Element assignment (=), 4-9 EN. See Enable input (EN) EN / ENO, meaning, 2-14 Enable input (EN), parameters, 2-3 Enable output (ENO) See also BR bit parameters, 2-3 ENO. See Enable output (ENO)

Index-3

Index

Examples, practical application of instructions, B-2 Exception Bit Binary Result (BR), 15-3 Exception Bit Overflow (OV), 15-7 Exception Bit Overflow Stored (OS), 15-8–15-10 Exception Bit Unordered (UO), 15-6 and floating-point math, 15-6 Exclusive OR, truth table, 2-8 Extended Pulse S5 Timer (S_PEXT), 5-7–5-8 Extended Pulse Timer (SE), 4-20

F FBD, explanation, 1-1 First Check (FC), 2-10–2-14 result, 2-10 status bit, 2-10 Flip flop, 4-32 Reset_Set, 4-33 Set_Reset, 4-32 Floating-point math and exception bit unordered (UO), 15-6 Subtract Double Integer (SUB_DI), 7-5 Floating-point math instructions Add Real (ADD_R), 8-3 Divide Real (DIV_R), 8-6 Multiply Real (MUL_R), 8-5 Subtract Real (SUB_R), 8-4 Floating-point numbers Compare Real, 9-4 data type for. See Real number, data type

Index-4

Floating-point math, 8-2 Arc Cosine (ACOS), 8-13–8-15 Arc Sine (ASIN), 8-13–8-14 Arc Tangent (ATAN), 8-13 effects on the bits of the status word, 8-7 result within the valid range, 8-7 Floor (FLOOR), 10-17 Format count value, 6-2 time value, 5-2 Function Block Diagram, 1-1 Function blocks (FBs) calling FBs as a box, 16-4–16-6 supplying parameters, 16-6 Functions (FCs) calling FCs as a box, 16-4–16-6 calling FCs with the Call FC/SFC without Parameters instruction, 16-2 supplying parameters, 16-6

G German SIMATIC names and SIMATIC mnemonics, alphabetical list, A-10

I I/O external inputs and outputs, address range, 2-4, 2-5 I_BCD. See Integer to BCD I_DI. See Integer to Double Integer


Index

Input inserting, 4-7 negating, 4-8 Input parameter, as part of a box, 2-3 Instance data block (DI), 16-6 Instruction as box with address, 2-2 as box with address and value, 2-2 as box with parameters, 2-3 as element, 2-2


Instructions alphabetical list, A-10–A-24 German SIMATIC names and SIMATIC mnemonics, A-10 international names and international mnemonics, A-2 international names and SIMATIC equivalents, A-6 SIMATIC names and international equivalents, A-14 SIMATIC names with SIMATIC mnemonics and international mnemonics, A-17 bit logic instructions, 4-2 practical application, B-3 comparison, practical applications, B-11–B-12 counter, practical applications, B-11–B-12 dependent on Master Control Relay (MCR), 16-8 evaluating the condition code bits (CC1 and CC0), 7-11, 8-7 evaluating the OS bit, 7-11, 8-7 evaluating the OV bit, 7-11, 8-7 floating-point math, 8-7 effects on the bits of the status word, 8-7 result within the valid range, 8-7 integer math instructions, 7-11 effects on the bits of the status word, 7-11 valid range for results, 7-11 jump instructions, 14-2 math instructions with integers, practical applications, B-13 practical application, B-2 result bits, 15-4–15-5 rotate instructions, 12-10–12-12 shift instructions, 12-2–12-10 status bit instructions, 15-2–15-10 timer, practical applications, B-7–B-10 word logic, practical applications, B-14–B-15 word logic instructions, practical applications, B-14–B-16 Integer (INT), range, 3-3

Index-5

Index

Integer math instructions Add Double Integer (ADD_DI), 7-3 Add Integer (ADD_I), 7-2 Divide Double Integer (DIV_DI), 7-9 Divide Integer (DIV_I), 7-8 effects on the bits of the status word, 7-11 Multiply Double Integer (MUL_DI), 7-7 Multiply Integer (MUL_I), 7-6 Return Fraction Double Integer (MOD_DI), 7-10 Subtract Integer (SUB_I), 7-4 valid range for results, 7-11 Integer to BCD (I_BCD), 10-4 Integer to Double Integer (I_DI), 10-5 Integers, comparing, 9-2, 9-3 International names and German SIMATIC equivalents, alphabetical list, A-6 International names with international mnemonics, alphabetical list, A-2 International names with SIMATIC mnemonics and international mnemonics, alphabetical list, A-17 INV_DI. See Ones Complement Double Integer INV_I. See Ones Complement Integer

J JMP. See Conditional Jump; Unconditional Jump Jump instruction, jump label as address, 14-2 Jump instructions, 14-2 conditional Jump (JMP), 14-4 unconditional jump, 14-3 Jump label, as address of the jump instruction, 14-2

L Languages, switching between LAD, FBD, and STL, 1-1 Loading a count value format, 6-2 range, 3-3 Loading a time value format, 5-2 range, 3-3 Local data, memory area, address range, 2-4, 2-5

Index-6

M Master Control Relay (MCR) effects on the instructions Set Output (S) and Reset Output (R), 16-8 important notes, 16-9 Master Control Relay (MCR) instructions, 16-8–16-9 Master Control Relay Activate (MCRA), 16-10 Master Control Relay Deactivate (MCRD), 16-10 Master Control Relay Off (MCR>), 16-13 Master Control Relay On (MCR<), 16-13–16-16 nesting, 16-14 Master Control Relay Activate (MCRA), 16-10–16-16 Master Control Relay Deactivate (MCRD), 16-10–16-16 Master Control Relay Off (MCR), 16-13–16-16 Master Control Relay On (MCR<), 16-13–16-16 Math instructions, practical applications with integers, B-13 MCR Functions, important notes, 16-9 MCR<. See Master Control Relay On MCR>. See Master Control Relay Off MCRA. See Master Control Relay Activate MCRD. See Master Control Relay Deactivate Memory area, process input image, 2-4 Memory areas, 2-3 bit memory, 2-4 counters, 2-4 data block, 2-4 I/Os (external inputs and outputs), 2-4 inputs and outputs, 2-4 local data, 2-4 process input image, 2-4 process output image, 2-4 timers, 2-4 MOD_DI. See Return Fraction Double Integer MOVE. See Assign Value Move instructions, Assign Value, 10-2 MUL_DI. See Multiply Double Integer MUL_I. See Multiply Integer MUL_R. See Multiply Real Multiple instances, calling, 16-6 Multiply Double Integer (MUL_DI), 7-7 Multiply Integer (MUL_I), 7-6


Index

Multiply Real (MUL_R), 8-5

N N. See Negative RLO Edge Detection NEG. See Address Negative Edge Detection NEG_DI. See Twos Complement Double Integer NEG_I. See Twos Complement Integer NEG_R. See Negate Real Number Negate Real Number (NEG_R), 10-13 Negative RLO Edge Detection (N), 4-29 Nesting, Master Control Relay (MCR), 16-14

O Off-Delay S5 Timer (S_OFFDT), 5-13–5-14 On-Delay S5 Timer (S_ODT), 5-9–5-10 Ones Complement Double Integer (INV_DI), 10-10 Ones Complement Integer (INV_I), 10-9 Open Data Block (OPN), instruction, 13-2 OPN. See Open Data Block, international mnemonic OR, 4-4 truth table, 2-7 OR status bit, 2-11 OR-before-AND, 4-5 OS. See Exception Bit Overflow Stored OS bit (stored overflow) Exception Bit Overflow Stored (OS), 15-8–15-10 status bit, 2-11 Output parameter, as part of the structure of a box, 2-3 OV. See Exception Bit Overflow OV bit (overflow) Exception Bit Overflow (OV), 15-7 status bit, 2-11 Overflow (OV), effects of math instructions, 7-11, 8-7

P P. See Positive RLO Edge Detection Parameter Enable input (EN), 2-3 Enable output (ENO), 2-3 inputs and outputs as part of a box, 2-3


Pointer, 3-5 POS. See Address Positive Edge Detection Positive RLO edge detection (P), 4-28 Process input image, memory area, 2-4 address range, 2-5 Process output image, memory area, 2-4 address range, 2-5 Program control instructions Call FC/SFC without Parameters (CALL), 16-2–16-3 Master Control Relay Activate (MCRA), 16-10–16-12 Master Control Relay Deactivate (MCRD), 16-10 Master Control Relay Off (MCR>), 16-13–16-16 Master Control Relay On (MCR<), 16-13–16-16 Return (RET), 16-7 Programming, practical applications, B-2 Pulse S5 Timer (S_PULSE), 5-5–5-6 Pulse Timer (SP), 4-18

R R. See Reset output Real number data type, 3-3 range, 3-3 Register, CPU, 2-9–2-14 Reset output (R), 4-13 Resolution. See Time base for S5 TIME Result bits checking the condition code bits (CC1 and CC0), 2-11 instructions, 15-4–15-5 Result of logic operation, description, 2-6 Result of logic operation (RLO) status bit, 2-6 status word bit, 2-10–2-11 RET. See Return instruction Retentive On-Delay Timer (S_ODTS), 5-11–5-12 Retentive on-delay timer (SS), 4-24 Return Fraction Double Integer (MOD_DI), 7-10 Return instruction (RET), 16-7 RLO. See Result of Logic Operation ROL_DW. See Rotate Left Double Word ROR_DW. See Rotate Right Double Word

Index-7

Index

Rotate instructions, 12-10–12-12 Rotate Left Double Word (ROL_DW), 12-10–12-12 Rotate Right Double Word (ROR_DW), 12-11–12-12 Rotate Left Double Word (ROL_DW), 12-10–12-12 Rotate Right Double Word (ROR_DW), 12-11–12-12 ROUND. See Round to Double Integer Round to Double Integer (ROUND), 10-14 RS. See Reset_Set Flip Flop

S S. See Set output S_AVERZ. See Off-Delay S5 Timer, SIMATIC mnemonic S_CD. See Down Counter, international mnemonic S_CU. See Up Counter, international mnemonic S_CUD. See Up Counter/Down Counter, international mnemonic S_EVERZ. See On-Delay S5 Timer, SIMATIC mnemonic S_IMPULS, 5-5 S_ODT. See On-Delay S5 Timer, international mnemonic S_ODTS. See Retentive On-Delay S5 Timer, international mnemonic S_OFFDT. See Off-Delay S5 Timer, international mnemonic S_PEXT. See Extended Pulse S5 Timer, international mnemonic S_PULSE. See Pulse S5 Timer instruction S_SEVERZ. See Retentive On-Delay S5 Timer, SIMATIC mnemonic S_VIMP. See Extended Pulse S5 Timer, SIMATIC mnemonic S5 TIME range, 3-3 time base, 5-2 time value, 5-2 SA. See Off-Delay Timer, SIMATIC mnemonic SAVE. See Save RLO to BR Memory Save RLO to BR memory (SAVE), 4-11

Index-8

SC. See Set counter value, international mnemonic SD. See On-Delay Timer, international mnemonic SE. See Extended Pulse Timer, international mnemonic; On-Delay Timer, SIMATIC mnemonic Set counter value, 4-14 Set counter value (SC), 4-14 Set output (S), 4-12 SF, 4-26 Shift instructions, 12-2–12-9 Shift Left Double Word (SHL_DW), 12-4–12-9 Shift Left Word (SHL_W), 12-2–12-9 Shift Right Double Integer (SHR_DI), 12-9 Shift Right Double Word (SHR_DW), 12-6–12-9 Shift Right Integer (SHR_I), 12-7–12-9 Shift Right Word (SHR_W), 12-5–12-9 Shift Left Double Word (SHL_DW), 12-4–12-9 Shift Left Word (SHL_W), 12-2–12-9 Shift Right Double Integer (SHR_DI), 12-9 Shift Right Double Word (SHR_DW), 12-6–12-9 Shift Right Integer (SHR_I), 12-7–12-9 Shift Right Word (SHR_W), 12-5–12-9 SHL_DW. See Shift Left Double Word SHL_W. See Shift Left Word SHR_DI. See Shift Right Double Integer SHR_DW. See Shift Right Double Word SHR_I. See Shift Right Integer SHR_W. See Shift Right Word SI. See Pulse Timer, SIMATIC mnemonic SIMATIC names and international equivalents, alphabetical list, A-14 SP. See Pulse Timer, international mnemonic SR. See Set_Reset Flip Flop SS. See Retentive On-Delay Timer STA. See Status bit Status bit (STA), 2-11


Index

Status bit instructions, 15-2 Exception Bit Binary Result (BR), 15-3 Exception Bit Overflow (OV), 15-7 Exception Bit Overflow Stored (OS), 15-8 Exception Bit Unordered (UO), 15-6 result bits, 15-4–15-5 Status word binary result bit (BR bit), 15-3 Binary Result bit (BR), 2-13 bits affected by math instructions, 7-11, 8-7 changing the bits, 2-9 condition code bits (CC1 and CC0), 2-11 and Exception Bit Unordered (UO), 15-6 relative to the result bit instructions, 15-4–15-5 description, 2-9 effects of calling an FB, FC, SFB or SFC on the status bits, 16-4 EN = 0, 2-14 EN = 1, 2-14 Exception Bit Overflow, 15-7 Exception Bit Overflow Stored, 15-8–15-10 First Check (FC), 2-10 OR bit, 2-11 OS bit (stored overflow), 2-11 OV bit (overflow), 2-11 result of logic operation (RLO) bit, 2-10–2-11 specifying the invalid range for integer math instructions, 7-11 specifying the valid range for integer math instructions, 7-11 Status bit (STA), 2-11 status bit instructions, 15-2–15-10 structure, 2-9, 15-2 Stored overflow (OS), effects of math instructions, 7-11, 8-7 String of logic operations definition, 2-10 end, 2-10 SUB_DI. See Subtract Double Integer SUB_I. See Subtract Integer SUB_R. See Subtract Real Subtract Double Integer (SUB_DI), 7-5 Subtract Integer (SUB_I), 7-4 Subtract Real (SUB_R), 8-4 SV. See Extended Pulse Timer, SIMATIC mnemonic Symbolic addressing, practical example, B-3 System function blocks (SFBs) calling SFBs as a box, 16-4–16-6 supplying parameters, 16-6


System functions (SFCs) calling SFCs as a box, 16-4–16-6 supplying parameters, 16-6 SZ. See Set counter value, SIMATIC mnemonic

T Time base, resolution, 5-3 Time base for S5 TIME, 5-2–5-14 Time of day (TOD), range, 3-3 Time resolution. See Time base for S5 TIME Time value, 5-3 format in timer cell, 5-3 range, 5-3–5-14 reading, 5-3 syntax, 5-2 Timer, instructions with timers Extended Pulse Timer (SE), 4-20 Off-Delay Timer (SF), 4-26 On-Delay Timer (SD), 4-22 Pulse Timer (SP), 4-18 Retentive On-Delay Timer (SS), 4-24 Timers address range, 2-5 components, 5-2–5-3 Extended Pulse S5 Timer (S_PEXT), 5-7–5-8 instructions used with timers, practical applications, B-7–B-10 memory area, 5-2 numbers supported, 5-2 overview, 5-4 Pulse S5 Timer (S_PULSE), 5-5–5-6 reading the time and the time base, 5-3 time value, 5-2 range, 5-2–5-14 syntax, 5-2 timer instructions Off-Delay S5 Timer (S_OFFDT), 5-13 On-Delay S5 Timer (S_ODT), 5-9 Retentive On-Delay S5 Timer (S_ODTS), 5-11 TRUNC. See Truncate Double Integer Part Truncate Double Integer Part (TRUNC), 10-15 Truth table AND, 2-6 exclusive OR, 2-8 OR, 2-7 Twos Complement Double Integer (NEG_DI), 10-12 Twos Complement Integer (NEG_I), 10-11

Index-9

Index

U Unconditional Jump (JMP), 14-3 UO. See Exception Bit Unordered Up Counter, (S_CU), 6-5–6-6 Up counter, CU, 4-16 Up Counter/Down Counter (S_CUD), 6-3

WXOR_DW. See (Word) Exclusive OR Double Word instruction WXOR_W. See (Word) Exclusive OR Word instruction

X XOR, 4-6

W WAND_DW. See (Word) AND Double Word instruction WAND_W. See (Word) AND Word instruction WOR_DW. See (Word) OR Double Word instruction WOR_W. See (Word) OR Word instruction WORD, range, 3-3 Word, as data object, 3-5 Word logic instructions (Word) AND Double Word (WAND_DW), 11-4–11-5 (Word) AND Word (WAND_W), 11-3–11-4 (Word) Exclusive OR Double Word (WXOR_DW), 11-8–11-9 (Word) Exclusive OR Word (WXOR_W), 11-7–11-8 (Word) OR Double Word (WOR_DW), 11-6–11-7 (Word) OR Word (WOR_W), 11-5–11-6 practical applications, B-14–B-16

Index-10

Z Z_RUECK. See Down Counter, SIMATIC mnemonic Z_VORW. See Up Counter, SIMATIC mnemonic ZAEHLER. See Up Counter/Down Counter, SIMATIC mnemonic ZR. See Down Counter, SIMATIC mnemonic ZV. See Up Counter, SIMATIC mnemonic


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Siemens Simatic S 7 300 - 400 -Function Block Diagram for S7-300 and S7-400

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