Semiconductor Process Engineer Resume

Semiconductor Process Engineer Resume Desired Desired Type of Desired

Industry: Manufacturing Job Location: Phoenix, Arizona Position: Full-Time Permanent Wage:

Job Level: Experienced with over 2 years experience Highest Degree Attained: Bachelors

SpiderID: 63402 Date Posted: 8/24/2012 Availability Date: U.S. Work Authorization: Yes Willing to Travel: Yes, Less Than 25% Willing to Relocate: Yes

Objective: Obtain a position in Process/Development Engineering to utilize and grow my technical skills and also provide me with opportunities for advancement and personal development. Experience in semiconductor (Si and GaN) manufacturing environment; strong analytical ability, excellent communication skills and innovative i nnovative root cause problem resolution.

Experience: WORK EXPERIENCE: Process Development Engineer October 2011 – Present Transphorm, Transphorm, Goleta, CA Work with team of scientists, engineers, and technicians to develop fabrication processes for advanced GaN-based electronic devices. Conduct periodically qualification on tools, making sure that all measurements stay within the tools specs. Wafers disposition.

Senior Process Eng. Technician May 2010 – September 2011 Transphorm, Transphorm, Goleta, CA Worked as a Senior Process Eng. Technician in an early stage start-up company supporting R&D engineers and processing of semiconductor (GaN) in a clean room environment from the front-end to the back-end back- end process. I’m certified in chemical wet etch and Dry etch; metal and dielectric deposition (e-Beam CHA, Sputter PERKIN 400 and PECVD Novellus); Metal LIFT-OFF; Photolithography (Coat, Exposure, Develop, Overlay and Defect Inspections); Visual Defect Inspection using microscope; Metrology (AFM, Ellipsometer, Nanospec, Veeco Dektak Profiler) and Auto Probe (PCM, Switching and DC testing). Support Engineering and Development on an “as needed” basis to perform basic tests and non-standard processing. Conduct periodically qualification on tools, making sure that all measurements stay within the tools specs. I monitor and inspect product run operations, using metrology equipments and microscopes, to determine control and output quality of each process, and where applicable, isolate any spec violation issues and tolerance margins.

Semiconductor Technician II Feb 2009 – Apr 2010

Honeywell Aerospace, Redmond, WA First, I worked as a contractor for Manpower and became a permanent full time employee for Honeywell, worked in a clean room environment under the MEMS division. Perform various silicon and gl ass wafer processing steps as assigned; include working with hazardous chemicals, operating and maintaining complex automated equipment used in production of silicon wafers. I’m certified i n chemical wet etch and cleaning; EDP; metal LIFT-OFF; PROBE (Wafer test); EVG 520 and EVG 620 (Wafers Bonding). I monitor and inspect product run operations to determine control and output quality of etch procedures, and where appli cable, isolate any spec violation issues i ssues and tolerance margins.

Production Specialist May 2007 – Jan 2009 Microchip Technology, Gresham, OR As a production specialist I drove quality controlled production in etch department (200mm wafer fabrication facility). I have operated complex equipment and tooling for wafer fabrication and certified in the functional use of the following tools: LAM Alliance 9400PTX Etcher; LAM Alliance 9600 (Metal Etch) PTX Etcher: TEL DRM and PE Plasma Etcher; Fusion Gemini UV Bake; Semitool SST; RUDOLPH and Hitachi CD SEM. I monitored and inspected product run operations to determine control and output quality of etch procedures, and where applicable, isolate any spec violation issues and tolerance margins. Machine (Reactor) Operator March 2006 – May 2007 SEH-A Company, Vancouver, WA Worked for Volt services as a machine (reactor) operator at SEH-A in a clean room environment under the Epitaxial department. Operated reactors (AMT and SMT) used in the production of silicon wafers Worked from product specifications to perform production tasks and drive quality output Checked and inspected operation against predetermined tolerances and specifications Drove quality improvement metrics up by 10% from baseline ACHIEVEMENTS/AWARDS Member of International Honor Society of the Two-Year College (PHI THETA KAPPA)

Education: B.S. Electrical Engineering, Portland State University, Portland OR (June 2008) Skills: Lean Manufacturing SPC (Statistical Process Control) DOE using JUMP(Design of experiment) Hardware: AMT and ASM reactor operation growing Epitaxial Silicon wafers Test equipments such as Oscilloscope Tools and Metrology equipments usage i n Fab (Semiconductor) Language skills: English, French Behavioral: Strong team orientation, fast learner, communication skills

semiconductor process engineer Resume

RESUME DETAILS

Objective: To secure a process engineer / failure analysis engineer position Professional Summary: An interdisciplinary researcher possessing solid background in materials science and abundant hands-on experience in semiconductor device fabrication. Professional Experience Postdoctoral Scholar, Arizona State University, Tempe, AZ - 2008 to present * Created a device fabrication process for metallic nanolasers consisting of InGaAs / InP epitaxial layers. Major fabrication steps include photolithography, e-beam lithography (EBL), reactive ion etching (RIE), inductively coupled plasma RIE (ICP RIE), dielectric thin film deposition by remote plasma enhanced chemical vapor deposition (PECVD), and metal depositions by evaporation and sputtering. * Characterized III-V and II-VI semiconductor nanowires using transmission electron microscopy (TEM). Integration Engineer, Engineer, Intel, chandler, AZ - 2005 to 2006 * Oversaw process development, development, including materials selection, process optimization, reliability testing and failure analysis * Set yield targets for platforms and ensured the targets were met by identifying major yield hitters for yield improvement, communicating communicating with different groups about trouble-shooting, and performing analyses by 7 -step, FMEA, and design of experiment (DOE). Associate Process Technologist, Department of Electrical Engineering, Arizona State University, Tempe, AZ - 2005 * Took full responsibility for the improvement of functionality of an EBL system. Creatively applied cold development technique and improved spatial resolution of the EBL system to 10nm, which is beyond the 20nm limit provided by the manufacturer. manufacturer. Fabricated gratings with 10nm-wide lines and sub-50nm pitch on 8 -inch Si wafers. * Involved in d aily maintenance of the EBL fabrication system. Worked with the vendor engineers for a major preventative maintenance. Research Assistant, Arizona State University, Tempe, AZ - 2000 to 2005 * Studied various magnetic materials using TEM, investigated the influence of microstructure microstructure on magnetic transport data, and applied the results to the development of tunnel magnetoresistance (TMR) based devices. * Independently developed a process flow and fabricated magnetic nanostructures using EBL. I nvestigated nvestigated the interaction between microstructure and magnetization processes using field-emission scanning electron microscopy (FESEM) and off-axis holography. Discovered a unique pattern as a good candidate for high density data storage devices. Quality Engineer, Changsha Fertilizer-Machine Factory, China -1996 to 1997 * Inspected quality of the materials for high-pressure vessels. Education Ph.D. in Materials Science and Engineering Arizona State University, Tempe, AZ ( 2005) M.S. in Materials Science and Engineering University of Science and Technology Beijing, China (2000) B.S. in Materials Science and Engineering, Metallurgy specialty Central South University of Technology, Technology, China (1996) Technical Skills Semiconductor Device Fabrication: Hands-on experience in a broad spectrum of device processing and characterization characterization equipment in class 100 cleanroom: * Photolithography Photolithography Fabricated photomasks using Heidelberg DWL 66 Laser Writer, and performed contact photolithography using EVG 620 Front and Backside Aligner for wafer alignment. * E-beam lithography Fabricated patterns on various semiconductor and dielectric substrates using JEOL JBX-6000FS/E EBL system. Created processes using PMMA and ZEP resists. * Thin film deposition Deposited metal thin films using Lesker physical vapor deposition (PVD) Magnetron Sputter, Torrvac VC-320 electron beam evaporator, and Edwards Auto306 thermal evaporator. Deposited dielectric thin film using PlasmaQuest 333 remote plasma-enhanced chemical vapor deposition (RPECVD). * Etching

Investigated plasma etching of InP and InGaAs multilayers using methane (CH4) and hydrogen (H2) gas mixtures by STS ICP All General Etch (AGE). Performed SiO2 and Si3N4 etching using Oxford Instrument PlasmaLab 80+ RIE. * Metrology Skillful at Woollam Ellipsometer, Filmetrics F20 Reflectance Spectrometer Spectrometer and Tencor P2 Profilometer. Materials Characterization: Characterization: Years of hands-on experience in TEM sample preparation and materials characterization using various electron microscopes. * Skillful at several TEM microscopes, including JEOL JEM-2010F (TEM/STEM), JEOL JEM-4000EX, JEM-4000EX, Philips CM200FEG (TEM/STEM) and TOPCON 002B electron microscopes. * Analyzed samples using FEI Nova 200 (SEM/FIB), FEI XL30 ESEM-FEG and Hitachi S4700 FESEM with highresolution images and EDX. * Specialized in electron-energy-loss electron-energy-loss spectroscopy (EELS) and energy dispersive X-ray (EDX) techniques using JEOL 2010F TEM/STEM and Philips CM200-FEG TEM/STEM. * Utilized X-Ray Diffractometer Diffractometer (XRD), Rutherford backscattering spectroscopy (RBS), and atomic force microscopy (AFM) on materials characterization. characterization. Relevant Courses * Advanced Silicon Processing * Fundamentals of Solid State Devices * Semiconductor Semiconductor Characterization * Growth and Processing of Semiconductor * Design of Engineering Experiments Experiments * TEM, HRTEM and labs * Advanced Materials Characterization * Materials Thermodynamics and Kinetics * Defects in Crystalline Solids * Reliability Engineering Projects Cooperated with Intel in a reliability project studying Cu migration behavior using biased highly accelerated stress test (BHAST) data. (2007) Publications 'Fabrication and photoluminescence property of vertical InP nanowires and InGaAs-based multilayer nanowires by inductively coupled plasma reactive ion etching', H. Wang, M. Sun, and C.Z. Ning (to be submitted) 'Low temperature ZEP-520A development process for enhanced critical dimension realization in reactive ion etch polysilicon', H. Wang, G.M. Laws, S. Milicic, P. Boland, A. Handugan, M. Pratt, T. Eschrich, S. Myhajlenko, J.A. Allgair, and B. Bunday, J. Vac. Sci. Technol. B 25 (1), (2007) 102 'Remanent states of nanoscale Co ferromagnets having different shapes', H. Wang, H. Hu, M.R.McCartney and David J.Smith, J. Magn. Magn. Mater., 303 (2006) 237 'Structural Characterization Characterization of Base/Collector Interfaces Interfaces for Magnetic Tunnel Transistors Grown on Si (001)', H. Wang, Martha R. McCartney, David J. Smith, Xin Jiang, Roger Wang, Sebastiaan Sebastiaan van Dijken, and Stuart S.P. Parkin, J. Appl. Phys. , 97(2005), 104514 'Off-axis electron holography of nanoscale ferromagnetic ferromagnetic slotted circular elements', H. Hu, H. Wang, M.R.McCartney, M.R.McCartney, and David J.Smith, Phys. Rev. B, 73 (2006), 153401 'Remanent states and magnetization reversal for nanopatterned Co elements', N. Agarwal, H. Wang, David J.Smith and M.R.McCartney, IEEE Transactions on Magnetics, 42 (2006), 2414 'Study of in-situ magnetization reversal processes for nanoscale Co rings using off -axis electron holography', H. Hu, H. Wang, M. R. McCartney, and David J. Smith, J. Appl. Phys. 97(2005), 054305 'Switching behavior of nanoscale Co ferromagnetic elements elements using off-axis holography', H. Hu, H. Wang, M. R. McCartney, and David J. Smith, J. Magn. Magn. Mater., 290(2005) , 234 'Virgin domain structures in mesoscopic Co patterns: Comparison between simulation and experiment', S. Cherifi, R. Hertel, H. Wang, R. Belkhou, A. Locatelli, S. Heun, A. Pavlovska, J. Kirschner and E. Bauer, J. Appl. Phys., 98 (2005), 043901 'Microscopy of mesoscopic ferromagnetic systems with slow electrons', E. Bauer, R. Belkhou, S. Cherifi, R. Hertel, S. Heun, A. Locatelli, A. Pavlovska, R. Zdyb, N. Agarwal, and H. Wang, Surf. Interface Anal. 38 (2006), 1622 Conference Presentations 'Characterization 'Characterization of magnetic tunnel tunnel transistors', poster presentation presentation at 9th Joint MMM/Intermag Conference, 2004 'Low Temperature ZEP-520A Development Process for Enhanced Critical Dimension Realization in RIE Etched PolySilicon', poster presentation at 50th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (EIPBN 2006) Honors and Activities Primary Mathematics Grade3 teacher at a weekend school 2009. Awarded Graduate Tuition Scholarship over the years 2000-2005. Excellent Graduate cadre of Graduate School, Univ. of Sci. and Tech. Beijing 1998 Excellent undergraduate, Central South Univ. of Tech. 1993, 1995 Mentor in Engineering and Applied Sciences Graduate Students Association(EAS GSA) 2003

Summary: . .

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Professional in Micro/Nanotechnology (MEMS, Semiconductor) system design, fabrication, and testing; 5 years experience of class 100 cleanroom for semiconductor fabrication processes (lithography, RIE/ICP-DRIE plasma etch, PECVD, PVD, etc.) and metrology (SEM, AFM, Surface profiler, etc.) for complex micro fabrication process development and integration; 5 years of experience for MEMS and electronic devices development; 5 years of experience in design of experiments (DOE) and statistical data analysis; Experience with sim ulation and mode ling for fabrication process, MEMS(Coventor), and electronic devices; Expertise in optical and electrical testing system setup; Strong background knowledge in semiconductor, electronics, optical detection devices; Fast learning, problem solving skills, and team spirit; Provided team leadership and projects management for multiple projects;

Objective I am seeking a full-time position as a semiconductor fabrication process engineer, testing engineer in semiconductors or MEMS for new product/process development or resear ch scena rios, ut ilizing my strong technical skills, systematic consideration, research, and management experiences to contribute to the success of your company. Education Ph.D. Microelectronics Engineering 2007 - 2012 Louisiana Tech University Dissertation: Basic Capillary Microfluidic Chip and highly Sensitive Optical Detector for Point of Care Application M.S. Mathematics and Statistics 2009 - 2011 Louisiana Tech University Thesis: Multiple Comparison Procedures for Population Variances B.S. Electronics and Information Engineering 2002 - 2006 Nantong University, China Academic Work Experience Graduate Research Assistant 2007 - 2012 Institute for Micromanufacturing (IFM) Louisiana Tech University . Fabrication the microelectronic devices with the wafers' diameter range from 4 inch to 8 inch for MEMS/NEMS applications; . Fabricated a MEMS device with photolithography and bonded two wafers with different approaches such as fusion bonding and anodic bonding, etc; . Strong background in a clean room environment such as conducting the fabrication process and steps for the semiconductor manufacture (MOSFET device with generating the proper I-V characteristics, potential contours, etc.); . Investigation in the optimization of wafer to wafer bonding parameters for bonding strength;

. Designed semiconductor chips and biochips for microfluidics and lab-ona-chip applications; . Bonded the fabricated MEMS chip (actuators) onto the specific PCB for the whole device packaging with ESEC 3018 wire bonder; Proficiency in wire bonding ball (Kulicke and Soffa Model 4524) and wedge (West Bond Model 7476E-79) bonders; . Utilized ICP isotropic etching and the properties of plasma etching such as the chamber pressure, plasma source power, substrate power, SF6 (sulfurhexa?uoride) ?ow rate relating to Si etching rate, undercutting rate, and isotropic ratio to release SiO2 microcantilever beams from the Si substrate and optimized the silicon etching rate; . Fabricated the SiO2 cantilever beams and released other suspending parts from the silicon substrate with high etch rate and good processing controls with ICP etching; . Conducted an investigation in high aspect ratio nanostructures on silicon wafers; . Developed some functional MEMS and electronic prototype devices from the ground up (nanostructured optical sensor, nanoassembly-enabled field-effect transistor/FET, biosensor; . Designed, fabricated, tested and packaged glucose sensor devices based on thin film field effect transistor (TFET) model and developed sensor interface circuit for detecting the fluorescence concentration of the cells between normal and prostate cancer patients; . Investigated polydimethylsiloxane (PDMS) characterization and bonding parameter properties for the micro testing analysis systems; . Designed and fabricated polymer organic field effect transistors using lithography or layer by layer self-assembly and spin-coating techniques; . Tested and electrically characterized polymer-based microelectronic devices with Keithley instrument; . Investigated PEDOT/PSS film with Fourier Transform Infrared Spectroscopy (FT-IR). Teaching 2009 - 2011 College of Engineering and Louisiana Tech University . Industrial Statistics (Grading homework and exams); . Mathematics Methods for Engineering Application (Giving Lectures and grading homework); . Advanced Microfabrication with CAD (Fabrication simulation/modeling demonstration);

Assistant Science

several process

Technical Skills . Mask layout design and photolithography: Layout design (L-edit), Cr mask fabrication, spin coating, mask aligner, contact printing photo lithography process for positive (S1813, SPR 220, etc.) and negative (SU8, KMPR 1000 series, etc.) thin and thick film photoresist (0.3µm to 300 µm in thickness); Maintenance and troubleshooting for SUSS MA6 mask aligner; . Layer-by-layer nanoassembly based field-effect-transistor and semiconductor fabrication process: Involved in design of fabrication process flow and layout to integrate bottom-up with top-down approaches. Participated and advised group member to successfully fabricated functional MOSFET devices. Conducted initial testing of IDVDS curve, gate voltage control on the fabricated MOSFET;

. Dry etching: ICP-DRIE, RIE process for Si Bosch Process, dielectric film (Si3N4, SiO2, PZT), metal films (Pt), organics (photo-resist ashing, etc.), polymer, Si XeF2 isotropic etching for MEMS device releasing; . Wet etching: BOE (SiO2, PZT), KOH (Si), Metal etchant (Ni, Cu, Al metal film etching); . Thin film growth, evaporation and deposition: thermal oxidation, PVD (Ebeam evaporation/DC sputtering for metals), PECVD (for polymer, Si3N4, SiO2 thin film), Sol-gel thin film process (PZT film); . Skills for annealing, wafer dicing, bonding, and other nanofabrication; . Fabrication Metrology and Testing for topology, electrical, optical properties: Surface profiler, AFM, SEM, ellipsometer, spectrometer (optical properties), probe station (electric characteristics), data Acquisition system programmed by LabVIEW; . FEA based micro/nano system, fabrication and property simulation/modeling: Experience in Coventor 2008, COMSOL Multiphysics 4.0, TCAD (TSUPREM4 and MEDICI); . Computer skills, programming, design of experiments (DOE), data analysis: JMP (for DOE: screening design, full factorial designs and fractional factorial designs and other statistical analysis), Matlab, VC++ programming language, skilled in Microsoft office (Word, Excel, PowerPoint); . Strong written and oral communication skills on English and Chinese. Papers and Publications . Mingjin Yao and Ji Fang, "A Novel High-Sensitive Miniaturized Optical System for Fluorescence Detection," In proceeding of SPIE Photonics West Conference, San Francisco, 2011. . Mingjin Yao and Ji Fang, "Modified PDMS for Microfluidic Applications: Capillary Stop Valve," In proceeding of 86th Annual Meeting of Louisiana Academy of Sciences in Louisiana State University at Alexandria, 2012. . Mingjin Yao an d Ji Fang, "Hydrophilic PEO-PDMS for Mi crofluidic Applications," Journal of Micromachining and Microengineering, 22 (2), 2012. . Mingjin Yao, Girish Shah and Ji Fang, "Capillary Stop Valve Design with Modified PDMS," Journal of Advanced Science, Engineering and Medicine, 4, 1-8, 2012. . Mingjin Yao, Girish Shah and Ji Fang, "Highly Sensitive Optical Detector with Autonomous Microfluidic Chip for Point of Care Applications," Journal of Micromachines, 3, Phone Number. Number.

Full Name [Street, City, State, Zip] | [Phone] [Email Address]

PROCESS ENGINEER A process engineering professional offering many years of cross-company experience in the production process, skilled in achieving high level of accuracy and problem solving, utilizing exceptional analytical abilities, focus dedication, and commitment to hard work. Career Objective - Seeking a position as a process engineer, who can contribute to the process development in designing equipment, perform process analysis, understand the reactions taking place, install control systems as well as upgrade the electrical and mechanical design process. Core Knowledge and Functional Skill Areas 

Hardware and mechanical design testing applications

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Technical documentation: Standards/procedures

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Security clearance

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Heat & material balance

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Relief device calculations

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P & ID review

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Process simulators: [list]

PROFESSIONAL EXPERIENCE Rar-Theon

Tewksbury, MA

2003 – Present

Process Engineer Was closely involved in every stage of the production process of [products] for the company. KEY PERFORMANCE HIGHLIGHTS Performance Analysis 

Assessed relevance of every process and arranged engineering equipment accordingly – Reviewed existing data to ensure sufficient information for process to be executed.

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Effectively arranged all relevant equipment [examples here] in acc ordance with close analysis of existing process of production.

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Supervised safety features and process efficiency – Designing new processes and introducing improvements as required.

QA test

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Ran safety and quality tests, installed upgrades, performed troubleshooting, created new production units.

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Used flow charts, graphs, diagrams, reports, and other documentation do cumentation to monitor and improve the process.

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Performed environmental environmental monitoring, handled facility safety and functionality, in accordance with regulations, and in cooperation with quality-control and maintenance engineer teams.

Other functions 

Monitored stock: evaluated availability and accessibility.

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Assessed and handled time and cost constraints. Key Skills/Competencies Skills/Competencies

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High level of accuracy and attention to details.

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Good problem solving and analytical skills.

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Ability to work in a team.

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Excellent communication proficiency

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Managerial and interpersonal expertise

Education & Qualifications MIT

Cambridge,MA

2000 – 2003

Bachelor’s in Nuclear/mechanical/man Nuclear/mechanical/manufacturing/chemical ufacturing/chemical

University of Massachusetts

Amherst, MA

1996 – 1999

Associate degree in applied chemistry/chemistry/polymer chemistry/chemistry/polymer science/technology

Objective: Seeking a semiconductor process/device engineer position in a leading semiconductor organization to utilize 3+ years of experience in semiconductor device design, fabrication and characterization. Experience: • 4 years of experience in MEMS device design, simulation, fabrication and characterization while working in Class 100 clean room • 3+ years of research resear ch experience in developing organic field effect and electrochemical transistors • Strong understanding of semiconductor device physics and understanding knowledge of DOE and SPC • Self -motivated -motivated individual with excellent interpersonal and team leading/player skills

Education: Doctor of Philosophy, Engineering (Electrical) GPA 3.84 Nov 2011 Louisiana Tech University, Ruston, LA Master of Science, Engineering (Electrical) GPA: 3.84 Nov 2011 Louisiana Tech University, Ruston, LA Bachelor of Technology, Electronics &  Communications Engineering GPA: 3.70 May 2006 Jawaharlal Nehru Technological University, Hyderabad, India

Skills: Design & Simulation: L-Edit, Solid Edge, CoventorWare, COMSOL, T-CAD, P-SPICE, Solid Works, AutoCAD, MATLAB Fabrication: Photolithography, Dry etching (ICP, RIE), Soft lithography,

Wet etching (BOE, Piranha & KOH), Layerby-layer Nanofabrication Characterization: Characterization: Electrical Probe Station (I-V and MOSFET), Surface Profilometer, Fluorescence Microscope, UV-Vis & Fluorescence Spectrophotometer Analysis & Productivity: SigmaPlot, Image-Pro Plus, ImageJ, C, MS Word, Excel, PowerPoint

Additional Information: Dissertation: Micromixers and Polymer Based Transistors for Biosensor Applications Developed a MEMS based lab-on-a-chip (LOC) for biosensor applications as a part of multi-disciplinary multi university collaborative project  Developed a novel omega channel micromixer that is capable of mixing 150 nL volume samples  Optimized the micromixer designs using COMSOL and CoventorWare simulation tools  Fabricated microfluidic devices in Class 100 clean room using photolithography and ICP etching  Developed a flexible and disposable micromixer with 97% mixing efficiency  Fabricated and characterized polymer based field effect transistor  Developed simple, robust and costeffective electrochemical transistors on flexible substrate  Engineered a novel inexpensive onestep method for transistor fabrication  Optimized the transistor design to yield an ON/OFF ratio of 500  Developed a miniaturized glucose sensor with a wide dynamic range of 1 µM – 10 mM  Developed a low-cost novel glutamate sensor with a dynamic range of 1– 1 –100 µM 