Sanity Checks

Checks in Netlist:

1) Number Number of Output Output Pins connect connect to Power Power/Grou /Ground nd 2) Number Number of Inst Inst with with input pins tied tied toget together her 3) Number Number of TiHi/Lo TiHi/Lo terms terms nets not connected connected to instnce instnces s PG terms !) Number Number o off Input/I Input/InOut nOut "oting "oting pins #) $Numbe $Numberr of Output Output "ot "oting ing pins pins %) $Numbe $Numberr of Output Output "ot "oting ing nets nets &) Number Number of nets with tri'stte tri'stte dri(ers dri(ers ) Number Number of nets with with Pr** Pr**e* e* dri(ers dri(ers +) Numbers Numbers of nets with with mu*tip mu*tip*e *e dri(ers dri(ers 1,) 1,) Numb Number er of High High -nou noutt net nets s 11) 11) Numb Number er of nets nets with with no dri( dri(er ers s 12) $Numbe $Numberr of ce**s ce**s of of input input net*is net*istt mr. mr.ed ed don dontt use0 use0 13) 13) $er $erif if  net* net*is istt is is ni4 ni4ue ue00 1!) 1!) $5he $5hec. c. the the ss ssig ign n st stte teme ment nt00 Check in Physical Library

1) 2) 3) 4) 5)

5e** with PG PIN missing 5e**s with missing dimension 5e**s pin with missing direction 5e**s pin with missing geometr 5e**s PG pin with missing geometr 6) 5e**s with missing L6-

Check in timing Library

1) 5hec.s whether whether the ce**s ce**s used in the design design h(e been been de7ned in the timing timing *ibrr0 2) If mu*tip*e mu*tip*e de* de* corners corners re being n*8 n*8ed ed then ech ce** ce** needs to be chrcteri8ed for ech corner Check timing constraint fle (SDC) 1) 2) 3) !)

5*oc. 5*oc. re reching ching ** c*oc. c*oc. pins of of "ops0 "ops0 Ports Ports missing missing i/p nd o/p de*s0 de*s0 Ports Ports missing missing s*ew/*od s*ew/*od constrints constrints00 9u*tip*e 9u*tip*e c*oc.s c*oc.s dri(ing dri(ing sme regist register er00

What is the error i one cell missing LEF an !resent in netlist  6:; 9:2:1 Warning " 9:2:1 " 9:2:1 hs no phsic* *ibrr or hs wrong dimension (*ues  
What is the error i one cell missing (#li$) an !resent in netlist 6= 9:2:1

E%%&%" ce** >9:2:1 is not de7ned in ** timing n*sis (iew0  The ce** shou*d be de7ned in ** n*sis (iews0 E%%&%" some ce**s re missing from ech of the timing n*sis (iews0 P*ese chec. the *ibrr 7nding of instnces in cti(e (iews using the commnd ?check'instance'li$rar'in'ie*s@ nd set the missing in corresponding (iews ?@@@@@Li$rar+is+atchError@@@@@@@@@@@@@@@@@@@@

What is the error i ,create'clock is not efne- in SDC. No constrined timing pth found0 Aesign m not be constrined or *ibrr is missing timing informtion0 $$ I ws found this error in report Btiming

What is the error i oot!rint is not efne in #li$. no wrning or no error is disp*ed0

What is the error i a /0 miss in LEF. 5ombintion* ce**; no pin p*cement C$$ but pin is t orienttion) De4uenti* ce**; pin is getting p*ced but no connecti(it is being estb*ished0 $$$$$$$obser(ed in routing stge

Wh *e ont hae assign statements in netlist In hierrch if we wnt to connect from one output of the ce** to input of nother ce** we need  ssign sttement In "t design we direct* connect from on ce** to nother ce**

What *ill ha!!en *hen the assign statement in the netlist.  Too* wi** do temporr buEers to remo(e ssign sttements $$ Aone with setDossign with 22 ssigns remo(ed0 $$ t stge p*ce in -*oorp*n mode0

What is the error i tech#le not loae frst# E%%&%" No techno*og informtion de7ned in the 7rst *ef 7*e