SiHP18N50C, SiHF18N50C Vishay Siliconix
Power MOSFET FEATURES
PRODUCT SUMMARY
VDS (V) at T J ma m ax.
Low Figur Figure-o e-of-M f-Meri eritt Ron x Qg
560
RDS(on) (Ω)
VGS = 10 V
• 100 % Aval Avalanc anche he Teste Tested d
0.225
Qg (M (Max.) (nC)
76
• High Peak Current Current Capabili Capability ty
Qgs (n (nC)
21
• dV/ dV/dt dt Rugged Ruggednes ness s
Qgd (n (nC)
29
• Impr Improv oved ed trr /Qrr
Configuration
Single
• Imp Improv roved ed Gate Gate Charg Charge e • High Power Power Dissipati Dissipations ons Capabilit Capability y
D
TO-220
• Compliant Compliant to RoHS RoHS Directive Directive 2002/95/ 2002/95/EC EC
TO-220 FULLPAK
G
G
D
S GDS
S N-Channel MOSFET
ORDERING INFORMATION
Package
TO-220
TO-220 FULLPAK
Lead (Pb)-free
SiHP18N50C-E3
SiHF18N50C-E3
ABSOLUTE MAXIMUM RATINGS
TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
V GS
± 30
Continuous Drain Current (T J = 150 °C) a
VGS at 10 V
TC = 25 °C TC = 100 °C
Pulsed Drain Currentb Linear Derating Factor
IDM FULLPAK
0.3
TO-220 FULLPAK
Peak Diode Recovery dV/dt d Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) d
for 10 s
PD
A
72 1.8
EAS
V
18 11
TO-220
Single Pulse Avalanche Energy c Maximum Power Dissipation
ID
UNIT
361 223 38
dV/dt
5
T J, Tstg
- 55 to + 150 300
W/°C mJ W V/ns °C
Notes a. Drain current current limited by maximum maximum junction junction temperature. temperature. b. Repetitive rating; rating; pulse width width limited by by maximum junction temperature. temperature. c. VDD = 50 V, starting T J = 25 °C, L = 2.5 mH, R g = 25 Ω, IAS = 17 A. d. ISD ≤ 18 A, dI/dt ≤ 380 A/µs, V DD ≤ VDS, TJ ≤ 150 °C. e. 1.6 mm from from case. case.
* Pb containing terminations are not RoHS compliant, exemptions may apply Document Number : 91374 S09-1257-Rev. B, 13-Jul-09
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SiHP18N50C, SiHF18N50C Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
Maximum Junction-to-Ambient Maximum Junction-to-Case (Drain)
SPECIFICATIONS
TO-220 FULLPAK TO-220 FULLPAK
TYP.
MAX.
-
62
RthJA RthJC
-
65
-
0.56
-
3.29
UNIT
°C/W
TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V DS
VGS = 0 V, I D = 250 µA
500
-
-
V
Static Drain-Source Breakdown Voltage VDS Temperature Coefficient
Reference to 25 °C, I D = 1 mA
-
0.6
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
3.0
-
5.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
I DSS
VDS = 500 V, V GS = 0 V
-
-
25
VDS = 400 V, V GS = 0 V, T J = 125 °C
-
-
250
-
0.225
0.270
Ω
-
6.4
-
S
Gate-Source Threshold Voltage (N)
Drain-Source On-State Resistance Forward Transconductancea
ΔVDS /TJ
R DS(on) gfs
VGS = 10 V
ID = 10 A
VDS = 50 V, I D = 10 A
µA
Dynamic Input Capacitance
Ciss
VGS = 0 V,
-
2451
2942
Output Capacitance
Coss
VDS = 25 V,
-
300
360
Reverse Transfer Capacitance
Crss
f = 1.0 MHz
-
26
32
Internal Gate Resistance
Rg
f = 1.0 MHz, open drain
-
1.1
-
-
65
76
-
21
-
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
29
-
Turn-On Delay Time
td(on)
-
80
-
Rise Time Turn-Off Delay Time Fall Time
tr t d(off)
VGS = 10 V
I D = 18 A, V DS = 400 V
VDD = 250 V, I D = 18 A Rg = 7.5 Ω, VGS = 10 V
tf
pF Ω
nC
-
27
-
-
32
-
-
44
-
-
-
18
-
-
72
-
-
1.5
V
-
503
-
ns
-
6.7
-
µC
-
30
-
A
ns
Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
t rr
Body Diode Reverse Recovery Charge
Q rr
Reverse Recovery Current
I RRM
MOSFET symbol showing the integral reverse p - n junction diode
D
A
G
TJ = 25 °C, I S = 18 A, V GS = 0 V TJ = 25 °C, I F = IS, dI/dt = 100 A/µs, V R = 35 V
S
Note a. Repetitive rating; pulse width limited by maximum junction temperature.
The information shown here is a preliminary product proposal, not a commercial product datasheet. Vishay Siliconix is not committed to produce this or any similar product. This information should not be used for design purposes, nor construed as an offer to furnish or sell such products.
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Document Number: 91374 S09-1257-Rev. B, 13-Jul-09
SiHP18N50C, SiHF18N50C Vishay Siliconix TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
70
) A ( t n e r r u
C n i a r D , D I
100
VGS Top 15 V 60 14 V 13 V 12 V 11 V 50 10 V 9.0 V 8.0 V 40 7.0 V 6.0 V Bottom 5.0 V 30
TJ = 25 °C 10
C n i a r
1
u
D , D I
20
TJ = 150 °C
) A ( t n e r r
TJ = 25 °C
0.1
7.0 V
10 0
0.01 0
6
12
18
24
30
5
Fig. 1 - Typical Output Characteristics, TC = 150 °C (TO-220)
40
VGS 15 V 14 V 13 V 12 V 30 11 V 10 V 9.0 V 8.0 V 7.0 V 20 6.0 V Bottom 5.0 V
) A ( t n e r r u
C n i a r
D , D I
10
n o ( S D
6
12
18
24
30
VDS, Drain-to-So urce Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C (TO-220)
Document Number: 91374 S09-1257-Rev. B, 13-Jul-09
8
9
10
Fig. 3 - Typical Transfer Characteristics
e 3 c n a t s i 2.5 s e R n 2 O ) d e e c z r i l u a 1.5 o m S - r o o t N - ( 1 n i a r D , 0.5 )
TJ = 150 °C
7.0 V
0
7
VGS, Gate-to-Source Voltage (V)
VDS, Drain-to-So urce Voltage (V)
Top
6
R
ID = 17 A
VGS = 10 V
0 - 60 - 40 - 20
0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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SiHP18N50C, SiHF18N50C Vishay Siliconix
100
105
) F p ( e c n a t i c a p a C
VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd
104
) A ( t n e r r u
C n i a r
Ciss 103
D e s r e
TJ = 25 °C
1
v
102
TJ = 150 °C
10
e R ,
Coss
D
S I
Crss
10 1
10
100
VGS = 0 V
0.1 1000
0.2
0.5
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
V
e c r
103 Operation in this area limited by RDS(on)
VDS = 400 V VDS = 250 V VDS = 100 V
12
S G
) A ( t n e r r
102
C n i a r
10
u
u
o S o t e t a G ,
1.4
Fig. 7 - Typical Source-Drain Diode Forward Voltage
ID = 17 A
16
1.1
VSD, Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
) V ( e g a t l o
0.8
8
1 ms
D , D I
4
100 µs
1
TC = 25 °C TJ = 150 °C Single Pulse
V
0
10 ms
0.1 0
30
60
90
120
102
10
QG, Total Gate Charge (nC)
103
104
VDS, Drain-to-So urce Voltage (V)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
20
) A ( t n e r r
15
C n i a r
10
u
D , D I
5
0 25
50
75
100
125
150
TC, Case Temperat ure (°C) Fig. 9 - Maximum Drain Current vs. Case Temperature (TO-220) www.vishay.com 4
Document Number: 91374 S09-1257-Rev. B, 13-Jul-09
SiHP18N50C, SiHF18N50C Vishay Siliconix
1 t n e i s n e a c r T n a e d v e i t p c e m 0.1 f f I l E a d m e r z e i l h a T m r o
Duty Cycle = 0.5
0.2 0.1 0.05 0.02
Single Pulse
N
0.01 10-4
10-2
10-3
0.1
1
Pulse Time (s)
Fig. 10 - Normalized Thermal Transient Impedance, Junction-to-Case (TO-220)
1 t n e i s n e a r c T n a e d v e i t p c e I m 0.1 f f E l a d m e r z e i l h a T m r o
Duty Cycle = 0.5 0.2 0.1 0.05
0.02 Single Pulse
N
0.01 10-4
10-2
10-3
0.1
1
10
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case (TO-220FP)
VDS VGS
RG
RD
VDS 90 %
D.U.T. + - VDD
10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 %
Fig. 12a - Switching Time Test Circuit
Document Number: 91374 S09-1257-Rev. B, 13-Jul-09
10 % VGS td(on)
tr
td(off)
tf
Fig. 12b - Switching Time Waveforms
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SiHP18N50C, SiHF18N50C Vishay Siliconix L Vary tp to obtain required IAS
VDS
D.U.T
RG
+ -
IAS
QG
10 V V DD
QGS
QGD
10 V
0.01
tp
VG
Ω
Fig. 13a - Unclamped Inductive T est Circuit
Charge
VDS Fig. 14a - Basic Gate Charge Waveform
tp VDD
Current regulator Same type as D.U.T.
VDS
50 kΩ
IAS
12 V
0.2 µF 0.3 µF
Fig. 13b - Unclamped Inductive Waveforms
+
D.U.T.
-
VDS
VGS 3 mA
IG ID Current sampling resistors
Fig. 14b - Gate Charge Test Circuit
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Document Number: 91374 S09-1257-Rev. B, 13-Jul-09
SiHP18N50C, SiHF18N50C Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer
+
D.U.T
•
• •
-
+
-
-
RG
• • •
dV/dt controlled by R G ISD controlled by duty factor "D" D.U.T. - device under test
Driver gate drive P.W.
+
Period
D=
+ -
VDD
P.W. Period VGS = 10 V*
D.U.T. I SD waveform Reverse recovery current
Body diode forward current dI/dt D.U.T. V DS waveform Diode recovery dV/dt
Re-applied voltage
Body diode
VDD
forward drop
Inductor current
Ripple
≤
5%
ISD
* VGS = 5 V for logic level and 3 V drive devices Fig. 15 - For N-Channel
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Document Number: 91374 S09-1257-Rev. B, 13-Jul-09
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Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all l iability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000 Revision: 18-Jul-08
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