Ovation Q Line

Q-Line Installation Manual Section

Title

Page

Summary of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changes-1

Section 1. Introduction 1-1 1-2 1-3

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Contents of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Section 2. Field Wiring Procedures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14

Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 WDPF Field Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 System Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Noise Minimization Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Thermocouple Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Common Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Field Termination Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 “B” Cabinet Field Terminations and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Q-Card Hardware Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 Using Address Selection Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 Pre-Wiring Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 Field Wiring Half-Shell Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

Section 3. Q-Card Reference Sheets 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15

Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 QAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 QAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 QAH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 QAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61 QAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 QAO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100 QAV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119 QAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148 QAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-173 QAXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-190 QAXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-193 QBE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-200 QBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-212 QBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-224

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Table of Contents, Cont’d Section 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 3-38 3-39 3-40 3-41 3-42 3-43 3-44

Title

Page

QCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QFR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QLJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QTB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-235 3-254 3-265 3-266 3-276 3-282 3-283 3-296 3-317 3-318 3-332 3-343 3-351 3-359 3-365 3-398 3-399 3-410 3-420 3-421 3-453 3-458 3-483 3-512 3-541 3-552 3-553 3-562 3-573

Appendix A. Worksheets A-1.

Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Appendix B. Setting Q-Card Addresses B-1.

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Appendix C. Card-Edge Field Termination C-1. C-2.

Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Card-Edge Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2

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Table of Contents, Cont’d Section C-3.

Title

Page

Field Wiring Card-Edge Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6

Glossary Index

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Table of Contents, Cont’d List of Figures Figure

Title

Page

Section 1. Introduction 1-1.

Phases of WDPF Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Section 2. Field Wiring Procedures 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 2-9. 2-10. 2-11. 2-12. 2-13. 2-14. 2-15.

Example Sort-by-Hardware Terminations List . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Termination List Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Amplitude Discrimination Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Typical Noisy Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Ideal Analog Signal Field Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Typical Thermocouple Analog Signal Wiring by User . . . . . . . . . . . . . . . . . . . . . 2-16 Typical Sensor Analog Signal Wiring by User . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 QAXT Half-Shell Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Standard “A” Cabinet and Field Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Enhanced “B” Cabinet, Termination Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 Address Jumpers on Cable Connector (“B” Cabinet Terminations) . . . . . . . . . . . 2-28 Q-Card Hardware Address Selection Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 Q-Card Number of Channels and Starting Address. . . . . . . . . . . . . . . . . . . . . . . . 2-33 Q-Card Hardware Address Selection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 Address Jumpering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

Section 3. Q-Card Reference Sheets 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 3-7. 3-8. 3-9. 3-10. 3-11. 3-12. 3-13. 3-14. 3-15. 3-16. 3-17.

Typical Q-Card Termination, “Standard” Cabinet . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Typical Q-Card Termination, Remote “B” Cabinet . . . . . . . . . . . . . . . . . . . . . . . . 3-3 QAA G01 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 QAA G02 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 QAA Card Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 QAA Card Usage Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 QAA Card State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 QAA G01 Detailed Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 QAA G02 Detailed Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 QAA Mother Card Components, Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 QAA DWC Daughter Card Components, Test Points. . . . . . . . . . . . . . . . . . . . . . 3-23 QAA DBK Daughter Card Components, Test Points . . . . . . . . . . . . . . . . . . . . . . 3-24 QAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 QAC Block Diagram (Groups 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 QAC Block Diagram (Group 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 QAC Block Diagram (Group 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 QAC Block Diagram (Group 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

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Table of Contents, Cont’d List of Figures, Cont’d Figure 3-18. 3-19. 3-20. 3-21. 3-22. 3-23. 3-24. 3-25. 3-26. 3-27. 3-28. 3-29. 3-30. 3-31. 3-32. 3-33. 3-34. 3-35. 3-36. 3-37. 3-38. 3-39. 3-40. 3-41. 3-42. 3-43. 3-44. 3-45. 3-46. 3-47. 3-48. 3-49. 3-50. 3-51. 3-52. 3-53. 3-54. 3-55. 3-56. 3-57. 3-58.

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Title

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QAC Block Diagram (Group 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 QAC Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 QAC Card Components (Indicators and test Points) . . . . . . . . . . . . . . . . . . . . . . . 3-48 QAH Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 QAH Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53 QAH Card Front-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 3-55 QAH Word Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 QAH Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 QAH Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59 QAH CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60 QAI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61 QAI Card Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 QAI Control Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68 QAI Analog Point Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 QAI Analog Point Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70 QAI Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 QAI Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72 QAI CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 QAM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 QAM Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76 QAM Card Systems Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 3-77 QAM Card Usage Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78 QAM Card Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91 QAM Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95 QAO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100 QAO Card Functional Block Diagram, 5-Level . . . . . . . . . . . . . . . . . . . . . . . . . 3-102 QAO Point Block Diagram, 5- Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103 QAO Card Functional Block Diagram, 6-Level and Later . . . . . . . . . . . . . . . . . 3-104 QAO Point Block Diagram, 6-Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105 QAO Bipolar Output Voltage Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111 QAO Unipolar Output Current Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112 QAO Unipolar Output Voltage Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113 QAO Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-114 QAO Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-116 QAO CE MARK Wiring Diagram (Groups 1 & 7). . . . . . . . . . . . . . . . . . . . . . . 3-117 QAO CE MARK Wiring Diagram (Groups 2 through 6, & 8) . . . . . . . . . . . . . . 3-118 QAV Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119 QAV Typical Control System Using QAV Cards . . . . . . . . . . . . . . . . . . . . . . . . 3-121 QAV Analog Input Circuits Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-124 QAV Card Digital Circuits Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125 QAV Analog-to-Digital Conversion Process Flowchart . . . . . . . . . . . . . . . . . . . 3-126

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Title

3-59. 3-60. 3-61. 3-62. 3-63. 3-64. 3-65. 3-66. 3-67. 3-68. 3-69. 3-70. 3-71. 3-72. 3-73. 3-74. 3-75. 3-76. 3-77. 3-78. 3-79. 3-80. 3-81. 3-82. 3-83. 3-84. 3-85. 3-86. 3-87. 3-88. 3-89. 3-90. 3-91. 3-92. 3-93. 3-94. 3-95. 3-96. 3-97. 3-98. 3-99.

QAV Card Front-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . QAV Card Rear-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . QAV Card Output Data Pattern Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAV Card Components (Level 6 and earlier) . . . . . . . . . . . . . . . . . . . . . . . . . . . QAV Card Components (Level 8 and later) . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAV Wiring Diagram (QAV Groups 1 through 5) . . . . . . . . . . . . . . . . . . . . . . . Wiring Diagram, QAV to TSC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAV CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAW Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAW Typical Control System Using QAW Cards . . . . . . . . . . . . . . . . . . . . . . . QAW Analog Input Circuits Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . QAW Digital Circuits Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAW Card Rear-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . QAW Card Front-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . QAW Card Output Data Pattern Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAW Card Components (Level 7 and earlier) . . . . . . . . . . . . . . . . . . . . . . . . . . QAW Card Components (Level 9 and later) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wiring Diagram, QAW Groups 1,2,3,4, and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . Wiring Diagram: QAW Group 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wiring Diagram, QAW to TSC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAW CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAX Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAX Output Data Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAX Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAX Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAX Shield Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAX Recommended Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAX CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAXT Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAXT Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAX Card with R75 Jumper Installed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QAXT Standard Half-Shell Cabinet Installation . . . . . . . . . . . . . . . . . . . . . . . . . QAXT Remote I/O Half-Shell Cabinet Installation. . . . . . . . . . . . . . . . . . . . . . . QBE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical, Multicrate, Q-Line System Using QBE Card Interfacing . . . . . . . . . . . QBE Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBE Timing Diagram of the Operation of the Bus Discharge Circuit . . . . . . . . QBE Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBE Transmit Mode Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBE Receive Mode Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBE No Level Shift Mode Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . .

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Page 3-130 3-131 3-133 3-134 3-136 3-143 3-145 3-147 3-148 3-150 3-153 3-154 3-157 3-159 3-161 3-162 3-163 3-165 3-168 3-170 3-172 3-173 3-183 3-184 3-186 3-187 3-188 3-189 3-193 3-195 3-197 3-198 3-199 3-200 3-202 3-204 3-205 3-207 3-208 3-208 3-209

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Table of Contents, Cont’d List of Figures, Cont’d Figure

Title

3-100. 3-101. 3-102. 3-103. 3-104. 3-105. 3-106. 3-107. 3-108. 3-109. 3-110. 3-111. 3-112. 3-113. 3-114. 3-115. 3-116. 3-117. 3-118. 3-119. 3-120. 3-121. 3-122. 3-123.

QBI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBI Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of a QBI Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . Typical G01 and G02 QBI Card – Point Wiring Diagram . . . . . . . . . . . . . . . . . Typical G03, G04 and G05 QBI Card – Point Wiring Diagram . . . . . . . . . . . . . Typical G06, G07, G09 and G10 QBI Card – Point Wiring Diagram. . . . . . . . . Typical G08 and G11 QBI Card – Point Wiring Diagram . . . . . . . . . . . . . . . . . QBI Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBI Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBO Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBO Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBO Typical Point Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBO Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBO Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QBO CE MARK Wiring Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCA Channel Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCA Channel Range Adjustment Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCA Channel Offset Adjustment Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCA Output Gain Stage - Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCA Output Gain Stage - Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCA Card Outline and User Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCA Wiring Diagram (Group 1) (Using AMP-18 conductor 18 AWG wiring) (3A99512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-124. QCA Wiring Diagram (Group 2) (Using AMP-18 conductor 18 AWG wiring) (3A99512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125. QCA CE MARK Wiring Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-126. QCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127. QCI Card Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-128. QCI Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129. Cable Length Limitations for QCI Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130. QCI Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-131. QCI Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-132. QCI CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-133. QDI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-134. QDI Card Address Jumper Assembly (Differential Input) . . . . . . . . . . . . . . . . . 3-135. QDI Card Address Jumper Assembly, Single Ended Input. . . . . . . . . . . . . . . . . 3-136. QDI G01 Point Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-137. QDI Typical Contact Input Point Wiring (G03, 05, 07, 08, 09, 10) . . . . . . . . . . 3-138. QDI Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Page 3-213 3-215 3-217 3-219 3-220 3-220 3-221 3-221 3-222 3-224 3-226 3-228 3-229 3-231 3-233 3-234 3-240 3-240 3-241 3-242 3-243 3-244 3-248 3-251 3-252 3-253 3-254 3-256 3-258 3-259 3-262 3-263 3-264 3-267 3-269 3-270 3-271 3-271 3-274

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Page

3-139. 3-140. 3-141. 3-142. 3-143. 3-144. 3-145. 3-146. 3-147. 3-148. 3-149. 3-150. 3-151. 3-152. 3-153. 3-154. 3-155. 3-156. 3-157. 3-158. 3-159. 3-160. 3-161. 3-162. 3-163. 3-164. 3-165.

Wiring Diagram: QDI Groups 2, 4, 6, and 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-275 QDT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-276 QDT Card Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-280 QIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-283 QIC Detailed Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-289 QIC Card Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-290 QID Block Diagram, Double Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-296 QID Block Diagram, Single Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-297 QID Card Address Jumper Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-305 QID Card Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-306 QID Group 1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-308 QID Group 8 and Group 17 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-308 QID Single Ended Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-309 QID Differential Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-309 QID Wiring for Groups 2, 4, 6, 11, 13, and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-310 QID Card Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-311 QID Card Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-312 QID Card Connections (G10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-313 QID CE MARK Wiring Diagram (Groups 2, 4, 6, 11, 13 and 15) . . . . . . . . . . . 3-314 CE MARK Wiring Diagram (Groups 1, 3, 5, 7, 8, 9, 12, 14 and 16) . . . . . . . . . 3-315 CE MARK Wiring Diagram (Group 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-316 QLI Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-318 QLI Card Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-319 QLI Card Address Jumper Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-324 QLI Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-324 QLI Wiring Diagram: WDPF Powered, Local Grounding . . . . . . . . . . . . . . . . . 3-327 QLI Wiring Diagram: Digital I/O-WDPF Powered Analog I/O-Self Powered with Remote Grounding . . . . . . . . . . . . . . . . . . . . . . . 3-328 3-166. QLI CE MARK Wiring Diagram (Analog Inputs Powered at Field Side) . . . . . 3-330 3-167. QLI CE MARK Wiring Diagram (Analog Inputs Powered at WDPF System Side)3-331 3-168. QLJ Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-332 3-169. QLJ Card Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-333 3-170. QLJ Card Address Jumper Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-337 3-171. QLJ Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-338 3-172. QLJ Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-340 3-173. QLJ Ground Inputs at System End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-341 3-174. QLJ Ground Inputs at Signal Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-341 3-175. QLJ Fused Half-Shell Extension Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-342 3-176. Loop Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-343 3-177. LIM Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-344 3-178. Keyboards for Group 1 and Group 2 LIMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-347

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3-179. 3-180. 3-181. 3-182. 3-183. 3-184. 3-185. 3-186. 3-187. 3-188. 3-189. 3-190. 3-191. 3-192. 3-193. 3-194. 3-195. 3-196. 3-197. 3-198. 3-199. 3-200. 3-201. 3-202. 3-203. 3-204. 3-205. 3-206.

LIM Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIM Small Loop Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboards for Group 1 and Group 2 SLIMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIM Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMT Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMT Card Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA +48 VDC Clock Input Signal Wiring (G01, G04) . . . . . . . . . . . . . . . . . . . QPA Control Signal (+48 VDC) Input Wiring (G01, G02). . . . . . . . . . . . . . . . . QPA +5 VDC Clock Input Signal Wiring (G02, G03) . . . . . . . . . . . . . . . . . . . . QPA Clock Signal Wiring (Differential Line Driver) G02 and G03. . . . . . . . . . QPA +5 VDC Control Input Wiring (G03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Card Counter/Comparator (1 of 2) (G01, 2, 3) . . . . . . . . . . . . . . . . . . . . . . QPA Card Counter/Comparator (2 of 2) (G04) . . . . . . . . . . . . . . . . . . . . . . . . . . QPA J2 Pin Connector (G01, 2 and 3) (Front View). . . . . . . . . . . . . . . . . . . . . . QPA J3 Pin Connector (G01, 2, 3, and 4) (Front View) . . . . . . . . . . . . . . . . . . . QPA Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Card Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Card Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Card Address Selection (Example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Card Address Selection (Example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Card Group Read Bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Card Used for Speed Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPA Card Used for Elapsed Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . QPA Used for Speed Ratio Measurement (For example, estimate stretch of materials between two rollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-207. QPA Used for Average Inverse Speed Measurement . . . . . . . . . . . . . . . . . . . . . 3-208. QPA Wiring Diagram, Groups 1 and 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-209. QPA Wiring Diagram, Groups 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-210. QPA CE MARK Wiring Diagram (Groups 1 and 4). . . . . . . . . . . . . . . . . . . . . . 3-211. QPA CE MARK Wiring Diagram (Group 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-212. QPA CE MARK Wiring Diagram (Group 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-213. QRF Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-214. QRF Card Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-215. QRF Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-216. QRF CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-217. QRO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-218. QRO Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Page 3-348 3-351 3-352 3-355 3-356 3-359 3-361 3-362 3-365 3-368 3-369 3-370 3-371 3-372 3-373 3-374 3-375 3-378 3-379 3-380 3-381 3-382 3-383 3-384 3-385 3-387 3-388 3-389 3-390 3-393 3-394 3-395 3-396 3-397 3-400 3-407 3-408 3-409 3-410 3-412

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Title

3-219. 3-220. 3-221. 3-222. 3-223. 3-224. 3-225. 3-226. 3-227. 3-228. 3-229. 3-230. 3-231. 3-232. 3-233. 3-234. 3-235. 3-236. 3-237. 3-238. 3-239. 3-240. 3-241. 3-242. 3-243. 3-244. 3-245. 3-246. 3-247. 3-248. 3-249. 3-250. 3-251. 3-252. 3-253. 3-254. 3-255. 3-256. 3-257. 3-258. 3-259.

QRO Safe Operating Area Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRO Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRO Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRO Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Control System Using QRT Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT Card Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT Card Output Dynamic Linear Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT Card Bridge and I to F Circuits Block Diagram . . . . . . . . . . . . . . . . . . . . . QRT Card Digital Circuits Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTDs and Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT Wiring Diagram: Plant Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT Wiring Diagram: Cabinet Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QRT CE MARK Wiring Diagram (Grounded at the B Cabinet). . . . . . . . . . . . . QRT CE MARK Wiring Diagram (Grounded in the Field) . . . . . . . . . . . . . . . . QSC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSC Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSC Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSD Typical QSD Card Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSD Card Input Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSD Card Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EH and MH Actuator Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSD Card Outline and User Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSD Analog Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSD CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSE Event Buffer Memory Arbitration Timing Chart . . . . . . . . . . . . . . . . . . . . QSE LED Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSE Event Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSE Status Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSE Wiring Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSE CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSR Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Data Format for Reading Demand, Feedback, and Scale Factors . . . . . . . Read Data Format for Reading Channel Valve-Type Assignments . . . . . . . . . . Write Data Format for Sending Demands to a Channel . . . . . . . . . . . . . . . . . . .

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x Westinghouse Proprietary Class 2C

Page 3-414 3-415 3-416 3-419 3-421 3-423 3-425 3-426 3-428 3-429 3-432 3-435 3-436 3-444 3-447 3-449 3-451 3-452 3-453 3-454 3-457 3-458 3-460 3-462 3-462 3-466 3-471 3-475 3-481 3-484 3-489 3-502 3-503 3-504 3-505 3-510 3-511 3-521 3-524 3-524 3-525

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Title

3-260. 3-261. 3-262. 3-263. 3-264. 3-265.

QSR Card Outline and User Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSR Analog Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSR Wiring Diagram (Groups 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSR Wiring Diagram (Groups 2 and 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSR CE MARK Wiring Diagram (Groups 1 & 3) . . . . . . . . . . . . . . . . . . . . . . . QSR CE MARK Wiring Diagram (Groups 2 & 4 with B Cabinet Earth Grounding). . . . . . . . . . . . . . . . . . . . . . . . . 3-266. QSR CE MARK Wiring Diagram (Groups 2 & 4 with Field Earth Grounding) 3-267. QSS Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-268. QSS Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-269. QSS Speed Selection Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-270. QSS Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-271. QSS Wiring Diagram (Recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-272. QSS Wiring Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-273. QSS CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-274. QTB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-275. QTB Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-276. QTB Real Time Clock Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-277. QTB Output Signal Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-278. QTB Card Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-279. QTO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-280. TRIAC Zero Voltage Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-281. TRIAC Operation with Load Current Below 75 mA. . . . . . . . . . . . . . . . . . . . . . 3-282. QTO Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-283. QTO Card Address Jumper Assembly Example . . . . . . . . . . . . . . . . . . . . . . . . . 3-284. QTO Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-285. QTO Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-286. Example of QVP DIOB Base Address Selection . . . . . . . . . . . . . . . . . . . . . . . . 3-287. QVP Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-288. QVP Wiring Diagram (Using #6 Screws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-289. QVP Wiring Diagram (Using #8 Screws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-290. QVP CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 3-526 3-530 3-535 3-536 3-537 3-539 3-540 3-541 3-542 3-543 3-546 3-548 3-550 3-551 3-553 3-556 3-558 3-559 3-559 3-562 3-564 3-565 3-566 3-568 3-569 3-572 3-578 3-580 3-582 3-583 3-584

Appendix A. Worksheets A-1.

Q-card Hardware Address Selection Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Appendix B. Setting Q-Card Addresses B-1. B-2.

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Address Jumpers on Cable Connector (“B” Cabinet Terminations) . . . . . . . . . . . . B-1 Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

xi Westinghouse Proprietary Class 2C

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Title

Page

Appendix C. Card-Edge Field Termination C-1. C-2. C-3.

Address Jumpers on Card-Edge Termination Connector . . . . . . . . . . . . . . . . . . . . C-2 Standard Card-Edge Field Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 Screw-Down Terminal Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4

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xii Westinghouse Proprietary Class 2C

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Table of Contents, Cont’d List of Tables Table

Title

Page

Section 1. Introduction 1-1. 1-2.

Available Q-Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Section 2. Field Wiring Procedures 2-1. 2-2. 2-3. 2-4. 2-5.

Noise Class Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . “B” Cabinet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced Half-Shell Terminal Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Half-Shell to Q-Card Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption and Heat Load for Q-Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-10 2-23 2-26 2-27 2-40

Section 3. Q-Card Reference Sheets 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 3-7. 3-8. 3-9. 3-10. 3-11. 3-12. 3-13. 3-14. 3-15. 3-16. 3-17. 3-18. 3-19. 3-20. 3-21. 3-22. 3-23. 3-24. 3-25. 3-26.

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Q-Card Groups and Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 QAA Status/Command Byte Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 QAA J1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 QAA J2 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 QAA G02 Analog Position Input Circuit Plug-in Resistor Selection. . . . . . . . . . . . . . 3-25 QAA Half-Speed Clock On and Off Time Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 QAA Card Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 QAA LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 QAA Potentiometers (Daughter Board). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 QAA Test Points (Daughter Board) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 QAC Output Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 QAC G01 and G02 Contact Allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 QAC G03 Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 QAC G04 Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 QAC G05 Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 QAC G06 Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 QAH Conversion Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 QAH Bipolar Conversion Dataword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56 QAH Unipolar Conversion Dataword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56 QAH Option Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58 QAI Analog Input Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 QAM Current Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79 QAM J2 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80 QAM Output Demand Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84 QAM J3 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86 QAM DIOB Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88

xiii

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Table of Contents, Cont’d List of Tables Table 3-27. 3-28. 3-29. 3-30. 3-31. 3-32. 3-33. 3-34. 3-35. 3-36. 3-37. 3-38. 3-39. 3-40. 3-41. 3-42. 3-43. 3-44. 3-45. 3-46. 3-47. 3-48. 3-49. 3-50. 3-51. 3-52. 3-53. 3-54. 3-55. 3-56. 3-57. 3-58. 3-59. 3-60. 3-61. 3-62. 3-63. 3-64. 3-65. 3-66. 3-67.

Title

Page

QAM Analog Values versus Hex Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89 QAM Manual Mode Demand Operations (G03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92 QAM Manual Mode Demand Operations (G01, 2, 4, 5, 6) . . . . . . . . . . . . . . . . . . . . . 3-92 QAM Watchdog Timer Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93 QAM RL Selected or Demand Linear Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . 3-96 QAM RE Selection of Demand Exponential Clock Frequency Sweep Rates . . . . . . . 3-96 QAM RS Selection of Setpoint Linear Clock Frequency. . . . . . . . . . . . . . . . . . . . . . . 3-97 QAM Jumper Selection of Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97 QAM Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98 QAM Potentiometer Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99 QAO Card Reset Switch Position (Update Period) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115 QAO Analog Output Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115 QAV Card Output Data Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-134 QAV Card Jumpers, Locations and Functions (Level 6 and earlier) . . . . . . . . . . . . . 3-135 QAV Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-136 QAV Thermocouple Coefficient Definitions (WDPF System) . . . . . . . . . . . . . . . . . 3-138 QAV Thermocouple Coefficient Definitions (Ovation System) . . . . . . . . . . . . . . . . 3-140 QAW Card Output Data Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-161 QAW Card Jumpers and Functions (Level 7 and earlier). . . . . . . . . . . . . . . . . . . . . . 3-163 QAW Jumper Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-164 QAX Card Groups and Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-174 QAX Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-176 QAX Input Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178 QAX Address Offsets (WDPF Systems) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-179 QAX Address Offsets (Ovation System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-180 QAX Thermocouple Coefficient Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-181 QAX Low-Level Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-182 QAX Low-Level Inputs with Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-182 QAX High Level Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-183 QAX Data Pattern Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-183 QAX Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-185 QAXD Card Groups and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-190 QAXD Counter Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-191 QAXT Power Supply Voltages (from QAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-194 QAXT Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-194 QAX/QAXT Based Thermocouple Compensation Kit Group Usage . . . . . . . . . . . . 3-195 QAXT Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-196 QAXT Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-196 QBE Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-205 QBE Internal Power Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-205 QBE +5 VDC to +11 VDC Level Shift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-206

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3-68. QBE +11 VDC to +5 VDC Level Shift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69. QBE J1 Connector Pin Assignments and Signal Names . . . . . . . . . . . . . . . . . . . . . . 3-70. QBE J2 and J3 Connector Pin Assignments and Signal Names. . . . . . . . . . . . . . . . . 3-71. QBI QID Card Equivalents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72. QBI Card Group Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73. QBI Card Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74. QBI Card Front-Edge Connector Pin Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75. QBO Digital Output Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76. QBO Card Reset Switch Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77. QBO DIP Switch Positions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78. QCA DIOB Card Edge Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79. QCA Field Front Card Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80. QCA Plug-in Scaling Resistor Reference Designators. . . . . . . . . . . . . . . . . . . . . . . . 3-81. Reference Designators for QCA Jumpers - Groups 1 and 2. . . . . . . . . . . . . . . . . . . . 3-82. QCA Test Point Reference Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83. QCI Contact Wetting Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84. Cable Length Limits for QCI Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85. QCI Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86. QCI G02 DIP Switch Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87. QDI-QID Card Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88. QDI Input Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89. QDI Pin Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90. Cable Length for QDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91. QDT Card Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92. QIC DIOB1 Card Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93. QIC DIOB2 for WDPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94. QIC DIOB2 (P4) for WIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95. QID Card Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96. QID Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97. QID Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98. QID Differential Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99. QID Single-Ended Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100. QID G10 Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101. QID Allowable Cable Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102. Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103. Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104. LIM Power Card-Edge Terminal Block Connector . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105. LIM Serial Port Card-Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106. SLIM Serial Port Card-Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107. QMT J5 (Power Monitor Relay) Pin Connections and Signal Names . . . . . . . . . . . . 3-108. QMT Card Fuse Ratings and Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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3-206 3-209 3-211 3-212 3-214 3-215 3-217 3-230 3-231 3-232 3-238 3-239 3-249 3-250 3-250 3-257 3-260 3-261 3-262 3-266 3-268 3-272 3-273 3-280 3-292 3-293 3-294 3-299 3-300 3-301 3-302 3-303 3-304 3-307 3-326 3-339 3-348 3-349 3-357 3-363 3-363

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3-109. QPA Field Signal (J3) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110. Field Signal Times (J3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111. QPA Clock Select Jumper Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112. QRF DIOB Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113. Field Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-114. QRO Card Reset Switch Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115. QRO Digital Output Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-116. QRT Card Conversion Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117. Normal Mode Voltage Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118. QRT Front Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119. Front Edge Pairs for QRT Card Address Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120. QRT Card RTD Bridge Modules (7380A92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121. Bridge, Count, and Output Values (Example A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-122. Bridge, Count, and Output Values (Example B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123. QSC Input Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-124. QSD Front-Edge M/A Station and Field Connector. . . . . . . . . . . . . . . . . . . . . . . . . . 3-125. QSD Card Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-126. QSD Watchdog Timeout Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127. QSD Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-128. QSD Analog Output Stage Plug-in Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129. LVDT Calibration resistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130. QSD Direct Output Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-131. QSD P + I Controller Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-132. Maximum Cable Lengths (Assume RC = 0) for QSE Card . . . . . . . . . . . . . . . . . . . 3-133. QSE J1 Connector DIOB Pin Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-134. QSE J2 Connector Pin Out for Address Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-135. QSE J2 Connector Pin Out for Field Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-136. QSE Current Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-137. QSE Status Word Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-138. QSE Status Word Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-139. QSE Point ID Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-140. QSR DIOB Card Edge Connector Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-141. Groups 1 and 3 (DC LVDT) Field/Addressing Front Card Edge Connector . . . . . . . 3-142. Groups 2 and 4 (AC LVDT) Field/Addressing Front Card Edge Connector . . . . . . 3-143. QSR DIOB Address Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-144. QSR Read Register Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145. Plug in Resistor Reference Designators (Groups 1 and 3) . . . . . . . . . . . . . . . . . . . . . 3-146. Plug in Resistor Reference Designators (Groups 2 and 4) . . . . . . . . . . . . . . . . . . . . . 3-147. Channel Jumper Reference Designators (Groups 1 and 3). . . . . . . . . . . . . . . . . . . . . 3-148. Channel Jumper Reference Designators (Groups 2 and 4). . . . . . . . . . . . . . . . . . . . . 3-149. Channel Test Point Reference Designators (Groups 1 and 3) . . . . . . . . . . . . . . . . . .

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3-376 3-377 3-380 3-406 3-406 3-417 3-417 3-426 3-430 3-433 3-434 3-434 3-441 3-442 3-455 3-469 3-473 3-473 3-474 3-476 3-478 3-479 3-480 3-488 3-490 3-491 3-493 3-495 3-496 3-497 3-499 3-518 3-519 3-520 3-522 3-523 3-531 3-531 3-533 3-533 3-534

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3-150. Channel Test Point Reference Designators (Groups 2 and 4) . . . . . . . . . . . . . . . . . . 3-151. QSS Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152. QSS Field Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-153. QTO Card Reset Switch Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-154. QTO Digital Output Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-155. LVDT Coil Drive Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156. LVDT Secondary Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-157. QVP Valve Coil Drive Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-158. QVP Setpoint Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-159. QVP Valve Position Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-160. QVP Current Loop Input (Groups 3 and 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-161. QVP Digital Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-162. QVP Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163. QVP Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-164. QVP Testjacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-165. QVP LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-166. QVP Option Select Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-534 3-546 3-548 3-570 3-570 3-574 3-575 3-575 3-575 3-576 3-576 3-577 3-577 3-577 3-579 3-581 3-581

Appendix B. Setting Q-Card Addresses B-1.

Conversion of Hexadecimal Number to Jumper Address. . . . . . . . . . . . . . . . . . . . . . . . B-3

Appendix C. Card-Edge Field Termination C-1.

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Summary of Changes This revision of “Q-Line Installation Manual” (M0-0053) includes the following changes:

• • • • • • • • • • •

QRF wiring diagram was changed to clarify A and B halfshells. QBI termination numbers were changed. QAX drawing number was changed. QPA clock rate was changed. QAW input value was changed QAI, QAV, and QAX conversion values were added. QLI-5 digital input ranges were changed. There were notes added to QLI-5 and QLI-8. QLI-7 wiring diagram was changed. QAO, QID, and QRT had additions and changes made. Appropriate information was added to describe the Q-Line cards which are now CE Mark compliant.

All sections may include additional miscellaneous reorganization, corrections, clarifications, and additions.

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Changes-1 Westinghouse Proprietary Class 2C

M0-0053

Section 1. Introduction 1-1. Overview The WDPF system consists of individual processing units (called drops) which communicate over networks (called highways). These drops are connected by coaxial cable or fiber optic cable to the WDPF Data Highway. Installation of a WDPF system includes planning, followed by the installation of the Data Highway, the individual drops, and I/O. This manual describes installation of Q-Line I/O, including field wiring and card addressing. Note Prior to beginning the I/O installation procedures described in this volume, earlier phases of WDPF installation must be completed. Refer to the applicable documents for details (see Figure 1-1). As Figure 1-1 indicates, this manual is one of several which describe the installation of a WDPF system. In combination, these manuals detail the considerations and decisions that face the user before the equipment arrives at the permanent site, and describe installation procedures from receipt of the equipment to power-up of all drops and peripheral devices.

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1-1 Westinghouse Proprietary Class 2C

M0-0053

1-1. Overview

Phase 1. Plan system layout as described in “Data Highway Installation Manual” (M0-0051) or “ Planning and Highway Installation Manual (WEStation)” (M0-8000).

Phase 1 Plan System Layout

Phase 2. Prepare site as described in “ Data Highway Installation Manual” (M0-0051) or “Highway Installation Manual (WEStation)” (M0-8000).

Phase 2 Prepare Site

Phase 3A. Install Data Highway as described in “ Data Highway Installation Manual” (M0-0051) or “Installation Manual (WEStation) ”(M0-8000). Phase 3A Install Data Highway

Phase 3B Install Field Wiring

Phase 4 Receive/ Install Drops

Phase 5 Start-up Highway

Phase 3B. Install field wiring as described in this manual (M0-0053) OR in “Remote Q-Line Installation Manual” (M0-0054) OR in “Distributed I/O Installation Manual” (NLAM-B204) and associated instruction leaflets.

Phase 4. Receive and install drops described in “Drop Installation Manual” (M0-0052) or “Drop Installation Manual (WEStation)” (M0-8005).

Phase 5. Start-up highway as described in “ Data Highway Installation Manual” (M0-0051) or “ Installation Manual (WEStation)” (M0-8000).

Figure 1-1. Phases of WDPF Installation

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1-2. Contents of this Document

1-2. Contents of this Document The contents of this document are described below: Section 1. Introduction describes the WDPF system installation documents, and the contents and scope of this document. Section 2. Field Wiring Procedures provides general information on recommended field wiring techniques, including termination and noise minimization. Section 3. Q-Card Reference Sheets describes the available Q-Cards, including termination information. Appendix A. Worksheets shows sample worksheets used to determine the wiring and addresses of the WDPF system. Appendix B. Setting Q-Card Addresses shows how to set card addresses on a WDPF system. A hexadecimal to binary table is included Appendix C. Card-Edge Field Termination shows an alternate method of wiring a WDPF system. Table 1-1 lists the Q-Cards that are described in this manual. Cards that are described in detail in other manuals are indicated by an asterisk (*) in front of the card name and the number of the manual after the card name

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1-2. Contents of this Document

Table 1-1. Available Q-Cards Q-Card

Q-Card

QAA (Actuator Auto/Manual Card)

* QLC (Serial Link Controller) (see also U0-1100)

QAC (Analog Conditioning Card)

QLI (Loop Interface Card)

QAH (High-Speed Analog Input Point Card) QLJ (Loop Interface Card with output readback) QAI (Analog Input Card)

LIM (Loop Interface Module)

QAM (Auto/Manual Station Controller Card) SLIM (Small Loop Interface Module) QAO (Analog Output Card)

QMT (M-Bus Terminator Card)

QAV (Analog Input Point Card)

QPA (Pulse Accumulator Card)

QAW (Analog High-Level Input Point Card) * QRC (Remote Q-Line) (see also M0-0054) QAX (Analog Input Point Card)

QRF (Four Wire RTD Input Card)

QAXD (QAX Digital Daughter Board)

QRO (Relay Output Card)

QAXT (Temperature Compensation)

QRS (Redundant Station Interface Card)

QBE (Bus Extender Card)

QRT (RTD Input Amplifier Card)

QBI (Digital Input Card)

QSC (Speed Channel Card)

QBO (Digital Output Card)

QSD (Servo Driver)

QCA (Current Amplifier Card)

QSE (Sequence of Events Recorder Card)

QCI (Contact Input Card)

QSR (Servo Driver with Position Readback Card)

* QDC (Digital Controller) (see also U0-1105)

QSS (Speed Sensor Card)

QDI (Digital Input Card)

* QST (Smart Transmitter Interface) (see also U0-1115)

QDT (Diagnostic Test Card)

QTB (Time Base Card)

* QFR (Fiber-Optic Repeater) (see also M0-0054)

QTO (TRIAC Output Card)

QIC (Q-Line DIOB Monitor)

QVP (Servo Valve Position Controller Card)

QID (Digital Input) * indicates this card is not fully described in this manual.

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1-3. Reference Documents

1-3. Reference Documents In addition to this manual, which describes installation of Q-Line I/O, Table 1-2 lists documents and pertinent standards which may be helpful:. Table 1-2. Reference Documents

Document Number

Document Name or Source

IEEE Standard No. 81-1962

Recommended Guide for Measuring Ground Resistance and Potential Gradients in the Earth

IEEE Standard No. 118-1978

IEEE Standard Test Code for Resistance Measurement

IEEE Standard No. 518

IEEE Service Center 445 Hoes Lane Piscataway, NJ 08854

M0-0051

Data Highway Installation Manual (Standard and PCH)

M0-0052

Drop Installation Manual (Standard and PCH)

M0-0054

Remote Q-Line Installation Manual

M0-8000

Highway Installation Manual (WEStation Equipped)

M0-8005

Drop Installation Manual (WEStation Equipped)

National Electric Code

National Fire Protection Association 470 Atlantic Avenue Boston, MA 02210

NLAM-B204

Distributed I/O Installation Manual

Power Line Disturbances and Their Effect Hewlett-Packard Journal, August 1981 on Computer Design and Performance by Duell, Arthur W. and W. Vincent Roland U0-0106

Standard Control Algorithm User’s Guide

U0-0131

Record Type User’s Guide

U0-0135

DPU Introduction and Configurations

U0-1100

QLC User’s Guide

U0-1105

QDC User’s Guide

U0-1115

Smart Transmitter Interface User’s Guide

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1-3. Reference Documents

Additional publications may be obtained by writing the following professional societies, and requesting their lists of available publications:

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Electronic Industries Association Engineering Department 20011 Street NW Washington, DC 20006

•

Instrument Society of America 67 Alexander Drive P.O. Box 12277 Research Triangle Park, NC 27709

•

Scientific Apparatus Makers Association Process Measurement & Control Section 1101 16th Street NW Washington, DC 20036


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Section 2. Field Wiring Procedures 2-1. Section Overview This section describes WDPF field wiring, defines both the field signal termination and noise minimization techniques, and provides specific field wiring procedures. Additional information on each Q-card can be found in Section 3. This information is designed to enable installation personnel to easily make field signal connections between the user’s process and the WDPF System. This section assumes that the user is familiar with the procedures given in “Data Highway Installation Manual (M0-0051) and “Highway Installation Manual (WEStation)” (M0-8000). This section includes the following:

• • • • • • • • • • • • •

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WDPF Field Wiring (Section 2-2). System Reference Documents (Section 2-3). Noise Minimization Techniques (Section 2-4). Thermocouple Considerations (Section 2-5). Common Input Considerations (Section 2-6). Field Termination Types (Section 2-7). “B” Cabinet Field Terminations and Addressing (Section 2-8). Q-Card Hardware Address Selection (Section 2-9). Using Address Selection Jumpers (Section 2-10). Pre-Wiring Consideration (Section 2-11). Field Wiring Half-Shell and Card-Edge Terminations (Section 2-12). Environmental Specifications (Section 2-13). Power Consumption (Section 2-14).


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2-2. WDPF Field Wiring

2-2. WDPF Field Wiring In WDPF System applications, field signal connections are made to drops which interface directly to the process. Typically, the process I/O interface and process point cards are contained in the Distributed Processing Unit (DPU). Field-signal wiring within WDPF Systems involves connecting user-supplied, pre-installed field cables/wires to the respective drops’ field terminations. These drops are pre-assembled at the factory, and all internal field signal cable and wiring connections up to the field termination points are already in place. To field-wire a WDPF System, two areas should be considered: noise minimization techniques and the drop field terminations. Noise minimization is discussed in Section 2-4. Section 2-5 through Section 2-12 present procedures for drop field wiring terminations.

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2-3. System Reference Documents

2-3. System Reference Documents Each system’s specific field signal requirements determine the mix of Q-cards within the drop, the field wiring connections, and the types of cabling and/or wiring to be used. Westinghouse provides the following task-related documentation to support system installation and maintenance:

• • • • •

Q-card descriptions Typical Q-Line or process I/O termination schematics External cabling lists Field signal termination lists Half-shell termination drawings

The “Field Signal Termination Lists” are used by installation personnel for field wiring purposes. The lists are computer-generated and are compiled in a variety of forms, column heads, and sorts to meet the specific user requirements, to support maintenance and to support installation. The two primary types are the sort-by-point and the sort-by-hardware lists. The sort-by-point (or signal) type of list supports post-installation maintenance activities, where easy point or signal identification is needed to aid diagnostic and troubleshooting procedures. The sort-by-hardware type of list is organized for easy identification of signal, card, cabinet, and field termination point (half-shell or card-edge connector) locations, needed for field wiring. An example of the sort-by-hardware list and its format is shown in Figure 2-1. This list illustrates the required wiring for a DPU, which utilizes a termination cabinet. This list is produced from the process I/O lists developed during the installation’s planning phase (see “Data Highway Installation Manual” (M0-0051) and “Highway Installation Manual (WEStation)” (M0-8000)).

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User defined signal point name User defined signal description User defined signal tag Card address I/O signal point number System cabinet number Half-shell zone location Ground connection point Terminal strip connection points POINT NAME HMF506 HMF512 HMF518 BMF506 BMF512 BMF518 GQF506 GQF512 GQF518 ZRF506 ZRF512 ZRF518

DESCRIPTION

TAG

REACTOR CORE INLET WATER TEMP REACTOR CORE OUTLT WATER TEMP REACTOR CORE STEAM TEMP FEEDWATER INLET TEMP FEEDWATER OUTLET TEMP FEEDWATER PRESS AT DISCHRGE RETURN STEAM TEMPERATURE STACK GAS FLOW RATE IONS PER SQUARE METER GALLONS OF WATER, FEEDWATER COOLANT FLOW, PRESSURE DISCHARGE TANK OVERFLOW ALRM

ABCD1234 ABCD1235 ABCD1236 FGHI4567 FGHI4568 FGHI4569 QWER2222 QWER3333 QWER4444 ASDF5555 ASDF6666 ASDF7777

CA AD RD DR

P N I

20 20 20 20 20 20 20 20 20 20 20 20

0 1 2 3 4 5 6 7 8 9 10 11

C A B

Z O N E

S H H L

35 35 35 35 35 35 35 35 35 35 35 35

A A A A A A A A A A A A

3 3 3 3 3 3 3 3 3 3 3 3

G N D

P O S A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A10 A11 A12 A13

C O M

B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 2 B10 B11 B12 B13

Figure 2-1. Example Sort-by-Hardware Terminations List

From this list, the user can find the point name, signal description, and signal tags, as specified by a process I/O list. This list also contains the following installation information provided by Westinghouse:

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Q-card Address -- This field is the specific card address (in hexadecimal) used by the process I/O bus (DIOB) for data communications; it enables system addressing of a specific card.

•

Point Number -- This field is the number which identifies the specific signal and input or output circuits of each Q-card. This can be used to identify specific circuits on the card schematics, card termination schematics, or example process field wiring diagrams.


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•

Cabinet Number -- This field identifies the specific termination cabinet within the system, at which the signal is to be terminated.

•

Half-Shell Zone Location -- This field identifies the specific half-shell within the termination cabinet, at which the signal is to be terminated. Note For card-edge termination applications, this is the Q-crate/slot location.

•

Ground Connection -- This field identifies the specific point within the termination cabinet where signal grounds are connected (as defined by the customer).

•

Terminal Strip Connection Points -- This field identifies the specific half-shell terminal points where the field signal connections are to be made (in this example, positive and common).

Figure 2-2 gives some of the various termination list formats and column heads used for installation purposes.

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POINT NAME

Terminations Cabinet Without Signal Conditioning S H P E S ZH CA O NT OE AD I SY C G P N C NL RD N OP A N O E O EL DESCRIPTION TAG DR T RE B D S G M

POINT NAME

Terminations Cabinet Without Signal Conditioning H P S ZH CA O OE G AD I C P C NL N RD N A O O EL D DESCRIPTION TAG DR T B S M

POINT NAME

Card-Edge Terminations With Signal Conditioning Q S C P E RS CA O NT AL AD I SY C G P N TO RD N OP A N O E ET DESCRIPTION TAG DR T RE B D S G

POINT NAME

Card-Edge Terminations Without Signal Q S C P E RS CA O NT AL AD I SY C TO RD N OP A ET DESCRIPTION TAG DR T RE B

POINT NAME

Cable Terminations With Signal Conditioning S P E C CA O NT O AD I SY C G P N N RD N OP A N O E N DESCRIPTION TAG DR T RE B D S G

POINT NAME

Cable Terminations Without P CA O AD I C RD N A DESCRIPTION TAG DR T B

R T N

SIGNAL COND

C O M

SIGNAL COND

C O M

SIGNAL COND

Conditioning

G N D

P O S

C O M

Signal Conditioning C O N N

G N D

P O S

C O M

Figure 2-2. Termination List Formats

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2-4. Noise Minimization Techniques

2-4. Noise Minimization Techniques 2-4.1. Background A wide variety of analog and/or digital circuits are associated with the WDPF System’s installation. There are low-level voltage circuits, high-level voltage circuits, circuits that transfer information, and circuits that transfer power. These circuits are placed into two categories: noise-producing circuits and noise-sensitive circuits. Noise problems typically occur when transmitting analog (voltage, current, and other measured values) or digital information (on/off conditions, pulse trains or similar data) via inter-connected or wired circuits. The information carried by signals in such circuits may become distorted during transfer and errors may result from this distortion. The difference between the signal of transmitted information and the signal of that information as received is called noise (see Figure 2-3 and Figure 2-4). The noise minimization techniques briefly described in this section focus on preventing errors by either eliminating the noise, or when elimination is not possible, performing steps to lessen its impact.

2-4.2. Noise Discrimination Natural signal properties (such as the peaks of a digital signal) or conditions created during signal transmission (such as the voltage of the analog signal) are used to make the desired information in the signal appear different from the noise. The recovery of correct information from a noisy signal therefore depends upon the ability to subtract the noise from the desired information. There are three components of a signal that can be used to separate the desired information from a noisy signal:

• • •

Energy Level Frequency Source (of both Signal and Noise)

The following pages explain how each of these components can be applied to minimize errors that may occur because of a noisy signal.

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Energy Level The energy level is the total energy for the signal plus any induced noise. If there is a significant difference between the signal and the noise, then the noise is rejected easily by thresholding techniques (as identified as Desirable in Figure 2-3). If there is not a significant difference between the signal and the noise, then the noise is not easily rejected (as identified as Undesirable in Figure 2-3).

Desirable

Undesirable 1 threshold 0 threshold

Ideal Signal

Ideal Signal

Signal plus Noise

Threshold discrimination is possible because of sufficient contrast between noise and signal amplitude.

Severe Noise Imposed

The noise and signal have insufficient amplitude contrast to permit simple threshold discrimination.

Figure 2-3. Amplitude Discrimination Example

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Frequency Most of the noise commonly encountered in industrial plants is related either to the power line frequency and its low harmonics, or to switching transients. The analog signals are usually lower in frequency than one cycle per second, while the digital signals between plant and controller appear from zero to a few hundred cycles per second. Both analog and digital signals can be discriminated easily by eliminating frequency content from external noise sources such as switching transients, since the transients do not contain appreciable energy below 0.5 MHz frequency. Low pass filtering is useful in recovering analog signals from either power line or transient noise, and for recovering digital signals from transient noise. Figure 2-4 shows an example of these two types of noise. mV 60

Power Line Frequency Noise

50 Transient Noise

40 30 20 Desired Signal 10 0 -10

0 Volt Reference

The signal above is shown at a 30mV level with both 14 mV RMS (60 Hz) and transient noise. Figure 2-4. Typical Noisy Signal

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Sources (Signal and Noise) When signals are originally generated, most are relatively noise-free. The bulk of the noise present on a received signal has been added to the signal during its transmission. Isolation and segregation of signal sources and wiring from noise sources is highly effective as a recovery means. This technique, as well as the low-pass filtering previously mentioned, serves to reduce the recovery problem to one of amplitude or energy level discrimination.

2-4.3. Noise Sources The following devices and circuits are common sources of noise:

• • • • •

Inductive devices, such as relays and solenoids AC and DC power circuits, and wiring Switchgear Fast-rise-time sources: thyristors and certain solid-state switching circuits Variable-frequency or variable current devices

2-4.4. Noise Classes Signal and power circuits, wiring, and cables are classified as high-level or low-level sources of noise and interference. A definition of each class of noise is given in Table 2-1. Table 2-1. Noise Class Definitions

Noise Class

Level

Definition

H

High

Includes all AC power circuits from household 115 VAC up to KV transmission levels. It includes all DC power circuits from 250 VDC and 15 A or less up to 500 VDC and 200 A or more.

M

Medium

Includes Contact Closure Input (CCI) and Contact Closure Output (CCO) signals. It also includes telephone and television circuits, and conventional (relay) logic circuits.

L

Low

Q

Very Low

Includes digital signals, data links, and low-speed pulse-counting circuits. Includes analog inputs as well as pulse inputs to high-speed counting and memory circuits.

For details on the selection and spacing of field wiring with respect to noise, refer to “Data Highway Installation Manual” (M0-0051) or “Highway Installation Manual (WEStation)” (M0-8000). M0-0053


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2-4.5. Digital Signal Noise Rejection The WDPF System employs three specific noise rejection measures for digital signal plant interconnections:

• • •

Low pass filtering (2 to 16 msec time constant) Substantial signal levels (48 VDC or 115 VAC) Isolation, or optical coupling

Low pass filtering and the use of large signal level techniques provide frequency and energy level discrimination, respectively. Isolation of the digital signal receiver from ground is important as a means for rejecting noise which causes both wires in a signal pair to change voltage-to-ground potentials. An example of this type of isolation is a signal source (transmitter) which is grounded at a point remote from the receiver, where transmitter and receiver grounds are not at the same voltage. In this case, ground potential difference appears as a voltage on both wires of the corresponding signal pair. Another example in which isolation may be required to reject ground potential difference noise would be in circuits where coupling exists between signal wires, inducing a potential in both wires. Induced potentials can occur when signal wires are present in environments with changing electromagnetic or electrostatic fields. Isolation may be required in this case. An optical isolator may be used to bring digital signals into the receiver. No receiver response to noise can occur unless signal line noise current flows. Low frequency current, which may flow as a result of equal noise voltage-to-ground potentials on both wires of the signal pair, is eliminated if the signal wires are not grounded at more than one point. This is called the common-mode voltage. Note High frequency noise currents can flow using stray capacitance as part of their path. This requires the use of low pass filtering in addition to the optical isolation.

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2-4.6. Analog Signal Noise Rejection Analog signal isolation is provided for the same reasons that are discussed for digital signals (as described in Section 2-4.5). However, since analog signals are typically low level, filtering and isolation noise rejection techniques are more critical for analog signals than for digital signals. Analog signal filtering is achieved by averaging applied signals for one cycle (or an integer multiple of cycles) of the AC power line frequency. Power line related noise, at the power line frequency and its harmonics, has exactly zero average value when the average is taken over exactly one cycle and is filtered out of the signal by this technique. Transient noise (high frequency damped ringing) has zero average value for averages taken over time periods much longer than the duration of the transients.

2-4.7. Output Signal Noise Rejection Digital output signals from the WDPF System to the plant are electromechanical or semiconductor outputs which are entirely isolated from ground. Resistor and capacitor circuits are placed across these contacts to control the rate of voltage rise upon turn-off. The only additional signal treatment needed is that required by the driven plant equipment itself. Interconnections between various WDPF subsystems (printers, etc.) generally are treated by filtering, isolation, large signal level, and other appropriate forms of noise suppression. Such signal conditioning is built into the equipment.

2-4.8. Noise-Sensitive Circuit Noise Rejection All transmitting, low-level analog and digital circuits must be assumed to be noise-sensitive and to require special protection against noise. Field signals from process transducers (thermocouples, RTDs, and so on) are especially susceptible to noise. Noise can be coupled into these sensitive circuits in three ways:

• • •

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Electrostatic coupling via distributed capacitances Electromagnetic coupling via distributed inductances Conductive coupling, such as circuits sharing a common return


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Noise suppression for these noise sensitive circuits involves one or more of the following basic measures:

• • • • •

Physical separation between noise-producing and noise-sensitive circuits Twisted-pair wiring for signal connection within plant Proper grounding, especially avoiding multiple grounding of cable shields Proper shielding, especially cable shielding Surge protection

Circuit Separation Circuit separation is a simple and effective means of electrostatic and electromagnetic field induced noise control. This is because electrostatic and electromagnetic fields decay with increasing distance, producing lower amplitude noise and maintaining a good signal-to-noise ratio. Twisted-pair Wiring Twisted-pair wiring suppresses noise by acting to eliminate circuit loops which are sensitive to stray electromagnetic fields. For this reason, Westinghouse recommends that all analog signal circuit connections should be made with twisted pairs wire. Digital signal connections should carry a group return (or common) wired in the same cable as the signal wires. Twisted pairs are also recommended in digital circuits where unusually noisy environments exist. Twisting of the signal wire and its return conductor becomes increasingly important as the length of the two becomes greater, and as the distance from noise sources becomes less. In twisted pairs or small cables (less than 1/2 inch outer conductor circle diameter), a twist rate of at least one to two twists per foot is recommended. Proper Grounding and Shielding Proper grounding along with Shielding causes noise-induced currents to flow in the shield, and from the shield to ground, rather than in the corresponding signal conductors. Shielding itself is useful in avoiding capacitively coupled noise. The shield’s sole function is to decrease effective capacitance from conductors inside the shield to conductors outside. To accomplish this, the shield should be as continuous as possible (foil or metallized plastic) and equipped with a “drain wire” for secure single-point grounding.

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Conductors and corresponding returns may be grouped within a shield only if capacitive coupling between them is acceptable. Avoid the grouping of low- and high-level analog inputs, contact inputs, and contact outputs within a single shield. Shields are used as current-carrying conductors on some systems. To be effective, shields are grounded at the same point as the signals within. lEEE Surge Protection Surge protection to IEEE 472-1974 (Ref. ANSI C37.902-1974) is provided on most Q-Line cards. Check individual card descriptions (Section 3) for availability or possible additional conditions. To ensure this feature works correctly, make sure the grounding screw on the card is clean and tight.

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2-4.9. Analog Signal Shielding Techniques For noise suppression purposes, analog signals of less than one volt are considered low-level and require shielding. Individually twisted and shielded pairs should be used for all analog input signal wiring. Multipair cable can be used if each twisted pair in the cable has its own insulated shield. Use the following guidelines to shield signals:

• • •

Ground the low-level analog signal shield.

•

Run the shield (unbroken) from the transducer to the guard terminal of the Analog to Digital (A/D) front-end at the Analog Input card. Maintain shield continuity at junction boxes when they are used.

Ground the shield only once, preferably to a single point at the signal source. Connect the low side of the signal to the shield at the signal source. If the shield cannot be conveniently grounded at or near the signal source, ground it at the DPU. An ideal analog signal field connection is shown in Figure 2-5.

Unbroken Cable Shield

A/D Guard

ES

A/D

Drain Wire

Twisted Pair

Single Point Ground Figure 2-5. Ideal Analog Signal Field Connection

Figure 2-6 shows the typical thermocouple analog signal wiring recommended for the WDPF user. Figure 2-7 shows the recommended sensor analog signal wiring.

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Half Shell Ground

Local Junction Box (when used)

Connection Head

(+) (-) Guard

Preferred

Thermocouples Field Grounded in Well

Cable Drain (+) (-) Guard

Preferred

(+) (-) Guard

Preferred

(+) (-) Guard (+) (-) Guard

Field Grounded Near Well

Field Grounded at Local Junction Box

Alternate Wiring for ungrounded thermocouple is installed by user.

(+) (-) Guard

Preferred

(+) (-) Guard

Not Grounded in Field

Alternate Note: Typical Cold Junction Box Terminal Strip (or Half Shell) Shown

Figure 2-6. Typical Thermocouple Analog Signal Wiring by User

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Half Shell Ground

Local Junction Box (when used)

Voltage Sensors

Field Grounded at or Near Sensor

(+) (-) Guard Preferred

Cable Drain (+) (-) Guard

Preferred

(+) (-) Guard

Field Grounded at Local Junction Box

Alternate

(+) (-) Guard Preferred

Not Grounded in Field

(+) (-) Guard Alternate

Note: Typical Cold Junction Box Terminal Strip (or Half Shell) Shown.

Figure 2-7. Typical Sensor Analog Signal Wiring by User

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2-5. Thermocouple Considerations

2-5. Thermocouple Considerations Currently, there are three methods of compensating thermocouples for cold junction reference temperature. They are listed below in order of preference:

• • •

Half-Shell compensation (QAX, QAXT cards) Cabinet compensation (QRT card) On-board compensation (QAV card)

2-5.1. Half-Shell Compensation The QAX card has 12 available channels. One channel is connected to an electronic temperature sensing module which is mounted at the B-cabinet half-shell. This module provides the capability for compensating the other 11 channels on the QAX card. As shown in Figure 2-8, a steel cover is placed over the QAX half-shells. This isolates the terminal blocks from the rest of the cabinet and equalizes the temperature. To provide compensation, the QAXT is mounted as indicated.

Ground Bar

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

QAXT

Half-Shell

Protective Cover

Figure 2-8. QAXT Half-Shell Mounting

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Benefits of this method include;

• • •

No baffles or fans are needed within the termination cabinet. Minimal impact on compensation if cabinet door is opened. Preferred with Remote Q-Line I/O.

Refer to the QAX card section for additional information on this method of compensation.

2-5.2. B-Cabinet Compensation This method uses cabinet mounted Resistance Temperature Detectors(RTDs) to determine an average temperature of an entire B-cabinet or a portion (segment) of the cabinet. A maximum of two segments can be defined for each termination cabinet, with two RTD temperatures in each segment. RTD cabinet temperatures are fed into a QRT card at a specific address (F8 - FB), and then presented to the DIOB. The system then averages the measurement and compensates the thermocouple values terminated within that segment of the cabinet. Considerations with cabinet mounted RTDs include:

• • •

Baffles and fans are used within the termination cabinet. QRT RTD input card and external circuitry are required. Compensation values are updated every 1/2 second. Compatible with systems equipped with “B” cabinets.

A twisted-three-conductor shielded cable is recommended for RTD signal field connections. The preferred method to interface RTD signals is to use the QRT card, which can have four isolated RTD bridges and A/D converters. An alternate method to interface RTD signals in WDPF applications is to use an external bridge power supply, externally mounted bridge, and a QAV card (low-level A/D converter). Note When using 10 ohm copper RTDs, the conversion coefficients may need to be re-calibrated in the field. The lead resistance varies greatly with the size and length of wire for this type of RTD. Refer to the QRT card section for additional information on this method of compensation.

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2-5.3. On-Board Compensation This method can only be used with card-edge terminations and remote Q-Line I/O. (For most applications, QAXT compensation is preferred). In operation, on-board compensation uses an on-card temperature sensor on a QAV card. QAV cards equipped with a thermocouple temperature compensation feature use the seventh channel for the sensor. The channel is read every time the card performs an autocalibration cycle. This eliminates the need for external sensor cards and ensures field temperature accuracy.

• • •

Compatible with card-edge terminations. Compensation values updated every 1/2 second. Usable with Remote I/O single crate enclosures or similar cabinets where the I/O cards and terminal blocks are housed within the same cabinet and the temperatures within the entire cabinet are equalized.

Refer to the QAV card section for additional information on this method of compensation.

2-5.4. Thermocouple Grounding Thermocouples used in WDPF applications should be grounded close to the well. For thermocouples that are in close proximity to a common ground, an overall cable shield is sufficient. An example of this type of thermocouple or voltage sensor would be a boiler-tube metal-temperature thermocouple which uses a common multi-conductor cable. In this case, jumpers would be added at the DPU input terminals to tie all of the signal shield guard points to the cable shield. Thermocouples which do not share a common ground should use individually shielded twisted pairs, with the shields grounded at the wells.

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2-6. Common Input Considerations

2-6. Common Input Considerations 2-6.1. 4 to 20 mA Signal Considerations When sufficient separation from noise sources exists, this standard class of control signal does not require shielded cables. Use of twisted pair cables is recommended.

2-6.2. Digital Signal Considerations The WDPF System’s digital circuits used in data transmission do not require individual twisted or shielded pair conductors unless installed in unusually noisy environments. A multi-conductor cable, in which one conductor serves as a common return and with a single overall cable shield, is sufficient for most WDPF digital signal applications.

2-6.3. Contact Closure Signal Considerations

• •

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Outputs (CCO) -- These circuits usually require no shielding. Inputs (CCI) -- These circuits require no shielding if the net current in the cable is zero.


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2-7. Field Termination Types

2-7. Field Termination Types The DPU drop utilizes one of two methods of field signal terminations:

• •

Cabinet termination Card-edge termination

Cabinet Termination In cabinet termination the drop is packaged in dual cabinets (“A” and “B” cabinets). Note There are two types of A and B cabinets, the Standard and the Enhanced. With the Enhanced cabinets, there are more slots for Q-Cards, more half-shell zones, and more terminals per half-shell zone. One of these dual cabinets is called an “A” Cabinet, which houses the Q-crates, Multibus crate, and related electronics. The other cabinet of this dual-cabinet package is the terminations “B” Cabinet, which houses the terminal blocks for field signal connections. Q-Card addresses are assigned using jumper wires on the card front-edge cable connector. Refer to Section 2-12 for more information on cabinet termination. Card-edge Termination In card-edge termination the drop is packaged in a single “A” Cabinet. This method uses field termination edge connectors at each Q-card for user field signal connections. Refer to Appendix C for more information on card-edge termination.

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2-8. “B” Cabinet Field Terminations and Addressing

2-8. “B” Cabinet Field Terminations and Addressing The Enhanced “B” Cabinet termination hardware consists of an eight-level array of barrier-type terminal blocks. Six 20-point terminal blocks (called A-blocks) occupy each level, giving a total of 48 (8 levels * 6 blocks) A-blocks for the “B” Cabinet (The Standard “B” cabinet has 36 18-point terminal blocks). The term “half-shell” is Westinghouse terminology for the metal structure that supports the terminal blocks in these cabinets. One half-shell supports one A-block. Conductors carrying field signals to and from the user’s process or plant are connected to each block’s No. 6 screw terminals (The Standard “B” cabinet uses No. 8 screw terminals). These screw terminals accept up to a No. 10 AWG conductor. An optional, 20-point B-block can be added to the half-shell when auxiliary power or grounding is required (for instance, when contact inputs requiring 48 V power are used). Like the A-block, the B-block uses No. 6 screw terminals, which can accept up to No. 10 AWG conductor (Standard “B” cabinet uses No. 8 screw terminals). Each half-shell is identified by “zone” and “row”. Table 2-2 illustrates some of the differences between the Standard and Enhanced Cabinets. Figure 2-10 shows the Enhanced “B” Cabinet termination hardware, and identifies the zones and rows. Table 2-2. “B” Cabinet Types Cabinet Type

Item

Capacity/Size

Terminal Blocks

36

Half Shell Zones

6

Terminal Points

18

Connecting Screw Size

#8

Terminal Blocks

48

Half Shell Zones

8

Terminal Points

20

Connecting Screw Size

#6

Standard

Enhanced

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Edge Connector for Field Terminations C A R D

Q C R A T E

Q1

E D G E

Q2 Paddle Card for Expansion

Z O N E Q3 S

Q-Crate Slot 1 Q-Card

F U S E

C O N N E C T O R

Electronics A-Cabinet Front

Figure 2-9. Standard “A” Cabinet and Field Connections

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Front View Top View of Cabinet with Half-Shells Cabinet Zones A

B

C

Detail of Half-Shell

D

E 20 19 18 17 16 15

F

14 13 12 11

G

10 9 8 7 6 5

H

4 3 2 1

Figure 2-10. Enhanced “B” Cabinet, Termination Structure

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Table 2-3 illustrates the half-shell zones, rows, and terminal point numbers (1 to 20 from bottom) of the Enhanced terminations cabinet. Table 2-3. Enhanced Half-Shell Terminal Locations

Row Numbers 3 4

1

2

5

6

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

20 • • 1

Zones

A

B

C

D

E

F

G

H

Notes B-Block Terminals not shown. Standard cabinets have only 18 terminals and Zones A-F.

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These terminal numbers, along with the half-shell identifiers, are used to label the signals (or points). For example, the analog signal which terminates at the bottom terminal of the half-shell A1 A-block is identified as A1 A01. The next terminal on that A-Block is identified as A1 A02, and so on. Digital points (terminated at B-Blocks), have labels such as C1 B20 (which indicated the highest terminal on the B-Block of half-shell zone C, row 1). The 48 half-shells are assigned on a one-for-one basis to 48 Q-line process I/O PC board (Q-card) locations (slots) in the associated “A” Cabinet. Table 2-4 shows the standard assignments of half-shells to Q-Card slots. In some control system applications, a 20-point A-block may be assigned to several Q-cards, to facilitate hard M/A station field wiring. The half-shell to Q-Card cable connectors are labeled to assist in identification and placement. The cable labeling convention is shown in Table 2-4.

Table 2-4. Half-Shell to Q-Card Connection

Q-Crate Number 1

Q-Crate Slot

5

6

7

8

9

10

11

12

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

A6

B6

C1

D1

C2

D2

C3

D3

C4

D4

C5

D5

C6

D6

E1

F1

E2

F2

E3

F3

E4

F4

E5

F5

E6

F6

Card Edge 402 404 406 408 410 412 414 416 418 420 422 424 Identification Half-Shell Zone-Row

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4


4

3


3

2


2

1

G1

H1

G2

H2

G3

H3


G4

H4

G5

H5

G6

H6

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A cable connects each half-shell with the corresponding Q-Card in the “A” cabinet. The cable connector, which attaches to the front edge of the Q-Card, incorporates nine jumpers used to select the Q-Card address (shown in Figure 2-11). For additional information on Q-Card address selection, refer to Section 2-10 and Appendix B.

28 (Last Address Jumper) 27 26 25 24 23 22 21 (First Address Jumper Location)

WD

PF Q- L II i I/ n e O

Note: The first 20 locations are reserved for card wiring.

Figure 2-11. Address Jumpers on Cable Connector (“B” Cabinet Terminations)

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2-9. Q-Card Hardware Address Selection

2-9. Q-Card Hardware Address Selection The following Sections provide guidelines for assigning hardware addresses to Q-Cards, and describe the use of the address jumpers. If using Westinghouse supplied termination lists (or hardware addresses have already been assigned), proceed to Section 2-12.

2-9.1. Determining Q-Card Addresses Q-Card address assignment is dependent on several factors, including the available hardware addresses and the number and type of cards. Constraints may also be imposed by the database size, and by the Q-Crate slot assignments (when default naming is used). Each of these factors is discussed below. Available Hardware Addresses (Standard) Each cabinet consists of up to three Q-crates with 12 slots per crate for a maximum total of up to 36 cards per cabinet. When using an extended A (AX) cabinet, this total is doubled to 72 per DPU. Available Hardware Addresses (Enhanced) Each cabinet consists of up to four Q-crates with 12 slots per crate, for a maximum total of up to 48 cards per cabinet. When using an extended A (AX) cabinet, this total is doubled to 96 per DPU. Address Blocks Two address blocks are available for Q-Card hardware addressing for each cabinet: 80-F7 and 08-7F. Within these blocks, addresses FC-FF and 00-07 are not available. Note that the hardware address range is the same for A cabinets and AX cabinets, although the software addresses will be different. For information on calculating software addresses, refer to “MAC Application Utilities User’s Guide” (U0-0136). Caution Do not use restricted blocks (FC-FF and 00-07) for hardware addressing. When possible, it is recommended that addressing be confined to the upper block (80-F7). Figure 2-12 shows a worksheet that can be used when assigning Q-Card addresses. This worksheet also appears in Appendix A.

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To use this worksheet, begin with the top block (80-F7), and fill in the cards using the guidelines given below:

•

Reserve address F8-FB for cold junction compensation QRT card (whether currently used or possible future addition), except when cold junction compensation is to be accomplished using a QAV card (level 6QAV or above) or half-shell compensation.

• •

QSE card cannot be placed in an extended (AX) cabinet. Reserve address 80 for QTB (Time Base) card, if applicable: — If any AI points for QAI cards are terminated in a cabinet, a QTB card must be placed in that cabinet. For example, if both the A and the AX cabinet have AI point terminations, each cabinet must have a QTB card. — With a 486-based DPU, a QBE is not currently supported. Therefore, if a QAI card is used, the QTB must be in the same crate as the QAI. — For QAV and QAW cards, the QTB card is optional (jumper selectable). If selected, in the event of QTB failure, the QAV/QAW card’s point quality will be set to bad. If QTB monitoring is not selected, the QAV/QAW noise rejection rating will be lower than otherwise specified. — When a second (back-up) QTB is used within a cabinet, it is assigned the same address (80) as the primary QTB. Refer to the QTB card description in Section 3 for additional details.

•

No more than 30 QLI cards may be used with a DPU, due to timing considerations.

•

If implementing DIOB Check, assign hardware addresses AA and 55 (which cannot be used by any other cards) to the QBO cards. The preferred layout is to place one QBO in crate 1 and one QBO in crate 2, 3 or 4. For additional information on DIOB Check, refer to “DPU Introduction and Configurations” (U0-0135).

•

To maximize utility, assign card hardware addresses (if applicable) in the following order: 1. Reserve F8-FB for QRT (for cold junction compensation) when a QAX card is used for temperature compensation, this address block can be used. 2. Assign QTB cards, (time base for QAI/QAV/QAW/QRT). 3. Assign QBO cards, (for DIOB Check). 4. Assign remaining point cards in descending order by number of channels, as described in Figure 2-12.

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Worksheet A Q-Card Address Assignments *80 81 82 83 84 85 86 87

*90 91 92 93 94 95 96 97

*A0 A1 A2 A3 A4 A5 A6 A7

*B0 B1 B2 B3 B4 B5 B6 B7

*C0 C1 C2 C3 C4 C5 C6 C7

D0 D1 D2 D3 *D4 D5 D6 D7

*E0 E1 E2 E3 *E4 E5 E6 E7

*F0 F1 F2 F3 *F4 F5 F6 F7

*88

*98

*A8

*B8

*C8

*D8

89 8A 8B 8C 8D 8E 8F

99 9A 9B 9C 9D 9E 9F

A9 AA AB AC AD AE AF

B9 BA BB BC BD BE BF

C9 CA CB *CC CD CE CF

D9 DA DB *DC DD DE DF

*E8 E9 EA EB *EC ED EE EF

*F8 F9 FA FB FC FD FE FF

00 01 02 03 04 05 06 07

*10

*20

*30

*40

*50

*60

11 12 13 14 15 16 17

21 22 23 24 25 26 27

31 32 33 34 35 36 37

41 42 43 44 45 46 47

51 52 53 54 55 56 57

61 62 63 64 65 66 67

*70 71 72 73 74 75 76 77

*08 09 0A 0B 0C 0D 0E 0F

*18

*28 29 2A 2B 2C 2D 2E 2F

*38

*48

*58

39 3A 3B 3C 3D 3E 3F

49 4A 4B 4C 4D 4E 4F

59 5A 5B 5C 5D 5E 5F

*68 69 6A 6B 6C 6D 6E 6F

19 1A 1B 1C 1D 1E 1F

*78 79 7A 7B 7C 7D 7E 7F

Indicates restricted address – DO NOT USE Indicates reserved address (80 = QTB; AA and 55 = QBO; F8-FB = QRT) Available only if QTB and/or DIOB checking is not implemented * Indicates address used with default naming feature Q-Cards with: 12 channels (QAX) must start at zero and use 2 blocks of 6 addresses 8 or 6 channels (QAH, QAV, QAW, QLI, QLJ) must start at x0, x8 4 channels (QAI, QAO, QPA, QSE) must start at x0, x4, x8, xC 2 channels (QAA, QAM, QLC) must start at x0, x2, x4, x6, x8, xA, xC, xE where x = 0 through F Other cards (QBI, QCI, QDI, QID, QRO, QSC, QSP, QTO) may use any address Note QBI and QDI are being replaced by the QID card

Figure 2-12. Q-Card Hardware Address Selection Form

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Placement of Q-Cards by Number of Channels Cards which have more than one channel require more than one hardware address, as illustrated in Figure 2-13. Starting addresses for these cards (circuit 0) must follow these rules:

•

Twelve-channel cards (QAX) must start at address 0 and use two blocks of six addresses.

•

Six and eight-channel cards (QAH, QAV, QAW, QLI) must start at address x0 or x8 (where x = 0 through F).

•

Four-channel cards (QAI, QAO, QRT, QPA, QSE must start at address x0, x4, x8, or xC (where x = 0 through F).

•

Two-channel cards (QAA, QAM must start at address x0, x2, x4, x6, x8, xA, xC, or xE (where x = 0 through F).

•

All other cards require a single address.

When assigning Q-Card addresses, begin with the largest channel number (eight and six) and assign those cards first. Proceed with the four-channel cards and then the two-channel cards. Finally, assign the digital single-channel cards. This approach will allow the smaller address assignments to be filled in around the larger assignments. Note that no more than 30 of the six- or eight-channel cards, or 15 of the 12-channel cards may be included in a cabinet, because of the addressing constraints. As Figure 2-13 illustrates, address blocks 80-FF and 00-7F each contain 16 starting addresses of 0 or 8, for a total of 32. However, because of the reserved addresses (FC-FF and 00-07), addresses F8 and 00 cannot be used for the six- or eight-channel cards. This leaves 30 addresses available. Enable and Hl/LO Signals In addition to the hardware address, some cards require an Enable or Hl/LO signal, as described in Section 2-10. For additional information, refer to the individual card descriptions in Section 3.

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Starting Address

Starting Address

Starting Address

0 or 8

0 or 8

0 or 8

QAH QAV* QLI

QAV* QAW

QAI QAO QPA QRT QSE

4 or C

Eight Channels/ Addresses

Six Channels/ Addresses

Starting Address

Four Channels/ Addresses

Starting Address

Starting Address

0 or 8

0 or 8

1 or 9 2 or A

QAA QAM

2 or A

QBI QBO QID

3 or B 4 or C

4 or C

5 or D 6 or E

6 or E

7 or F

Two Channels/ Addresses

One Channel/ Addresses

0 or 8 Hi/Lo 1 or 9 Hi/Lo 2 or A Hi/Lo 3 or B Hi/Lo 4 or C Hi/Lo 5 or D Hi/Lo 6 or E Hi/Lo 7 or F Hi/Lo

QRO QTO

Eight Bits 1/2 Address

Figure 2-13. Q-Card Number of Channels and Starting Address

Q-Card Address Example Figure 2-14 illustrates address selections for a DPU with the following cards: 1 QRT 1 QTB 2 QBO

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2 QCI 3 QSE 3 QAO

3 QLI 6 QAM 6 QAW


15 QAV

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80 81 82 83 84 85 86 87

QTB

88 89 8A 8B 8C 8D 8E 8F

QAW

QCI QCI QAM

QAM

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

QAV

90 QAW 91 92 93 94 95 96 QAM 97

A0 QAW A1 A2 A3 A4 A5 A6 QAM A7

B0 QAV B1 B2 B3 B4 B5 B6 B7

C0 QAV C1 C2 C3 C4 C5 C6 C7

D0 QAV D1 D2 D3 D4 D5 D6 D7

E0 QAV E1 E2 E3 E4 E5 E6 E7

F0 QAV F1 F2 F3 F4 F5 F6 F7

98 QAW 99 9A 9B 9C 9D 9E QAM 9F

A8 A9 AA QBO AB AC QSE AD AE AF

B8 QAV B9 BA BB BC BD BE BF

C8 QAV C9 CA CB CC CD CE CF

D8 QAV D9 DA DB DC DD DE DF

E8 QAV E9 EA EB EC ED EE EF

F8 QRT F9 FA FB FC FD FE FF

10 QAV 11 12 13 14 15 16 17

20 QAV 21 22 23 24 25 26 27

30 QAV 31 32 33 34 35 36 37

40 QAO 41 42 43 44 QSE 45 46 47

50 QSE 51 52 53 54 55 QBO 56 57

60 QLI 61 62 63 64 65 66 67

70 QAW 71 72 73 74 75 76 QAM 77

18 QAV 19 1A 1B 1C 1D 1E 1F

28 QAV 29 2A 2B 2C 2D 2E 2F

38 QAO 39 3A 3B 3C QAO 3D 3E 3F

48 QLI 49 4A 4B 4C 4D 4E 4F

58 QLI 59 5A 5B 5C 5D 5E 5F

68 QAW 69 6A 6B 6C 6D 6E 6F

78 79 7A 7B 7C 7D 7E 7F

INDICATES RESTRICTED ADDRESS Notice this example shows level 6 QAV cards, which require eight addresses.

Figure 2-14. Q-Card Hardware Address Selection Example

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Q-Card Addresses and Q-Crate Slot Assignments In most cases, the address assigned to a Q-Card does not depend on the Q-Crate slot in which it is placed. However, if using the MEDIT default naming feature, specific addresses must be associated with the Q-Crate card slots. Appendix A contains two worksheets which can be copied and used to record the Q-Cards placement and addressing. Worksheet B can be used for any card placement scheme. Worksheet C, to be used when default naming will be used, shows the addresses assigned to each card slot. Refer to “MAC Application Utilities User’s Guide” (U0-0136) for additional information on MEDIT and default naming. Database Limitations When selecting a set of Q-Cards, it is necessary to consider the database requirements as well as the addressing requirements. Each address used by a Q-Card is associated with a point in the DPU database. A specified amount of memory space within the DPU is set aside for the database. Points defined by control algorithms are also allocated space within the DPU. The total amount of space available is as follows:

•

For a single-speed DPU, there is 82K is available for the database and 64K is available for control.

•

For a multi-speed DPU: — At software level 6, there is 82K is available for the database. — At software level 7, there is 122 K is available. — For software levels 6 and 7, four areas of 64K and one of 32K are available for control.

The amount of space used by each point depends on its record type (refer to “Record Types User’s Guide” (U0-0131) for information on record types). To verify that a configuration is acceptable, calculate the amount of memory required for the points defined.

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2-10. Using Address Selection Jumpers

2-10. Using Address Selection Jumpers As described in Section 2-12 and Appendix C, both the termination card-edge connectors and the half-shell cable card-edge connector provide addressing jumpers. For both types of termination hardware, the use of the jumpers is the same. The Q-Card’s hexadecimal address is translated into binary. This binary address is represented by jumpers 21 through 28. For example, the card address E9 translates into binary 1110 1001. The jumpering for this address is shown in Figure 2-15. As shown, each jumper represents a 1, and is removed to represent 0. Refer to Appendix B for a conversion table that provides a hexadecimal address conversion. Note that certain cards (QAA, QAX, QPA, and QLl) use different jumpering schemes. Refer to the individual card descriptions in Section 3 for details. E9

1

1

1

0

1

0

0

1 Jumper 20 in place = High Byte or Enabled

Top of Connector

Removed = Low Byte 28

27

26

25

24

23

22

21

20

Jumper in Place =1 Jumper Removed = 0 Figure 2-15. Address Jumpering Example

High/Low or Enable Jumpering While the first eight jumpers are used to select the address, the ninth jumper (pin number 20) is used to select Hl/LO or ENABLE. The QRO and QTO can address the high or low 8 bits of a 16 bit address, based on the setting of this jumper. When the jumper is inserted, HI is selected (bits 8-15). When the jumper is removed, LO is selected (bits 0-7). Jumper pin 20 is a required address enable jumper for the following cards: QAV, QAW, QLl, QRT, and QSE. Refer to the individual card descriptions in Section 3 for details.

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2-11. Pre-Wiring Considerations

2-11. Pre-Wiring Considerations Site Preparation and Planning -- The WDPF System’s field wiring troughs, ducts, channels, and/or false floors should already have been planned and installed (refer to “Data Highway Installation Manual” (M0-0051) and “Highway Installation Manual (WEStations)” (M0-8000). Most potential noise problems should have been resolved during this installation phase. Cable Routing -- In the typical WDPF installation, cables are routed between the plant or process and the data acquisition system via conduit and raceways (cable trays). Generally, covered trays are not necessary for class Q, class L, and class M cables when minimum spacing is maintained between dissimilar trays. Use the following precautions to minimize or avoid noise and inter-circuit interferences.

• •

Do not route computer cables near AC or DC power conductors.

•

Keep generator output buses with kilovolt or kiloampere power levels several feet away from trays with signal cables.

•

Because of the associated high-frequency noise, induction heater supply cables should be far from computer cables. Spacing from such cables to any computer input or output cable should be very large (approximately 50 to 100 ft).

Tightly twist power conductors (including return or neutral) as these conductors may share a cable tray with signal cables. If the cables are not twisted, power conductors should not be in the same trays as signal cables.

Additional information on selection of signal cables and on minimum spacing between cables can be found in Section 2 of this manual, in “Data Highway Installation Manual” (M0-0051), and in “Highway Installation Manual (WEStations)” (M0-8000). Card Replacement -- Q-line I/O cards can be removed and replaced with the + 13 VDC power on. The front-edge connector should be removed from the card and the card should be replaced before the front-edge connector is re-installed. Caution Power to the Multibus cards within the DPU must be off before the Multibus cards are removed and replaced.

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2-12. Field Wiring Half-Shell Terminations

2-12. Field Wiring Half-Shell Terminations When a terminations cabinet is used, connections are made to its half-shell terminal strips. Installation Data Sheets have been provided in Section 3 as an aid to the installer. These sheets show the “B” Cabinet terminal block connections used for most applications. When using the field terminations card-edge connectors for process I/O field signals (where connections are made directly to each Q-card, see Appendix C). Follow the procedures listed below for field wiring a WDPF System to the terminal blocks of the Enhanced termination cabinets. Use the custom Termination Lists supplied for your system to locate specific termination points. Also refer to the specific card information provided in Section 3. WARNING Remove drop power and use extreme caution when making field connections to terminal blocks. A shock hazard to personnel may exist on some of the higher voltage signals. 1. Locate the field wires or cables to be connected to the selected block, and make connections to the No. 8 (Standard) or the No. 6 (Enhanced) screw terminals. Connection to these terminals can be made with up to No. 12 AWG conductors or No. 10 AWG with ring terminals. Only wires and/or cables which comply with each field connection’s signal and noise minimization requirements should be used. 2. Bundle the wires connected to the terminal block with tie wraps and then tie-wrap these cables to the cabinet frame. Remember to leave service loops to relieve stress and/or to permit access to the cabinet when it is to be moved out of position for maintenance purposes. 3. Repeat the procedures of Steps 1 and 2 for each remaining terminal block until all terminations to the cabinet have been completed. 4. If not previously done at the factory, insert the appropriate jumpers in the Q-Card’s edge connectors. Each card’s selected address should be in compliance with the terminations list. Caution After address selection, do not switch connectors between cards. Doing so will unpredictably switch card addresses and change the half-shell to card assignments.

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2-13. Environmental Specifications

2-13. Environmental Specifications All Q-cards can be expected to perform as specified subjected to the following environmental specifications. Any deviation form these specifications is noted with the affected card. Ambient Air Temperatures From 0°C through +60°C (32°F through 140°F) as measured approximately 1/2 inch from any point on the printed circuit card while it is mounted in its normal (vertical) position and while subject to air movements which result from natural convection only (that is, no forced air movement). Humidity Rating 10 to 90%, noncondensing. Vibration From 0.7g acceleration at 10Hz, following a straight line change, to 10g acceleration at 40Hz, and at a constant acceleration of 10g from 40 to 50 Hz.

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2-14. Power Consumption

2-14. Power Consumption Table 2-5. Power Consumption and Heat Load for Q-Cards

Current (A rms) @ 115V


Power (Watts)

Heat Dissipation (BTU/Hr)

QAA

0.11

0.05

8.1

27.7

QAC G01

0.26

0.13

19.5

66.6

QAC G02

0.10

0.05

7.2

24.9

QAC G03

0.09

0.04

6.5

22.2

QAC G04

0.16

0.08

12.2

41.7

QAC 5

0.17

0.08

13

44.4

QAH

0.17

0.08

13

44.4

QAI

0.12

0.05

8.9

30.4

QAM

0.09

0.04

6.5

22.2

QAO

0.28

0.14

21.1

72

QAV

0.22

0.1

16.3

55.7

QAW

0.22

0.1

16.3

55.7

QAX

0.19

0.09

14.5

49.8

Card Type

QAXD

NONE - Covered by the QAX numbers

QAXT

0.016

0.008

1.2

4.2

QBE

0.08

0.04

6.6

22.5

QBI

0.04

0.02

3.3

11.3

QBO

0.05

0.03

4.1

14

QCA

Load Dependent - Consult the EPS

QCI

0.11

0.05

8.1

27.7

QDC

0.16

0.08

12.2

41.7

QDI G01, G03, G05, G07, G08, GO9, G10

0.04

0.02

3.3

11.3

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2-14. Power Consumption

Table 2-5. Power Consumption and Heat Load for Q-Cards (Cont’d)

Card Type



Power (Watts)

Heat Dissipation (BTU/Hr)

QDI G02, G04, G06, G11

0.02

0.01

1.6

5.5

QDT

0.16

0.08

12.2

41.7

QIC

0.09

0.04

7.15

24.4

QID

0.04

0.02

3.3

11.3

QLC

0.28

0.14

21.1

72

QLI

0.26

0.13

19.5

66.6

QLJ

0.26

0.13

19.5

66.6

LIM

0.22

0.11

18.0

61.5

SLIM

0.07

0.04

6.0

20.5

QPA

0.02

0.01

1.6

5.5

QRC

0.15

0.08

11.4

38.9

QRF

0.14

0.07

10.5

35.8

QRO

0.09

0.04

6.5

22.2

QRS

0.18

0.09

13.8

46.9

QRT

0.26

0.13

19.5

66.6

QSC

0.09

0.04

6.5

22.2

QSD

0.26

0.13

21.0

71.1

QSE

0.22

0.11

16.3

55.7

QSR

0.18

0.09

13.8

46.9

QSS

0.11

0.05

8.1

27.7

QST

0.14

0.07

10.5

35.8

QTB

0.02

0.01

1.6

5.5

QTO

0.04

0.02

2.6

8.9

QVP

0.14

0.07

10.5

35.8

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Section 3. Q-Card Reference Sheets 3-1. Section Overview This section contains reference sheets for each available Q-Card. To allow easy reference, these sheets are arranged alphabetically by the three-character Q-Card identifier (the exceptions are the Loop Interface Module (LIM) and the Small Loop Interface Module (SLIM) which appear immediately after the QLJ card reference sheets). The Q-Card identifier is shown in the upper outside corner of each page. For each Q-Card, the following is provided in the reference sheets:

• • • •

Functional Description Specifications Controls/Indicators Description Installation Data Sheet(s)

The Installation Data Sheets provide card-specific termination information. These sheets are provided at the end of each card description, except for those cards which do not require field termination. Figure 3-1 illustrates a typical “Standard” Q-Card half-shell termination. As shown, the connections from the terminal block are different for each card. Table 3-1 lists the Q-Cards that are described in this section, and provides a brief description of each group of each card. Note Many of the wiring diagrams for the Q-cards indicate the “Standard” termination of the cards with 18 posts. When ordering new systems with the “Enhanced” cabinets, there will be 20 termination points on a half-shell. The basic wiring for both the 18 and 20 terminal half-shells stays the same, with only the first 18 terminations being used.

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Figure 3-1. Typical Q-Card Termination, “Standard” Cabinet

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Figure 3-2. Typical Q-Card Termination, Remote “B” Cabinet

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Table 3-1. Q-Card Groups and Ranges Name

Group

QAA (Actuator Auto/Manual Card)

QAC (Analog Conditioning Card)

QAH (High-Speed Analog Input Point Card)

QAI (Analog Input Card)

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Range

G01

-16 to +16 mA (Velocity), +4 to +20 mA (Position)

G02

+4 to +20 mA (Standard), Voltage ranges between -10 and +10 VDC (Optional)

G01

0 to 10 VDC +4 to +20 mA at 24/40 VDC (1 power supply)

G02

0 to 10 VDC +4 to +20 mA at 24/40 VDC (2 auctioneered power supplies)

G03

Signal switching

G04

1 to 5 VDC +4 to +20 mA at 24/40 VDC

G05

+120 mA at + 48 VDC

G06

0V to 10VDC

G01

-10.24 to +10.235 VDC

G02

-5.12 to +5.117 VDC

G03

0 to +10.237 VDC

G04

0 to +5.119 VDC

G01

-20 to +20 mVDC

G02

-50 to +50 mVDC

G03

-100 to +100 mVDC

G04

-500 to +500 mVDC

G05

-1 to +1 VDC

G06

-10 to +10 VDC

G07

0 to +20 mA

G08

-50 to +50 mA


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Table 3-1. Q-Card Groups and Ranges (Cont’d) Name

Group

QAM (Auto/Manual Station Controller Card)

QAO (Analog Output Card)

QAV (Analog Input Point Card)

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Range

G01

0 to +10 VDC (Output)

G02

0 to +20 mA, 0 to +5 VDC (Output)

G03

0 to 5VDC

G06

1 to 5VDC

G01

0 to +20.475 mA

G02

0 to +10.2375 VDC

G03

-10.24 to +10.235 VDC

G04

0 to +5.1187 VDC

G05

-5.12 to +5.1175 VDC

G06

-10.24 to +10.235 VDC

G07

0 to +20.475 mA

G08

-10.24 to +10.235 VDC

G01

-5 to +20 mVDC, 500Ω source impedance

G02

-12.5 to +50 mVDC, 500Ω source impedance

G03

-25 to +100 mVDC, 1KΩ source impedance

G04

-12.5 to +50 mVDC, 500Ω source impedance

G05

-25 to +100 mVDC, 1KΩ source impedance

G06

-12.5 to +50 mVDC, 1KΩ source impedance

GO7

-5mV to 20mV (with temperature compensation)

GO8

-12.5mV to 50mV (with temperature compensation)

GO9

-25mV to 100mV (with temperature compensation)


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Group

QAW (Analog High-Level Input Point Card)

QAX (12 Point Analog Input Card)

QAXD (QAX Digital Daughter Board)

QAXT (Terminal Block Temperature Sensing Module)

QBE (Bus Extender Card)

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Range

G01

0 to +1 VDC, 1KΩ source impedance

G02


G03


G04

0 to +20 mA

G05

0 to +20 mA (self-powered)

G06

0 to +50 mA

GO1

-5mV to 20mV, 500Ω source impedance

GO2

-12.5mV to 50mV, 500Ω source impedance

GO3

-25mV to 100mV, 1KΩ source impedance

GO4

0 to 1V, 1KΩ source impedance

GO5


GO6


GO1

-5mV to 20mV

GO2

-12.5mV to 50mV

GO3

-25mV to 100mV

GO4

0 to 1V

GO5

0 to 5V

GO6

0 to 10V

GO1

+20mV

GO2

+50mV

GO3

+100mV

GO4

+20mV

GO5

+50mV

GO6

+100mV

G01

DIOB discharging

G02

No DIOB discharging


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QBI (Digital Input Card) (Superseded by QID Card)

Group

Range

G01

+5 (4 to 6) V Logic

G02

+12 (10 to 15) V Logic

G03

+12 (10 to 15) VDC

G04

+24 (20 to 30) VDC

G05

+48 (40 to 60) VDC

G06

+48 (40 to 60) VDC

G07

+125 (100 to 150) VDC

G08

+120 (100 to 150) VAC

G09

+12 (10 to 15) VDC

G10

+24 (20 to 30) VDC

G11

+120 (100 to 150) VAC (High Threshold)

G01

60 VDC at 300 mA (max)

G02

60 VDC at 300 mA (max.)

G03


G04


G05


QCA (Current Amplifier Card)

G01

Voltage Input, Voltage Output

G02

Voltage Input, Current Output

QCI (Contact Input Card)

G02

6 to 22 mA (closed contact)

QDC (Q-Line Digital Controller Card)

G01 G02

See “QDC User’s Guide” (U0-1105).

QBO (Digital Output Card)

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QDI (Digital Input Card) (Superseded by QID Card)

Group

Range

G02

24 VAC/VDC (8-bit differential)

G04

48 VAC/VDC (8-bit differential

G06

120 VAC/VDC

G08

12 VDC (8-bit differential

G10

48 VAC/VDC (16-bit angle-ended)

G11

120 VAC/VDC (high threshold) (8-bit differential

QDT (Diagnostic Test Card)

G01

N/A

QFR (Fiber-Optic Repeater)

G01

See “Remote Q-Line Installation Manual” (M0-0054).

QIC (Q-Line DIOB monitor)

G01

N/A

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Group

QID Q-Line Digital Input (To be used where QDI or QBI were formerly specified).

Range

G01

+5 (4 to 6) V Logic, 16 single-ended

G02

24 VAC/VDC (20 to 30), 8 differential

G03

24 VAC/VDC (20 to 30), 16 single-ended

G04


G05


G06


G07


G08

12 VDC (10 to 15) 16 single-ended

G09

12 VAC/VDC (10 to 15) 16 single-ended

G10

48 VDC (40 to 60), 16 single-ended

G11

120 VAC (95 to 150), 8 differential

G12

120 VAC (95 to 150), 16 single-ended

G13

220 VAC (190 to 264), 8 differential

G14

220 VAC (190 to 264), 16 single-ended

G15

220 VDC (180 to 264), 8 differential

G16

220 VDC (180 to 264), 16 single-ended

G17

5 VDC (3A99159 only)

QLC (Q-Line Serial Link Controller)

G01

See “QLC User’s Guide” (U0-1100).

QLI (Loop Interface Card)

G01

0 to 10 VDC (Analog Input/Output)

G02

0 to 5 VDC (Analog Input), 0 to 10 VDC (Analog Output)

G03

0 to 20 mA (Analog Input), 4 to 20 mA (Analog Output)

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QLJ (Loop Interface Card with output Readback)

Group

Range

G01

0 to 10 VDC (Analog Input) 0 to 10 VDC (Analog Output) 0 to 10 VDC (Output Readback)

G02

0 to 5 VDC (Analog Input) 0 to 10 VDC (Analog Output) 0 to 10 VDC (Output Readback)

G03

0 to 20 mA (Analog Input) 4 to 20 mA (Analog Output) 4 to 20 mA (Output Readback)

LIM (Loop Interface Module)

G01

Four selectable operating modes

G02

One operating mode

SLIM (Serial Loop Interface Module)

G01

Four selectable operating modes

G02

One operating mode

QMT (M-Bus Terminator Card)

G01

DIOB extension with 13 VDC power status indication, discharge circuits, voltage threshold detection, and timeout detection and recovery

G02

DIOB extension with 13 VDC power status indication, discharge circuits, and voltage threshold detection

G03

DIOB extension with 13 VDC power status indication

G01

48 VDC Clock Inputs 48 V Control Inputs

G02


G03


G04

48 VDC Clock Inputs No Control Inputs

QPA (Pulse Accumulator Card)

See “Remote Q-Line Installation Manual” (M0-0054).

QRC (Remote Q-Line)

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Group

Range

QRF (Four Wire RTD Input Card)

G01

Range set by QRD (3A99114) plug-in module

QRO (Relay Output Card)

G01

330 VDC/250 VAC (max.) Form A (open)

G02

330 VDC/250 VAC (max.) Form B (closed)

G03

330 VDC/250 VAC (max.) Form A (open) Non-inductive loads only.

G04

330 VDC/250 VAC (max.) Form B (closed) Non-inductive loads only.

QRS (Redundant Station Interface Card)

G01 Consult Westinghouse for information. through G06

QRT (RTD Input Amplifier Card)

G01

10 mV (nominal)

G02

33.3 mV (nominal)

QSC (Speed Channel Card)

G01

1.5, 1.8, 3.0, 3.6, 4.0, or 6.67 kHz; 1/8 second update

G02


QSD (Servo Driver Card)

G01

Input: 20 V peak-to-peak, 1KHz sine wave (LVDT) Output: +/- 24 mA

QSE (Sequence of Events Recorder Card)

G01

7 to 21 mA; event tagging 1/8 msec

G02

7 to 21 mA; event tagging 1 msec

G01

DC LVDT Supply

G02

AC LVDT Supply

G03

DC LVDT Supply

G04

AC LVDT Supply

QSR (Servo Driver with Position Readback Card)

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Group

Range

G01


G02


QST (Smart Transmitter Interface)

G01

See “Smart Transmitter Interface User‘s Guide” (U0-1115).

QTB (Time Base Card)

G01

60 Hz (+2 Hz Input)

G02

50 Hz (+2 Hz Input)

G03

60 Hz (+2 Hz On-board)

G04

50 Hz (+2 Hz On-board)

QTO (TRIAC Output Card)

G01

115 (80 to 140) VAC

QVP (Servo Valve Position Controller Card)

G01

LVDT interface; 80Ω (+ 24 mA)

G02

LVDT interface; 280Ω (+ 50 mA)

G03

4-20 mA loop interface; 80Ω (+ 24 mA)

G04

4-20 mA loop interface; 280Ω (+ 50 mA)

QSS (Speed Sensor Card)

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Q-Card Descriptions The following pages describe Q-card functionality, features, and wiring.

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M0-0053

3-2. QAA

3-2. QAA Actuator Auto Manual Card (Style 7379A91G01 and G02)

3-2.1. Description The QAA card provides the interface between the DIOB controller, the OIM (M/A station), and a final controlled device such as a WEMAC or a Beck drive. If only soft M/A stations (CRT’s) are provided, the QAA card is still required to interface the final drive to the DIOB. The QAA card-to-OIM interface is a group of hard-wired DIM level signals. Block Diagrams

DIOB

DIOB Interface

Position Register

M/A Logic

DAC

ADC Gain

+ -

Error Comparators

Gain Plug Braking Comparator

Output Buffer

Input Buffer

Input Buffer

Position RIM Output

Position RIF Input

Velocity RIF Input

Output Control Logic

Increase/ Decrease/ DIM Outputs DIM DIM Inputs Outputs

Figure 3-3. QAA G01 Block Diagram

The QAA card is available in two groups (G01 and G02). Group one is for controlling fast acting actuators such as a WEMAC which provide position and velocity feedback plus limit inputs (see Figure 3-3). Plug braking is used to stop the actuator. Group two is used to control slow acting actuators like Beck drives which provide position feedback and limit inputs, but do not provide velocity feedback (see Figure 3-4).

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3-2. QAA

DIOB

DIOB Interface

Position Register

M/A Logic

DAC

ADC -

+ Error Comparators

Gain

Quarter Speed Clock Half Speed Clock Output Buffer

Input Buffer

Position RIM Output

Position RIF Input

Output Control Logic

Increase/ Decrease/ DIM Outputs DIM DIM Inputs Outputs

Figure 3-4. QAA G02 Block Diagram

3-2.2. Features The QAA card provides the following features:

• • • • • • • • • •

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Computer (Automatic) or Local Manual mode operation Mode selection via external OIM signals Watchdog timer Two plug-in resistor variable rate clocks (G02 only) Local Manual mode selection via DIOB controller OIM indication of computer or Local Manual mode operating status OIM indication of actuator position high or low limit status Jumper selectable QAA card logic options Two external auctioneered DC power supplies On-card potentiometer parameter adjustments


M0-0053

3-2. QAA

The QAA card is actually two separate printed circuit cards. One card has the standard Q-line I/O card outline and serves as the mother card. The second card is a smaller, rectangular daughter card that is attached to the mother board by nylon spacers. A fifty-conductor flat flex cable transfers signals and power from the mother board to the daughter board. An outline of the QAA card and a daughter board is shown in Figure 3-5. Detailed card views are shown in Figure 3-10 through Figure 3-12.

J1 Connector Daughter Card

Connector is under Daughter Card

Figure 3-5. QAA Card Outline

Card Usage A typical QAA usage scheme is shown in Figure 3-6.

DIOB Controller QAW/ QAX

QAW/ QAX

QAA

QCI

QAO

DI’S/PB’S

P P O B S S N

Meters

Process Variable

C L

FEEDBACK

DI = Digital Input

BIAS

PB = Push-button

BIAS Demand

PT

Relay Panel

INCR DECR Motor Drive

Figure 3-6. QAA Card Usage Scheme

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3-2. QAA

Functional block diagrams of the QAA card are shown in Figure 3-7, Figure 3-8, and Figure 3-9.

QAA Alive Bit Reset

Local Manual Not Alive Mode

Local Manual Mode

QAA Healthy Bit Reset

Computer Mode

OIM Comp. Push-button OIM LMAN Push-button

QAA Alive Bit Set DIOB LMAN Bit QAA Healthy Bit Set

QAA Alive Bit Reset QAA Healthy Bit Reset

Figure 3-7. QAA Card State Diagram

OIM AND FIELD DIM INPUTS

WATCHDOG TIMER

OIM LAMPS (DIM OUTPUTS)

• • •••

COMMAND REGISTER

M/A LOGIC ACTUATOR ENABLE

STATUS REGISTER

DAC + –

ERROR COMPARATORS

– DIOB INTERFACE

OUTPUT CONTROL LOGIC

FOUR SECOND DELAY

INCREASE DECREASE (DIM OUTPUTS)

DEMAND REGISTER

GAIN PLUG BRAKING COMPARATORS

POSITION REGISTER

ADC

BUFFER

VELOCITY (RIF INPUT)

BUFFER

POSITION (RIF INPUT)

GAIN

BUFFER

POSITION OUTPUT TO OIM METER (RIM OUTPUT)

Figure 3-8. QAA G01 Detailed Block Diagram

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3-2. QAA

OIM AND FIELD DIM INPUTS

WATCHDOG TIMER

LAMPS (DIM OUTPUTS)

• • •••

COMMAND REGISTER

M/A LOGIC

STATUS REGISTER

DAC +

OUTPUT CONTROL LOGIC

ERROR COMPARATORS

–

INCREASE DECREASE (DIM OUTPUTS)

DIOB INTERFACE

DEMAND REGISTER

QUARTER SPEED CLOCK HALF SPEED CLOCK

POSITION REGISTER

ADC

GAIN (RIM OR RIF INPUT) BUFFER

BUFFER

POSITION

POSITION OUTPUT TO OIM METER (RIM OUTPUT)

Figure 3-9. QAA G02 Detailed Block Diagram

3-2.3. Specifications Inputs/Outputs G01 Analog Position Input and Analog Velocity Input Analog Position Input

Analog Velocity Input

Signal Type

Unipolar RIF

Bipolar RIF

Input Range

4 to 20 mA = 0 to 100%

(−) 16 mA to 16 mA

Input Impedance

250 ohms + 2%

250 ohms + 2%

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3-2. QAA

G02 Analog Position Input

•

Standard factory installed range = 4 to 20 mA = 0 to 100% Note With jumper JE inserted, the resultant 250 ohms +2% input impedance converts the input current into an equivalent 1 to 5V input voltage range.

•

Input Ranges: -10V to +10V, 1 to 5V, -10V to 0V, 0 to 8V, and 0 to 10V. Each range is = 0 to 100%

• • •

Allowable Span: 3.5V to 20V Bias Subtraction: 2.5V to (−)10V, selectable using various plug-in resistors Gain Adjustment: 0.46 to 4.0 using a plug-in resistor (5k to 75k)

Watchdog Timer Two jumper selected time-out periods, 0.5 seconds +20% and 2.0 seconds +20%. An additional jumper may be used to disable the timer. Operating Modes The QAA card has two modes of operation: Computer and Local Manual (LMAN). In addition, Local Manual mode has a submode that is entered when the DIOB controller has not updated the QAA card’s watchdog timer over the DIOB. This submode is called Local Manual Not Alive (LMNA).

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3-2. QAA

3-2.4. Card Addressing and QAA Word Format The QAA card occupies two continuous DIOB addresses (four bytes). Address bit UADD0 and control bit HI/LO are used to select one of the four bytes. When the QAA Card’s Demand Register is written to or read from, the low byte must precede the high byte. The maximum time between the reading or writing of the Demand bytes is 0.1 msec. DIOB BASE ADDRESS PLUS 0

POSITION (READ)/STATUS (READ) OR COMMAND (WRITE) 15 MSB

1

HIGH BYTE POSITION

8 LSB

7

LOW BYTE

0

STATUS /COMMAND

DEMAND (READ/WRITE) 15

HIGH BYTE

MSB

8

7

6

LOW BYTE

0

LSB

The Status/Command byte is as follows:

Table 3-2. QAA Status/Command Byte Interpretation Bit Number

Status

Command

0

COMPUTER/LMAN

KEEP ALIVE

1

LO-LIM

GO TO LMAN

2

HI-LIM

RESET ACTUATOR (LATCHED)

3

QAA ALIVE

COMP MODE PERMIT (LATCHED)

4

QAA HEALTHY

PRIORITY COMMAND (LATCHED)

5

NOT USED (LOGIC 0)

FULL SPEED (LATCHED) G02

6

NOT USED (LOGIC 0)

NOT USED

7

NOT USED (LOGIC 0)

NOT USED

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3-2. QAA

DIOB Pin Assignments Pin assignments for the J1 connector are given in Table 3-3. Pin assignments for the J2 connector are given in Table 3-4. Table 3-3. QAA J1 Pin Assignments Solder State

J1 Connector Pins

Component Side

PRIMARY

1

2

PRIMARY

BACKUP

3

4

BACKUP

GROUND

5

6

GROUND

UADD0

7

8

UADD1

UADD2

9

10

UADD3

UADD4

11

12

UADD5

UADD6

13

14

UADD7

HI/LO

15

16

R/W

*

17

18

DATA-GATE

GROUND

19

20

DEV-BUSY/ACK

UDAT0

21

22

UDAT1

UDAT2

23

24

UDAT3

UDAT4

25

26

UDAT5

UDAT6

27

28

UDAT7

GROUND

29

30

*

*

31

32

*

*

33

34

GROUND

Notes

* These pins are open. The QAA Card does not interface to the following DIOB signals: UFLAG, UCAL, USYNC, UCLOCK, and UNIT.

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3-2. QAA

Table 3-4. QAA J2 Connector Pin Assignments Component Side Signals (B)

Pins

CA7 CA6 CA5 CA4 CA3 CA2 CA1 POSITION INPUT SIGNAL COMMON POSITION TO METER (+) SLOT OIM GO TO COMPUTER (See Note 1) RAISE (See Note 1) HIGH LIMIT (See Note 1) ACTUATOR ALIVE (See Note 1) HIGH LIMIT (See Note 2) COMPUTER (See Note 2) ACTUATOR ENABLE (See Note 2) INCREASE (See Note 2) 13 V CARD BACKUP PSC FOR SHIELD (+) 8V FOR SLIDEWIRE PSP  PSP  For Actuator and PSP  Feedback Unit PSP FOR OIM (See Note 3) SYSTEM BACKUP SYSTEM PRIMARY 1. 2. 3.

28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Solder Side Signals (A)

DIOB GROUND DIOB GROUND DIOB GROUND DIOB GROUND DIOB GROUND DIOB GROUND DIOB GROUND VELOCITY INPUT SIGNAL COMMON POSITION TO METER (−) SLOT OIM GO TO LMAN (See Note 1) LOWER (See Note 1) LOW LIMIT (See Note 1) RESET WEMAC (See Note 1) LOW LIMIT (See Note 2) LMAN (See Note 2) DECREASE (See Note 2) PSC  PSC  For Actuator and Feedback Unit PSC PSC  PSC FOR OIM PSC FOR OIM SHIELD (See Note 3) BACKUP RETURN PRIMARY RETURN

Notes DIM Inputs DIM Outputs PSC = POWER SUPPLY COMMON (SYSTEM GROUND) PSP = AUCTIONEERED 21 TO 27 VOLT POWER

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3-2. QAA

3-2.5. Controls, Indicators, and Test Points Figure 3-10 through Figure 3-12 illustrate the locations of the QAA controls, indicators, and test points.Table 3-8, Table 3-9, and Table 3-10 describe them. Power On JA1

Status LEDs

JS6,7,8

J1 JS1,2,3

Watchdog Timer Reset

JA J2 TP1

TP2

JS5

JS4

TP3

JF

Figure 3-10. QAA Mother Card Components, Test Points

VR3 TP13

VR6 VR7

TP7

TP5

TP8

TP1,2 VR4

VR1

VR8

VR9

TP6 TP9-12 VR5 TP14 TP3,4

R59 R60

VR2 VR10 VR11

DWC

VR12

Figure 3-11. QAA DWC Daughter Card Components, Test Points

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3-2. QAA

VR6 TP5

VR7 TP13

TP1

R26,27,28 R16,17

TP6 VR4 VR8

VR9

JE J2,3 TP7-10

VR1

VR3

TP4

TP2,3 VR10 VR11 VR2 VR12 R59, 60

DBK TP11

TP12

Figure 3-12. QAA DBK Daughter Card Components, Test Points

3-2.6. QAA Tuning Depending on the application, the QAA card may require adjustments from the factory-shipped potentiometer settings and plug-in resistors. The following adjustments may be made to the QAA card:

• • • • •

Position feedback range (G02 only) Positioning accuracy (G01 and G02) Half-speed clock ON/OFF time (G02 only) Quarter-speed clock pulse width (G02 only) High and low limit (G02 only)

Each of these adjustments are described below.

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3-2. QAA

Equipment and Set-up In order to adjust the QAA potentiometers, the following test equipment is required:

• • •

Q-Line Extender Card (QEX) Digital voltmeter Trim potentiometer adjustment tool (or small screwdriver) Note The QAA card must be installed on the QEX to provide access to potentiometers and other components.

To re-calibrate the G02 QAA (after changing the position feedback range), the following additional test equipment will be required:

• •

Precision 0 - 20 VDC power supply (adjustable to 0.1 V) Special Q-Line card edge connector with external test leads tied to pins 21B and 20B.

Select Position Feedback Range (G02 Only) The valve position feedback range for the G02 QAA card is selectable using plug-in resistors R16, R26, R27, and R28. The card is factory-shipped with the appropriate resistors for a 4 to 20mA range. Determine the desired range. For the standard ranges listed in Table 3-5, use the plug-in resistors as shown. To use a nonstandard range, refer to the following discussion of resistor selection. When the plug-in resistors are changed, it may be necessary to re-calibrate the card, as described below: Table 3-5. QAA G02 Analog Position Input Circuit Plug-in Resistor Selection Position Signal Range 1V to 5V

R16

45.3K 0.1W 0.1% 499K 0.25W 1% 669A664H53 406A069549

-10V to 10V 5K 0.1W 0.1% 669A664H08

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R26

R27

R28

200K 0.1W 0.1% 669A664H13

–

499K 0.25W 1% 406A069549

–


20K 0.1W 0.1% 669A664H10

Jumpers Used J2 or J3 J2 or J3

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3-2. QAA

Table 3-5. QAA G02 Analog Position Input Circuit Plug-in Resistor Selection Position Signal Range

R16

R26

R27

R28

Jumpers Used

0 to 10V

15K 0.1W 0.1% 669A664H44

–

–

–

–

0 to 8V

20K 0.1W 0.1% 669A664H10

–

–

–

–

4 to 20 mA

45.3K 0.1W 0.1% 499K 0.25W 1% 669A664H53 406A069549

200K 0.1W 0.1% 669A664H13

–

JE, J2 or J3

Resistor Selection for Non-Standard Position Signal Ranges The DBK card position feedback input circuit has the ability to convert a number of different input voltage or current values to a common 0 to -10 V range. The conversion is scaled based on the values of three zero bias resistors (R26, R27, and R28) and one gain resistor (R16). To select a non-standard position signal range, it is necessary to calculate the values for these resistors. Note the following definitions: VFB(0%) = Zero percent of span position feedback voltage, where -10 V <

VFB(0%) < 2.5 V. VFB(100%) = One hundred percent of span position feedback voltage Span = VFB(100%) - VFB(0%), where 3.5 V < Span < 20 V

If a current position feedback signal (IFB) is used, IFB is converted into an equivalent voltage VFB, where: IFB maximum = 20mA VFB = IFB * 250 Ω

Note that jumper JE must be inserted to use a current position signal. When the zero bias and gain resistors are calculated, three cases may occur:

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•

Case 1: VFB(0%) = 0 V In this case, resistors R26, R27, and R28 are not required.

•

Case 2: VFB(0%) < 0 V


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3-2. QAA

R26 = 499 kΩ R27 is not used

10 V * 20 kΩ V FB ( 0% )

R28 = – ----------------------------------

•

Case 3: VFB(0%) > 0 V R26 = 499 kΩ

10 V * 20 kΩ V FB ( 0% )

R27 = ----------------------------------

R28 is not used.

For all three cases, R16 must meet the following conditions: 10 V * 20 kΩ Span

R16 < ---------------------------------- - 4.02 kΩ

10 V * 20 kΩ Span

R16 + 2 kΩ > ---------------------------------- - 4.02 kΩ

Ideally, the value of R16 should be as shown below: 10 V * 20 kΩ Span

R16 = ---------------------------------- - 5.02 kΩ

The zero bias and gain may be fine tuned using the following calibration procedures. Calibration of G02 QAA (DBK) The G02 QAA is factory-shipped with the appropriate plug-in resistors for a 4 to 20 mA position signal range. If the resistors are changed to select a new range (as described above), it may be necessary to re-calibrate the card, using the following procedure (see Figure 3-11 for component locations). To set-up the card for calibration, install the QAA card using the QEX extension card, and connect the QAA J2 to the special card-edge connector. Connect pin 21B to the positive output terminal of the precision power supply: connect pin 20B to the negative output terminal; then turn the precision power supply on.

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3-2. QAA

The VFB(0%) of the new position feedback voltage range equals 0 V, then no zero bias adjustment is required. If VFB(0%) does not equal 0 V, then the amount of zero bias should be adjusted using potentiometer VR4 and jumper J2 or J3, as described below: 1. Adjust the output voltage of the precision power supply to equal VFB(0%) + 0.1 mV. Use the digital voltmeter to verify the power supply output voltage. 2. Connect the positive lead of the digital voltmeter to test point TP4, and connect the negative lead to test point TP13. 3. Adjust potentiometer VR4 until the voltage displayed on the voltmeter equals 0 V + 0.5 mV. If the voltage cannot be adjusted to within this range, move jumper JU3 from the J2 position to the J3 position. Once the voltage is within range, leave this jumper in the selected position. The amount of gain may be adjusted using potentiometer VR3, as described below: 1. Adjust the output of the precision power supply to equal VFB(100%) + 0.3 mV. Use the digital voltmeter to verify the power supply output voltage. 2. Connect the positive lead of the digital voltmeter to test point TP4, and connect the negative lead to test point TP13. 3. Adjust potentiometer VR3 until the voltmeter displayed on the voltmeter equals -10 V + 2 mV.

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3-2. QAA

Adjusting Positioning Accuracy of G01 QAA (DWC Daughter Board) The positioning accuracy of the G01 QAA may be adjusted using potentiometers VR8 (Negative Small Error Band), VR9 (Positive Small Error Band), VR10 (Positive Large Error Band), and VR11 (Negative Large Error Band). Test points TP9, TP10, TP11, and TP12 may be used to verify the adjustments. The usable Large Error Band adjustment range is as follows: + 1% to + 10% of span OR + 0.5V to + 5V

The usable Small Error Band adjustment range is as follows: + 0.15% to + 2% of span OR + 75mV to + 1V

Adjusting Positioning Accuracy of G02 QAA (DBK Daughter Board) The positioning accuracy of the G02 QAA may be adjusted using potentiometers VR8 (Negative Small Error Band), VR9 (Positive Small Error Band), VR10 (Positive Large Error Band), and VR11 (Negative Large Error Band). Test points TP7, TP8, TP9, and TP10 may be used to verify the adjustments. The usable Large Error Band adjustment range is as follows: + 3% to + 19.7% of span OR + 1.5V to + 9.85V

For example, a large error deadband of approximately 5% of span is represented by a measured voltage of -2.5V at test point TP9 and 2.5V at test point TP10. The usable Small Error Band adjustment range is as follows: + 0.3% to + 5% of span OR + 0.15V to + 2.5V

For example, a small error deadband of approximately 1% of span is represented by a measured voltage of 0.5V at test point TP7 and -0.5V at test point TP8.

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3-2. QAA

Adjusting Half-Speed and Quarter-Speed Clocks (G02 Only) On the G02 QAA, two variable duty clocks are provided to allow operation of the actuator at reduced speeds. Two plug-in resistors (R59 and R60) are used to select OFF and ON time values (respectively) for the medium speed clock (called the “Half-speed” clock). The low speed (or “Quarter-speed”) clock is synchronized with the medium speed clock. A potentiometer (VR12) may be used to adjust the pulse width of the second clock, to provide a lower speed. To adjust the Half-speed and Quarter-speed clocks, use the following procedure: 1. Set up the QAA on the QEX extender card, as described above. Use a strip chart recorder to monitor the voltages on TP11 and TP12. 2. Determine the desired ON and OFF time values for the Half-speed clock. Refer to Table 3-6 and select the appropriate resistors for R59 and R60 (49.9 kΩ resistors are factory-installed). Install the selected resistors (see Figure 3-12) for component locations). 3. Check test point TP11 voltage waveform to verify the Half-speed clock on and off times. 4. Adjust potentiometer VR12 to achieve the desired pulse width for the Quarter-speed clock. Note that if VR12 is adjusted clockwise to its limit, the Quarter-speed clock’s output pulse will match that of the Half-speed clock. As VR12 is adjusted counterclockwise, the ON time of the Quarter-speed clock is reduced. 5. Check test point TP12 to verify the Quarter-speed clock on and off times. Table 3-6. QAA Half-Speed Clock On and Off Time Selection Resistor

On-Time

R60

On-time (seconds)

R59

Off-Time

Off-time (seconds)

10K

0.12

0.12

20K

.24

.24

49.9K

.6

.6

100K

1.2

1.2

200K

2.4

2.4

499K

5.9

5.9

R59 and R60 are 0.25W 1% metal film (406A069) resistors whose values may vary from 10K to 499K. 49.9K resistors are supplied in the R59 and R60 locations on the standard G02 QAA’s DBK daughter card.

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3-2. QAA

Adjusting High and Low Limit (G02 Only) The Low and High Limit of the G02 QAA (DBK) may be adjusted using potentiometers VR6 and VR7.

•

The nominal High Limit adjustment range is from 94% (-4.7V) to 103.2% (-5.16V) of span.

•

The nominal Low Limit adjustment range is from -2% (+0.1V) to 7.3% (-0.365V) of span.

The card is factory-shipped with the limits set at -1% and 101% of span (test points TP5 = -5.05V, TP6 = +0.05V. If a different range is desired, use the following procedure: 1. Adjust VR6 to change the High Limit, if desired. 2. Check test point TP5 voltage. 3. Adjust VR7 to change the Low Limit, if desired. 4. Check test point TP6 voltage.

Note The test point TP5 or TP6 voltages multiplied by (-20%) equals the High Limit and Low Limit settings respectively as a percentage of the input position feedback span.

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3-2. QAA

The operations possible in each mode are summarized in Table 3-7. Table 3-7. QAA Card Operation Table QAA DIOB Status Bits State

COMPUTER/LMAN LOW LIMIT HIGH LIMIT QAA ALIVE QAA HEALTHY Possible DIOB Operations

READ DEMAND WORD WRITE DEMAND WORD TO CONTROL DRIVE POSITION READ DRIVE POSITION READ STATUS BITS WRITE KEEP ALIVE LMAN REQUEST PRIORITY COMMAND RESET ACTUATOR Possible OIM Operations

COMP MODE REQUEST LMAN MODE REQUEST RAISE/LOWER OUTPUT

COMP

Mode LMAN

LMNA

1 1/0 1/0 1 1

0 1/0 1/0 1 1

0 1/0 1/0 1/0 1/03

COMP

LMAN

LMNA

Y Y

Y N1

Y N

Y Y Y Y N –

Y Y Y −2 N/Y4 –

Y Y Y N N Y/N5

COMP

LMAN

LMNA

−2

Y5

Y N

−

N N Y/N7

2

Y8

Notes 1. 2. 3. 4. 5. 6. 7. 8.

A QAA Card option is available (via a plug-in jumper) that allows the data in the QAA Card’s Demand Register to control the card’s output while it is in LMAN mode. New values of data may be written into the Demand Register in order to change the position of the actuator. See also Note 4. It has no effect while the QAA Card is in the present mode. If the QAA HEALTHY bit is reset, the card is rejected to LMNA mode. For the card option described in Note 1 to be available, a plug-in jumper must be inserted onto the card and the PRIORITY COMMAND bit must be set. The UIOB/DIOB controller must have previously written a COMP. MODE PERMIT bit into the Command Register. The QAA ALIVE bit must be set in order to permit the actuator to be reset via a DIOB command bit. For the OIM RAISE/LOWER inputs to be operative while the QAA Card is in LMNA mode, the actuator power must be available. The OIM RAISE/LOWER inputs are ignored if the PRIORITY COMMAND bit is set and the option discussed in Notes 1 and 4 is selected.

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3-2. QAA

Light Emitting Diodes QAA (7379A91) Table 3-8. QAA LEDs

Group 1

Group 2

POWER-OK

POWER-OK

ACTUATOR ALIVE

ACTUATOR ALIVE

INCREASE

INCREASE

DECREASE

DECREASE

Potentiometers Table 3-9. QAA Potentiometers (Daughter Board) Group 1 DWC (7380A66)

Group 2 DBK (7380A67)

VR1

DEMAND GAIN

DEMAND GAIN

VR2

ADC VOLTAGE REFERENCE ADJ.

ADC VOLTAGE REFERENCE ADJ.

VR3

VELOCITY DAMPING

POSITION GAIN

VR4

POSITION BIAS

POSITION BIAS

VR5

POSITION GAIN

POSITION FEEDBACK GAIN

VR6

POSITIVE PLUG BRAKE DEADBAND

HIGH LIMIT ADJUST

VR7

NEGATIVE PLUG BRAKE DEADBAND

LOW LIMIT ADJUST

VR8

NEGATIVE SMALL ERROR BAND


VR9

POSITIVE SMALL ERROR BAND


VR10 POSITION FEEDBACK GAIN

POSITIVE LARGE ERROR BAND

VR11 POSITIVE LARGE ERROR BAND

NEGATIVE LARGE ERROR BAND

VR12 NEGATIVE LARGE ERROR BAND

QUARTER SPEED CLOCK DUTY CYCLE ADJUST

VR1* -

EIGHT VOLT SUPPLY OUTPUT ADJ.

* located on 7379A91 mother board

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3-2. QAA

Test Points Table 3-10. QAA Test Points (Daughter Board) Group 1 DWC (7380A66) Test Points

Group 2 DBK (7380A67) Test Points

TP1

MINUS VELOCITY

MINUS ERROR TIMES FIVE

TP2

MINUS ERROR TIMES FIVE

POSITION VOLTAGE

TP3

POSITION VOLTAGE

DEMAND

TP4

DEMAND

MINUS POSITION

TP5

VELOCITY DAMPING

HIGH LIMIT

TP6

MINUS POSITION

LOW LIMIT

TP7

POSITIVE PLUG BRAKE DEADBAND


TP8

NEGATIVE PLUG BRAKE DEADBAND


TP9



TP10



TP11


HALF SPEED CLOCK

TP12


QUARTER SPEED CLOCK

TP13

ANALOG COMMON

ANALOG COMMON

TP14

ANALOG COMMON

-

TP1*

AOK

AOK

TP2*

POWER-UP

POWER-UP

TP3*

+5.9V (TP3)

+5.9V (TP3)

* located on 7379A91 mother board

Plug-In Jumpers

JA (Both Groups) QAA (7379A91) When this jumper is connected to test points JS2 and JS3, the PRIORITY COMMAND option is available. If the PRIORITY COMMAND option is not used, the jumper is moved so that it connects test points JS1 and JS2.

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3-2. QAA

JD (Group Two) QAA (7379A91) When this jumper is connected to test points JS7 and JS8, the QAA card will operate the actuator at a fraction of the nominal velocity. This is accomplished by controlling the DIM outputs, INCREASE and DECREASE, with the plus train output of the HALF SPEED CLOCK circuit. This option is only effective while the QAA card is in LMAN mode. Connecting the jumper to test points JS6 and JS7 disables this option. The INCREASE and DECREASE DIM outputs will then operate at a 100 percent duty cycle when they are activated (LMAN mode).

JE (Group Two) DBK (7380A67) Out – Selects voltage position feedback In – Selects 4 to 20 mA position feedback

Watchdog Timer Period Selection (Both Groups) QAA (7379A91) JA1 Jumper

Nominal Timer Period

Pin 3 to Pin 6

2.0 seconds

Pin 2 to Pin 7

0.5 seconds

Pin 1 to Pin 8

Timer disabled

JF (Both Groups) QAA (7379A91) This jumper is not included on the board if the voltage supplied to pin 1B and/or pin 2B of the J2 connector is between 22.0 and 27.0 V. If the voltage supplied to pin 1B and/or 2B is between 12.4 and 13.1 V, jumper JF is inserted onto the board between test points JS4 and JS5 on the mother board. Warning Verify the JF jumper setting prior to tuning or installing a QAA card. Failure to perform this check may result in damage to the QAA card.

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3-2. QAA

J2 and J3 (Group Two) DBK (7380A67) These jumpers are used to provide different bias voltages for the position voltage gain and bias stage. Their use is dependent on the particular position voltage range that is used. DIOB Power Supply Requirements

• • •

Primary: 12.4 to 13.1 VDC, 13.0 VDC nominal Backup: 12.4 to 13.1 VDC Current: 500 mA maximum

G02 QAA Slidewire Power Supply

• •

Output Voltage: 8.0V ±0.1V, user adjustable Output Current: 16 mA nominal for a 500-ohm load

External Power Supply Limits

•

G01 WEMAC Primary:

22.5 VDC Minimum 27.0 VDC Maximum

•

G01 WEMAC Backup:

22.5 VDC Minimum 27.0 VDC Maximum

•

G02 Beck Primary and Backup: Low Voltage+12.4 VDC Minimum 13.1 VDC Maximum

High Voltage+22.0 VDC Minimum 27.0 VDC Maximum

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3-3. QAC

3-3. QAC Analog Conditioning Card (Style 2840A86G01 through G06)

3-3.1. Description The primary QAC function is as an analog signal conditioner. Additionally some signal switching is provided for online testing. Automatic test versions can be used in conjunction with other Q-line cards (such as, QAI and QMD). These test versions select either process data signal inputs or test data signal inputs for a Q-line system. There are four analog points on the QAC card. Each analog point has one field contact connection, two internal contact connections which may receive input data or test data, and one field output connection. A test signal may be injected to verify operation of succeeding logic stages. Six QAC groups are available.

Block Diagram

Figure 3-13. QAC Block Diagram

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3-3. QAC

Circuit Description Functional block diagrams of the QAC groups are shown in Figure 3-14 through Figure 3-17.

FRONT CARD EDGE CONNECTOR (J2) +48 V G02

DIOB

+12 V

TO SIMILAR CIRCUITS AS SHOWN BELOW

24/48 V CHOPPER (G01 ONLY)

VOLTAGE REGULATOR AND CURRENT LIMITING I

TO THREE OTHER CIRCUITS

LATCH

DATA

ROUT (PLUGGABLE)

4 TO 20 mA

250 Ω I

TRANSMITTER K1

+ K1 −

K1

TEST INPUT FROM QAO

UNIT (RESET)

+

STROBE

−

8

COMPARE

ADDRESS

TEST PERMIT

+ −

0 TO 10 V OUTPUT

I 8

CONTACT

JUMPER

FRONT CONNECTOR JUMPER ARRANGEMENT

+12 V

EITHER OPTION MAY BE USED

Figure 3-14. QAC Block Diagram (Groups 1 and 2)

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3-3. QAC

JUMPER

+ +12

DIOB

CONTACT

DATA

LATCH

LATCH

CMOS SUPPLY

UNIT (RESET)

TO THREE OTHER CIRCUITS

TEST PERMIT

K1

NORMAL INPUT

K1

TEST INPUT

TEST

OUTPUT

STROBE

8

COMPARE

ADDRESS

K1

FRONT CARD EDGE CONNECTOR (J2)

8

FRONT CONNECTOR JUMPER ARRANGEMENT

Figure 3-15. QAC Block Diagram (Group 3)

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3-3. QAC

DIOB TO THREE OTHER CIRCUITS +24/48 V CHOPPER ROUT

TRANSMITTER

I 4 TO 20 mA

250 Ω VOLTAGE REGULATORS AND CURRENT LIMITERS

I −

NOTE

+

TO QAI

NO ADDRESS SPACE IS REQUIRED. G04 DOES NOT ADD TO THE 48 CARD LIMIT SPECIFIED FOR THE UIOB.


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3-3. QAC

DIOB

+48 V.D.C. 48 VOLTS CHOPPER

I

I


DIOB TO THREE OTHER CIRCUITS +24/48 V CHOPPER ROUT

TRANSMITTER

(PLUG SELECTABLE)

VOLTAGE REGULATORS AND CURRENT LIMITERS

4 TO 20 mA

250 Ω

+ 10 V PLUGGABLE

0 - 10 V OUTPUT

10 V


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3-3. QAC

3-3.2. Features

•

G01 provides one internal transmitter power supply with four current-limited voltage regulators (40 to 24 V). Four amplifiers convert a loop current of 4 to 20 mA to a corresponding output voltage of 0 to 10 VDC. Test relays are available to switch the field input off, and inject a test input from a QAO.

•

G02 converts two +48 VDC external power supplies (auctioneered) to 24 or 40 V transmitter supplies. Four amplifiers convert a loop current of 4 to 20 mA to a corresponding output voltage of 0 to 10 VDC. Test relays are available to switch the field inputs off and inject a test input from a QAO.

•

G03 provides four DIOB-controlled DPDT, signal selectors for relaying RS-232C and controls or other low-current signals (less than 50 mA).

•

G04 provides one internal transmitter power supply with four current-limited voltage regulators (24 or 40 V). Four amplifier outputs convert a loop current of 4 to 20 mA to a corresponding output voltage of 1 to 5 VDC. The outputs may be directly connected to a high impedance (1.0 megaohm or more) analog input card (such as., QAI). There is no test provision.

•

G05 provides one on-card +48 VDC power supply which supplies contact wetting voltage for up to ten QPA, QBI,QDI, or QID field inputs.

•

G06 provides one on-card power supply with four current limited voltage regulators. Both the 1.00 to 5.00 volt signals obtained from the 4-20 mA loop currents via 250 Ω resistors and the two proportional 0-10 volt outputs of the card on-card amplifiers are available at the card edge.

3-3.3. Specifications Inputs/Outputs DIOB Input Requirements Logic 0: 0 V to 3 V Logic 1: 7 V to 12 V Table 3-11. QAC Output Capabilities Group

Specification

G01:

0 V to 10 VDC, 4 mA to 20 mA at 24 or 40 VDC

G02:

0 V to 10 VDC,4 mA to 20 mA at 24 or 40 VDC

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3-3. QAC

Table 3-11. QAC Output Capabilities Group

Specification

G03:

Signal Switching

G04:

1 V to 5 VDC, 4 mA to 20 mA at 24 or 40 VDC

G05:

120 mA at +48 VDC

G06:

0 V to 10 VDC

Output Buffer Specifications (G01 and G02 only) Accuracy: 0.2 percent (additive to a QAI with a 0 to 10 V span) Load Resistance: 4 k Ω (minimum) Temperature Coefficient: 40 PPM/°C Signal Switching (G03 Only) Form C Reed Relay Contacts Voltage: 50 VDC (maximum) Current: 50 mA (maximum) Operate Time: 7 msec (maximum) Release Time: 7 msec (maximum) Relay Coil Voltage: 12 VDC nominal Current: 310 mA (four relays energized simultaneously) Power Supply Primary: 12.4 VDC to 13.1 VDC (13 VDC typical) Backup: 12.4 VDC to 13.1 VDC Current:

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G01 – 1750 mA (maximum) G02 – 675 mA (maximum) G03 – 400 mA (maximum) G04 – 1000 mA (maximum) G05 – 1000 mA (maximum) G06 – 1500 mA (maximum)


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3-3. QAC

Transmitter Power Supply Voltage: 40 V + 2.0 VDC (jumper selected) 24 V + 2.0 VDC (jumper selected) Current: 4 mA to 20 mA (nominal) 30 mA + 7 mA (short-circuit limit) Impedance: 25.0 + 10 Ω (output) Space is provided on the card for insertion of a resister (up to 1 W), for additional loop impedance.

3-3.4. Card Addressing The QAC card uses eight address lines, four data lines, and four DIOB control lines. The first step in QAC operation involves the QAC address lines.

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3-3. QAC

The address lines (UADD0 through UADD7) enter the QAC card via the rear-edge connector. The address available on the DIOB is compared to the address which is physically jumpered in on the front, card-edge connector. The QAC address is selected by eight jumpers on the top, front, card-edge connector. Insertion of a jumper encodes a 1 in the address line; absence of the jumper encodes a 0 in the address line. The jumpered address lines and the DIOB address lines are exclusive OR’d. This configuration gates the compared addresses and outputs an AOK signal from pin 13 (W319-1) if the address jumpers are opposite the DIOB address. This allows ground potential to appear at the front, card-edge connector instead of a voltage. Once the QAC determines it has been addressed, the address circuitry outputs the AOK signal and four data bits are latched onto the QAC. An address selection example is shown in Figure 3-19.

FRONT CONNECTOR 404A037

A7 = 0 JUMPER: A6 = 1 A5 = 0 A4 = 0 JUMPER: A3 = 1

CARD ADDRESS = 01001001 (49H)

A2 = 0 A1 = 0 JUMPER: A0 = 1

Figure 3-19. QAC Address Jumper Assembly

Connectors and Terminations The QAC card interfaces the DIOB via a standard DIOB, rear, card-edge connector. The analog outputs are brought out to the front, card-edge connector (J2). Table 3-12 lists the contact allocations for G01 and G02. Table 3-13 through Table 3-15 list the contact allocations for G03, G04, and G05, respectively. The QAC card connectors and test points are shown in Figure 3-20.

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3-3. QAC

Table 3-12. QAC G01 and G02 Contact Allocations Point 0

Point 1

Point 2

Point 3

0 to 10 V QAI Signal

Positive Negative Shield

5A 3A 3B

9A 7A 7B

13A 11A 11B

17A 15A 15B

Transmitter Loop

Out Return

2B 2A

6B 6A

10B 10A

14B 14A

Test Input

Positive Negative

5B 4B

9B 8B

13B 12B

17B 16B

Power

Primary +48 V Backup +48 V +12V TEST PERMIT 48V RETURN

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19A G02 only 19B 20A Jumpered 20B 1A and 1B – G02 only

} }


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3-3. QAC

Table 3-13. QAC G03 Contact Allocations Point 0

Point 1

Point 2

Point 3

Normal Input (Normally Closed)

Positive Negative

2A 2B

6A 6B

10A 10B

14A 14B

Test Input (Normally Open)

Positive Negative

5B 4A

9B 8B

13B 12A

17B 16A

Output (Armature)


5A 3A 3B

9A 7A 7B

13A 11A 11B

17A 15A 15B

Power

+12V TEST PERMIT

}

Jumpered

20A 20B

19A, 19B 1A, 1B

}

No Connection


Point 1

Point 2

Point 3

Transmitter Loop

Out Return

2B 2A

6B 6A

10B 10A

14B 14A

Output


5A 3A 3B

9A 7A 7B

13A 11A 11B

17A 15A 15B

No Connections

1A, 1B, 19A, 19B, 20A, 20B

Table 3-15. QAC G05 Contact Allocations

Power Supply

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+48V

19A, 19B

+48V Return

1A, 1B


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3-3. QAC


Point 1

Point 2

Point 3

0 - 10 V Signal


5A 3A 3B

9A 7A 7B

13A 11A 11B

17A 15A 15B

Transmitter Loop

Out Return

2B 2A

6B 6B

10B 10A

14B 14A

1.0 - 5.0 V Signal

Plus Minus

5B 4B

9B 8B

13B 12B

17B 16B

Power

+12V auctioneered, fused TEST PERMIT

20A 20B

+48 Backup +48 Backup

}

Jumpered 19A 19 B

3-3.5. Controls and Indicators LED G01-6 LED G01-3

Test Points G01-4, 6

LEDs G01,2,3

Figure 3-20. QAC Card Components (Indicators and test Points)

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3-4. QAH

3-4. QAH High Speed Analog Input Point (Style 7379A36G01 through G04)

3-4.1. Description Groups 01, 02, 03, 04, are applicable for use in the CE MARK Certified System The QAH card is a high-speed, A/D converter which interfaces to the DIOB in process control systems. The QAH card processes up to eight high level differential inputs from the field process points in the plant environment. Each bipolar input is converted to a 16-bit digital value and stored in RAM. The analog signal value (11 bits), a polarity bit, an overrange bit, and a system-in-operation bit and one unused bit comprise the 16-bit digital value. This stored data is multiplexed via the DIOB to the DIOB controller when the QAH is addressed.

DIOB DATA

Address

Address Selection and Control

RAM Memory

Optical Isolation

A/D Converter Analog MUX

Signal Conditioning

0

...

7

From Process Field Points

Figure 3-21. QAH Block Diagram

3-4.2. Features The QAH card is available in four groups (G01 through G04), providing several analog input ranges. The QAH card offers the following features:

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3-4. QAH

• • • • • • •

Two jumper-selectable modes of operation. Continual input scanning and RAM updating 0.64 msec scan rate for all groups. Jumper-selectable zero checking and + and − full scale checking for both bipolar and unipolar operation. Isolated on-card power supplied. Analog/digital isolation. IEEE surge withstand protection on input circuits.

The QAH card multiplexes eight high-level differential inputs to a high-speed, successive approximation, A/D converter. Optical and transformer isolation separates the analog section from the digital and/or DIOB interface section (see Figure 3-21). The input point scan period is 0.64 msec. Scan rates can be increased by truncating the number of points per card to be scanned. One, two, four, or eight points can be scanned by the QAH card. The scan rate approximately doubles for each truncation step. The QAH has two jumper-select modes of scan: “Continuous Scan” and “Scan and Hold.” In the “scan and hold” mode, a scan can be initiated in two ways. The first method is to write to the normal DIOB address of the QAH. The second method uses a group write address which triggers a group of QAH cards to provide simultaneous data snapshots.

3-4.3. Specifications Power Requirements

• • •

M0-0053

Primary: 12.4 to 13.1 VDC Secondary: 12.4 to 13.1 VDC Current: 800mA Maximum


5/99

3-4. QAH

0.3 µs (min.) 10 µs (max.)

Input Filter Time Constant:

DC Common Mode Rejection: 60dB DC Input Impedance: 5 megohm at full scale. Sustained overrange input: 30 V relative to analog common. Source Impedance: 200 Ω max. Overrange input impedance: 2,000 Ω min. Input Range (Volts)

Common Mode Range

Span (Volts)

(Typ.) Volts/Step

G01: −10.240 to +10.235

±1.76 V

20.475

5.0 mV

G02: −5.120 to +5.1175

±6V

10.2375

2.5 mV

G03: 0 to +10.2375

± 1.76 V

10.2375

2.5 mV

G04: 0 to +5.11875

±6V

5.11875

1.25 mV

Isolation: Analog common to DIOB common: 500 V max. The analog common will withstand the IEEE surge waveform applied with respect to the DIOB common without damage to the QAH card. Note All QAH data is invalid until another complete scan has been made after the surge waveform is removed. A block diagram of the QAH is shown in Figure 3-22.

5/99


M0-0053

3-4. QAH

Inputs and Outputs The QAH input consists of eight differential inputs which are multiplexed to a high speed A/D converter. This analog section is isolated from the digital and DIOB interface section. The isolation is transformer-type for power and optical-type for data. Each input contains an RLC filter with a time constant of approximately 1 microsecond and a clamp. This circuit allows the inputs to withstand the IEEE surge without damage. To increase the scan rate for the continuous scan operating modes, the input points can be truncated to only scan 1, 2, or 4 points. The scan rate is doubled for each truncated step. See Table 3-17. Table 3-17. QAH Conversion Scan Time

Number of Points

G01, 2, 3, 4

8

640 µsec

4

320 µsec

2

160 µsec

1

80 µsec

Input DC Accuracy Reference accuracy: ± 0.1% of span ± 1/2 LSB at 99.7% confidence. Temperature coefficient: 40 ppm/°C of 20.475 V span 45 ppm/°C of 10.2375 V span 50 ppm/°C of 5.11875 V span Linearity: 0.05% of span Reference condition:25°C temperature, +13 VDC power supply, 0 V common mode

M0-0053


5/99

DATA MULTIPLEXER LATCH CHANNEL

ADDRESS COUNTER STATUS

ANALOG COMMON

INPUT CONTROL SIGNAL (−)

SIGNAL (+)

MEMORY ADDRESS

DIOB DATA

CLOCK

CONV

A/D CONVERTER

DATA

CLOCK

SERIALPARALLEL CONVERTER

CLOCK AND CONTROL CIRCUITRY

(R/W)

2:1 DATA MULTIPLEXER

RAM

DIOB ADDRESS

READ/ SCAN INITIATE SCAN/HOLD

SCAN CONTROLLER POWER SUPPLY TYPICAL INPUT

ADDRESS

3-4. QAH

Figure 3-22. QAH Card Functional Block Diagram

3-4.4. Card Addressing and Data Output Address Jumpers The QAH card address is established by five jumper fixtures which are located in the front-edge connector. The insertion of a jumper encodes a “1” on the selected address line (ADD3 through ADD7) which when matched by the UIOB or DIOB address signals selects the QAH card by the system controller.

5/99


M0-0053

3-4. QAH

The optional group address for the QAH card is established by three jumpers on the front-edge connector. Figure 3-23 shows the pin configuration of the front-edge connector. The “B” pins of the connector are located on the component side and the “A” pins are located on the solder side of the p-c card. Field Input Connections The QAH card uses a standard Q-series front edge connector. Eight pairs of contacts exist for the eight analog input points. One contact is for the signal (+) and the second is for its return (−). See Figure 3-23. The analog common is also brought out with the field inputs. This analog common should be tied to the system ground or earth ground. Output Data There are two status bits: overrange and system operational. The overrange bit is determined by a digital comparison of the most positive or most negative conversion results. If the input is overrange, the conversion result is the most positive or most negative result. In the scan mode, the system operational bit is high if the converter is operating. In the scan and hold mode, the system operational bit goes high during the first point conversion and stays high for at least ten milliseconds after the end of the scan. QAH word formats are shown in Figure 3-24.

M0-0053


5/99

3-4. QAH

Solder Side

Point 0 + Input

Point 1 + Input

Point 2 + Input

Point 3 + Input

Point 4 + Input

Point 5 + Input

Point 6 + Input

Point 7 + Input

Component Side

1A

1B

2A

2B

3A

3B

4A

4B

5A

5B

6A

6B

7A

7B

8A

8B

9A

9B

10A

10B

11A

11B

12A

12B

13A

13B

14A

14B

15A

15B

16A

16B

17A

17B

18A

18B

Point 0 – Input

Point 1 – Input

Point 2 – Input

Point 3 – Input

Point 4 – Input

Point 5 – Input

Point 6 – Input

Point 7 – Input

Analog Common

19A

19B

Group Address Line S0 Common

20A

20B

Group Address Line S0


21A

21B



22A

22B


23A

23B

Address Line A3 Common

24A

24B

Address Line A3


25A

25B

Address Line A4


26A

26B

Address Line A5


27A

27B

Address Line A6


28A

28B

Address Line A7

Analog Common

Figure 3-23. QAH Card Front-Edge Connector Pin Assignments

BINARY

xx

xxxx

xxxx

x0

BIPOLAR

} Card OK

SIGN

Overrange Not Used

0xxx

xxxx

xxxx

x0

UNIPOLAR Card OK Overrange Not Used

Figure 3-24. QAH Word Formats

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M0-0053

3-4. QAH

A bipolar conversion produces a 12-bit 2’s complement result (11 bits plus sign). This number is left justified minus one with an extended sign in the MSB. See Table 3-18 Table 3-18. QAH Bipolar Conversion Dataword High Byte

Low Byte

XXXX XXXX XXXX X0XX Extended Sign Sign

System Operational

2’s Complement Conversion

Overrange

G01 Input

G02 Input

Result

+10.235 V +10.230 V 0.0 V -10.235 V −10.240 V −0.005 V

+5.1175 V +5.115 V 0.0 V −5.1175 V −5.120 V −0.0025 V

3FFB 3FF1 0001 C009 C003 FFF9

A unipolar conversion produces a 12-bit binary result. This number is left justified minus one with the MSB set to 0. See Table 3-19. Table 3-19. QAH Unipolar Conversion Dataword Low Byte

High Byte

0XXX XXXX XXXX X0XX System Operational

Binary Conversion

Overrange

M0-0053

G03 Input

G04 Input

Result

+10.2375 V

+5.11875 V

7FFB

+10.235 V

+5.1175 V

7FF1

+0.0025 V

+0.00125 V

0009

0.0 V

0.0 V

0003


5/99

3-4. QAH

3-4.5. Controls and Indicators The QAH normally scans eight input points. By positioning three jumpers, the scan can be optionally truncated to one, two or four input points. Truncating the scan will increase the scan rate of the input points (see Figure 3-25 and Table 3-20).

PS Osc (Pin 8)

Clock Adjust

Jumpers

W339

Span

PS Osc Adj

Common Mode Null Positive

Common Mode Null Negative

+16.5 ADJ +16.5 VDC

TP6 TP5

TP7

-16.5 ADJ Clock (Pin 8)

Span

VC Output

VC Zero Offset Adj

Jumper Detail

8

14

-16.5 VDC

2

4

S

/H S/H S/H

1

7

1

Figure 3-25. QAH Card Components

Jumper Settings Two operating modes: Continuous and Scan and Hold are set by inserting various jumpers in the sockets shown in Figure 3-25. The jumpers control either which points are scanned or set a scan and hold for all points. The Continuous scan mode the RAM is continuously updated (see Figure 3-21). In the scan-and-hold mode, the data is only written on command. The scan rate for the eight points for Groups 1, 2, 3 and 4 is 0.64 milliseconds per point. When the data is read from the card, the low byte must be read first and the high byte must be read within 2 milliseconds of the low byte.

5/99


M0-0053

3-4. QAH

Table 3-20. QAH Option Jumpers

QAH Operating Mode

Pins Jumpered

Continuous Scan: Points 0, 1, 2, 3, 4, 5, 6,7

None

Continuous Scan: Points 0, 1, 2, 3

3 - 12

Continuous Scan: Points 0, 1

2 - 13

Continuous Scan: Point 0

1 - 14

Scan-and-hold Points 0, 1, 2, 3, 4, 5, 6,7

M0-0053

5 - 10, 6 -9, 7 - 8 (All S/H jumpers in place).


5/99

3-4. QAH

3-4.6. Installation Data Sheet 1 of 2

REQUIRED ENABLE JUMPER

TERMINAL BLOCK

HALF SHELL EXTENSION (B-BLOCK)

20B

CARD

20A ANALOG COMMON

POINT 7

POINT 6

POINT 5

POINT 4

POINT 3

POINT 2

POINT 1

POINT 0

19B

A

COMMON*

19A

18

(−)

17B

17

(−)

(+)

17A

16

(+)

(−)

15B

15

(−)

(+)

15A

14

(+)

(−)

13B

13

(−)

(+)

13A

12

(+)

(−)

11B

11

(−)

(+)

11A

10

(+)

(−)

9B

09

(−)

(+)

9A

08

(+)

(−)

7B

07

(−)

(+)

7A

06

(+)

(−)

5B

05

(−)

(+)

5A

04

(+)

(−)

3B

03

(−)

(+)

3A

02

1B

01

B 18

(+)

17 POINT 7

16 15

POINT 6

14 13

POINT 5

12 11

POINT 4

10 09

POINT 3

08 07

POINT 2

06 05

POINT 1

04 03

POINT 0

INTERNAL BUS STRIP

02 01

1A

EDGE-CONNECTOR

CUSTOMER CONNECTIONS

* Common is connected to system ground at one point only. Analog common used for all eight points.

Figure 3-26. QAH Wiring Diagram

5/99


M0-0053

3-4. QAH

For CE MARK Certified System 2 of 2

CARD

POINT 0

POINT 1

POINT 2

POINT 3

POINT 4

POINT 5

POINT 6

POINT 7

A

1A

A

1B

1

01

01

1

+

3A

2

02

02

2

+

-

3B

3

03

03

3

-

+

5A

4

04

04

4

+

-

5B

5

05

05

5

-

+

7A

6

06

06

6

+

-

7B

7

07

07

7

-

+

9A

8

08

08

8

+

-

9B

9

09

09

9

-

+

11A

10

10

10

10

+

-

11B

11

11

11

11

-

+

13A

12

12

12

12

+

-

13B

13

13

13

13

-

+

15A

14

14

14

14

+

-

15B

15

15

15

15

-

+

17A

16

16

16

16

+

-

17B

17

17

17

17

-

19A

18

18

18

PE

PE

ANALOG COMMON

B

19B

COMMON*

POINT 0

POINT 1

POINT 2

POINT 3

POINT 4

POINT 5

POINT 6

POINT 7

18

COMPRESSION-STYLE TERMINAL BLOCK EDGE-CONNECTOR

* Common is connected to system ground at one point only. Analog common used for all eight points.

Figure 3-27. QAH CE MARK Wiring Diagram

M0-0053


5/99

3-5. QAI

3-5. QAI Analog Input Card (Style 2840A19G01 through G08)

3-5.1. Description Groups 01 through G08 are applicable for use in the CE MARK Certified System The QAI card contains four analog-to-digital (A/D) converters and a digital multiplexed interface to the DIOB of a process control system (see Figure 3-28). Analog input systems consist of one or more QAI cards, a QTB card, and one Bus Controller; no other cards are required to perform the analog input function. The subsystem may be expanded in increments of four points by adding QAI cards (48 QAI cards maximum).

DIOB Address and Control

Data

Subtractor and Offset Check

Interface Logic

Point RAM

Memory Control Logic

Offset RAM

A/D Control Logic

Counter

Optical Isolators Signal Conditioning

Integrator

Field Input

Figure 3-28. QAI Block Diagram

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M0-0053

3-5. QAI

3-5.2. Features Each A/D converter is dedicated to a process point in the plant environment, converting a bipolar analog field input to a 16-bit digital output. The 16-bit digital data includes the analog signal value (12 bits), polarity, overrange, and 2 error bits. The QAI can be utilized in a system with any type of DIOB controller (such as MBU or MSQ), provided a QTB card is present. The card will accept four bipolar signals ranging from +20 mV to +10 V with 12-bit binary resolution. Inputs are fault-voltage protected and can withstand high common mode voltages and IEEE surge The QAI card is available in eight groups (G01 through G08), providing a range of analog input parameters.

• • • • • • • •

G01: +20 mV analog inputs with a 700Ω source impedance (maximum) G02: +50 mV analog inputs with a 700Ω source impedance (maximum) G03: +100 mV analog inputs with a 1 kΩ source impedance (maximum) G04: +500 mV analog inputs with a 5 kΩ source impedance (maximum) G05: +1 V analog inputs with a 10 kΩ source impedance (maximum) G06:+10 V analog inputs with a 10 kΩ source impedance (maximum) G07: 0 to 20 mA of current for analog inputs G08: +50 mV analog inputs with a 1 kΩ source impedance (maximum)

The QAI card offers the following features:

• • • • • • • • • • • •

M0-0053

Accepts four bipolar signals ranging from +20 mV to +10 V, with 12-bit binary resolution Fault-voltage protected inputs which withstand IEEE surge High ac normal mode and common mode rejection without any filters Open thermocouple detection Dual slope integration Line frequency tracking High conversion rate Digital auto-zeroing Auto-conversion check Isolated power supply for each point Digitized value readily available for transfer anytime Lock-out to facilitate system snap-shot


5/99

3-5. QAI

3-5.3. Specifications DIOB Input Requirements Logic 0: 0 V to 3 V

Logic 1: +8 V to +12 V The signal lines at the DIOB interface are specified by the DIOB description. Analog Input Capabilities G01: −20 mV to +20 mV G02: −50 mV to +50 mV G03: −100 mV to +100 mV G04: −500 mV to +500 mV G05: −1V to +1V G06: −10V to +10V G07: 0 mA to +20 mA G08: −50 mA to +50 mA Input Impedance (minimum) Groups 1 through 6 and 8 Below 60 percent Relative humidity: 108Ω/volt Below 90 percent Relative humidity: 107Ω/volt Overload: 103Ω Input Impedance Group 7 250Ω Point Sampling (Rate/second) 60 Hz power line frequency: 30 50 Hz power line frequency: 25 Resolution Full Scale: 12 bit

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M0-0053

3-5. QAI

Full Scale and Polarity: 13 bit Reference Accuracy 99.7 percent confidence:+0.125 percent +10 µV +1/2 LSB of full scale Reference Condition: 25°C ambient temperature, 0V (ac and dc) Common Mode, 0 VAC Normal Mode Normal Mode Rejection At power-line frequency and harmonics with frequency tracking: 60 dB At power-line frequency +5 percent and harmonics without line frequency tracking: 20 dB Common Mode Rejection At DC, power line frequency and harmonics with line frequency tracking: 120 dB At nominal power line frequency +5 percent without line frequency tracking: 100 dB Line Frequency Tracking Input Voltage: 120 VAC +10 percent (rms) Input Voltage Frequency: 60 Hz + 2Hz or 50 Hz + 5Hz Input Voltage Frequency Stability: + 0.6 percent/sec (maximum change) Frequency Tracking Compensation: +0.01 percent increments (hardware compensation) Open Thermocouple Detection Open thermocouple detection with a minus over-range signal is provided on the following card groups:

• • • M0-0053

Group 1 Group 2 Group 3


5/99

3-5. QAI

•

Group 8 (no minus over-range)

Power Requirements Minimum

Nominal

Maximum

Primary Voltage:

+ 12.4 V

+ 13.0V

+ 13.1 V

Backup Voltage: (optional)

+ 12.4 V

--

+ 13.1 V

--

550 mA

600 mA

Current

Output Codes Output Data (Hexadecimal)

Input

C000

0 input

C001

+1

D000

+ Full Scale

DXXX or 18000

+ Over Range

FFFF

-1

F000

- Full Scale

EXXX

- Over Range (Open thermocouple detection).

18000

Out of Range Offset

to BFFF

0000 to 7FFF

Card Trouble

X – Don’t Care 18000

may indicate either an out of range offset or an over range of at least 5%.

Functional Description All QAIs in an analog input process control system utilize one QTB card per DIOB to start continuous conversion of all four points and to establish the conversion cycle. The conversion is conducted for a full cycle of line frequency to provide high noise rejection without relying on approximations from previous readings. This enables the card to recover quickly from surges and continuous overvoltages.

5/99


M0-0053

3-5. QAI

Each QAI card contains four isolated A/D converters sharing a non-isolated digital interface to the DIOB. The digital section is composed of a counter accumulator, RAM memory, and an interface to the DIOB. Signal coupling between the isolated and non-isolated sections is through optical isolators. On cards rated up to +100 mV, open thermocouple detection is performed by means of a high-impedance voltage source which is shorted out if the thermocouple is good. If the thermocouple is open, the voltage for the open point is read by the converter. Each time a reading is completed, the digitized value is placed in RAM and stored until the next reading is complete. The stored value is unaffected by calibration checks. Circuit Description A functional block diagram of the QAI card is shown in Figure 3-29. QAI Control Timing A control timing diagram is shown in Figure 3-30. The Pre-Amp input and RAM selection is synchronized with the USYNC signal pulse. The integrator output provides the offset signal when the pre-amp input is shorted. UIOB transactions (for example, Read operations) may occur at any time during these pulses. However, if a UIOB transaction occurs at the same time as an END OF CONVERSION (EOC) pulse, the EOC pulse is ignored and RAM update does not occur. Similarly, the UCAL Lockout pulse (for taking a plant snapshot) overrides an EOC pulse and inhibits RAM updating.

M0-0053


5/99

5/99 3-67

Westinghouse Proprietary Class 2C OFFSET CONVERSION

CLOCK

MEMORY CONTROL LOGIC

DIOB INTERFACE LOGIC

ADDR

WRITE

OFFSET CONVERSION

+24V

EOC CONVERSION

A/D LOGIC CONTROL

EOC

CHOPPER

ANALOG POINT CIRCUITRY

RAMP CONTROL

FIELD SIGNAL

POWER DRIVE

DIOB

ENABLE

RAM

ADDR R/W OFFSET

WORD

R/W POINT

RAMP CONTROL

CLOCK

OFFSET RAM

TRI-STATE BUS DRIVERS

14 DATA BITS

SUBTRACTOR

14 BIT OUTPUT

POINT RAM

14-BIT COUNTER

2 ERROR BITS

OFFSET CHECK

WORD ADDR

R/W OFFSET RAM

3-5. QAI

8

ADDR

BUS CONTROL

8 UDATA BITS

DATA

8 UADDR BITS HI/LO UNIT DATAGATE DATADIR

POWER

12V GND

A/D CONTROL

USYNC UCAL UCLOCK

Figure 3-29. QAI Card Block Diagram

M0-0053

3-5. QAI

POSITIVE FIELD INPUT NEGATIVE

USYNC

UCAL

LOCK-OUT

UIOB TRANSACTION OCCURRENCE

SHORTED PRE-AMP INPUT

FIELD

FIELD

(ZERO) OFFSET RAM SELECT

POINT

POINT

INTEGRATOR OUTPUT

END OF CONVERSION

RAM UPDATE INHIBITED DUE TO DIOB TRANSACTION

INHIBITED DUE TO LOCKOUT

Figure 3-30. QAI Control Timing Diagram

Analog Point Circuitry A general block diagram of the analog point circuitry is shown in Figure 3-31. Figure 3-32 shows Analog Point Timing. When USYNC goes high, the SIG signal also goes high and enables the summer output signal to pass into the integrator amplifier. Consequently, the integrator begins ramping up as shown in Figure 3-32. The integrator continues to ramp up until USYNC fails.

M0-0053


5/99

ANALOG INPUT

SWC NM FILTER

SHIELD CONNECTED TO LOW INPUT AT SOURCE

−

+

BUFFERED ATTENUATOR G06, 7

3-69

Westinghouse Proprietary Class 2C REF REF. VOLTAGE GENERATOR

SUMMER

ANALOG FRONT END

CLAMP

BIAS

5/99 OTD

CHARGE

DUAL SLOPE A/D

CHARGE

INTEGRATOR

ΤΟ

POINT/OFFSET SELECT

PRE AMP

Σ

CONTROL

COMPARATOR

1V F. S.

SHIELD

POWER SUPPLY

CONTROL

RAMP

EOC

CONV

OFFSET

INTERFACE TO NONISOLATED SECTION

50K HZ

3-5. QAI

Figure 3-31. QAI Analog Point Block Diagram

M0-0053

3-5. QAI

USYNC (Ramp Control) 10µsec coupling delay Signal Interval

Reference Interval

Clamp

10V + F.S Input 5.5 V

0V Input - F.S Input

1V

Integrator Output O.T.D. Charge

Discharge Time

Signal Integration

End of Conversion E.O.C.

-F.S

Count Accumulation Time

0V

+F.S

Figure 3-32. QAI Analog Point Timing Diagram

3-5.4. Card Addressing Connectors and Terminations The QAI card interfaces with the DIOB via a standard DIOB rear, card-edge connector (see Figure 3-33).

M0-0053


5/99

3-5. QAI

The analog inputs enter the QAI on the front-edge of the card. The QAI inputs are three wire and use the same pin-outs for all groups. The contact allocations are shown in Table 3-21. Table 3-21. QAI Analog Input Contact Allocations

Point

Pin Out

Point 0

5A – (+ input) 3A – (− input) 3B – (shield)

Point 1


Point 2


Point 3


Channel 3

Channel 1 Digital Circuitry Channel 2

Channel 0

Figure 3-33. QAI Card Components

5/99


M0-0053

3-5. QAI


CARD 19B 19A


17B

POINT 3

(+)

17A

(+)

(SHIELD)

15B

(SHIELD)

(−)

15A

(−)

POINT 3

13B

POINT 2

(+)

13A

(+)

(SHIELD)

11B

(SHIELD)

(−)

11A

(−)

POINT 2

9B

POINT 1

(+)

9A

(+)

(SHIELD)

7B

(SHIELD)

(−)

7A

(−)

POINT 1

5B

POINT 0

(+)

5A

(SHIELD)

3B

(−)

3A

(+) POINT 0 TRANSDUCER (−)

1B 1A

PLANT GROUND

EDGE-CONNECTOR

Figure 3-34. QAI Wiring Diagram

M0-0053


5/99

3-5. QAI


CARD

POINT 0

POINT 1

POINT 2

POINT 3

1A

A

A

1B

1

1

(−)

3A

2

2

(SHIELD)

3B

3

3

(+)

5A

4

4

5B

5

5

(−)

7A

6

6

(−)

(SHIELD)

7B

7

7

(SHIELD)

(+)

9A

8

8

(+)

9B

9

9

(−)

11A

10

10

(−)

(SHIELD)

11B

11

11

(SHIELD)

(+)

13A

12

12

(+)

PLANT GROUND

(−) TRANSDUCER POINT 0 (+)

13B

13

13

(−)

15A

14

14

(SHIELD)

15B

15

15

(+)

17A

16

16

17B

17

17

19A

18

18

19B

PE

PE

POINT 1

POINT 2



EDGE-CONNECTOR

Note The QAI inputs may be grounded in the field or at the B cabinet as shown.

Figure 3-35. QAI CE MARK Wiring Diagram

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M0-0053

3-6. QAM

3-6. QAM Automatic/Manual Station Controller (Style 7379A28G01 through G06)

3-6.1. Description The Automatic/Manual (QAM) card provides the interface between the DIOB controller, the M/A station and a final controlled device. A final controlled device can be a voltage to pressure (E/P) or a current to pressure (I/P) converter (see Figure 3-36). The QAM card is available in six groups (G01 through G06). Electrical connection to the QAM card is made through a 9-pin connector, a 28-pin card edge connector and a 34-pin backplane connector. The QAM card connections are shown in Figure 3-40.

Data

DIOB

UIOB or DIOB Interface Logic Control Logic Demand Up/Down Counter

Set Point Up/Down Counter

Demand D/A Converter

Set Point D/A Converter

Demand Set Point I/P

E/P

Digital DIM Outputs Inputs

M/A Interface

Field Interface

Figure 3-36. QAM Block Diagram

3-6.2. Features The QAM card provides the following capabilities:

• M0-0053

Automatic or Manual mode operation


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3-6. QAM

Note The DIOB controller does not need to be present for Manual mode operation.

• • •

Ability of DIOB controller to place QAM card in Manual mode

• • • •

Ability to indicate the output demand and setpoint at the M/A station

•

Ability of the QAM card to produce an ALIVE digital output, which is used as a logic input in a redundant configuration

• •

Jumper selection and deselection of the QAM card options

• •

Ability to place QAM card in either mode via external reject signals Switch selectable watchdog timer which places QAM card in Manual mode if not periodically updated by the DIOB controller, during Automatic mode operation.

Ability to indicate Automatic or Manual mode selection at the M/A station Ability to indicate the demand’s high or low limit status at the M/A station Ability to input MANUAL/AUTO, POWER OKAY, WATCHDOG ALIVE, and REJECT TO MANUAL status bits to the DIOB controller

Ability of the QAM card to auctioneer two external power sources (+13 VDC to 26 VDC), supplying this voltage to the M/A station’s lamps Three plug in resistor variable rate clocks On-card Demand and Set Point zero and gain potentiometers

A QAM card functional block diagram is shown in Figure 3-37, and a systems application block diagram is shown in Figure 3-38. Figure 3-39 shows a typical QAM usage scheme.

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M0-0053

M0-0053 D I O B 8

12

DIOB INTERFACE LOGIC

DEMAND UP/DOWN COUNTER

12

CONTROL LOGIC

12

DIM INPUTS

SETPOINT UP/DOWN COUNTER

12

12

5

DEMAND D/A CONVERTER

SETPOINT D/A CONVERTER

DIGITAL OUTPUTS

3-76

Westinghouse Proprietary Class 2C

G02, 6

RIM

G01

+10 VDC REF

G02

RIF

2

2

DEMAND

2

FIELD INTERFACE G02, 4: 4 - 20 mA G03: 0 - 180 mA G05, 6: 10 - 50 mA

G01: 0 - 10 VDC

G01: 0 - 10 VDC G02, 4, 6: 1- 5 VDC G03: 0 to 5 VDC

SETPOINT G01, 2, 3, 6: 0 - 10 VDC G04, 5: 1 - 5 VDC

M/A INTERFACE

3-6. QAM

Figure 3-37. QAM Card Functional Block Diagram

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5/99 A

I/D

M/A STATION

3-77


FEEDBACK (4 - 20 mA)

DEMAND

E/P OH I/P CONVERTER

QAM CARD

PROCESS VARIABLE AND FEEDBACK

AUX. CONTROL (INFO CENTER REQUIRED)

SETPOINT INC./DEC.

DEM

DIOB CONTROLLER

QAC CARD

INFO CENTER

QAO CARD

PROCESS VARIABLE

QAI/V CARDS

3-6. QAM

Figure 3-38. QAM Card Systems Application Block Diagram

M0-0053

BIAS

DEMAND (1)

BIAS

P B S

DI = DIGITAL INPUT PB = PUSHBUTTON

(OR MSQ)

MSL

MBU

PROCESS VARIABLE

QAW

PT

QAW

QAM

D E M A N D

(E)

C L

I

OUT

P

PV

DI’s/PB’s

QCI

SP

METERS

QAO

OIM

3-6. QAM

Figure 3-39. QAM Card Usage Scheme

3-6.3. Specifications Power Requirements Primary Voltage: +12.4 V to 13.1 VDC Backup Voltage: +12.4 V to 13.1 VDC

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3-6. QAM

Current: Table 3-22. QAM Current Specification

Group

Typical

Maximum

01, 02, 04

0.4 A

0.75 A

03

1.00A

1.48 A

05, 06

0.65 A

0.90 A Note

For Groups 1, 2, 4, 5, and 6, QAM card short circuit protection is provided by 1.0 A plug-in fuse. For Group 3 short circuit protection is provided by 1.0 A plug-in fuse and a 1.5 A plug-in fuse. J1 Signal Specifications (DIOB Interface) The QAM occupies the high and low byte of two DIOB addresses. The QAM card address is established by seven jumpers on the J2 card-edge connector (Table 3-23). The insertion of a jumper encodes a “1” on the address line. J2 Signal Specifications (Operator Interface) Digital Inputs These signals are typically connected to the operator panel pushbuttons.

• • • • • •

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Voltage Limits: −0.5 VDC to +30 VDC VIH (Logic zero voltage): 10 VDC minimum IIH (Logic zero current): 0.1 mA maximum (at 30 VDC) VIL(Logic one voltage): 2.0 VDC maximum IIL (Logic one current): −3 mA maximum Delay: 0.75 msec maximum


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3-6. QAM

Digital Outputs These signals typically drive the operator panel lamps.

• • • • •

Voltage Limits: −0.5 VDC to +30 VDC LIH (Logic zero current): 0.1 mA maximum (e + 30 VDC) VOL(Logic one voltage)*: 1.3 VDC maximum LIL(Logic one current)*: 200 mA maximum LIL(Total)(Logic zero current)*: 450 mA maximum Note These values are true with the exception of the ALIVE signal, where the maximum logic 1 voltage is 1.1 VDC and the maximum logic 1 current is 50 mA. Table 3-23. QAM J2 Connector Pin Assignments

Pin Number (Solder Side)

1A 2A* 3A* 4A* 5A* 6A* 7A* 8A 9A 10A 11A 12A 13A 14A 15A** 16A 17A

Signal Name

DIM Input Common LOWER INHIBIT RAISE INHIBIT PRIORITY LOWER PRIORITY RAISE AUX MAN AUX AUTO “CONNECTOR IN PLACE” Jumper System Common IMASHLD IMADEM − IMADEM + System Common ALIVE OUT MA PWRA MA PWRB

Pin Number (Component Side)

1B 2B* 3B* 4B* 5B* 6B* 7B* 8B 9B 10B 11B 12B 13B 14B** 15B** 16B** 17B**

Signal Name

DIM Input Common DECREASE SP INCREASE SP LOWER IN**** RAISE IN*** MAIN IN AUTO IN VMASHLD VMADEM − VMADEM + SPSHLD SETPOINT − SETPOINT + LO LIMIT OUT HI LIMIT OUT MAN OUT AUTO OUT

SLOT

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3-6. QAM

Table 3-23. QAM J2 Connector Pin Assignments (Cont’d) Pin Number (Solder Side)


Signal Name

19B 20B 21B 22B 23B 24B 25B 26B 27B 28B

MA RTN DIOB Ground DIOB Ground DIOB Ground DIOB Ground DIOB Ground DIOB Ground DIOB Ground DIOB Ground DIOB Ground

19A 20A 21A 22A 23A 24A 25A 26A 27A 28A Where: DIOB Ground =

Signal Name

MA PWR Unused Unused ASEL1 (LS) ASEL2 DIOB ASEL3 Address ASEL4 Select ASEL5 Jumpers ASEL6 ASEL7 (MS)

and System Common =

Notes The following J2 connector pins are connected together on the QAM card: 10A, 11A, 14A, 8B, 9B, 11B, and 12B * = These are DIM input signals. ** = These are DIM output signals. *** = This signal is not connected on Group 3. **** = The signal provides a card reset on Group 3.

Output Demand Indication Signals

Voltage This signal drives the operator panel meter or bargraph, indicating output demand.

•

G01 Span: Load Resistance: Current: Common Mode Voltage:

•

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0 to 10 VDC 2 KΩ minimum 5 mA maximum

+ 10 V maximum Accuracy: + 0.1 percent of span Temperature coefficient: 20 ppm of span/˚C G02, 03, 04, 05, 06


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3-6. QAM

Span: Load Resistance: Current: Common Mode Voltage: Accuracy: Temperature coefficient:

1 to 5 VDC, G03 = 0 to 5 VDC 2 KΩ minimum 2.5 mA maximum + 10 V maximum + 0.25 percent of span 50 ppm of span/˚C Note

Accuracy and temperature coefficients determined with respect to the demand output.

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3-6. QAM

Current This signal drives current meter on the operator panel via a series diode on the QAM card.

•

Groups 02, 03, 04, 05, 06 Group 02, 04 Span:

4 to 20 mA

Group 03 Span:

0 to 180 mA

Group 05, 06 Span:

10 to 50 mA

Load Resistance G02, 04:20 Ω maximum, 0 Ω minimum Load Resistance G03:

2.1 Ω maximum, 0 Ω minimum

Load Resistance G02, 04:8 Ω maximum, 0 Ω minimum Common Mode Voltage: + 10 V maximum + 0.0%, -0.2% of span

Accuracy:

Temperature coefficient: 50 ppm of span/˚C Note The load resistance is required to ensure compliance of accuracy and temperature specifications. If desired, this load may be left open. Accuracy and temperature coefficients determined with respect to the demand output. M/A Station Lamp Power

• • • •

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Input Voltage:

+12.4 VDC to +30 VDC

Output Voltage:

(Input Voltage) + 0.0 VDC to -1.3 VDC

Current:

450 mA maximum

Overcurrent Protection:

0.5 A Plug-in Fuse


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3-6. QAM

Setpoint Indication Signal

• • • • • • • •

Span (G01, 02, 03, 06)

0 to 10.000 VDC

Span (G04, 05)

1.000 to 5.000 VDC

Load Resistance:

2 kΩ’s

Current (G01, 02, 03, 06): 5 mA maximum Current (G04, 05:

2.5 mA maximum

Common Mode Voltage:

+ 10 V maximum

Accuracy:

+ 0.1 percent of span

Temperature coefficient:

50 ppm of span/˚C

J3 Signal Specifications (Field Interface) Output Demand Voltage (G01)

• • • • • •

Type:

Unipolar Direct Positive (RIM)

Span:

0 to 10 VDC

Load Resistance:

500 Ω’s minimum

Current*:

20 mA maximum

Common Mode Voltage:

+ 10 V maximum

Accuracy:

+ 0.05 percent of span Note * The J3 Demand Output can be shorted to common without damage.

Output Demand Current Table 3-24. QAM Output Demand Current

Parameter

G02, 04

G03

G05, 06

Type

RIF (Unipolar Direct Positive)



Span

0 to 20.000 mA

0 to 20.000 mA

0 to 20.000 mA

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3-6. QAM

Table 3-24. QAM Output Demand Current

Parameter

G02, 04

G03

Load Resistance (Min./Max.)

0 Ω/1 KΩ

Common Mode Voltage

+ 10 V maximum + 10 V maximum + 10 V maximum

Accuracy

+ 0.05% of span

Temperature coefficient

50 ppm of span/˚C 50 ppm of span/˚C 50 ppm of span/˚C

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0 Ω/111 Ω

G05, 06

+ 0.05% of span


0 Ω/400 Ω + 0.05% of span

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3-6. QAM

Table 3-25. QAM J3 Connector Pin Assignments

Pin Number

Signal Name

1

Unused

2

VDEM+**

3*

VDEM−**

4*

VSHLD

5

Unused

6

IDEM+ ***

7*

IDEM− ***

8*

ISHLD

9

Unused

9 5

8 4

7 3

6 2

1

PRINTED CIRCUIT BOARD

M410 CONNECTOR

Notes * These pins are connected to System Common. ** These are RIM output signals. *** These are RIF output signals.

Clock Timing Manual Clock 1 This clock is used for the PRIORITY RAISE and PRIORITY LOWER commands, providing linear operation. This clock provides full scale output travel (span) times of from 18 to 490 seconds (30 seconds standard). Manual Clock 2 This clock is used for the RAISE and LOWER commands, providing exponential operation. The characteristics of this clock are as follows:

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3-6. QAM

Time

Frequency

0 to 1/2 T

fl/64

1/2 T to 1-1/2 T

fl/32

1-1/2 T to 2-1/2 T

fl/16

2-1/2 T to 3-1/2 T

fl/8

3-1/2 T to 4-1/2 T

fl/4

4-1/2 T to 5-1/2 T

fl/2

5-1/2 T to 6-1/2 T

fl

6-1/2 T to Infinite

2fl

Where the frequency of the Priority Linear Clock is fl (140 Hz standard). Time (T) is selected by a plug-in resistor and ranges from 0.2 to 2.0 seconds (0.8 seconds standard).

Setpoint Clock This clock is used for SETPOINT INCREASE and SETPOINT DECREASE commands, providing linear operation. This clock provides full scale output travel times of 35 to 980 seconds (90 seconds standard).

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3-6. QAM

DIOB Data Format The DIOB data format is shown in Table 3-26. Table 3-27 gives analog values for some of the hex codes of the DIOB data field. These DIOB data hex codes may vary from X’000’ to X’FFF’ Table 3-26. QAM DIOB Data Format Type of Operation

Command Word

DataDIR

UADD0

DIOB Data Word

HI-LO

UDAT Bits

Write

Write*

Read

Read

6

Automatic Demand/ Control

0 0

0 0

1 0

Byte 1

MSB

Byte 2

LSB

Setpoint/ Control

0 0

1 1

1 0

Byte 1

MSB

Byte 2

LSB

Automatic Demand/ Control

1 1

0 0

1 0

Byte 1

MSB

Byte 2

LSB

Setpoint/ Status

1 1

1 1

1 0

Byte 1

MSB

Byte 2

LSB

5

4

3

2

1

0

Unused R K

Unused R K

P M R A

P M R A

Where: K= KEEP ALIVE & reset timer when 1 R = REJECT to MANUAL when 1 P = POWER OK when 1 M = MANUAL MODE =1, AUTO = 0 A = ALIVE when 1 MSB = Most Significant Bit LSB = Least Significant Bit

* = Disable by changing field jumper.

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3-6. QAM

Software Parameters Due to the double DIOB cycle requirements for QAM card applications, care must be taken in programming the DIOB controller. Two DIOB transfers to or from the QAM card must be successive, in order to transfer the required 12-bit data words. Table 3-27. QAM Analog Values versus Hex Codes

HEX

Demand/ Setpoint 0-10.000 V

Setpoint

1-5.000 V

Demand 4 - 20.000 mA

Demand 10- 50.000 mA

Demand 0 - 180.00 mA

000

0.000 V

1.000 V

4.000 mA

10.000 mA

0.000 mA

001

2.442 mV

1.001 V

4.004 mA

10.010 mA

0.044 mA

200

1.250 V

1.500 V

6.000 mA

15.001 mA

22.505 mA

400

2.501 V

2.000 V

8.001 mA

20.002 mA

45.011 mA

800

5.001V

3.000 V

12.002 mA

30.005 mA

90.022 mA

C00

7.502 V

4.001 V

16.003 mA

40.007 mA

135.03 mA

E00

8.752 V

4.501 V

18.003 mA

45.009 mA

157.54 mA

FFE

9.998 V

4.999 V

19.996 mA

49.990 mA

179.96 mA

FFF

10.000 V

5.000 V

20.000 mA

50.000 mA

180.00 mA

Demand or Setpoint Outputs The QAM card must be written to in the proper sequence. The normal order of DIOB transactions during a write to the QAM is to first write the Low Byte and then write the High Byte, during a successive DIOB cycle. However, it is not necessary to send the High Byte to the QAM within any specific amount of time after sending the Low Byte. Note The Low Byte cannot be changed at the Up/Down counter without also sending the High Byte. The Low Byte is received but is not loaded into the appropriate Up/Down counter (Demand or Setpoint) until the corresponding High Byte is also received.

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3-6. QAM

Each time the Low Byte is written to the QAM card, the REJECT TO MANUAL bit of this byte is latched and held on the QAM card. The latched state of this bit is maintained by the QAM card until the next Low Byte is written. As a result, this bit remains set, causing a continuous manual reject, until reset by a subsequent Low Byte write. Additionally, the QAM card’s Reject to Manual latch may be reset by the QAM RESET signal. Unlike the REJECT TO MANUAL bit, the Low Byte’s KEEP ALIVE bit is not latched and held. Therefore, it is not necessary to alternate this bit between 1 and 0 on successive Low byte writes. A 1 state of the KEEP ALIVE bit on each Low byte write keeps the QAM “alive”, providing these writes occur within the selected Watchdog time-out period. Demand or Setpoint Inputs The QAM card must be read in the same sequence as it was written (Low Byte read first and High Byte read second), during successive DIOB cycles. Again, as in the case of a write, there can be a delay between reading the Low and High Bytes. The appropriate up/down counter (Demand or Setpoint) is prevented from counting during and following each Low Byte read until a subsequent DIOB operation, other than another Low Byte read, has taken place or a Watchdog time-out occurs. Note The DIOB controller should not be programmed for continuous QAM Low Byte reads of the demand with the Watchdog timer disabled and no other DIOB activity. This type of programming would prevent manual manipulation of the output demand.

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3-6. QAM

3-6.4. Controls and Indicators DIOB Backplane Connector

To E/P or I/P

J3 J1

Power OK Manual Alive

LED’s

J2

Card EDGE Connector or M/A Station

Figure 3-40. QAM Card Connections

Automatic Mode In the Automatic mode, the QAM card provides either a voltage or a current demand output, which tracks the 12-bit demand signal output of the DIOB controller. The operator or external device can prevent the output demand signal from changing more than 0.375 percent of span in one or both directions by using the RAISE or LOWER INHIBIT commands. Additionally, while in the Automatic mode, the QAM card provides a voltage output which tracks the 12-bit setpoint signal output from the DIOB controller. The operator can alter this signal via INCREASE or DECREASE SETPOINT commands, which produce a constant rate of change in the setpoint signal. The output of the QAM card’s setpoint counter/register logic is in turn provided as an input to the DIOB controller. Manual Mode In the Manual mode, the QAM card increases or decreases the demand output on the RAISE or LOWER signals from the M/A station. Exponential changes in these demands are produced by a variable rate clock circuit. Commands to RAISE or LOWER the demand may also be executed by using the PRIORITY RAISE and LOWER inputs. These commands reject the card to Manual mode and override the normal directional commands. A linear clock is provided for these options, providing a constant rate of change in the demand output.

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3-6. QAM

The DIOB controller can monitor the output demand when the manual mode is selected because the 12-bit demand counter/register is an input to the DIOB controller. This enables a bumpless transfer when the QAM card is switched from Manual or Automatic mode. The demand operation variations for the Manual mode are given in Table 3-28 and Table 3-29. Table 3-28. QAM Manual Mode Demand Operations (G03) Priority Lower

Priority Raise

Lower

Raise

0

0

0

0

HOLD

–

No

Don’t Care

0

1

0

1

RAISE

LINEAR

Yes

Don’t Care

1

0

0

0

LOWER

LINEAR

Yes

Don’t Care

1

1

0

0

HOLD

Yes

Don’t Care

1

1

1

1

LOWER

Yes

J Installed

X

X

1

X

Reset Card: Setpoint = 0

Yes

H Removed

Action

Clock Rate

– LINEAR

Manual Reject

Jumpers

Where: 0 = Inactive Signal 1 = Active Signal

Table 3-29. QAM Manual Mode Demand Operations (G01, 2, 4, 5, 6) Priority Priority Lower Raise

Lower

Raise

Action

Clock Rate

0

0

0

0

HOLD

–

0

0

0

1

RAISE

0

0

1

0

0

0

1

0

0

0

Manual Reject

Jumpers

No

Don’t Care

EXPONENTIAL

Yes*

Don’t Care

LOWER

EXPONENTIAL

Yes*

Don’t Care

1

HOLD

–

No

G Installed

1

1

LOWER

EXPONENTIAL

Yes*

G Removed

1

0

0

RAISE

LINEAR

Yes

Don’t Care

0

1

0

1

RAISE

LINEAR

Yes

Don’t Care

0

1

1

0

RAISE

LINEAR

Yes

Don’t Care

0

1

1

1

RAISE

LINEAR

Yes

Don’t Care

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3-6. QAM

Table 3-29. QAM Manual Mode Demand Operations (G01, 2, 4, 5, 6) (Cont’d) Priority Priority Lower Raise

Lower

Raise

Action

Clock Rate

Manual Reject

Jumpers

1

0

0

0

LOWER

LINEAR

Yes

Don’t Care

1

0

0

1

LOWER

LINEAR

Yes

Don’t Care

1

0

1

0

LOWER

LINEAR

Yes

Don’t Care

1

0

1

1

LOWER

LINEAR

Yes

Don’t Care

1

1

0

0

HOLD

–

Yes

H Installed

1

1

0

1

HOLD

–

Yes

H Installed

1

1

1

0

HOLD

–

Yes

H Installed

1

1

1

1

HOLD

–

Yes

H Installed

1

1

0

0

LOWER

LINEAR

Yes

H Removed

1

1

0

1

LOWER

LINEAR

Yes

H Removed

1

1

1

0

LOWER

LINEAR

Yes

H Removed

1

1

1

1

LOWER

LINEAR

Yes

H Removed

Where: 0 = Inactive Signal 1 = Active Signal * Manual Reject only if jumper F is installed, otherwise no manual reject occurs.

Watchdog Timer The QAM card must be periodically updated via the keep-alive bit (DIOB controller) to maintain selection of the Automatic mode. The period within which the QAM card must be updated is selected by a 4-bit DIP switch on the QAM card. If this card is not updated before a timeout of the selected watchdog time, the card automatically reverts to the Manual mode. The available update period times for the 4-bit Watchdog Timer switch settings are shown in Table 3-30. Table 3-30. QAM Watchdog Timer Switch Settings Switch Segments

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Update Period Times

D

C

B

A

0

0

0

0

62 msec. timeout

0

0

0

1

125 msec. timeout

0

0

1

0

250 msec. timeout

0

0

1

1

500 msec. timeout


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3-6. QAM

Table 3-30. QAM Watchdog Timer Switch Settings Switch Segments

Update Period Times

D

C

B

A

0

1

0

0

1 sec. timeout

0

1

0

1

2 sec. timeout

0

1

1

0

4 sec. timeout

0

1

1

1

8 sec. timeout

1

X

X

X

no timeout

Where: 0 = Open switch segment 1 = Closed switch segment X = Either open or closed. All times have tolerance of +20 percent.

QAM Reset The QAM card will reset under either of the two following conditions:

• •

When the +13 VDC input supply voltage drops below +9 VDC When the DIOB’s UNIT control is active.

A RESET causes the card to enter Manual Mode and the setpoint is defined as 00016. The demand and Manual Mode operations will not be affected by the UNIT signal, however, the demand will be set to 00016 whenever the +13 VDC input voltage drops somewhat below the +9VDC level. With a Group 03 card, the LOWER signal from the M/A station will reset and provide a zero setpoint within 5 msec of activating the lower signal. This reset causes the card to enter the Manual Mode. Because the UNIT signal is not connected on a Group 03 card, a reset has no effect on the UNIT signal.

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3-6. QAM

Figure 3-41 illustrates the card components. LEDs DEM Gain Pot. DEM Zero Pot.

DIP Switch

RS

Speed Selection Jumpers

RE

SP Zero Pot

SP Gain Pot

EFGHJK

RW

PWR OK MANUAL ALIVE

RL

Figure 3-41. QAM Card Components

LED Indicators The QAM card has three front edge LED’s which indicate: PWR OK

– lights when proper DIOB power is applied to card

MANUAL

– lights when QAM card is in Manual mode; off during Automatic mode operation.

ALIVE

– lights when Watchdog Timer is in timeout period; goes off when timer’s timeout period expires, indicating that DIOB controller has failed to update the KEEP ALIVE bit within selected period.

Plug-In Resistors The QAM card contains four plug-in resistors which determine the timing for the QAM clocks and timer. Each of these resistors is listed below.

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•

RW – Watchdog Timeout Period – value selected to control the range of the DIP switch selected Watchdog Timeout periods.

•

RL – Linear Clock Frequency – value selected to determine the linear clock frequency for demand operations (priority raise and lower). Refer to Table 3-31 for suggested resistor values and corresponding clock rates.


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3-6. QAM

•

RE – Exponential Clock Frequency – value selected to determine the exponential clock frequency for demand operations (normal raise and lower). Refer to Table 3-32 for suggested resistor values and corresponding clock rates.

•

RS – Setpoint Clock Frequency – value selected to determine the linear clock frequency for setpoint operations (setpoint increase or decrease). Refer to Table 3-33 for suggested resistor values and corresponding clock rates.

Table 3-31. QAM RL Selected or Demand Linear Clock Frequency RL Values

Selected Frequency

Full Scale Ramp

Change/Minute

2 kΩ

230 Hz

18 seconds

340 percent

5 kΩ*

135 Hz

30 seconds

200 percent

10 kΩ

90 Hz

45 seconds

135 percent

20 kΩ

60 Hz

70 seconds

85 percent

50 kΩ

30 Hz

140 seconds

43 percent

100 kΩ

16 Hz

260 seconds

23 percent

200 kΩ

8.5 Hz

490 seconds

12 percent

* Standard Value Table 3-32. QAM RE Selection of Demand Exponential Clock Frequency Sweep Rates RE Values

Clock Period Time

Selected Frequency

Frequency Sweep Period

100 kΩ

0.23 seconds

4.4 Hz

1.5 seconds

200 kΩ*

0.45 seconds

2.2 Hz

2.9 seconds

365 kΩ*

0.83 seconds

1.2 Hz

5.4 seconds

750 kΩ

2.0 seconds

0.5 Hz

13.0 seconds

* Standard Value

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3-6. QAM

Table 3-33. QAM RS Selection of Setpoint Linear Clock Frequency RS Values

Selected Frequency

Full Scale Ramp

Change/Minute

2 kΩ

115 Hz

35 seconds

170 percent

5 kΩ

68 Hz

60 seconds

100 percent

10 kΩ*

45 Hz

90 seconds

67 percent

20 kΩ

30 Hz

140 seconds

43 percent

50 kΩ

15 Hz

280 seconds

21 percent

100 kΩ

8 Hz

515 seconds

12 percent

200 kΩ

4.3 Hz

980 seconds

6 percent

* Standard Value

Plug-In Jumpers The QAM card contains six plug-in jumpers for option selections. Table 3-34 lists the selected options of each jumper. An option is selected when its corresponding jumper is inserted. Table 3-34. QAM Jumper Selection of Options Jumper

Selected Option

E

The REJECT TO MANUAL bit from the DIOB controller switches the card to Manual mode.

F*

The RAISE IN or LOWER IN inputs switch card to Manual mode. Note Simultaneous RAISE IN or LOWER IN signals do not switch card to Manual mode unless jumper G is removed.

G*

Simultaneous RAISE IN or LOWER IN signals cause output to hold instead of lower.

H

Simultaneous RAISE IN and PRIORITY LOWER signals cause the output to hold instead of lower.

J

The DIOB controller may set the 12-bit setpoint word.

K

Absence of the cable to the MA station does not reject the card to Manual mode.

* On Group 03 cards, jumpers F and G have no effect. Activation of the LOWER will always cause a card reset.

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3-6. QAM

Test Points The QAM card contains thirteen test points (TP1 through TP13) for monitoring QAM card option. Table 3-35 lists these test points. Table 3-35. QAM Test Points

Test Point TP1

Frequency G01 – OUTPUT DEMAND G02 to 06 – V/I Converter Input Voltage

TP2

G02 to 06 – V/I Output Voltage

TP3

SETPOINT

TP4

System Common

TP5

M/A OUTPUT DEMAND

TP6

VREF (+10 VDC)

TP7

DIOB Ground

TP8

CLEAR

TP9

+ 12 VDC

TP10

+ 15 VDC

TP11

+ 15 VDC

TP12

+ 15 VA

TP13

− 15 VA

Potentiometers The QAM card contains four potentiometers (pots), on each for the demand and setpoint gain adjustments (D/A converter), and one each for the demand and setpoint zero adjustments. Table 3-36 lists each pot and its related adjustment.

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3-6. QAM

Table 3-36. QAM Potentiometer Adjustments

Pot

Adjustment

DEM ZERO (M128-1)

Adjusted to zero the Demand D/A Converter logic, for a demand of X000 (see Table 3-24).

DEM GAIN (H61-1)

Adjusted to set the amount of span for the Demand D/A Converter logic’s analog output, for a demand count of XFFF (see Table 3-24).

SP ZERO (M128-2)

Adjusted to zero the Setpoint D/A Converter logic, for a setpoint count of X000 (see Table 3-24).

SP GAIN (H61-2)

Adjusted to set the amount of span for the Setpoint D/A Converter logic’s analog output, for a setpoint count of XFA0 (see Table 3-24).

DIP Switch The QAM card contains a four segment DIP switch which is used to select Watchdog timeout periods. The range of switch selected times is determined by plug-in resistor RW. Table 3-30 lists the switch settings and the timeout periods.

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3-7. QAO

3-7. QAO Analog Output (Style 2840A21G01 through G08)

3-7.1. Description Groups 01 through 08 are applicable for use in the CE MARK Certified System The QAO card accepts four 12-bit digital signals via the DIOB and individually converts the data to analog field outputs. Each two-wire output (plus shield) has an isolated, digital-to-analog (D/A) converter. Several output ranges are provided for unipolar or bipolar voltage outputs (see Figure 3-42). The QAO interfaces to the DIOB through a rear-edge connector. The DIOB signals at this interface are defined by DIOB standards. The analog outputs are brought out to the front edge of the card.

Address

Data

Bus Control and 4 X 12 Bit Memory

Multiplexer with Optical Isolation

DAC

Output Drivers (VDC or mA)

DAC


DAC


DAC


To Field Process

Figure 3-42. QAO Block Diagram

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3-7. QAO

Digital data from the DIOB is fed to a 4-word by 12-bit memory. The data is periodically multiplexed to the appropriate point register and presented to the D/A converter. The resultant analog value is buffered and provided at the card edge for transmission to the field process. There are four points available on the QAO Card. Each point is a three-wire output comprised of negative, positive, and shield connections. The shield is tied to the negative side of the outputs. Each D/A converter (point) converts a 12-bit digital number to a current or voltage field output. These outputs may be unipolar or bipolar. Eight QAO groups are available.

•

G01 provides four, 0 to 20.475 mA current outputs. A 40 VDC supply voltage is supplied by the QAO Card.

• • • • • •

G02 provides four, 0 to 10.2375 VDC analog outputs.

•

G08 provides one analog output with a range of −10.24 to +10.235 VDC with a high-speed update.

G03 provides four analog outputs with a range of −10.24 to +10.235 VDC. G04 provides four analog outputs with a range of 0 to 5.1187 VDC. G05 provides four analog outputs with a range of −5.12 to +5.1175. G06 provides one analog output with a range of −10.24 to +10.235 VDC. G07 provides four, 0 to 20.475 mA current outputs. An external 40 VDC supply is required.

The QAO Card is a self-contained, analog-output card. Analog output subsystems consist of one or more QAO Cards and one Bus Controller; no other cards are required to perform the analog output functions. The subsystem may be expanded in increments of four points by adding QAO Cards (48 QAO Cards maximum per DIOB controller). The QAO Card complies with DIOB interface design specifications and may be used in a Q-crate assembly. Functional block diagrams of the QAO are shown in Figure 3-43 and Figure 3-45. Point block diagrams are shown in Figure 3-44 and Figure 3-46.

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3-7. QAO

Block Diagrams DIOB

Read

Point 0

Point 2 Point 3

Data

Drive

Chopper

Point 1

12 X 4 Memory MultiPlexer

Control

Read

Write

Serial Data (Same to all four points)

Clear Control

Point 0

Point 1 (Clear, Strobe) Comparator

Address

Strobe

Point 2 (Clear, Strobe) Point 3 (Clear, Strobe) Clock (Same to all four points)

Front Connector Jumper Address

Figure 3-43. QAO Card Functional Block Diagram, 5-Level

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3-7. QAO

Jumper To Invert Msb of Bipolar Data Groups

Clear

+

Strobe

Jumper Range Select V/I Converter (G01 and G07 Only)

+ Current

D/A Converter

12

Latch

Shift Register

Optical Isolation

MSB

11

−40 VDC

G01 G07

− Shield

+ Voltage

Clock Analog Offset of 1/2 Span for Bipolar Output

Buffer (Voltage Output Groups Only)

− Shield

Serial Data

Power Supply

Process Output

− 40 VDC (G01 Only) + 15 VDC + 5 VDC

Figure 3-44. QAO Point Block Diagram, 5- Level

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Driver 0

Data

Drive

Osc.

Point 0

Driver 1

Read

Point 1

Driver 2

DIOB

Point 2

Driver 3

3-7. QAO

Point 3

12 X 4 Memory Bits 0 - 10

Multiplexer

MSB (Bit 11)

Serial Data (Same to all four points) Multiplexer

Ch 3

Ch 0

Write

Read

Ch 1 Ch 2

+

Remove to invert MSB of bipolar data

Control Latch Clear

Clear

Comparator

Address

Point 0 Strobe Point 1 (Clear, Strobe) Control Point 2 (Clear, Strobe) Point 3 (Clear, Strobe) Clock (Same to all four points) Front Connector Jumper Address

Figure 3-45. QAO Card Functional Block Diagram, 6-Level and Later

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3-7. QAO

15V

+ -

10V Ref

Clear

λ Strobe

Gain Adj.

Light Bulb (Overload Protection)

Range Select Resistor

DA Converter

λ

+ -

+ shield

Buffer -10

+10

Clock

Offset Adj.

λ λ

-10V Current Output

Voltage Output

Offset Adj. +10 -10

Serial Data

Voltage Output

Current Output

φ

Power Supply

G01 - 40 V

-40 (G01 Only) ±15V +5V

+ shield

G07

Process Output Surge Protected

Figure 3-46. QAO Point Block Diagram, 6-Level

3-7.2. Specifications Output Capabilities G01: G02: G03: G04: G05: G06: G07: G08:

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0 to 20.475 mA (internal supply) 0 to +10.2375 VDC −10.24 to +10.235 VDC 0 to +5.1187 VDC −5.12 to +5.1175 VDC −10.24 + 10.235 VDC (single channel) 0 to 20.475 mA (external supply) −10.24 + 10.235 VDC (single channel, high speed update)


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3-7. QAO

Output Loading

• •

Current Outputs (G01, 7): 0 to 1KΩ resistance

• •

G01 through G07: 1.4 to 7.4 msec digital delay

Voltage Outputs (G02, 3, 4, 5, 6, 8): 0 to 20 mA Output Current with 500Ω minimum load resistance, short circuit protected.

Throughput

G08: 0.5 to 1.2 msec digital delay Note G08 should not be written to again for 1.5 msec.

Resolution 12-bit resolution (including polarity in bipolar group) Reference Accuracy (including polarity in bipolar groups) +0.05 percent of SPAN (SPAN = 20.475 mA for G01, 10.2375 VDC for G02, 20.475 VDC for G03, etc.) Temperature Coefficient

• •

40 ppm RMS of Span/°C for Voltage Outputs 50 ppm RMS of Span/°C for Current Outputs

Power Supply

• • •

Primary: +12.4 VDC minimum, +13.0 VDC nominal, +13.1 VDC maximum Backup: 12.4 VDC minimum, 13.1 VDC maximum Current: 1.3 A maximum

Electrical Environment IEEE surge withstand capability (except G08)

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3-7. QAO

Common Mode Voltage: 500 VDC or peak AC (line frequency) Data Output The analog outputs result from DIOB digital data which is presented to the D/A converters. The output values and output codes are listed below for each group. G01 Input Data (Data received from Controller WRITE to QAO)

Output Value

000X

See Note

001X

See Note

010X

80 µA

320X

4.000 mA

400X

5.120 mA

800X

10.240 mA

C00X

15.360 mA

FFEX

20.470 mA

FFFX

20.475 mA X = Any digit

Note Accuracy specifications do not apply below 4 mA. Do not operate below 80µA. G02 Input Data (Data received from Controller WRITE to QAO)

Output Value

000X

0 VDC

001X

+2.50 mV

400X

+2.5600 VDC

800X

+5.1200 VDC

C00X

+7.6800 VDC

FFEX

+10.2350 VDC

FFFX

+10.2375 VDC X = Any digit

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3-7. QAO

G03 Input Data (Data received from Controller WRITE to QAO)

Output Value

800X

−10.2400 VDC

C00X

−5.1200 VDC

FFFX

-0.00500 VDC

000X

0.0000 VDC

001X

+0.0050 VDC

400X

+5.1200 VDC

7FFX



Output Value

000X

0 VDC

001X

+1.2500 mV

400X

+1.2800 VDC

800X

+2.5600 VDC

C00X

+3.8400 VDC

FFEX

+5.1175 VDC

FFFX



Output Value

800X

−5.1200 VDC

C00X

−2.5600 VDC

FFFX

−0.0025 VDC

000X

0.0000 VDC

001X

+0.0025 VDC

400X

+2.5600 VDC

7FFX


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3-7. QAO


Output Value

800X

−10.2400 VDC

C00X

−5.1200 VDC

FFFX

−0.0050 VDC

000X

0.0000 VDC

001X

+0.0050 VDC

400X

+5.1200 VDC

7FFX



Output Value

000X

See Note

001X

See Note

010X

80 µA

320X

4.000 mA

400X

5.120 mA

800X

10.240 mA

C00X

15.360 mA

FFEX

20.470 mA

FFFX

20.475 mA X = any digit

Note Accuracy specifications do not apply below 4 mA. Do not operate below 80µA.

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3-7. QAO


Output Value

800X

−10.2400 VDC

C00X

−5.1200 VDC

FFFX

−0.0050 VDC

000X

0.0000 VDC

001X

+0.0050 VDC

400X

+5.1200 VDC

7FFX


Figure 3-47 shows the output value curves. The input data codes are plotted against the output voltage. This graph applies to bipolar voltage groups (G03, G05, G06 and G08). Figure 3-48 shows the output value curves for unipolar current groups (G01 and G07). The input data codes are plotted against output current. Figure 3-49 shows the output value curves for unipolar voltage groups (G02 and G04). The input data codes are plotted against output voltage.

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3-7. QAO

Hexadecimal Value (Two’s Complement)

1000

FFF

E00

C00

C18

A00

830

7D0

800

800

7FF

600

400

3E8

200 −10.240 V −5.120 V

G03, G06

−10

−8

−6

−4

−2

0

+2

+4

+6

+8

+10 +10.235

G05, G08

−5

−4

−3

−2

−1

0

+1

+2

+3

+4

+5 +5.127

Bipolar Voltage (V)

Figure 3-47. QAO Bipolar Output Voltage Curves

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3-7. QAO

Hexadecimal Value (Binary) FFF

FAO

E00

C00

A00 960 800

600

400 320 200

000 G01, G07

0

4

8

12

16

20

20.475

Unipolar Current (mA) NOTE Accuracy Specifications Do Not Apply in Shaded Area

Figure 3-48. QAO Unipolar Output Current Curves

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3-7. QAO

Hexadecimal Value (Binary) FFF

FAO

E00

C00

A00

800 7D0 600

400

200

000 G02

0

2

4

6

8

10

10.2375

G04

0

1

2

3

4

5

5.1187

Figure 3-49. QAO Unipolar Output Voltage Curves

3-7.3. Card Addressing Address Jumpers The QAO card address is established by six jumpers on the top, front, card-edge connector. The insertion of a jumper encodes a “1” on the address line.

3-7.4. Controls and Indicators If the QAO Card is not periodically updated, the card resets. The update period is set by four dual-in-line (DIP) switches as given in Table 3-37. The QAO Card components are shown in Figure 3-50.

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3-7. QAO

Power LED Update Period Switch Figure 3-50. QAO Card Components

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3-7. QAO

Table 3-37. QAO Card Reset Switch Position (Update Period) Dip Switch A

B

C

D

Reset Time

0

0

0

0

62 ms + 20 percent

0

0

1

0

125 ms + 20 percent

0

1

0

0

250 ms + 20 percent

0

1

1

0

500 ms + 20 percent

1

0

0

0

1 sec + 20 percent

1

0

1

0

2 sec + 20 percent

1

1

0

0

4 sec + 20 percent

1

1

1

0

8 sec + 20 percent

X

X

X

1

No time out, data latched (X = 0 or 1)

3-7.5. Field Connections The analog outputs are brought out to the front edge of the card. The QAO outputs are three wire bundles, and use the same pinouts for all groups. The contact allocations are shown in Table 3-38. Table 3-38. QAO Analog Output Contact Allocations

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Point

Pin Out

Point 0

5A – (+ output) 3A – (− output) 3B – (shield)

Point 1


Point 2


Point 3



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3-7. QAO


TERMINAL BLOCK #8-32 SCREW CARD

POINT 3

POINT 2

POINT 1

POINT 0

19B

A

19A

18

17B

17

(+)

17A

16

(+)

(S)

15B

15

(SHIELD)

(−)

15A

14

(−)

13B

13

(+)

13A

12

(+)

(S)

11B

11

(SHIELD)

(−)

11A

10

(−)

9B

09

(+)

9A

08

(+)

(S)

7B

07

(SHIELD)

(−)

7A

06

(−)

5B

05

(+)

5A

04

(+)

(S)

3B

03

(SHIELD)

3A

02

(−)

1B

01

(−)

POINT 3

POINT 2

POINT 1

POINT 0

1A

EDGE CONNECTOR


Figure 3-51. QAO Wiring Diagram

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3-7. QAO


CARD 1A

A

A

1B

1

1

3A

2

2

(-)

3B

3

3

(SHIELD)

5A

4

4

(+)

5B

5

5

7A

6

6

(−)

7B

7

7

(SHIELD)

8

(+)

9A

8

9B

9

9

11A

10

10

(−)

11B

11

11

(SHIELD)

13A

12

12

(+)

13B

13

13

15A

14

14

(−)

15B

15

15

(SHIELD)

17A

16

16

(+)

17B

17

17

19A

18

18

19B

PE

PE

POINT 0

POINT 1

POINT 2

POINT 3

EDGE-CONNECTOR

Note QAO groups 1 and 7 must have the shield and return connected together and to earth ground at the B cabinet as shown.

Figure 3-52. QAO CE MARK Wiring Diagram (Groups 1 & 7)

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3-7. QAO


CARD 1A

A

A

1B

1

1

3A

2

2

(-)

3B

3

3

(SHIELD)

5A

4

4

(+)

5B

5

5

7A

6

6

(−)

7B

7

7

(SHIELD)

9A

8

8

(+)

9B

9

9

11A

10

10

(−)

11B

11

11

(SHIELD) (+)

13A

12

12

13B

13

13

15A

14

14

(−)

15B

15

15

(SHIELD)

17A

16

16

(+)

17B

17

17

19A

18

18

19B

PE

PE

POINT 0

POINT 1

POINT 2

POINT 3

EDGE-CONNECTOR

Note QAO Groups 2 through 6 and Group 8 may have the shield and return connected together and to earth ground in the field or at the B cabinet.

Figure 3-53. QAO CE MARK Wiring Diagram (Groups 2 through 6, & 8)

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3-8. QAV

3-8. QAV Analog Input Point (Syle 7379A21G01 through G09)

3-8.1. Description Groups 01through G09 are applicable for use in the CE MARK Certified System The QAV card converts an analog field signal to digital data (see Figure 3-54). (For new applications, a QAX card is recommended). The digital data is the summation of a frequency that has been counted for a time period. The time period is a multiple of the power line frequency (50 or 60 Hz). DIOB Data

Address

Data Buffer RAM

Address Decoder

Control

µC, Counter and Control Circuits

Transformer Isolation

...


Channel 1 Voltage to Frequency Converter

...


(+) (-) SHD

...

(+) (-) SHD

Six Sets of Analog Field Inputs

Figure 3-54. QAV Block Diagram

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3-8. QAV

Each QAV card contains six individually isolated voltage-to-frequency converter circuits (channels). The output of each input circuit is processed by a common microcomputer and the resulting digital data is multiplexed to the Distributed Input/Output Bus (DIOB) as a 13-bit word. Figure 3-55 shows a typical control system configuration using QAV cards. The QTB card is necessary for applications where large variations of power line frequency exist to obtain a high normal mode rejection. Up to 30 QAV cards (180 channels) can be used with one DIOB controller. Cards equipped with the thermocouple temperature compensation feature use channel 6 for the on-card temperature sensor. The channel is read every time the card performs an auto-calibration cycle. The on-card temperature sensor eliminates the need for external sensor boards, and ensures field temperature accuracy. The QAV card uses an electrical isolation circuit (transformer) to separate the analog input from the digital counting circuits. The isolation circuit provides power for each analog input channel in addition to precise timing from a stable frequency which is generated on the digital side of the QAV card circuits. Each analog input circuit contains circuitry for signal conditioning, biasing, auto-zero and gain correction, open thermocouple detection (not available on G04 and G05 QAV cards) and a clocked voltage-to-frequency converter. Offset and gain correction factors are calculated on a periodic basis by the QAV card microcomputer. The frequency of the offset and gain calibration cycle is determined by a constant which has been programmed into the memory of the system controller. Two known potentials on the analog section of the QAV card are used as standards for offset and gain calibrations. One standard is a 0 VDC (shorted input), which is used to determine the offset correction factor. The second calibrating potential (gain) is derived from a separate, stable voltage reference which is set approximately −150% of the maximum expected analog input value. The gain correction factor is compared to a 16-bit calibration constant which is programmed into the memory of the system controller at the time of factory card calibration. The calibration constant is necessary because the QAV card has no mechanical adjusting devices (such as potentiometers, and so on). This method yields a trimmer (or pot) -less calibrating method.

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3-8. QAV

DIOB CONTROLLER

QTB

POWER LINE INPUT

QAV #1

FIELD INPUTS

QAV #30

FIELD INPUTS

DIOB

Figure 3-55. QAV Typical Control System Using QAV Cards

The QAV card microcomputer is programmed to “limit check” (reasonability check) the offset correction factor for each analog input channel. Failure of the reasonability check causes bit 14 (offset over-range) of the output data for that channel to be set to a logical zero. A failure on two or more channels causes bit 15 (IMOK bit) of the output data to be set to a logical zero which indicates card trouble to the system controller. Note The two-channel failure feature is available on QAV cards at levels 1QAV through 4QAV. Bit 15 is also set to zero during the power-up routine of the QAV card. The QAV microcomputer is reset at this time and conversion of data is begun when the reset control is removed and the QAV card buffer memory is updated. Bit 15 is reset to a logical 1 after a warm-up pause is completed. The length of the warm-up pause is determined by a programmed constant in the memory of the system controller.

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3-8. QAV

•

G01 and G07 1: −5 to +20 mVDC (−20 to +20 mVDC at reduced accuracy 2); 500 Ω maximum source impedance.

•

G02 and G081: −12.5 to +50 mVDC (−50 to +50 mVDC at reduced accuracy2); 500 Ω maximum source impedance.

•

G03 and G091: −25 to +100 mVDC (−100 to +100 mVDC at reduced accuracy2); 1 KΩ maximum source impedance.

•

G04: −12.5 to +50 mVDC (−50 to +50 mVDC at reduced accuracy2); 500 Ω maximum source impedance (G04 is not available with the Open Thermocouple Detection feature).

•

G05: −25 to +100 mVDC (−100 to +100 mVDC at reduced accuracy2); 1 KΩ maximum source impedance (G05 is not available with the Open Thermocouple Detection feature).

•

G06: −12.5 to +50 mVDC (−50 to +50 mVDC at reduced accuracy2); 1 KΩ maximum source impedance.

1Level

8 QAV and later artwork support groups 1-3 without “On-Card” thermocouple compensation. Groups 7-9 are identical to Level 6 QAV groups 1-3 with “On-Card” thermocouple compensation. If “OnCard” thermocouple compensation is required, order groups 7-9 in place of groups 1-3 respectively. reference accuracy is +0.20 percent of the upper range value (+10 µV, +1/2 LSB at 99.7 percent confidence.

2Reduced

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3-8. QAV

3-8.2. Features Each QAV card has the following features:

• • • • •

IEEE surge withstand capability

• • • • • •

Common mode rejection

Auto zero, auto gain correction Electrical isolation on all channels On-card digital memory (buffer) Open thermocouple detection (This feature is not available on G04 and G05 QAV cards.)

Normal mode rejection Automatic reasonability test (shorted input) Auto-conversion check Jumper selectable 50/60 Hz operation On-card thermocouple temperature compensation (Available on QAV cards at level 6 QAV)

The QAV card is designed to be mounted in a standard Q-line card cage. Connection to the control system is made by a 34-pin rear-edge backplane connector which interfaces the UIOB or DIOB and a 56-pin front-edge connector, which connects to field terminals.

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3-8. QAV

Block Diagram

VIN

+

ANALOG INPUT (VIN)

LOW PASS FILTER

−

CLAMP VBIAS

SH

R2

R1

VOLTAGE REFERENCE

(MULTI PLEXER SOLID STATE SWITCH)

-

A block diagram of one of the six analog sections of the QAV card is shown in Figure 3-56. Figure 3-57 shows a block diagram of the QAV digital circuits. Figure 3-58 shows a flow diagram of the QAV card analog-to-digital conversion process.

R3 VREF

-

R4 PREAMPLIFIER

+12V

-

C1

I1

−12V

-

(−) POWER SUPPLY

INTEGRATOR

MULTIPLEXER CONTROLLER

-

-

SYNCHRONOUS COMPARATOR

-

(+)

-

CLOCK +12V

I REF

-

X1

CAPACITOR DISCHARGE

1

-

T1

PSD (250 KHZ) FREQUENCY INPUT (FI1-FI6)

D1

-

C2

-

R5

-

-

-

Figure 3-56. QAV Analog Input Circuits Block Diagram

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3-8. QAV

ADDRESS JUMPERS

ANALOG POWER CONTROL

PSD POWER SUPPLY DRIVE-250 KHZ

CL

RAM LOAD ENABLE P15

AOK

UADD0-7 DATA-DIR

ADDRESS DECODER

USYNC HI-LO DATA GATE

TADD0-2 HI-LO

UDAT0-7 DEV BUSY

DOUT P13

I/O

LEVEL SHIFT AND BUFFER

TUSYNC RD0-7

P24 to P27 CL WR SS

MICROCOMPUTER

BUFFER RAM LOAD CONTROLLER

BUS (DB0-7)

PSEN P20

PROGRAM MEMORY

ADDRESS

LEN

ADDRESS LATCH

BUFFER RAM

WD0-7

D I O B

BUFFER LATCH

CONTROL ADDRESS

I/O A0 A1

P10-12

P14

TRESET

POWER UP AND RESET

COUNTERS (6)

+5V

5 VOLT REGULATOR +12V

(FI1-FI6)

Figure 3-57. QAV Card Digital Circuits Block Diagram

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3-8. QAV

RESET TEST WARM-UP CTR SET “IMOK”

INITIALIZE TEST CALIBRATION CTR READ OFFSET (COS)

COS OFFSET CONVERSI ON = VBIAS CONVERSI ON DATA

READ* INPUT (CX) READ REF (COS) (CX − COS) [COS − CREF] LIMIT OVERRANGE RESET CALIBRATION (COUNTER) A(CX − COS)

TEST REASONABILITY

CALCULATE SLOPE (A)

SET FLAG(S)S OUTPUT TO BUFF RAM

*TIME BASE CORRECTION

Figure 3-58. QAV Analog-to-Digital Conversion Process Flowchart

3-8.3. Specifications Inputs Point Sampling Rate (samples/second):

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3-8. QAV

Note QAV cards with prefixes of 5 or greater are selected for 50 or 60 Hz operation by jumper. The sampling rate is 4 per second and the sample period is 0.2 seconds for both 50 or 60 Hz operation.

• •

4 at a power line frequency of 60 Hz 3.4 at a power line frequency of 50 Hz Note Once every 32 conversion, auto gain and auto zero calibration are performed; 8 seconds apart in 60 Hz systems, and 9.4 seconds apart in 50 Hz systems.

Resolution: 13-bits (includes polarity bit) Input Channel Sample Period:

• •

0.20 seconds at a power line frequency of 60 Hz 0.24 seconds at a power line frequency of 50 Hz

Normal Mode Voltage

•

Surge: Meets IEEE/SWC test specifications without damage; however, the accuracy of data is reduced during, and up to 10 secs. after the removal of the surge.

•

Continuous: An overrange of +120 VDC or 120 VAC rms at 50 or 60 Hz will not damage the input channels; however, a sustained overrange can affect subsequent data for several minutes following the removal of the overrange voltage.

Normal Mode Rejection

•

60 dB at 50 or 60 Hz using QTB card line frequency tracking or at 50 or 60 Hz +0.5 percent without QTB card

•

30 dB at 50 Hz +5 percent or 60 Hz +5 percent without QTB card line frequency tracking Note The input (peak-to-peak) AC voltage must not exceed 100 percent of the upper range value for specified accuracy and normal mode rejection.

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3-8. QAV

Common Mode Voltage

•

Surge: Meets IEEE/SWC test specifications without damage; however, the accuracy of data is reduced during, and up to 10 seconds following the removal of the surge.

•

Continuous: A maximum of +500 VDC or peak AC can be applied without damage.

Common Mode Rejection

•

120 dB at DC and power line frequency and its harmonics with QTB card line frequency tracking or at 50 or 60 Hz +0.5 percent without QTB card

•

100 dB for nominal line frequency at +5 percent and harmonics without QTB card line frequency tracking Note Common mode rejection does not apply if the peak AC value exceeds 200,000 % of upper range value.

Input Impedance

• •

107 Ω/Volt 103 Ω in overload

Reference Accuracy (per SAMA Standard PMC 20)

•

+0.10 percent of the upper range value (+10 µV); +1/2 of the Least Significant Bit (LSB) at 99.7 percent confidence.

•

Reference Conditions: 25°C + 1°C Ambient Temperature; 50 percent +2 percent of relative humidity; 0 V common mode; 0 V normal mode

• •

0.002 percent per month (typical) 0.02 percent long term (typical)

Drift

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3-8. QAV

Power Requirements Minimum Primary Voltage:

12.4 VDC

Optional Backup:

12.4 VDC

Nominal + 13.0 VDC --

Nominal Power Supply Current: Power Used:

Maximum 13.1 VDC 13.1 VDC

Maximum

1.0 ADC

1.2 ADC

13.0 Watts

15.7 Watts

Input Signal Requirements

•

G01 and G07 1cards: −5 to +20 mVDC, −20 to +20 mVDC at reduced accuracy2

•

G02 and G081 cards: −12.5 to +50 mVDC, −50 to +50 mVDC at reduced accuracy2

•

G03 and G091 cards: −25 to +100 mVDC, −100 to +100 mVDC at reduced accuracy2

• • •

G04 cards: −12.5 to +50 mVDC, −50 to +50 mVDC at reduced accuracy2 G05 cards: −25 to +100 mVDC, −100 to +100 mVDC at reduced accuracy2 G06 cards: −12.5 to +50 mVDC, −50 to +50 mVDC at reduced accuracy2

Field signals are input to a standard Q series front-edge connector (see Figure 3-59). The DIOB address and DIOB address protection jumpers are also located in this connector. Each field signal input requires a plus, minus and shield pin.

1Level

8 QAV and later artwork support groups 1-3 without “On-Card” thermocouple compensation. Groups 7-9 are identical to Level 6 QAV groups 1-3 with “On-Card” thermocouple compensation. If “OnCard” thermocouple compensation is required, order groups 7-9 in place of groups 1-3 respectively reference accuracy is +0.20 percent of the upper range value (+10 µV, +1/2 LSB at 99.7 percent confidence.

2Reduced

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M0-0053

3-8. QAV

SOLDER SIDE

COMPONENT SIDE

UNUSED

1A

1B

UNUSED

2A

2B

UNUSED

POINT 0 SHIELD

3A

3B

POINT 0 + INPUT UNUSED

POINT 0 – INPUT SIGNAL

UNUSED

4A

4B

POINT 1 − INPUT

5A

5B

POINT 1 SHIELD

UNUSED

6A

6B

UNUSED

POINT 1 + INPUT

7A

7B

POINT 2 – INPUT

UNUSED

8A

8B

UNUSED

POINT 2 SHIELD

9A

9B

POINT 2 + INPUT

UNUSED

10A

10B

UNUSED

POINT 3 − INPUT

11A

11B

POINT 3 SHIELD

UNUSED

12A

12B

UNUSED

POINT 3 + INPUT

13A

13B

POINT4 – INPUT

UNUSED

14A

14B

UNUSED

POINT 4 SHIELD

15A

15B

POINT 4 + INPUT

UNUSED

16A

16B

UNUSED

POINT 5 − INPUT

17A

17B

POINT 5 SHIELD

UNUSED

18A

18B

UNUSED UNUSED

POINT 5 + INPUT

19A

19B

DIOB ADDRESS PROTECTION GROUND

20A

20B

DIOB ADDRESS PROTECTION

UNUSED

21A

21B

UNUSED

UNUSED

22A

22B

UNUSED

UNUSED

23A

23B

UNUSED

ADDRESS LINE A3 GROUND

24A

24B

ADDRESS LINE A3


25A

25B

ADDRESS LINE A4


26A

26B

ADDRESS LINE A5


27A

27B

ADDRESS LINE A6


28A

28B

ADDRESS LINE A7 JUMPER MUST BE IN PLACE FOR PROPER CARD OPERATION

Figure 3-59. QAV Card Front-Edge Connector Pin Assignments

Output Signal Requirements Output signal requirements are specified for DIOB requirements. DIOB connection is made to the QAV card through the Q-card backplane connector to connector pins located on the rear-edge of the card (see Figure 3-60).

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3-8. QAV

3-8.4. Card Addressing and Data Output Address Jumpers The QAV card address is established by five jumper fixtures which are located in the front-edge connector. The insertion of a jumper encodes a “1” on the selected address line (ADD3 through ADD7) which when matched by the DIOB address signals selects the QAV card by the system controller. Figure 3-59 shows the pin configuration of the front-edge connector. The “B” pins of the connector are located on the component side and the “A” pins are located on the solder side of the card.

COMPONENT SIDE

SOLDER SIDE

+V PRIMARY

2

1

+V PRIMARY

+V BACKUP

4

3

+V BACKUP

GROUND

6

5

GROUND

UADD1

8

7

UADD0

UADD3

10

9

UADD2

UADD5

12

11

UADD4

UADD7

14

13

UADD6

DATA-DIR

16

15

HI-LO

DATA-GATE

18

17

UNIT*

DEV-BUSY

20

19

GROUND

UDAT1

22

21

UDAT0

UDAT3

24

23

UDAT2

UDAT5

26

25

UDAT4

UDAT7

28

27

UDAT6

UFLAG*

30

29

GROUND

USYNC

32

31

UCAL*

GROUND

34

33

UCLOCK*

POWER

CARD ADDRESSING

CONTROL

BIDIRECTIONAL DATA BUS

CONTROL

* NOT USED ON QAV CARD

Figure 3-60. QAV Card Rear-Edge Connector Pin Assignments

QAV card addresses are programmed in groups of eight addresses in order to maintain the address recognition circuits at a minimum. However, cards equipped with the thermocouple temperature compensation feature use all eight addresses. Address 7 provides the temperature data, and address 8 is used during card calibration.

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3-8. QAV

The addressing method allows up to 30 QAV cards to be used which means that 180 analog input channels can be provided (30 possibilities at a maximum of 6 channels per card yields 180 channels per DIOB controller). Address protection is provided by a jumper insert on the front-edge connector pin pair (20A and 20B). This contact has been machined to be shorter than the other front-edge contacts so that it disconnects before the other contacts when the front card-edge connector is removed from the QAV card. Output Data Figure 3-61 shows a general, 16-bit, QAV card output data pattern format. The first 12 bits (0 through 11) are binary data obtained through a software routine in the QAV card microcomputer circuit. The actual binary data that is sent to the system controller over the DIOB is calculated by the microcomputer using data from a precision voltage network and from an analog-to-digital converter circuit. Data from the precision voltage network is used to adjust the converted analog input (digital data) for offset and gain correction before it is output to the DIOB as point data. Bit 12 is an overrange bit and bit 13 is a sign bit. A logic one signal at bit 12 indicates that the count data is in the positive overrange when bit 13 is at a logic zero and that the count data is in the negative range when bit 13 is a logical one. A logical zero at bit 12 indicates that the count data is in the negative overrange when bit 13 is a logical one and in the positive range when bit 13 is a logical zero. A logical one at bit 13 indicates the count is in the negative range and a logical zero at bit 13 indicates that the count is in the positive range.

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3-8. QAV

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

OVERRANGE BIT BINARY DATA

1 = COUNT IS IN POSITIVE OVERRANGE WHEN SIGN BIT 13 = 0, AND IN NEGATIVE RANGE WHEN SIGN BIT 13 = 1

SIGN BIT 1 = COUNT IS NEGATIVE

FLAG BIT SET BY QAV CARD MICROCOMPUTER 1 = OFFSET DATA OBTAINED DURING AUTO CALIBRATION IS WITHIN REASONABLE LIMITS

FLAG BIT (SET BY MICROCOMPUTER) 1 = HARDWARE IS OPERATING PROPERLY

Figure 3-61. QAV Card Output Data Pattern Format

Bits 14 and 15 are flag bits. A logical one at bit 14 indicates that the offset factor data that was obtained during the auto-zero calibration microcomputer routine is within reasonable limits and a logical zero indicates unreasonable auto-zero data. A logical one at bit 15 (called IMOK bit) indicates that the hardware is operating properly (power is present, warm-up is complete, and the controller is operating). A logical zero at bit 15 indicates hardware trouble or that the offset factors from the auto-zero calibration are unreasonable on more than one input channel. Note Multiple channel offset errors will not set bit 15 on QAV cards with prefixes of 5 or greater.

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3-8. QAV

Table 3-39 shows the nomenclature and the hexadecimal ranges for the QAV card output data. Note that bits 14 and 15 are set by QAV card microcomputer; therefore, the positive range to negative transitions occurs in 14 bits. Table 3-39. QAV Card Output Data Ranges

Data Classification

Output Data Hexadecimal Code

Zero Input

C000

Positive Range

C001 to CFFF

Positive Full Scale

D000

Positive Overrange

D001 to DFFF

Negative Overrange

E001 to EFFF

Negative Full Scale

F000

Negative Range

F001 to FFFF

Out of Range Offset

8000 to BFFF

Card Hardware Trouble

0000 to 7FFF

3-8.5. Controls and Indicators (Level 6 and earlier) The (Level 6 and earlier) QAV components are shown in Figure 3-62.

LED J1,J2

J3,J4

Figure 3-62. QAV Card Components (Level 6 and earlier)

Light Emitting Diodes (LED) The QAV card has one LED which is used to indicate power “on”.

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3-8. QAV

Jumpers Table 3-40 lists the jumper numbers, locations and functions of the jumpers used on the QAV card. Table 3-40. QAV Card Jumpers, Locations and Functions (Level 6 and earlier)

Function (Jumper in Place)

Jumper Number J1

For future use

J2

ORs signal IMOK (P13) to W274-2 Inverter

J31,2

Installed for 50 Hz systems

J41,2


J51

For future use

J63

For future use

1 Jumpers 2 The

QAV card operates on its own time base when jumpers J3 or J4 are not inserted.

3 Jumper

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J3, J4 and J5 are not used on QAV cards with prefixes lower than 5.

J6 is not shown on cards with prefixes lower than 5.


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3-8. QAV

3-8.6. Controls and Indicators (Level 8 and later)

LE1

SW

1 2 3 4

LE2

Figure 3-63. QAV Card Components (Level 8 and later)

Switches The (Level 8 and later) QAV card uses a four-position DIP switch (see Figure 3-63 for the location of the switch). The definitions of the switches are as follows: Table 3-41. QAV Jumper Configuration

Configuration

SW1

SW2

SW3

SW4

50Hz operation

X

ON

OFF

X

60Hz operation

X

OFF

ON

X

No QTB1

X

ON

ON

X

1The

QTB card is necessary in installations where large variations of the power line frequency exist to provide for large normal mode rejection. X = Reserved (Don’t Care) Notes Any other switch combination is not valid and the QAV card will not operate. The QAV also has several factory preset jumpers. Changing these jumpers will affect calibration, therefore, no changes are recommended.

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3-8. QAV

LEDs The QAV card has two LED’s (see Figure 3-63). LE1 indicates that power is applied to the board. LE2 is used during the initial calibration of the board. For on-line applications, LE2 will illuminate for about 1/2 second during power-up and will remain off thereafter. Should this LED remain on or flash, return the board to Westinghouse for repair. Notes Before returning the board for repair, check the following: 1. Ensure that the DIOB power supplies are in tolerance. 2. Ensure that the DIP switch is set according to the valid configurations in the previous tables.

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3-8. QAV

Thermocouple Information Table 3-42 shows the standard WDPF thermocouple coefficient definitions. Coefficients may also be user-defined. For additional information on selecting these coefficients, refer to the CI record field discussion in “Record Types User’s Guide” (U0-0131).

Table 3-42. QAV Thermocouple Coefficient Definitions (WDPF System) Thermocouple Type

Coefficients

B

70% Platinum + 30% Rhodium or 94% Platinum + 6% Rhodium 427-1093°C 800-2000°F

C0 = 0.3516470E + 03 C1 = 0.6138849E + 03 C2 = −0.1539774E + 03

C3 = 0.3359373E + 02 C4 = −0.4051826E + 01 C5 = 0.2003933E + 00

E

Chromel/Constantan −18-982°C 0-1800°F

C0 = 0.3167283E + 02 C1 = 0.3030628E + 02 C2 = −0.3344949E + 00

C3 = 0.6849588E − 02 C4 = −0.6975349E − 04 C5 = 0.2923653E − 06

J

Iron/Constantan −96-760°C −140-1400°F

C0 = 0.3112531E + 02 C1 = 0.3607027E + 02 C2 = −0.4288617E + 00

C3 = 0.2261382E − 01 C4 = −0.5174379E − 03 C5 = 0.3972783E − 05

C0 = 0.3034473E + 02 C1 = 0.4403191E + 02 C2 = 0.1615839E + 00

C3 = −0.1616257E − 01 C4 = 0.4401109E − 03 C5 = −0.3599650E − 05

K

Chromel/Alumel −18-1093°C 0-2000°F (The upper range may be extended to 2500 with less accuracy) R

Platinum + 13% Rhodium 260-1093°C 500-2000°F

C0 = 0.8362848E + 02 C1 = 0.2273716E + 03 C2 = −0.1248286E + 02

C3 = 0.1206254E + 01 C4 = −0.7422128E − 01 C5 = 0.1899300E − 02

S


C0 = 0.1180344E + 03 C1 = 0.1985918E + 03 C2 = −0.1973096E − 01

C3 = −0.5009329E + 00 C4 = 0.4110488E − 01 C5 = −0.1155794E − 02

T

Copper/Constantan 46-399°C −50-750°F

C0 = 0.3189224E + 02 C1 = 0.4669328E + 02 C2 = −0.1325739E + 01

C3 = 0.6962067E − 01 C4 = −0.2327808E − 02 C5 = 0.3330646E − 04

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3-8. QAV

When selecting a Q-card or Ovation I/O module for a thermocouple, you need to select the proper card/group number to ensure an accurate reading. The information shown below provides the millivolt (MV) to temperature range for 20, 50, and 100 mv cards. This range limitation exists for Ovation I/O modules 1C31113G01/1C31116G04, 1C31113G02/1C31116G04, and 1C31113G03/1C31116G04 as well as Q-Line I/O cards: QAI, QAV, and QAX. Note that for a low millivolt reading, you could use a G01, G02 or G03 card, but better accuracy is obtained by using a G01, the group that provides a better fit. Do not use lower millivolt cards for the higher temperature (millivolt) readings. The coefficients listed in Table 3-42 are the recommended coefficients for the ranges shown for WDPF systems. The coefficients listed in Table 3-43 are the recommended coefficients for the ranges shown for Ovation systems.

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Table 3-43. QAV Thermocouple Coefficient Definitions (Ovation System) Thermocouple Type

B or TB

400 to 1100 Degrees C 800 to 2000 Degrees F

Actual range in MV / TEMP 0.000 to 13.814 0.006 to 13.814

(0 to 1820) (0 to 3308)

Best Fit 20 mv card 20 mv card

Fahrenheit COEF_1 = 3.5164700E+02 COEF_2 = 6.1388490E+05 COEF_3 = -1.5397740E+08 COEF_4 = 3.3593730E+10 COEF_5 = -4.0518260E+12 COEF_6 = 2.0039330E+14

Centigrade COEF_1 = 1.7758167E+02 COEF_2 = 3.4104717E+05 COEF_3 = -8.5543000E+07 COEF_4 = -8.5543000E+07 COEF_5 = -8.5543000E+07 COEF_6 = 1.1132961E+14

COEF_7 = -2.0E-06 COEF_8 = 0.0

COEF_7 = -2.0E-06 COEF_8 = 0.0

Thermocouple Type

E or TE

M0-0053

Standard Temperature Range

Standard Temperature Range -18 to 286 Degrees C 0 to 550 Degrees F -18 to 661 Degrees C 0 to 1200 Degrees F -18 to 1000 Degrees C 0 to 1832 Degrees F

Actual range in MV / TEMP -9.835 to 19.945 -9.835 to 19.945 -9.835 to 49.992 -9.835 to 49.956 -9.835 to 76.358 -9.835 to 76.358

(-270 to 286) (-450 to 548) (-270 to 661) (-450 to 1221) (-270 to 1000) (-450 to 1832)

Best Fit 20 mv card 20 mv card 50 mv card 50 mv card 100 mv card 100 mv card

Fahrenheit COEF_1 = 3.1672830E+01 COEF_2 = 3.0306280E+04 COEF_3 = -3.3449490E+05 COEF_4 = 6.8495880E+06 COEF_5 = -6.9753490E+07 COEF_6 = 2.923653E0+08

Centigrade COEF_1 = -1.8176111E-01 COEF_2 = 1.6836822E+04 COEF_3 = -1.8583050E+05 COEF_4 = 3.8053267E+06 COEF_5 = -3.8751939E+07 COEF_6 = 1.6242517E+08

COEF_7 = -1.0939E-03 COEF_8 = 3.365E-05

COEF_7 = -1.71E-05 COEF_8 = 6.057E-05


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3-8. QAV

Table 3-43. QAV Thermocouple Coefficient Definitions (Ovation System) (Cont’d) Thermocouple Type J or TJ

-18 to 365 Degrees C -140 to 700 Degrees F -18 to 760 Degrees C -140 to 1400 Degrees F

Actual range in MV / TEMP -8.096 to 19.971 -8.137 to 19.977 -8.096 to 42.922 -8.137 to 42.922

(-210 to 366) (-350 to 691) (-210 to 760) (-350 to 1400)

Best Fit 20 mv card 20 mv card 50 mv card 50 mv card

Fahrenheit COEF_1 = 3.112531E+01 COEF_2 = 3.6070270E+04 COEF_3 = -4.2886170E+05 COEF_4 = 2.2613820E+07 COEF_5 =-5.1743790E+08 COEF_6 = 3.9727830E+09

Centigrade COEF_1 = -4.8593889E-01 COEF_2 = 2.0039039E+04 COEF_3 = -2.3825650E+05 COEF_4 = 1.2563233E+07 COEF_5 = -2.8746550E+08 COEF_6 = 2.2071017E+09

COEF_7 =-9.256E-04 COEF_8 = 2.862E-05

COEF_7 = -9.76E-06 COEF_8 = 5.1516E-05

Thermocouple Type K or TK

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Standard Temperature Range -18 to 480 Degrees C 0 to 900 Degrees F -18 to 1230 Degrees C 0 to 2250 Degrees F -18 to 1370 Degrees C 0 to 2500 Degrees F

Actual range in MV / TEMP -6.458 to 19.959 6.456 to 19.978 6.458 to 49.988 6.456 to 49.996 -6.458 to 54.875 -6.456 to 54.845

(-270 to 484) (-450 to 904) (-270 to 1232) (-450 to 2250) (-270 to 1372) (-450 to 2500)

Best Fit 20 mv card 20 mv card 50 mv card 50 mv card 100 mv card 100 mv card

Fahrenheit COEF_1 = 3.0344730E+01 COEF_2 = 4.4031910E+04 COEF_3 = 1.615839E+05 COEF_4 = -1.616257E+07 COEF_5 = 4.4011090E+08 COEF_6 = -3.599650E+09

Centigrade COEF_1 = -9.1959444E-01 COEF_2 = 2.4462172E+04 COEF_3 = 8.9768833E+04 COEF_4 = -8.9792056E+06 COEF_5 = 2.4450606E+08 COEF_6 =- 1.9998056E+09

COEF_7 = -7.259E-04 COEF_8 = 2.243E-05

COEF_7 = -8.14E-06 COEF_8 = 4.0374E-05


M0-0053

3-8. QAV

Table 3-43. QAV Thermocouple Coefficient Definitions (Ovation System) (Cont’d) Thermocouple Type R or TR

260 to 1100 Degrees C 500 to 2000 Degrees F

Actual range in MV / TEMP 0.000 to 19.998 0.089 to 19.997

(0 to 1684) (0 to 3063)



Centigrade COEF_1 = 2.8682489E+01 COEF_2 = 1.2631756E+05 COEF_3 = -6.9349222E+06 COEF_4 = 6.7014111E+08 COEF_5 = -4.1234044E+10 COEF_6 = 1.0551667E+12

COEF_7 =-1.084E-04 COEF_8 = 3.24E-06

COEF_7 = 4.72E-06 COEF_8 = 5.832E-06

Thermocouple Type S or TS

Standard Temperature Range 400 to 1100 Degrees C 750 to 2000 Degrees F

Actual range in MV / TEMP 0.000 to 18.698 -0.092 to 18.696

(0 to 1768) (0 to 3214)


Fahrenheit COEF_1 = 1.1803440E+02 COEF_2 = 1.9859180E+05 COEF_3 = -1.9730960E+04 COEF_4 = -5.0093290E+08 COEF_5 = 4.1104880E+10 COEF_6 = -1.1557940E+12

Centigrade COEF_1 = 4.7796889E+01 COEF_2 = 1.1032878E+05 COEF_3 = -1.0961644E+04 COEF_4 = -2.7829606E+08 COEF_5 = 2.2836044E+10 COEF_6 = -6.4210778E+11

COEF_7 = -1.0847E-04 COEF_8 = 3.26E-06

COEF_7 = -4.15E-06 COEF_8 = 5.868E-06

Thermocouple Type T or TT

M0-0053


Standard Temperature Range -46 to 400 Degrees C -50 to 750 Degrees F

Actual range in MV / TEMP -6.258 to 19.945 -6.254 to 19.979

(-270 to 385) (-450 to 726)



Centigrade COEF_1 =-5.9866667E+02 COEF_2 = 2.5940711E+04 COEF_3 = -7.3652167E+05 COEF_4 = 3.8678150E+-7 COEF_5 = -1.2932267E+09 COEF_6 = 1.8503589E+10

COEF_7 = -7.3333E-04 COEF_8 = 2.243E-05

COEF_7 = -1.55700E-05 COEF_8 = 4.0374E-05


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3-8. QAV


REQUIRED ENABLE JUMPER CARD

#8-32 SCREW

20B 20A

POINT 5

POINT 4

POINT 3

POINT 2

POINT 1

POINT 0

19B

A

(+)

19A

18

(+)

(SHIELD)

17B

17

(SHIELD)

(−)

17A

16

(−)

(+)

15B

15

(+)

(SHIELD)

15A

14

(SHIELD)

(−)

13B

13

(−)

(+)

13A

12

(+)

(SHIELD)

11B

11

(SHIELD)

(−)

11A

10

(−)

(+)

9B

09

(+)

(SHIELD)

9A

08

(SHIELD)

(−)

7B

07

(−)

(+)

7A

06

(+)

(SHIELD)

5B

05

(SHIELD)

(−)

5A

04

(−)

(+)

3B

03

(SHIELD)

3A

02

(−)

1B

01

POINT 5

POINT 4

NOTE: THIS DRAWING IS POINT 3 FOR PLANT GROUNDED TRANSDUCERS.

POINT 2

POINT 1


1A PLANT GROUND

EDGE CONNECTOR

Figure 3-64. QAV Wiring Diagram (QAV Groups 1 through 5)

Installation Notes: QAV Groups 1 through 5 (Refer to Figure 3-64) 1. If inputs are to be grounded at the system end, insert a #6 screw and nut in the hole located near the shield terminal on Terminal Block A. Then add two jumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 14, & 17, have been drilled for this purpose.

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M0-0053

3-8. QAV

A (+)

(+) TRANSDUCER

S (−)

(−) #6 SCREW

2. If inputs are to be grounded at the signal source, ground both the (−) side of the signal and the cable shield as shown below.

A (+)

(+) TRANSDUCER

S (−)

M0-0053

(−)


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3-8. QAV

Installation Data Sheet 2 of 3

Required Enable Jumper Terminal Block #8-32 Screw

20B

Card

UIOB/DIOB 13 V Power Supply

20A

Point5

Point4

Point3

Point2

Point1

Point0

TB1 or TB2

TB1 or TB2

2 1

19B

A

A

19A

18

18

S1

S1

Shield

17B

17

17

(-)1

(-)1

(+)

(-)

17A

16

16

(+)1

(+)1

(-)

(+)

15B

15

15

S2

S2

Shield

Shield (-)

15A

14

14

(-)2

(-)2

(+)

13B

13

13

(+)2

(+)2

(-)

(+)

13A

12

12

S3

S3

Shield

Shield (-)

11B

11

11

(-)3

(-)3

(+)

11A

10

10

(+)3

(+)3

(-)

(+) Shield

C + TB3

(+)

9B

09

09

S4

S4

Shield

Shield

9A

08

08

(-)4

(-)4

(+)

(-)

7B

07

07

(+)4

(+)4

(+)

7A

06

06

S5

S5

(-) Shield

Shield

5B

05

05

(-)5

(-)5

(+)

(-)

5A

04

04

(+)5

(+)5

(-)

(+)

3B

03

03

S6

S6

Shield

Shield (-)

3A

02

02

(-)6

(-)6

(+)

1B

01

01

(+)6

(+)6

(-)

Point5

Point4

Point3

Point2

Point1

Point0

1A TSC Card Terminal Block #6-32 Screw

Edge Connector Note: This drawing is for plant grounded transducers.

Figure 3-65. Wiring Diagram, QAV to TSC Card

Installation Notes (Refer to Figure 3-65): 1. If inputs are to be grounded at the system end, insert a #6 screw and nut in the hole located near the shield terminal on Terminal Block A. Then add two jumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 14, & 17, have been drilled for this purpose.

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M0-0053

3-8. QAV

A (+)

(+) TRANSDUCER

S (−)

(−) #6 SCREW


A (+)

(+) TRANSDUCER

S (−)

M0-0053

(−)


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3-8. QAV


PLANT GROUND

CARD

(−) POINT 0

POINT 1

POINT 2

POINT 3

POINT 4

POINT 5

1A

A

A

1B

1

1


(SHIELD)

3A

2

2

(+)

3B

3

3

(−)

5A

4

4

(−)

(SHIELD)

5B

5

5

(SHIELD)

(+)

7A

6

6

(+)

(−)

7B

7

7

(−)

8

(SHIELD) (+)

(SHIELD)

9A

8

(+)

9B

9

9

(−)

11A

10

10

(−)

(SHIELD)

11B

11

11

(SHIELD)

(+)

13A

12

12

(+)

(−)

13B

13

13

(SHIELD)

15A

14

14

(+)

15B

15

15

(−)

17A

16

16

(−)

(SHIELD)

17B

17

17

(SHIELD)

(+)

19A

18

18

(+)

19B

PE

PE

POINT 1

POINT 2

POINT 3


POINT 5

EDGE-CONNECTOR

Note The QAV inputs may be grounded in the field or at the B cabinet as shown.

Figure 3-66. QAV CE MARK Wiring Diagram

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3-9. QAW

3-9. QAW Analog High Level Input Point (Style 7379A31G01 through G06)

3-9.1. Description Groups 01through G06 are applicable for use in the CE MARK Certified System The QAW card is designed to convert an analog field signal to digital data (see Figure 3-67). (For new applications, a QAX card is recommended). The digital data is the summation of a frequency that has been counted for a time period which is a multiple of the power line frequency (50 or 60 Hz).

DIOB Data

Address

Data Buffer RAM

Address Decoder

Control



...



...


(+) (-) SHD

...

(+) (-) SHD

Six Sets of Analog Field Inputs

Figure 3-67. QAW Block Diagram

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3-9. QAW

Each QAW card contains six individually isolated voltage-to-frequency converter circuits (channels). The output of each input circuit is processed by a common microcomputer and the resulting digital data is multiplexed to the Distributed Input/Output Bus (DIOB) as a 13-bit word. Figure 3-68 shows a typical control system configuration using QAW cards. The QTB card is necessary for applications where large variations of power line frequency exist, to obtain a high normal mode rejection. Up to 30 QAW cards (180 channels) can be used with one DIOB controller. The QAW card uses an electrical isolation circuit (transformer) to separate the analog input from the digital counting circuits. The isolation circuit provides power for each analog input channel in addition to precise timing from a stable frequency which is generated on the digital side of the QAW card circuits. Only card Group 5 provides an on-board current loop power supply. By using Group 5 cards for current transducers requiring 4-20 mA, a separate power supply is not needed. On a Level 7 or earlier QAW, the power supply is activated by installing jumper number 6. On a Level 9 or later QAW, the power supply is activated by setting jumpers 7 - 17 to the 2-3 position. Each analog input circuit contains circuitry for signal conditioning, biasing, auto-zero and gain correction, and a clocked voltage-to-frequency converter. Offset and gain correction factors are calculated on a periodic basis by the QAW card microcomputer. The frequency of the offset and gain calibration cycle is determined by a constant which has been programmed into the memory of the system controller. Two known potentials on the analog section of the QAW card are used as standards for offset and gain calibration. One standard is a 0 VDC (shorted input), which is used to determine the offset correction factor. The second calibrating potential (gain) is derived from a separate, stable voltage reference which is set to approximately 100 percent of the maximum expected analog input value. The gain correction factor is compared to a 16-bit calibration constant which is programmed into the memory of the system controller at the time of factory card calibration. The calibration constant is necessary because the QAW card has no mechanical adjusting devices (such as potentiometers, and so on). This method yields a trimmer (or pot) -less calibrating method. The QAW card microcomputer is programmed to “limit check” (reasonability check) the offset correction factor for each analog input channel. Failure of the reasonability check causes bit 14 (offset over-range) of the output data for that channel to be set to a logical zero. A failure on two or more channels causes bit 15 (IMOK bit) of the output data to be set to a logical zero which indicates card trouble to the system controller.

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3-9. QAW

DIOB CONTROLLER

QTB

POWER LINE INPUT

DIOB

QAW NO. 1

FIELD INPUTS

QAW NO. 30

FIELD INPUTS

~ ~

Figure 3-68. QAW Typical Control System Using QAW Cards

Note The two-channel failure feature is available on QAW card with prefixes of 1 and 2. Bit 15 is also set to zero during the power-up routine of the QAW card. The QAW microcomputer is reset at this time and conversion of data is begun when the reset control is removed and the QAW card buffer memory is updated. Bit 15 is reset to a logical 1 after a warm-up pause is completed. The length of the warm-up pause is determined by a constant which is programmed into the memory of the system controller.

3-9.2. Features The QAW card is available in six design groups (G01 through G06) to accommodate a variety of analog input voltages. The group numbers, maximum source impedance, and input voltage range are as follows:

• • • •

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G01: 0 to +1 VDC 1 KΩ maximum source impedance. G02: 0 to +5 VDC 5 KΩ maximum source impedance. G03: 0 to +10 VDC; 10 KΩ maximum source impedance. G04: 0 to +20 mA


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3-9. QAW

• •

G05: 0 to +20 mA, on-board current loop power supply G06: 0 to +50 mA

Each QAW card has the following features:

• • • • • • • • • •

IEEE surge withstand capability Auto zero, auto gain correction Electrical isolation on all channels On-card digital memory (buffer) Common mode rejection Normal mode rejection Automatic reasonability test (shorted input) Auto-conversion check Jumper selectable 50/60 Hz operation On-board current loop power supply (G05 only)

The QAW card is designed to be mounted in a standard Q-line card cage. Connection to the control system is made by a 34-pin rear-edge backplane connector which interfaces to the DIOB, and a 56-pin front-edge connector, which connects to field terminals.

3-9.3. Specifications Figure 3-69 and Figure 3-70 show block diagrams of the QAW analog and digital circuits. Inputs Point Sampling Rate (samples/second): Note QAW cards with prefixes of 3 or greater are selected for 50 or 60 Hz operation by jumper. The sampling rate is 4 per second and the sample period is 0.2 seconds for both 50 or 60 Hz operation.

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4 at a power line frequency of 60 Hz 3.4 at a power line frequency of 50 Hz


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3-9. QAW

Note Once every 32 conversions, auto gain and auto zero calibration are performed; 8 seconds apart in 60 Hz systems, and 9.4 seconds apart in 50 Hz systems. Resolution: 13-bits (includes polarity bit) Input Channel Sample Period:

• •

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0.20 seconds at a power line frequency of 60 Hz 0.24 seconds at a power line frequency of 50 Hz


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3-9. QAW

RD (FOR GROUPS 4, 5, & 6) +

LOW PASS FILTER

VIN

CLAMP

−

V0

SH

R1 GROUP 5 ONLY

(MULTI PLEXER SOLID STATE SWITCH)

R2

VOLTAGE REFERENCE

-

R3 R4

SURGE PROTECTION

VREF PREAMPLIFIER

I1 CURRENT LIMITER

-

-

18V (NORMAL) +15V −15V 18 V (NOM)

-

(−) (+) -

POWER SUPPLY

INTEGRATOR

MULTIPLEXER CONTROLLER

-


-

CLOCK

+12V -

-

X1

CAPACITOR DISCHARGE

I REF

1

T1

PSD (250 KHZ) FREQUENCY INPUT (FI1-FI6)

D1 -

-

R5

C2 -

-

-

Figure 3-69. QAW Analog Input Circuits Block Diagram

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3-9. QAW

ADDRESS JUMPERS

ANALOG POWER CONTROL

PSD POWER SUPPLY DRIVE-250 KHZ

CL

RAM LOAD ENABLE P15

AOK

UADD0-7 DATA-DIR

ADDRESS DECODER


TADD0-2 HI-LO

UDAT0-7 DEV BUSY

DOUT P13

I/O

LEVEL SHIFT AND BUFFER

TUSYNC P24 to P27 CL WR SS

MICROCOMPUTER


BUS (DB0-7)

PSEN P20

PROGRAM MEMORY

RD0-7

ADDRESS

LEN

ADDRESS LATCH

BUFFER RAM

WD0-7

D I O B

BUFFER LATCH

CONTROL ADDRESS

I/O A0 A1

COUNTERS (6)

P10-12

P14

TRESET

POWER UP AND RESET

+5V

5 VOLT REGULATOR +12V

(FI1-FI6)

Figure 3-70. QAW Digital Circuits Block Diagram

Normal Mode Voltage

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•

Surge: Meets IEEE/SWC test specifications without damage; however, the accuracy of data is reduced during, and up to 10 seconds after the removal of the surge.

•

Continuous: An overrange of +120 VDC or 120 VAC rms at 50 or 60 Hz will not damage the input channels; however, a sustained overrange can affect subsequent data for several minutes following the removal of the overrange voltage.


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3-9. QAW

Note This specification does not apply to Group 4, 5, and 6 cards. Normal Mode Rejection

• •

60 dB at 50 or 60 Hz using QTB card line frequency tracking 25 dB at 50 Hz +5 percent or 60 Hz +5 percent without QTB card line frequency tracking Note The input (peak-to-peak) AC voltage must not exceed 50 percent of the upper range value or 2V, for specified accuracy and normal mode rejection.

Common Mode Voltage

•

Surge: Meets IEEE/SWC test specifications without damage; however, the accuracy of data is reduced during, and up to 10 seconds following the removal of the surge.

•

Continuous: A maximum of +500 VDC or peak AC can be applied without damage.

Common Mode Rejection

•

120 dB at DC and power line frequency and its harmonics with QTB card line frequency tracking

•

100 dB for nominal line frequency at +5 percent and harmonics without QTB card line frequency tracking Note Common mode rejection does not apply if the peak AC value exceeds 200,000 percent of upper range value.

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3-9. QAW

Input Impedance 250Ω Reference Accuracy (per SAMA Standard PMC 20)

•

+0.10 percent of the upper range value (+10 µV); +1/2 of the Least Significant Bit (LSB) at 99.7 percent confidence.

•

Reference Conditions: 25°C + 1°C Ambient Temperature; 50 percent +2 percent of relative humidity; 0 V common mode; 0 V normal mode

Power Requirements Minimum Primary Voltage:

12.4 VDC

Optional Backup:

12.4 VDC


Nominal Power Supply Current:

1.0 ADC

Power Used:

13.0 Watts


Maximum 1.2 ADC 15.7 Watts

On-Board Power Supply for Each Channel (G05 Only)

• • •

Current Limit: 60 mA

•

Minimum Transducer Operating Voltage: 12 VDC with no load

Loop Resistance (excluding transducer): not greater than 60 ohms Worst Case VDC Output: 14 VDC (for a 7 level and earlier QAW), or 20 VDC (for 9 level and later QAW) @ 20 mA (DIOB power supply @ 12.4 VDC)

Input Signal Requirements

• • • M0-0053

G01 cards: 0 to +1 VDC G02 cards: 0 to +5 VDC G03 cards: 0 to +10 VDC


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3-9. QAW

• • •

G04 cards: 0 to +20 mA G05 cards: 0 to +20 mA (on-board current loop power supply) G06 cards: 0 to +50 mA

Field signals are input to a standard Q series front-edge connector. The DIOB address and DIOB address protection jumpers are also located in this connector. Each field signal input requires a plus, minus and shield pin. Output Signal Requirements Output signal requirements are specified for DIOB requirements. DIOB connection is made to the QAW card through the Q-card backplane connector to connector pins located on the rear-edge of the card (see Figure 3-71). COMPONENT SIDE

SOLDER SIDE

+V PRIMARY

2

1

+V PRIMARY

+V BACKUP

4

3

+V BACKUP

GROUND

6

5

GROUND

UADD1

8

7

UADD0

UADD3

10

9

UADD2

UADD5

12

11

UADD4

UADD7

14

13

UADD6

DATA-DIR

16

15

HI-LO

DATA-GATE

18

17

UNIT*

DEV-BUSY

20

19

GROUND

UDAT1

22

21

UDAT0

UDAT3

24

23

UDAT2

UDAT5

26

25

UDAT4

UDAT7

28

27

UDAT6

UFLAG*

30

29

GROUND

USYNC

32

31

UCAL*

GROUND

34

33

UCLOCK*

POWER

CARD ADDRESSING

CONTROL

BIDIRECTIONAL DATA BUS

CONTROL

* NOT USED ON QAW CARD

Figure 3-71. QAW Card Rear-Edge Connector Pin Assignments

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3-9. QAW

3-9.4. Card Addressing and Data Output Address Jumpers The QAW card address is established by five jumper fixtures which are located in the front-edge connector. The insertion of a jumper encodes a “1” on the selected address line (ADD3 through ADD7) which when matched by the DIOB address signals selects the QAW card Figure 3-72 shows the pin configuration of the front-edge connector. The “B” pins of the connector are located on the component side and the “A” pins are located on the solder side of the p-c card. QAW card addresses are programmed in groups of eight addresses in order to maintain the address recognition circuits at a minimum. Two addresses are not used by the QAW card since each card contains six analog input channels; however, the unused address can be used by other cards when required. The addressing method allows up to 30 QAW cards to be used which means that 180 analog input channels can be provided. Address protection is provided by a jumper insert on the front-edge connector pin pair (20A and 20B). This contact has been machined to be shorter than the other front-edge contacts so that it disconnects before the other contacts when the front card-edge connector is removed from the QAW card.

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3-9. QAW

SOLDER SIDE

COMPONENT SIDE

UNUSED

1A

1B

POINT 0 – INPUT SIGNAL

UNUSED

2A

2B

UNUSED

POINT 0 SHIELD

3A

3B

POINT 0 + INPUT

UNUSED

4A

4B

UNUSED

POINT 1 − INPUT

5A

5B

POINT 1 SHIELD UNUSED

UNUSED

6A

6B

POINT 1 + INPUT

7A

7B

POINT 2 – INPUT

UNUSED

8A

8B

UNUSED

POINT 2 SHIELD

9A

9B

POINT 2 + INPUT

UNUSED

10A

10B

UNUSED

POINT 3 − INPUT

11A

11B

POINT 3 SHIELD

UNUSED

12A

12B

UNUSED

POINT 3 + INPUT

13A

13B

POINT 4 – INPUT UNUSED

UNUSED

14A

14B

POINT 4 SHIELD

15A

15B

POINT 4 + INPUT

UNUSED

16A

16B

UNUSED

POINT 5 − INPUT

17A

17B

POINT 5 SHIELD

UNUSED

18A

18B

UNUSED

POINT 5 + INPUT

19A

19B

UNUSED


20A

20B


UNUSED

21A

21B

UNUSED

UNUSED

22A

22B

UNUSED

UNUSED

23A

23B

UNUSED

ADDRESS LINE A3

24A

24B


ADDRESS LINE A4

25A

25B


ADDRESS LINE A5

26A

26B


ADDRESS LINE A6

27A

27B


ADDRESS LINE A7

28A

28B


JUMPER MUST BE IN PLACE FOR PROPER CARD OPERATION

Figure 3-72. QAW Card Front-Edge Connector Pin Assignments

Output Data Bit Patterns Figure 3-73 shows a general, 16-bit, QAW card output data pattern format. The first 12 bits (0 through 11) are binary data that is obtained through a software routine in the QAW card microcomputer circuit.

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3-9. QAW

The actual binary data that is sent to the system controller over the DIOB is calculated by the microcomputer using data from a precision voltage network and from an analog-to-digital converter circuit. Data from the precision voltage network adjusts the converted analog input (digital data) for offset and gain correction before it is output to the DIOB as point data. Bit 12 is an overrange bit and bit 13 is a sign bit. A logic one signal at bit 12 indicates that the count data is in the positive overrange when bit 13 is at a logic zero and that the count data is in the negative range when bit 13 is a logical one. A logical zero at bit 12 indicates that the count data is in the negative overrange when bit 13 is a logical one and in the positive range when bit 13 is a logical zero. A logical one at bit 13 indicates the count is in the negative range and a logical zero at bit 13 indicates that the count is in the positive range. Bits 14 and 15 are flag bits. A logical one at bit 14 indicates that the offset factor data that was obtained during the auto-zero calibration microcomputer routine is within reasonable limits and a logical zero indicates unreasonable auto-zero data. A logical one at bit 15 (called IMOK bit) indicates that the hardware is operating properly (power is present, warm-up is complete, and the controller is operating). A logical zero at bit 15 indicates hardware trouble or that the offset factors from the auto-zero calibration are unreasonable on more than one input channel. Note Multiple channel offset errors will not set bit 15 on QAW cards with prefixes of 5 or greater.

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3-9. QAW

Bit Number 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

OVERRANGE BIT

BINARY DATA

1 = COUNT IS IN POSITIVE OVERRANGE WHEN SIGN BIT 13 = 0, AND IN NEGATIVE RANGE WHEN SIGN BIT 13 = 1 0 = COUNT IS IN POSITIVE RANGE

SIGN BIT 1 = COUNT IS NEGATIVE

FLAG BIT SET BY QAW CARD MICROCOMPUTER 1 = OFFSET DATA OBTAINED DURING AUTO CALIBRATION IS WITHIN REASONABLE LIMITS

FLAG BIT (SET BY MICROCOMPUTER) 1 = HARDWARE IS OPERATING PROPERLY

Figure 3-73. QAW Card Output Data Pattern Format

Table 3-44 shows the nomenclature and the hexadecimal ranges for the QAW card output data. Note that bits 14 and 15 are set by QAW card microcomputer; therefore, the positive range to negative transitions occurs in 14 bits. Table 3-44. QAW Card Output Data Ranges

Data Classification


Zero Input

C000

Positive Range

C001 to CFFF

Positive Full Scale

D000

Positive Overrange

D001 to DFFF

Negative Full Scale

F000

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3-9. QAW

Table 3-44. QAW Card Output Data Ranges

Data Classification


Negative Range

F001 to FFFF

Out of Range Offset

8000 to BFFF

Card Hardware Trouble

0000 to 7FFF

Controls and Indicators (Level 7 and earlier) Figure 3-74 shows the card components for 7 level and earlier QAW.

J1,J2

J6,J7 G05 Only

LED

J3,J4

Figure 3-74. QAW Card Components (Level 7 and earlier)

Light Emitting Diodes (LED) The QAW card (Level 7 and earlier) has one LED which indicates power “on”. For Group 5 QAWs, a current limiting lamp is part of each current loop. During normal operation, the lamp is off. However, a short in the circuit causes the lamp to turn on. Jumpers Table 3-45 lists the jumper numbers, locations and functions of the jumpers used on the QAW card.

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3-9. QAW

Table 3-45. QAW Card Jumpers and Functions (Level 7 and earlier)

Function (Jumper in Place)

Jumper Number J1

For future use

J2

ORs signal IMOK (P13) to W274-2 Inverter

J31,2


J41,2


J51

For future use

J63

Selects on-board current loop supply for Group 5 only

J74

Selects external current loop supply for Group 5 only

1 Jumpers 2 The

J3, J4 and J5 are not used on QAW cards with prefixes lower than 5.

QAW card operates on its own time base when jumpers J3 or J4 are not inserted.

3 Jumper


4 Jumper


3-9.5. Controls and Indicators (Level 9 and later) Figure 3-75 shows the card components for 9 level and later QAW.

LE1 JS13 JS11 JS15 JS9

SW

1 2 3 4

JS17 JS7

JS14

LE2

JS12 JS16 JS10 JS18 JS8

Figure 3-75. QAW Card Components (Level 9 and later)

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3-9. QAW

Switches The (Level 9 and later) QAW card uses a four-position DIP switch (see Figure 3-75 for the location of the switch). The definitions of the switches are as follows: Table 3-46. QAW Jumper Configuration

Configuration

SW1

SW2

SW3

SW4

50Hz operation

X

ON

OFF

X

60Hz operation

X

OFF

ON

X

No QTB1

X

ON

ON

X

1The

QTB card is necessary in installations where large variations of the power line frequency exist to provide for large normal mode rejection. X = Reserved (Don’t Care) Notes Any other switch combination is not valid and the QAW card will not operate. The QAW also has several factory preset jumpers. Changing these jumpers will affect calibration, therefore, no changes are recommended. Jumpers On Group 5 QAW cards, jumpers J7 and J8 (channel 0); jumpers J17 and J18 (channel 1); jumpers J9 and J10 (channel 2); jumpers J15 and J16 (channel 3); jumpers J11 and J12 (channel 4); and jumpers J13 and J14 (channel 5) MUST BE in the 2-3 position to enable on-card loop Power Supply. Refer to Figure 3-75 for the jumper locations. LEDs The QAW card has two LED’s (see Figure 3-75). LE1 indicates that power is applied to the board. LE2 is used during the initial calibration of the board. For on-line applications, LE2 will illuminate for about 1/2 second during power-up and will remain off thereafter. Should this LED remain on or flash, return the board to Westinghouse for repair.

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3-9. QAW

Notes Before returning the board for repair, check the following: 1. Ensure that the DIOB power supplies are in tolerance. 2. Ensure that the DIP switch is set according to the valid configurations in the previous tables.

3-9.6. Installation Data Sheets 1 of 4

TERMINAL BLOCK #8-32 SCREW


20B 20A

POINT 5

POINT 4

POINT 3

POINT 2

POINT 1

POINT 0

19B

A

(+)

19A

18

(+)

(SHIELD)

17B

17

(SHIELD)

(−)

17A

16

(−)

(+)

15B

15

(+)

(SHIELD)

15A

14

(SHIELD)

(−)

13B

13

(−)

(+)

13A

12

(+)

(SHIELD)

11B

11

(SHIELD)

(−)

11A

10

(−)

(+)

9B

09

(+)

(SHIELD)

9A

08

(SHIELD)

(−)

7B

07

(−)

(+)

7A

06

(+)

(SHIELD)

5B

05

(SHIELD)

(−)

5A

04

(−)

(+)

3B

03

(SHIELD)

3A

02

(−)

1B

01

POINT 5

POINT 4


POINT 2

POINT 1


1A PLANT GROUND

EDGE CONNECTOR

Figure 3-76. Wiring Diagram, QAW Groups 1,2,3,4, and 6

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3-9. QAW

Installation Notes: QAW Groups 1, 2, 3, 4, 6 (Refer to Figure 3-76) 1. If inputs are to be grounded at the system end, insert a #6 screw and nut in the hole located near the shield terminal on Terminal Block A. Then add two jumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 14, & 17, have been drilled for this purpose.

A (+)

(+) TRANSDUCER

S (−)

(−) #6 SCREW


A (+)

(+) TRANSDUCER

S (−)

(−)

Installation Notes: QAW Groups 4, 6 (Refer to Figure 3-76) If loop power is supplied by the customer but is external to the transducer, inputs are grounded as follows: 3. If inputs are to be grounded at the system end, ground as described in Note 1 and as shown below:

A (+)

(−) TRANSDUCER

S (−)

− #6 SCREW

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+

(+)

POWER SUPPLY


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3-9. QAW

4. If inputs are to be grounded at the signal source, ground as described in Note 2 and as shown below:

A (+)

(−) TRANSDUCER

S (−)

−

+

(+)

POWER SUPPLY

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M0-0053

3-9. QAW




20B 20A

POINT 5

POINT 4

POINT 3

POINT 2

POINT 1

POINT 0

19B

A

(+)

19A

18

RTN

SHIELD

17B

17

SHIELD

(−)

17A

16

SRC

(+)

15B

15

RTN

SHIELD

15A

14

SHIELD

(−)

13B

13

SRC

(+)

13A

12

RTN

SHIELD

11B

11

SHIELD

(−)

11A

10

SRC

(+)

9B

09

RTN

SHIELD

9A

08

SHIELD

(−)

7B

07

SRC

(+)

7A

06

RTN

SHIELD

5B

05

SHIELD

(−)

5A

04

SRC

(+)

3B

03

SHIELD

3A

02

(−)

1B

01

POINT 5

POINT 4


POINT 2

POINT 1 RTN (−) POINT 0 SRCTRANSDUCER (+)

1A PLANT GROUND

EDGE CONNECTOR

Figure 3-77. Wiring Diagram: QAW Group 5

Installation Notes: QAW Group 5 (Refer to Figure 3-77) 1. If inputs are to be grounded at the system end, insert a #6 screw and nut in the hole located near the shield terminal on Terminal Block A. Then add two jumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 14, & 17, have been drilled for this purpose.

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3-9. QAW

A RETURN

(+)

(−)

S

TRANSDUCER SOURCE

(−)

(+)

#6 SCREW


A RTN

(+) S

TRANSDUCER

(−)

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(−)

SRC

(+)


M0-0053

3-9. QAW


Required Enable Jumper Terminal Block #8-32 Screw

20B

Card

UIOB/DIOB 13 V Power Supply

20A

Point4

Point3

Point2

Point1

Point0

TB1 or TB2

2 1

A

A

19A

18

18

S1

S1

Shield

17B

17

17

(-)1

(-)1

(+)

(-)

17A

16

16

(+)1

(+)1

(-)

(+)

15B

15

15

S2

S2

Shield

Shield (-)

15A

14

14

(-)2

(-)2

(+)

13B

13

13

(+)2

(+)2

(-)

(+)

13A

12

12

S3

S3

Shield

Shield (-)

11B

11

11

(-)3

(-)3

(+)

11A

10

10

(+)3

(+)3

(-)

(+) Shield

Point5

TB1 or TB2

19B

C + TB3

(+)

9B

09

09

S4

S4

Shield

Shield

9A

08

08

(-)4

(-)4

(+)

(-)

7B

07

07

(+)4

(+)4

(+)

7A

06

06

S5

S5

(-) Shield

Shield

5B

05

05

(-)5

(-)5

(+)

(-)

5A

04

04

(+)5

(+)5

(-)

(+)

3B

03

03

S6

S6

Shield

Shield (-)

3A

02

02

(-)6

(-)6

(+)

1B

01

01

(+)6

(+)6

(-)

Point5

Point4

Point3

Point2

Point1

Point0

1A TSC Card Terminal Block #6-32 Screw

Edge Connector Note: This drawing is for plant grounded transducers.

Figure 3-78. Wiring Diagram, QAW to TSC Card

Installation Notes (Refer to Figure 3-78): 1. If inputs are to be grounded at the system end, insert a #6 screw and nut in the hole located near the shield terminal on Terminal Block A. Then add two jumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 14, & 17, have been drilled for this purpose.

A (+)

(+) TRANSDUCER

S (−)

(−) #6 SCREW

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3-9. QAW


A (+)

(+) TRANSDUCER

S (−)

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(−)


M0-0053

3-9. QAW


PLANT GROUND

CARD

(+) POINT 0

POINT 1

POINT 2

POINT 3

POINT 4

POINT 5

1A

A

A

1B

1

1


(SHIELD)

3A

2

2

(−)

3B

3

3

(+)

5A

4

4

(−)

(SHIELD)

5B

5

5

(SHIELD)

(−)

7A

6

6

(+)

(+)

7B

7

7

(−)

(SHIELD)

9A

8

8

(SHIELD)

(−)

9B

9

9

(+)

(+)

11A

10

10

(−)

(SHIELD)

11B

11

11

(SHIELD)

(−)

13A

12

12

(+)

(+)

13B

13

13

(SHIELD)

15A

14

14

(−)

15B

15

15

POINT 1

POINT 2

POINT 3


(+)

17A

16

16

(−)

(SHIELD)

17B

17

17

(SHIELD)

(−)

19A

18

18

(+)

19B

PE

PE

POINT 5

EDGE-CONNECTOR

Note The QAW inputs may be grounded in the field or at the B Cabcabinet as shown. This diagram is shown for Group 5 QAWs. Figure 3-79. QAW CE MARK Wiring Diagram

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3-10. QAX

3-10. QAX 12 Point Analog Input Card (Style 4256A64G01 through G06)

3-10.1. Description G01 through G06 are applicable for use in the CE MARK Certified System The QAX card converts an analog field signal to digital data. The digital data is a summation of a frequency that has been counted for a period of time.Time periods are a multiple of the nominal power line frequency (50 or 60Hz). There are six possible card groupings, representing various input ranges. Up to 15 QAX cards (180 points) may be used with one DIOB controller. The QAX is the recommended functional replacement for two QAV (or QAW) cards.

DIOB Data

Address

Data Buffer RAM

Address Decoder

Control



...



...


(+) (-) SHD

...

(+) (-) SHD

Twelve Sets of Analog Field Inputs

Figure 3-80. QAX Block Diagram

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3-10. QAX

The design groups are as follows: Table 3-47. QAX Card Groups and Capabilities

Group

Resistance (Maximum Source Impedance)

Range Low-Level Groups

GO1

-5mV to 20mV (-20mV to 20mV at reduced accuracy)

500 Ω

GO2

-12.5mV to 50mV (-50mV to 50mV at reduced accuracy)

500 Ω

GO3


1K Ω

High-Level Groups GO4

0 to 1V

1K Ω

GO5

0 to 5V

5K Ω

GO6

0 to 10V

10K Ω Note

The kit drawing which comes with each of the specified groups lists additional details on cabling, jumper settings, and installation.

3-10.2. Features Each QAX card has the following features:

• • • • • • • • M0-0053

IEEE surge withstand capability Auto zero - Auto gain correction Electrical isolation on all channels On card buffer memory for DIOB data transfers Open thermocouple detection (low level cards only) Common mode noise rejection Normal mode noise rejection Automatic reasonability test on the offset


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3-10. QAX

•

Operation with a QTB timebase (in 50 or 60 Hz) or without a QTB

Each daughter board features:

• • • • • •

Signal conditioning Biasing Auto-zero and auto-gain correction Open thermocouple detection (low-level configurations only) Synchronous voltage to frequency converter. Offset and gain calibration factors are calculated approximately every 8 seconds for each daughter board channel by the microprocessor on the mother board.

The QAX card is designed to be mounted in a standard Q-line card cage. Connection to the control system is made by a 34 pin rear edge backplane connector for the DIOB interface. Interface to the field wiring is made by a 56 pin front edge connector. Each QAX card consists of a mother board and 12 Surface Mount Technology daughter boards. Each daughter board handles one A/D channel and contains the circuitry for an independent voltage to frequency converter. The daughter boards interface to the mother board via 30 pin SIMM connectors. The mother board provides for the DIOB interface, field interface, daughter board control, and data processing. The QAX card uses a transformer based electrical isolation circuit on each daughter card which separate the 12 cards from each other and from the mother board. In addition, the isolation circuit provides power for each daughter board and precise timing from a stable frequency generated on the mother board. The QAX card features electronic (non-mechanical) auto-calibration which behaves as follows:

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•

Two known potentials on the analog daughter boards are used as standards for offset and gain calibration.

• •

One standard is 0 volts (shorted input) which is used for offset calibration.

•

On low-level cards, the second standard is derived from a stable voltage reference and is approximately -150% of the maximum analog input reading.

On high-level cards, the second standard is derived from a stable voltage reference and is approximately 100% of the maximum analog input reading.


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3-10. QAX

•

The gain calibration value is compared against a calibration constant loaded into an EEPROM on the mother board during initial calibration. This calibration constant is necessary in order to provide a non-mechanical (no potentiometer) calibration system.

The QAX processor also provides on-card diagnostics. One feature is a reasonability check for the offset calibration factor. Failure of the reasonability check causes bit 14 (offset-out-of-range) in the data package to be set to logic 0. With this feature, any one channel can fail while the others are still active and accurate. When the card is warmed up (about 15 seconds after power up), bit 15 of the data package is set to logic one to indicate the card is ready. Note All daughter boards located on a given mother board MUST be of the same design group.

3-10.3. Specifications Power Supply Voltage Table 3-48. QAX Power Requirements

Minimum Primary Voltage

12.4VDC

Backup

12.4VDC

Nominal 13.0VDC

Maximum 13.1VDC 13.1VDC

Power supply current

0.9 A DC

1.1 A DC

Power dissipation

11.7 Watts

14.5 Watts

Inputs Point Sampling rate (samples/second): 4 Once every 32 conversions, auto zero and auto gain calibration are performed. Resolution: 13 bits (including polarity bit) Input Channel Sample Period: 0.20 seconds

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3-10. QAX

Normal Mode Voltage Surge: Meets IEEE test specification without damage; however, the accuracy of the reading is reduced during, and up to 10 seconds following the removal of the surge. Continuous: An overvoltage of ±120 VDC or VAC RMS at 50 or 60 Hz will not damage the card; however, a sustained overvoltage can affect subsequent data for several minutes following the removal of the overvoltage. Normal Mode Rejection 60 DB at 50 or 60 Hz using QTB line frequency tracking or at 50 or 60 Hz +0.5 percent without QTB line frequency tracking. 25 DB at 50 HZ ± 5% or 60 Hz ± 5% without QTB line frequency tracking. Note The input peak to peak AC voltage must not exceed 100% of the upper range value for specified accuracy and normal mode rejection. Common Mode Voltage Surge: Meets IEEE test specification without damage; however, the accuracy of the data is reduced for up to 10 seconds following the removal of the surge. Continuous: A maximum of 500 VDC or peak AC can be applied without damage. Common Mode Rejection 120 DB at DC and power line frequency including harmonics with QTB line frequency tracking. 100 DB for nominal line frequency ±5% including harmonics with QTB line frequency tracking or at 50 or 60 Hz ±0.5% w/o QTB line frequency tracking. Note Common mode rejection does not apply if peak AC input exceeds 200,000% of the upper range value. Input Impedance:

10 MΩ 4 KΩ in overload or powered down

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3-10. QAX

Reference Accuracy: ± 0.1% of the upper range value ±10µV ±1/2 LSB @ 99.7% confidence. Reference conditions: Drift:

25 ±1°C ambient temperature, 50 ±2% relative humidity, 0V common mode noise, 0V normal mode noise. 0.002% per month (typical) 0.02% long term (typical)

Table 3-49. QAX Input Signal Requirements

Group G01 G02 G03 G04 G05 G06

Signal Requirements -5 to 20 mV (-20 mV to 20 mV at reduced accuracy) 500Ω maximum source impedance. GO2: -12.5mV to 50mV (-50mV to 50mV at reduced accuracy) 500Ω max source impedance. -25mV to 100mV (-100mV to 100mV at reduced accuracy) 1KΩ max source impedance. 0 to 1 V 1KΩ max source impedance. 0 to 5 V 5KΩ max source impedance. 0 to 10 V 10KΩ max source impedance.

3-10.4. Card Addressing The QAX card address is established by four jumpers on the top, front, card-edge connector. The insertion of a jumper encodes a “1” on the address line. The fifth jumper is used for Address Protection. This addressing method allows up to 15 QAX cards or a total of 180 analog points. The front edge connector pin pair 24A-B. This contact has been machined to be shorter than the other front edge contacts so that it disconnects before the other contacts when the front edge connector is removed. This gap eliminates the possibility of a momentary false address while the card is being removed.

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3-10. QAX

Point Addressing on the QAX Card (WDPF System) To specify the desired grouping, the Card Type Index (CD) and the Hardware Offset (HW) fields of the analog input point record must be initialized with the proper values to ensure that the point will be processed correctly by the analog scan routines of the DPU. The QAX card allows for as many as 12 analog inputs per card. Each QAX requires a block of 16 DIOB addresses. Since there can only be a maximum of 12 points per QAX, but 16 DIOB addresses taken, 4 of the 16 addresses are not used. The following illustrates point addressing on the QAX card: Each point's hardware offset calculation is as follows: For analog points 1 though 6: HW = 2 [ADD + (PN-1)] + MBU For analog points 7 though 12: HW = 2[ADD + (PN-7)] + 10H + MBU where: HW ADD PN MBU

= = = =

point's hardware offset card address (in hexadecimal) relative point number on card MBU offset

Example For a QAX at card address (ADD) of 80H, the following addresses must be used for the Hardware Offset (HW) field of each analog input: Table 3-50. QAX Address Offsets (WDPF Systems)

Input Identification ANALOG INPUT 1 ANALOG INPUT 2 ANALOG INPUT 3 ANALOG INPUT 4 ANALOG INPUT 5 ANALOG INPUT 6 AVAILABLE AVAILABLE

Hexadecimal Address 100H 102H 104H 106H 108H 10AH 10CH 10EH



Note that if thermocouple compensation is selected (CD = 71, 72, 73) on any of the analog inputs, ANALOG INPUT 12 must not be used as a field input. It is reserved by the QAX, so that it can read the temperature of the terminal block from the QAXT.

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3-10. QAX

Point Addressing on the QAX Card (Ovation System) To specify the desired grouping, the Card Type Index (CD) and the Hardware Offset (HW) fields of the analog input point record must be initialized with the proper values to ensure that the point will be processed correctly by the analog scan routines of the Controller. The QAX card allows for as many as 12 analog inputs per card. Each QAX requires a block of 16 DIOB addresses. Since there can only be a maximum of 12 points per QAX, but 16 DIOB addresses taken, 4 of the 16 addresses are not used. Ovation automatically assigns the correct addresses and adjusts for the spare addresses (identified as AVAILABLE in Table 3-51 shown below). However, the four AVAILABLE addresses can still be used by other Q-Line cards, if needed. Example For a QAX at card address (ADD) of 80H, the following addresses must be used for the Hardware Offset (HW) field of each analog input: Table 3-51. QAX Address Offsets (Ovation System)





Note that if thermocouple compensation is selected (CD = 71, 72, 73) on any of the analog inputs, ANALOG INPUT 12 must not be used as a field input. It is reserved by the QAX, so that it can read the temperature of the terminal block from the QAXT.

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3-10. QAX

Thermocouple Information Table 3-52 shows the standard WDPF thermocouple coefficient definitions. Coefficients may also be user-defined. For additional information on selecting these coefficients, refer to the CI record field discussion in “Record Types User’s Guide” (U0-0131). Table 3-52. QAX Thermocouple Coefficient Definitions Thermocouple Type

Coefficients

B

70% Platinum + 30% Rhodium or 94% Platinum + 6% Rhodium 427-1093°C 800-2000°F

C0 = 0.3516470E + 03 C1 = 0.6138849E + 03 C2 = −0.1539774E + 03

C3 = 0.3359373E + 02 C4 = −0.4051826E + 01 C5 = 0.2003933E + 00

E

Chromel/Constantan −18-982°C 0-1800°F

C0 = 0.3167283E + 02 C1 = 0.3030628E + 02 C2 = −0.3344949E + 00

C3 = 0.6849588E − 02 C4 = −0.6975349E − 04 C5 = 0.2923653E − 06

J

Iron/Constantan −96-760°C −140-1400°F

C0 = 0.3112531E + 02 C1 = 0.3607027E + 02 C2 = −0.4288617E + 00

C3 = 0.2261382E − 01 C4 = −0.5174379E − 03 C5 = 0.3972783E − 05

C0 = 0.3034473E + 02 C1 = 0.4403191E + 02 C2 = 0.1615839E + 00

C3 = −0.1616257E − 01 C4 = 0.4401109E − 03 C5 = −0.3599650E − 05

K

Chromel/Alumel −18-1093°C 0-2000°F (The upper range may be extended to 2500 with less accuracy) R


C0 = 0.8362848E + 02 C1 = 0.2273716E + 03 C2 = −0.1248286E + 02

C3 = 0.1206254E + 01 C4 = −0.7422128E − 01 C5 = 0.1899300E − 02

S


C0 = 0.1180344E + 03 C1 = 0.1985918E + 03 C2 = −0.1973096E − 01

C3 = −0.5009329E + 00 C4 = 0.4110488E − 01 C5 = −0.1155794E − 02

T

Copper/Constantan 46-399°C −50-750°F

C0 = 0.3189224E + 02 C1 = 0.4669328E + 02 C2 = −0.1325739E + 01

C3 = 0.6962067E − 01 C4 = −0.2327808E − 02 C5 = 0.3330646E − 04

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3-10. QAX

Low-Level Analog Inputs The following card type indices must be used when low-level analog inputs are to be read from the QAX card: Table 3-53. QAX Low-Level Inputs

Group/ Rev.Range

Index

G01

68

G02 G03

Input/Output

Voltage Range

Units

Input

- 20 to + 20

mV

69

Input

- 50 to + 50

mV

70

Input

-100 to +100

mV

Low-Level Analog Inputs with QAXT Thermocouple Compensation The following card type indices must be used when low-level analog inputs are to be read from the QAX card and thermocouple compensation using the QAXT Temperature Sensor Board is to be performed: Table 3-54. QAX Low-Level Inputs with Compensation

Group/Rev.

Index

Input/Output

Voltage Range

Units

G01

71

Input

- 20 to + 20

mV

G02

72

Input

- 50 to + 50

mV

G03

73

Input

-100 to +100

mV

Special Considerations with Card Types 71, 72, 73: 1. When Card Types 71, 72, 73 are used the QAX is limited to handling only 11 analog inputs. The 12th input is reserved for sensing the thermocouple temperature from the QAXT. The temperature can be read by using an analog input point addressed to channel 12 of the QAX, and using a Card Type of 68, 69, or 70. 2. The CV field of the analog input record must be initialized to 7 to indicate that a thermocouple conversion is to be done. 3. The CI field of the analog must be initialized according to the thermocouple type and temperature range. Values for CI are listed in the “Record Types User’s Guide” (U0-0131).

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3-10. QAX

High-Level Analog Inputs The following card types must be used when high-level analog inputs are to be read from the QAX card: Table 3-55. QAX High Level Inputs

Group/Rev.

Index

Input/Output

Voltage Range

Units

G04

74

Input

0 to + 1

V

G05

75

Input

0 to + 5

V

G06

76

Input

0 to + 10

V

Output Data The analog signal is converted to the output data pattern below and sent to the DIOB as:

PCSO DDDD DDDD DDDD Binary digital data representing the analog input voltage, as computed by the A/D converter on the QAX Overrange bit. Logic 1 represents positive overrange if sign bit “S”=0. Logic 0 represents negative overrange if sign bit “S”=1. Sign bit. Logic 1 indicates a negative value. Offset Quality. Logic 1 indicates that a reasonable offset or zero was read during auto-calibration. I’m OK bit. Set if the card is warmed up (15 seconds after power up) and the hardware is operating properly. Figure 3-81. QAX Output Data Pattern

The following chart shows the data pattern ranges for each of the two channels of output data Table 3-56. QAX Data Pattern Range

Classification

Output Data C000 C001 to CFFF

Zero Input Positive range

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3-10. QAX

Table 3-56. QAX Data Pattern Range

Classification

Output Data

Positive Full Scale Positive Overrange Negative Overrange and Open Thermocouple Detect Negative Full Scale Negative range Offset out of range Card Trouble or Not Warmed Up

D000 D001 to DFFF E000 to EFFF F000 F001 to FFFF 8000 to BFFF 0000 to 7FFF

3-10.5. Controls and Indicators LE1 LE2

Spring sockets for QAXT with half-shell thermocouple compensation SW1

Figure 3-82. QAX Card Components

Note If the QAXT card is to be used to provide thermocouple compensation, the resistor provided in the QAXT kit must be installed.

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3-10. QAX

Switches The QAX card uses a four-position DIP switch (see Figure 3-82 for the location of the switch). The definitions of the switches are as follows: Table 3-57. QAX Jumper Configuration

Configuration

SW1

SW2

SW3

SW4

50Hz operation

X

ON

OFF

X

60Hz operation

X

OFF

ON

X

No QTB1

X

ON

ON

X

1The

QTB card is necessary in installations where large variations of the power line frequency exist to provide for large normal mode rejection. X = Reserved (Don’t Care) Notes Any other switch combination is not valid and the QAX card will not operate. The QAX also has several factory preset jumpers. Changing these jumpers will affect calibration, therefore, no changes are recommended. LED The QAX card has two LED’s (see Figure 3-82). LE1 indicates that power is applied to the board. LE2 is used during the initial calibration of the board. For on-line applications, LE2 will illuminate for about 1/2 second during power-up and will remain off thereafter. Should this LED remain on or flash, return the board to Westinghouse for repair. Notes Before returning the board for repair, check the following: 1. Ensure that the DIOB power supplies are in tolerance. 2. Ensure that the DIP switch is set according to the valid configurations in the previous tables.

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3-10. QAX


Point 11 Point 10 Point 9 Point 8 Point 7 Point 6

Point 5 Point 4 Point 3 Point 2 Point 1 Point 0

sh + sh + sh + sh + sh + sh + sh + sh + sh + sh + sh + sh +

24A 24B 23B 22B 21B 23A 22A 21A 19B 18B 17B 19A 18A 17A 15B 14B 13B 15A 14A 13A

17 16 18 14 “A” 13 Block 15 Halfshell 11 #2 10 12 8 7 9 5 4 6 2 1 3

11B 10B 9B 11A 10A 9A 7B 6B 5B 7A 6A 5A 3B 2B 1B 3A 2A 1A

17 16 18 “A” 14 Block 13 Halfshell 15 #1 11 10 12 8 7 9 5 4 6 2 1 3

6 Pair Twisted Shielded Cable (Dotted line indicates shielding)

6 Pair Twisted Shielded Cable

Transducer (-) (+)

Figure 3-83. QAX Wiring Diagram

Figure 3-83 shows inputs grounded at the signal source. If signals are to be grounded at the system end, insert a #6 screw in the hole located near the shield terminal on halfshell block “A” and add two jumpers as shown in Figure 3-84. Six holes on each halfshell block have been drilled for this purpose.

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3-10. QAX

(+)

(+)

(S)

Transducer (-)

(-)

Jumpering to shield for loop power developed internal to transducer. (-)

(+) (S)

Transducer (+)

(-) (-)

(+)

Power Supply Jumpering to shield for loop power by customer but external to transducer.

Figure 3-84. QAX Shield Wiring

Notes 1. Field Signals interface to the standard 56 pin Q-line front edge connector. The DIOB address and address protection jumpers are located on this connector. Each input requires a +, -, and shield pin. 2. The density of the card requires unique cabling to the field termination half shells. The QAX requires the use of the Enhanced Q-line B cabinet and terminations (2 halfshell termination blocks per card) (see Figure 3-83). 3. If it is necessary to interface to current loops, appropriate termination resistors will be required to be placed across to (+) and (-) inputs on the “A” terminal block to convert the current to the proportional voltage. For example, with a Group 5 card at 5V and 20mA current, a 250Ω resistor is used. (Using Ohm’s law of V=IR, rearranging to V/I = R, R = 5/0.02 = 250Ω.

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3-10. QAX

Recommended Standard B-Cabinet Configuration The following Q-Crate configuration is recommended when using 15 or less QAX cards.

B-Cabinet

Halfshell Terminal Blocks 1

QAX #2

QAX #4

QAX #6

Q104

Q112

Q120

QAX #7

QAX #9

QAX #11

Q202

Q210

Q218

QAX #8

QAX #10

QAX #12

Q204

Q212

Q220

QAX #13

QAX #15

Q302

Q310

Q422

Q406 Q408

Zone H

Q402

Zone G

Q404

Q304

Q324

QAX #14

Q322

Q118

Q318

Q110

Q424

Zone F

6

Q320

Zone E

Q102

Q418

Slot Number

QAX #5

Q420

Zone D

QAX #3

Q316

Q-Crate Location

11

Q414

Zone C

6

Q416

Zone B

5

QAX #1

Q312

Channel Number

4

Q410

0

3

Q412

Zone A 5

2

Figure 3-85. QAX Recommended Configuration

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3-10. QAX


A

CARD

1

A

2A

1

1

(−)

3A

2

2

1A

3

3

POINT 0 TRANSDUCER (+)

2B

4

4

(-)

3B

5

5

1B

6

6

(SHIELD) POINT 1 (+)

6A

7

7

(−)

7A

8

8

5A

9

9


6B

10

10

(−)

7B

11

11

5B

12

12


10A

13

13

(−)

11A

14

14

9A

15

15


10B

16

16

(−)

11B

17

17

9B

18

18


PE

PE

EDGE-CONNECTOR A

2

A

14A

1

1

(−)

15A

2

2

13A

3

3

POINT 6 TRANSDUCER (+)

14B

4

4

(-)

15B

5

5

13B

6

6


18A

7

7

(−)

19A

8

8

17A

9

9


18B

10

10

(−)

19B

11

11

17B

12

12


22A

13

13

(−)

23A

14

14

21A

15

15


22B

16

16

(−)

23B

17

17

21B

18

18


PE

PE

Note The QAW inputs may be grounded in the field or at the B cabinet as shown.

Figure 3-86. QAX CE MARK Wiring Diagram

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3-11. QAXD

3-11. QAXD QAX Digital Daughter Board (Style 4256A65G01 through G06)

3-11.1. Description The 12 point analog input module may consist of the mother board (referred to as the QAX) with a set 12 low level daughter boards (referred to as QAXD boards). The daughterboards attach to the mother board via SIMM connectors located on the QAX mother board. The QAX mother board contains the DIOB interface, the processor for data manipulation and buffering, the timing and power control for the daughter boards and the termination and signal conditioning for the field interface. The daughter boards contain the A/D circuitry.

Table 3-58. QAXD Card Groups and Capabilities

Group

Range Low-Level Groups

GO1


GO2

-12.5mV to 50mV (-50mV to 50mV at reduced accuracy)

GO3

-25mV to 100mV (-100mV to 100mV at reduced accuracy) High-Level Groups

GO4

0 to 1V

GO5

0 to 5V

GO6

0 to 10V Note All daughter boards on the configured module must be the same voltage range.

The features of each daughter board are provided by the custom resistor network. The resistor networks are used to generate calibration voltages from the precision voltage reference and to scale the preamplifier so that the output of the preamplifier provides the same voltage swing for all groups.

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3-11. QAXD

The input multiplexer switches between the input voltage and the calibration voltages provided by the precision voltage reference and the resistor network. Like the QAV/QAW the counter is incremented by short duration stoppages of PSD (~13 µ sec.) and the counter is reset by longer stoppages of PSD (~194 µ sec.). The counter nodes are different depending on whether the card is high-level or low-level as shown in the Table 3-59: Table 3-59. QAXD Counter Nodes

Node

High Level

Low level

Q0

VIN

VIN

Q1

REF (+100% full scale)

OTD (-150% full scale)

Q2

ZERO (0% full scale)

BIAS (0% full scale)

Q3

N/A

REF (+100% full scale)

Since the low-level card has the OTD (open thermocouple detect node) and the order of the other nodes is slightly different, it is necessary for the QAX mother board’s processor to know which type of daughter board is installed. A 1 Ω resistor is installed on the high-level board between pin 6 at the SIMM connector and logic ground. On the low-level board, this resistor is absent. Therefore, pin 6 is essentially grounded on the high-level board and left floating on the low-level board. All 12 “pin sixes” on the mother board are daisy chained, pulled-up, and routed to bit 4 of the mother board’s status register. When bit 4 of the status register is logic 1/0, low/ high-level boards are present. As mentioned in the QAX reference sheets, the PSD signal has a 25% duty cycle which necessitates the need for a transformer discharge circuit. To provide a load for the discharge circuit (FET and Schottkey diode on the mother board), a 150 Ω resistor is provided between the transformer primary and pin 4 of the SIMM connector. The integrator/synchronous comparator circuit used to generate the voltage to frequency conversion operate essentially the same as the corresponding circuit on the QAV/QAW. Also the capacitor discharge circuit used to generate the frequency input pulse for the 12 counters on the mother board operates similar to the QAV/ QAW. The +/-15 volt power supply on each daughter board uses shunt regulation to provide a low input to output voltage dropout.

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3-11. QAXD

The QAXD cards provide consistent counts among all groups on a % full scale basis. While the high-level boards can read negative values, no accuracy specification is provided at this time. The approximate counts for each QAXD as a percentage of full scale over a 200 msec sampling time is as follows:

M0-0053

Percent of full scale

Counts

+100

12,600

0

8,400

-100

4,200


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3-12. QAXT

3-12. QAXT Terminal Block Temperature Sensing (Style 4256A86G01)

3-12.1. Description Applicable for use in the CE MARK Certified System The QAXT printed circuit board provides temperature sensing of the terminal block (at the point where the thermocouple wire is terminated). The QAXT facilitates “Cold Junction” or “Reference Junction” compensation in a QAX based thermocouple input temperature measuring system. The QAXT printed circuit board complements the QAX card when used to measure temperatures with thermocouple inputs. The QAX senses the QAXT output between the (+) and (-) input terminals. The QAX card powers the QAXT via the Channel #12 (Shield) (+12V). The power return is via the “B” cabinet’s “PG” ground. With this configuration, the “B” and “A” cabinet “PG” grounds must be tied together. +12V

Voltage Reference

Zero Adjust

Gain Adjust

Common Sensor (Temperature to current conversion)

Op Amp Common Output

-12V J1 +12V Common

Switched Capacitor Converter

Voltage Divider

Common

Figure 3-87. QAXT Block Diagram

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3-12. QAXT

3-12.2. Features The QAXT provides half-shell temperature compensation for the QAX card. The QAXT can be configured to match the input ranges of any of the following three “low level” QAX scales. (For a listing of thermocouples and their temperature ranges see “Record Types User’s Guide” (U0-0131) or QAX card reference pages in this manual).

• • •

+ 20 mV +50 mV +100 mV

The output of the QAXT is automatically scaled to Engineering Units. This means that in any of the three configurations, the “0” output from the QAXT represents 0°C and the (+ Full Scale) output equals 100°C. Note Due to operating limits of the QAXT, the temperature output is limited to the range of 0°C to 60°C.

3-12.3. Specifications

Table 3-60. QAXT Power Supply Voltages (from QAX)

Minimum 10.8 V

Nominal 10.0 V

Maximum 13.1 V

Table 3-61. QAXT Accuracy

Parameter

Specification*

Absolute error

+1.0°C over the ambient temperature range of 0 - 60 °C.

Drift

+0.1°C - typical

*Does not include errors introduced during initial card calibration and errors of the QAX card.

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3-12. QAXT

Table 3-62. QAX/QAXT Based Thermocouple Compensation Kit Group Usage

QAX/QAXT Based Thermocouple Compensation Kit

Range

3A99722 G01

± 20 mV - Standard half-shells

3A99722 G02


3A99722 G03


3A99722 G04

± 20 mV - Remote I/O Assembly

3A99722 G05

± 50 mV - Remote I/O Assembly

3A99722 G06

± 100 mV -Remote I/O Assembly

3-12.4. Controls and Indicators

Header (JS1)

6 4 2

150% of Full Size

5 3 1

Jumper (J1)

(+)

SHLD

(-)

Figure 3-88. QAXT Card Components

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M0-0053

3-12. QAXT

Jumpers The QAXT board contains a dual row, 3 - position header (JS1) (see Figure 3-88). A program jumper (J1) is used to short posts on the adjacent rows of the header. The jumper selects one of the three possible ranges (20, 50 or 100 mV) to match the QAXT to the corresponding QAX Group: Table 3-63. QAXT Jumpers

Header Reference Designator

Posts Shorted

JS1

*1-2

Scales to 1.0 mV/°C for Group 03 and 06 QAX cards.

JS1

3-4


JS1

5-6


Result

*Default QAXT jumper configuration.

3-12.5. Wiring Table 3-64. QAXT Terminations

Terminal Indicator

Signal

(+)

Output

20 mV, 50 mV, or 100 mV Full Scale, jumper selectable.

SHLD

+12V

The cable shield supplies power from the QAX.

(-)

Common

Description

Output reference.

B-Cabinet Installation 1. The “B” type cabinets must be equipped with an isolated bus bar (1B29912 Sub 2 or later) (see Figure 3-90). This bus bar must be connected to the “A” cabinet PG ground to facilitate the power return for the QAXT. 2. Half shells for QAX cable must be adjacent (side-by-side, not vertically) Point Number

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Termination Point

1

Terminal 1, bottom of left half-shell

12

Terminals 16, 17, 18, top of the adjacent (right) half-shell


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3-12. QAXT

Installing R75 Jumper A jumper must be installed across R75 on the QAX card (as shown in Figure 3-89) when using the 12th input point on a QAX card, with the QAXT card. This QAX card (with R75 jumper installed) is no longer exchangeable with a standard QAX card.

WESTINGHOUSE MADE IN U.S.A.

R69 LE1 POK

R76

R75

Install Jumper

R70 LE2 CAL

REMOVING MODULES WILL VOID CALIBRATION

QAX Card

Figure 3-89. QAX Card with R75 Jumper Installed

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3-12. QAXT

Ground Bar

Note: Component side of QAXT towards terminal block. 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

QAXT Card

Half-Shell

Protective Cover

Figure 3-90. QAXT Standard Half-Shell Cabinet Installation

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3-12. QAXT

Ground Bar

Note: Component side of QAXT towards terminal block. 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

QAXT Card

Half-Shell

Protective Cover

Figure 3-91. QAXT Remote I/O Half-Shell Cabinet Installation

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M0-0053

3-13. QBE

3-13. QBE Q-Line Bus Extender (Style 7379A84G01 through G02)

3-13.1. Description Applicable for use in the CE MARK Certified System The QBE card links DIOB backplanes between different card cages. This card provides DIOB extension within the microprocessor-based or WDPF process control systems while reducing transient potential differences between card crate grounds to a safe level. The QBE card, together with compatible flat-flex cable assemblies, provides a continuous DIOB for multiple card-cage system configurations (see Figure 3-92).

DIOB

Clamp Circuit

Level Shift and DMA Clamp “UCLOCK”

On-Card Power Supplies

Bus Discharge Circuit “G01”

MBU Power

DIOB Bus Expansion To/From Adjacent QBE cards

+12 VDC

Common

Figure 3-92. QBE Block Diagram

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3-13. QBE

3-13.2. Features The QBE card provides the following functions for Q-line applications:

•

Signal transfer from one Q-line card crate to another with provision to eliminate driver latch-up

• • •

Distributed Input/Output Bus (DIOB) discharge to eliminate data errors. Signal-level clamping for all DIOB signals. Signal-level shifting for signal UCLOCK.

The thirty-four conductor Distributed I/O Bus (DIOB) is the protocol and structure for Q-Line I/O data collection and distribution. The DIOB permits an eight-bit, byte-oriented digital exchange of information between a multiplexing controller and a variety of Q-line point cards. Physically, the DIOB consists of a number of printed circuit backplanes (one per card cage) which are linked together by interposing paddle cards and flat-flex cable assemblies. When a DIOB is extended beyond a single printed circuit backplane, it becomes susceptible to problems caused by transient differences between card cage DIOB ground potentials. The problems that occur are data errors and driver latchup. The QBE card is designed to link the printed circuit DIOB backplanes in different card cages together and at the same time reduce transient potential differences between card crate ground to a safe level (see Figure 3-93). These transient ground potential differences may be due to industrial noise, IEEE surge, or card insertion. A DIOB may be extended beyond a single card cage backplane by transferring the 25 DIOB signals to adjacent card cage backplanes via the QBE card and compatible flat-flex cable assemblies, thus providing a continuous bus for multiple card cages. The QBE card also links the DIOB grounds in each cage together, but has no provision for distributing or transferring power to the DIOB. Studs mounted on the rear of each DIOB printed circuit backplane receive power from the 13 VDC power supply, and transfer the power to the printed circuit backplane DIOB power conductors. A two-point terminal block located near the upper front edge of the QBE card is used to supply power to the Multibus-to-DIOB interface card (MBU/MSQ).

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M0-0053

3-13. QBE

13 VDC Primary Supply

To 50-pin DIOB Edge Connector of the MBU/MSQ Card

13 VDC Backup Supply

G01 QBE Card

DIOB Backplane

J2 Connector J3 Connector Q-Line Card Crate

50-conductor Flat-Flex Cable Assembly G01 QBE Card

DIOB Backplane

J2 J3

To MBU/MSQ Card Power Terminals (Redundant DPU Only) DIOB Backplane

G01 QBE Card J2 J3

Note: In this configuration, the DIOB is controlled by a Multibus controller card. The MBU or MSQ card serves as an interface between the DIOB and the Multibus.

To 50-pin DIOB Edge Connector of the MBU/MSQ Card (Redundant DPU Only)

Figure 3-93. Typical, Multicrate, Q-Line System Using QBE Card Interfacing

The QBE card’s 34-pin J1 backplane connector is normally inserted into the DIOB backplane’s right-most card-edge connector. On the front edge of the QBE, two 50-pin connectors (J2 and J3) interface with 50-conductor flat-flex cable assemblies, transferring the 25 DIOB signals via the cable assemblies to QBE cards located in adjacent card cages (see Figure 3-94). The DIOB grounds of adjacent card crates are linked together by the same QBE cards and cable assemblies. Note The QBE card will not interface to the front edge connectors of the QMT, QPD, or QPP cards.

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3-13. QBE

If the QBE card’s fuse blows, the QBE card “pulls down” the DIOB if the frequency of DIOB word cycles is less than 200/sec. A word cycle involves the transfer of two-bytes of data between the controller and a point card. All DIOB signals except UCLOCK are nominally +11 VDC logic signals. UCLOCK is a nominal +5 VDC logic signal which is inverted and level shifted to a +11 VDC logic level for transmission over the flat-flex cable assemblies that link the QBE cards of adjacent crates together. The card cage that houses the UCLOCK signal source has a QBE mounted in it that takes the +5 VDC UCLOCK signal off the card cage DIOB backplane, inverts it, and shifts it to +11 VDC level (UCLOCK). UCLOCK is transferred to the QBE card’s J2 and J3 front edge connectors where it is transmitted to other QBE cards on the same DIOB. These QBE cards receive the +11 VDC UCLOCK signal via their J2 and J3 front edge connectors. UCLOCK is then inverted, level shifted to a +5 VDC level (UCLOCK) and is transferred to the card cage’s DIOB backplane via the QBE card’s J1 connector. The user may use jumpers to select what type of UCLOCK level shift is required for a specific QBE card. The QBE card is available in two assembly groups:

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•

Group 1 provides DIOB signal transfer and clamping, bus discharging of the DIOB data lines (UDAT 0-7) and the DEV-BUSY line, UCLOCK level shifting, and distributes twelve volt power to the MBU/MSQ card (see Figure 3-95).

•

Group 2 provides the same functions as Group 1 minus the DIOB discharging feature.


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3-13. QBE

M0-0053 3-204


Figure 3-94. QBE Card Functional Block Diagram

To DIOB Crate Backplane

24

25

MBU/ MSQ Card Power 25

J1

+12 VDC DIOB Common

24

UCLOCK

Level Shift and Clamp Circuits

Clamp Circuit (All DIOB Signals Except UCLOCK)

UCLOCK

Data-gate

J2

R/W

15 Volt Supply 0.8 Volt Supply

5 Volt Supply

Bus Discharge Circuit (Group 1 Only)

9

UDAT0-7 and DEV-BUSY

J3

DIOB Signals and Common to and from Adjacent QBE Card

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3-13. QBE

Read Existing Point Card

Read Missing Point Card

Write to a Point Card

Data Gate

Input Output R/W Data line voltage without bus discharging Read “One” Typical DIOB Data line (UDAT 0 -7)

Read “Zero”

UDAT 0-7 BUS CLAMP ENABLE Signal (TP1)

Clamp Initiation Delay

Figure 3-95. QBE Timing Diagram of the Operation of the Bus Discharge Circuit

3-13.3. Specifications Power Requirements Table 3-65. QBE Power Supply Voltage

Minimum Primary Voltage:

12.4 VDC

Optional Backup:

12.4 VDC



Table 3-66. QBE Internal Power Supply Voltages

Minimum 5 VDC Supply

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4.80 VDC


Maximum 5.20 VDC

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3-13. QBE

Table 3-66. QBE Internal Power Supply Voltages (Cont’d)

Minimum

Maximum

Clamp Voltage Supply

0.60 VDC

1.00 VDC

15 VDC Supply

13.5 VDC

16.50 VDC

Current (Supplied by the DIOB) Group 1: 500 mA maximum Group 2: 350 mA maximum Maximum Power Required Group 1: 6.6 watts Group 2: 4.6 watts UCLOCK Signal Static Parameters

Table 3-67. QBE +5 VDC to +11 VDC Level Shift Circuit

Min. Voltage Output VOL Low

-0.6 VDC

Max. 1.0 VDC

Voltage Output VOH High

10.0 VDC

Voltage Input VIL Low

−0.6 VDC

0.8 VDC

Voltage Input VIH High

2.0 VDC

5.2 VDC

Condition IOL = 15.2 mA IOH = 5.0 mA

Input Current IIH High

0.10 mA

VI = 2.0 VDC

Input Current IIL Low

−1.20 mA

VI = 0.5 VDC


Min. Voltage Output VOL Low

−0.6 VDC


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Max.

Condition

0.4 VDC

IOL = 5 mA

5.2 VDC

IOH = 0 mA


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3-13. QBE


Min.

Max.

Condition IOH = −8 mA


2.5 VDC

Voltage Input VIL Low

−0.6 VDC

Voltage Input VIH High

8.5 VDC

3.0 VDC


LEDs QBE PWR MBU PWR

Jumpers

Figure 3-96. QBE Card Components

Light Emitting Diodes (LED) The QBE card uses two LEDs shown in Figure 3-96. The QBE PWR LED indicates (when lit) that the QBE card fuse is intact and that the card is receiving power from the DIOB power supply. The MBU PWR LED indicates (when lit) that the MBU/MSQ card is intact and that DIOB power for the MBU/MSQ card is available. Jumpers Jumpers are used to select the Transmit Mode, Receive Mode, or No Level Shift Mode for the DIOB signal UCLOCK. Figure 3-97 through Figure 3-99 show the required jumper configurations.

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M0-0053

3-13. QBE

NO LEVEL SHIFT

O G

O H

UCLOCK JU5 (ITEM 54) O E

A XMIT

F RECV XMIT

C

RECV

JU5 (ITEM 54)

D

O B

Figure 3-97. QBE Transmit Mode Jumper Configuration

O G

NO LEVEL SHIFT UCLOCK

C

XMIT

O H JU5 (ITEM 54) E

RECV

F

O A XMIT

RECV

JU5 (ITEM 54)

O D

B

Figure 3-98. QBE Receive Mode Jumper Configuration

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3-13. QBE

NO G

O XMIT

H

O

O

O

A

E

RECV

E XMIT

RECV

C

LEVEL SHIFT UCLOCK

JU5

O

O

B

D

Figure 3-99. QBE No Level Shift Mode Jumper Configuration

Signal Interface DIOB signals are input to the QBE card through the DIOB backplane to the J1 connector. Signals are output from the QBE card on the J2 and J3 connectors. Figure 3-94 shows the location of the J1, J2 and J3 connectors. Table 3-69 gives the J1 connector pin assignments and signal names and Table 3-70 gives the J2 and J3 connector pin assignments and signal names. Table 3-69. QBE J1 Connector Pin Assignments and Signal Names

Solder Side Signals

Card-Edge Pin Numbers

Component Side Signals

PRIMARY

1

2

PRIMARY

BACKUP

3

4

BACKUP

GROUND

5

6

GROUND

UADD 0

7

8

UADD 1

UADD 2

9

10

UADD 3

UADD 4

11

12

UADD 5

UADD 6

13

14

UADD 7

HI-LO

15

16

R/W**

UNIT

17

18

DATA-GATE

GROUND

19

20

DEV-BUSY

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3-13. QBE

Table 3-69. QBE J1 Connector Pin Assignments and Signal Names (Cont’d)

Solder Side Signals



UDAT 0

21

22

UDAT 1

UDAT 2

23

24

UDAT 3

UDAT4

25

26

UDAT 5

UDAT6

27

28

UDAT 7

GROUND

29

30

UFLAG

UCAL

31

32

USYNC

UCLOCK*

33

34

GROUND

*UCLOCK is a +5 VDC TTL level signal **Formally signal DATA-DIR.

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3-13. QBE

Table 3-70. QBE J2 and J3 Connector Pin Assignments and Signal Names

Solder Side Signals



GROUND

1

2

UADD 0

GROUND

3

4

UADD 1

GROUND

5

6

UADD 2

GROUND

7

8

UADD 3

GROUND

9

10

UADD 4

GROUND

11

12

UADD 5

GROUND

13

14

UADD 6

GROUND

15

16

UADD 7

GROUND

17

18

HI-LO

GROUND

19

20

R/W**

GROUND

21

22

UNIT

GROUND

23

24

DATA-GATE

GROUND

25

26

DEV-BUSY

GROUND

27

28

UDAT 0

GROUND

29

30

UDAT 1

GROUND

31

32

UDAT 2

GROUND

33

34

UDAT 3

GROUND

35

36

UDAT 4

GROUND

37

38

UDAT 5

GROUND

39

40

UDAT 6

GROUND

41

42

UDAT 7

GROUND

43

44

UFLAG

GROUND

45

46

UCAL

GROUND

47

48

USYNC

GROUND

49

50

UCLOCK*

*UCLOCK is a +11 VDC CMOS level signal **Formally signal DATA-DIR.

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M0-0053

3-14. QBI

3-14. QBI Digital Input (Style 2840A80G01 through G11)

3-14.1. Description The QBI card had been superseded by the QID card. For new applications, refer to the following table to determine the equivalence between QID and QBI cards: Table 3-71. QBI QID Card Equivalents

M0-0053

QBI Group

Equivalent QID Group

Input Level

Inputs

G01

G01

5 VDC

16

G02

G08

12 VDC

16

G03

G09

12 VAC/DC

16

G04

G03

24 VAC/DC

16

G05

G05

48 VAC/DC

16

G06

G05

48 VDC

16

G07

G07

125 VDC

16

G08

G07

120 VAC/DC

16

G09

G09

12 VAC/DC

16

G10

G03

24 VAC/DC

16

G11

G12

120 VAC

16


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3-14. QBI

The QBI card provides signal conditioning for 16 digital voltage process inputs, and interfaces these signals to the DIOB (see Figure 3-100). The 16 single-ended (one-wire) inputs share a common line. Eleven different QBI groups (G01 through G11) provide a variety of input voltage ranges (Table 3-72).

Figure 3-100. QBI Block Diagram

3-14.2. Features The QBI has the following features:

• • • • • • •

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IEEE surge-withstand protection. 500 VDC common mode voltage. Separate status indicating LED’s for each input. Optional 5V, 12V, 24V, 48V or 120V input ranges. Optical isolation for each input. Any DIOB controller card can read the QBI. The common wire can be connected to either + or − input supply voltage


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3-14. QBI

The field signals enter the card through the 16 single-ended inputs. Each signal is rectified and turns on an optical isolator. The signal is conditioned, latched into a buffer, and upon request, transferred to the DIOB. As data appears at the latch inputs, a LED lights to indicate the digital input status. Table 3-72. QBI Card Group Specifications

Group Number

Input Level

Propagation Time (Typical)

Common Line Connection

IEEE SWC

G01

5 V Logic

0.1 msec

+5 VDC

No

G02

12 V Logic

0.1 msec

+12 VDC

No

G03

12 VDC

4 msec

+12 VDC

Yes

G04

24 VDC

4 msec

+24 VDC

Yes

G05

48 VDC

4 msec

+48 VDC

Yes

G06

48 VDC

4 msec

48 VDC RETURN

Yes

G07

125 VDC

4 msec

125 VDC RETURN

Yes

G08

120 VAC

11 msec

–

Yes

G09

12 VDC

4 msec

12 VDC RETURN

Yes

G10

24 VDC

4 msec

24 VDC RETURN

Yes

G11

120 VAC

17 msec

–

Yes

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3-14. QBI

Block Diagram A functional block diagram of the QBI is shown in Figure 3-101. DIOB 1 Hi-lo

Point 0

8

Data

16

Bus Drivers

16

2:1 Multiplexer

(16)

Signal Conditioning

Point 15

Optical Coupling And R-c Filtering

Select

Enable

16 Circuit Common Card Edge Indicators

1

Address

Address Comparator

Jumper Address Selection

Data-dir

DIOB Ground

Figure 3-101. QBI Card Functional Block Diagram

3-14.3. Specifications Input specifications are defined in Table 3-73. Table 3-73. QBI Card Input Specifications

Group

ON Input Voltage (VDC) Min/Max

OFF OFF Input Input Voltage Current (VDC) (mA dc)

ON Input Current (mA dc) Min/Max

Power In Propagation Front End-All with Time Units (msec) On, (Nominal Voltage) Min/Max (Watts)

G01

4

6

2

0.19

7.75

16.0

–

0.2

1

G02

10

15

2.5

0.19

7.5

16.25

–

0.2

2.3

G03

10

15

2.5

0.19

7.5

16.25

1.1

7.0

2.3

G04

20

30

3

2.0

8.0

16.0

1.1

7.0

4.6

G05

40

60

4

0.35

8.5

16.75

1.1

7.0

9.2

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3-14. QBI

Table 3-73. QBI Card Input Specifications (Cont’d)

ON Input Voltage (VDC) Min/Max

Group

OFF OFF Input Input Voltage Current (VDC) (mA dc)

ON Input Current (mA dc) Min/Max

Power In Propagation Front End-All with Time Units (msec) On, (Nominal Voltage) Min/Max (Watts)

G06

40

60

4

0.35

8.5

16.75

1.1

7.0

9.2

G07

100

150

6

0.5

7.0

14.2

1.1

7.0

19.0

G08

100*

150*

6*

0.8*

7.0* 14.2*

2.5

30.0

19.0

G09

10

15

2.6

0.17

7.75 16.25

1.0

7.0

2.3

G10

20

30

3

2.0

8.0

16.0

1.1

7.0

4.6

G11

100*

150*

26.0*

0.8*

6.0*

2.5*

5.5

43.0

19.0

Notes * VAC RMS or mA ac RMS as indicated

Group Characteristics Refer to the following table. Group

Description

1

5 VDC logic with +5 VDC common line connection (0.1 msec propagation),

2

12 VDC logic with +12 VDC common line connection (0.1 msec propagation).

3

12 VDC logic with +12 VDC common line connection (4 msec propagation).

4


5


6

48 VDC with 48 VDC return common line connection (4 msec propagation)

7

125 VDC with 125 VDC return common line connection (4 msec propagation).

8

120 VAC (11 msec propagation).

9


10


11

120 VAC high threshold (17 msec propagation).

Power Supply Primary: +13 VDC + 0.1 VDC

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3-14. QBI

Backup: +12.6 VDC +0.2 VDC Current: 200 mA (maximum) supplied by DIOB Electrical Environment IEEE Surge withstand capability (not available on G01 and G02). Common Mode Voltage: 500 VDC or peak ac (line frequency)

3-14.4. Card Addressing and Data Output The QBI card address is established by eight jumpers on the front card-edge connector as shown in Figure 3-102. The insertion of a jumper encodes a “1” on the address line.

Card-edge Connector (Front View)

Blank:

A7 = 0

Blank:

A6 = 0

Jumper:

A5 = 1

Blank:

A4 = 0

Blank:

A3 = 0

Blank:

A2 = 0

Jumper:

A1 = 1

Jumper:

A0 = 1

Card Address = 00100011 (X' 23')

Figure 3-102. Example of a QBI Card Address Jumper Assembly

Connections and Field Cabling The digital inputs enter the QBI card on the front-edge connector. The pin assignments for the connector are listed in Table 3-74. Table 3-74. QBI Card Front-Edge Connector Pin Allocations

Input Digital Bit Number

PC Card Edge Pin

Field Terminal Block Terminal Number

B15

17B

17

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3-14. QBI

Table 3-74. QBI Card Front-Edge Connector Pin Allocations (Cont’d)

Input Digital Bit Number

PC Card Edge Pin


B14

17A

16

B13

15B

15

B12

15A

14

B11

13B

13

B10

13A

12

B9

11B

11

B8

11A

10

B7

9B

9

B6

9A

8

B5

7B

7

B4

7A

6

B3

5B

5

B2

5A

4

B1

3B

3

B0

3A

2

Common or Return

1A and 1B

Figure 3-103 through Figure 3-106 show typical wiring to the various groups of the QBI card. Note The common terminal (terminal 1) for G01, G02, G03, G04, and G05 is tied to the positive supply voltage. The common terminal (terminal 1) is tied to the negative supply voltage for G06, G07, G09 and G10. G08 and G11 are used for AC inputs and the common terminal is tied to one of the 120 VAC supply leads.

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3-14. QBI

Field Cable Length When 120 VAC is used to wet contacts (G08 and G11), cable length is limited by: Cable Stray Capacitance: 15,000 pF (maximum) Stray Capacitance: 50 pF/ft. (typical) Maximum Cable Length: 250 ft.

QB1 G01 and G02

POINT 15

16

POINT 0 COMMON -

+

Logic Voltage

Logic Voltage G01 5V G02 12 V

Figure 3-103. Typical G01 and G02 QBI Card – Point Wiring Diagram

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3-14. QBI

Figure 3-104. Typical G03, G04 and G05 QBI Card – Point Wiring Diagram

Figure 3-105. Typical G06, G07, G09 and G10 QBI Card – Point Wiring Diagram

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3-14. QBI

Figure 3-106. Typical G08 and G11 QBI Card – Point Wiring Diagram

3-14.5. Controls and Indicators Separate status-indicating LEDs for each input are located at the front of the card (see Figure 3-107).

LED Detail

LEDs PWR 15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

Figure 3-107. QBI Card Components

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3-14. QBI



20B

CARD


20A 19B

A

19A

18

17B

17

17A

16

15B

15

15A

14

13B

13

13A

12

11B

11

11A

10

9B

09

9A

08

BIT 5

7B

07

BIT 5

07

BIT 4

7A

06

BIT 4

06

BIT 3

5B

05

BIT 3

05

BIT 2

5A

04

BIT 2

04

BIT 1

3B

03

BIT 1

03

3A

02

BIT 0

02

1B

01

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6

BIT 0

5A

B

3/4 A

18 BIT 15

17

BIT 14

16

BIT 13

15

BIT 12

14

BIT 11

13

BIT 10

12

BIT 9

11

BIT 8

10

BIT 7

09

BIT 6

08

INTERNAL BUS STRIP

01

1A

EDGE-CONNECTOR

CUSTOMER CONNECTIONS BLACK

RED

TP BUS +

~

−

Figure 3-108. QBI Wiring Diagram

Installation Notes (Refer to Figure 3-108):

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Group

TP Bus - Black (QBI -1A)

TP Bus - Red (QBI -19B)

3

+ 12 V

+ 12 V Return

4

+ 24 V

+ 24 V Return

5

+ 48 V

+ 48 V Return


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3-14. QBI

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Group

TP Bus - Black (QBI -1A)

TP Bus - Red (QBI -19B)

6

48 V Return

+ 48 V

7

125 V Return

+ 125 V

8

120 VAC (Hot)

120 VAC (Neutral)

9

12 V Return

12 V

10

24 V Return

24 V

11

120 VAC (HOT)

120 VAC (Neutral)


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3-15. QBO

3-15. QBO Digital Output (Style 2840A79G01 through G05)

3-15.1. Description G01 through G05 are applicable for use in the CE MARK Certified System The QBO card receives DIOB signals and provides up to 48 VDC, 300 mA, field-level signals for relay coils, stepping motors, lamps, etc., within the plant environment (see Figure 3-109). This card contains 16 current sinking transistor outputs with a common return line. An on card read/write latch provides an 8-bit memory function. This card also contains switch-selectable dead-computer time-out and flasher circuitry.

DIOB Data

Data Latch

Address

Bus Drivers

Optical Isolators

Address Decoder

Card-Edge LED Indicators

Flash/ Non-Flash Select

Current Sinking Drivers ... RTN

0

15

Source

Field Process Outputs

Figure 3-109. QBO Block Diagram

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3-15. QBO

3-15.2. Features This card provides the following features:

• • • • • • • •

IEEE surge-withstand protection Read/write output data operation On-card power-up, bus, and dead-computer time-out resets Card-edge LED indicator for each output Optional flashing output to drive field process lamps Switch-selectable time-out periods Switch-selectable flasher periods Compatible with any DIOB controller

The QBO card is available in five groups (G01 through G05), offering a variety of output parameters.

•

G01 provides a high-voltage output and a capability of flashing the output and varying the dead computer timeout

•

G02 has high-voltage outputs with steady operation (no flash) and a set value of 62 msec for timeout

•

G03 provides logic outputs and is capable of flashing the output and varying the timeout

•

G04 has logic level outputs with steady operation (no flash) and a set value of 62 msec for timeout

•

G05 is the same as G03 except that a 10 kΩ on card pull-up resistor is connected between pins 19A and 19B.

The QBO Card complies with the DIOB interface design specifications. This card may be used in a Q-crate assembly.

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3-15. QBO

Block Diagram

RETURN

POINT 0

POINT 15

(CLAMP)

SUPPLY

A functional block diagram of the QBO is shown in Figure 3-110.

THREE BITS RATE SELECT, ONE BIT DISABLE/ENABLE

(16) LATCH

CARD REFRESH UNIT

EIGHT

DATA

POWERUP

COMPARE

~

~

4

(16) DRIVERS

OR

OPTICAL ISOLATORS

LED’s

RESET LATCH

FRONT CONNECTOR EIGHT JUMPER ARRANGEMENT

4

FLASH/ NON-FLASH SELECTION

ONE BIT ENABLE, TWO BITS RATE ONE BIT DUTY CYCLE

CURRENT SINKING DRIVERS

ADDRESS

Figure 3-110. QBO Detailed Block Diagram

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3-15. QBO

3-15.3. Specifications Output Capabilities Parameter

G01 and 2

G03, 4, and 5

OFF Voltage

60 VDC (maximum)

20 VDC (maximum)

OFF Current

.5 mA (maximum)

.1 mA (maximum)

ON Voltage

2 VDC (maximum)

.5 VDC (maximum)

ON Current

300 mA (maximum)

16 mA (maximum)

Power Supply

• • •

Primary: +13 V +0.1 VDC Backup: +12.6 V + 0.2 VDC Current: 250 mA (maximum) supplied by DIOB

Electrical Environment IEEE Surge withstand capability Common Mode Voltage: 500 VDC or peak AC (line frequency)

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3-15. QBO

3-15.4. Card Addressing The QBO card address is established by eight jumpers on the top, front, card-edge connector. The insertion of a jumper encodes a “1” on the address line (Figure 3-111).

CARD ADDRESS = 11001010 (X ‘CA’)

JUMPER:

A7 = 1

JUMPER:

A6 = 1

BLANK:

A5 = 0

BLANK:

A4 = 0

JUMPER:

A3 = 1

BLANK:

A2 = 0

JUMPER:

A1 = 1

BLANK:

A0 = 0

CARD EDGE CONNECTOR (FRONT VIEW)

Figure 3-111. QBO Card Address Jumper Assembly

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3-15. QBO

Field Connections

~

Figure 3-112 shows typical field wiring for a QBO card. The digital outputs are brought out on the front edge of the card. The contact allocations are listed in Table 3-75.

QBO

Supply Io Load 15 + −

Point 15

Power Supply

(16) Io

Load 0

Point 0 Return

~

Ir (Max) = 16 X Io

Figure 3-112. QBO Typical Point Wiring

Note The QBO may be used to drive the coils of interposing relays. These relay contacts may be connected to the AC mains. For CE Mark certified systems, field wiring that carries the AC mains must have double insulation.

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3-15. QBO

Table 3-75. QBO Digital Output Contact Allocations Output Digital Bit No.

P-C Card Edge Pin No.

Field Terminal Block Terminal No.

SUPPLY CLAMP

19A and B

18

B15

17B

17

B14

17A

16

B13

15B

15

B12

15A

14

B11

13B

13

B10

13A

12

B9

11B

11

B8

11A

10

B7

9B

9

B6

9A

8

B5

7B

7

B4

7A

6

B3

5B

5

B2

5A

4

B1

3B

3

B0

3A

2

RETURN

1A and B

1

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3-15. QBO


LEDs A B C D

Output Flash Switch Update A B C D Period Switch

Figure 3-113. QBO Card Components

Separate LEDs for each output are located at the front of the card to indicate the status of each output. The flash option is available on G01, G03, and G05. G02 and G04 cards have a steady only operation If the QBO card is not periodically updated, the card resets. The update period is set by four DIP switches as given in Table 3-76 and shown in Figure 3-113. Table 3-76. QBO Card Reset Switch Position

Dip Switch

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A

B

C

D

0 0 0 0 1 1 1 1 X

0 0 1 1 0 0 1 1 X

0 1 0 1 0 1 0 1 X

0 0 0 0 0 0 0 0 1

Reset Time 62 ms + 20% 125 ms + 20% 250 ms + 20% 500 ms + 20% 1 sec + 20% 2 sec + 20% 4 sec + 20% 8 sec + 20% No time out, data latched (X = don’t care)


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3-15. QBO

For the QBO card groups that have optional output flashing, DIP switches select the rate at which the outputs are turned on and off. Table 3-77 lists the DIP switch positions and available selections. QBO card components are shown in Figure 3-113. Table 3-77. QBO DIP Switch Positions Switch B, C = Result Switch A

Switch B

Switch C

Switch D

0, open = output steady 1, closed = output flashing

0 0 1 1

0 = 5 flashes/sec 1 = 2.5 flashes/sec 0 = 1.25 flashes/sec 1 = 0.625 flashes/sec

0 = 33% ON, 67% OFF 1 = 67% ON, 33% OFF

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3-15. QBO


External Power Supply

-

+ Terminal Block #6-32 Screw

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7

Common

A

B

20A

20

20

19B

19

19

19A

18

18

17B

17

20B

Card

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Half Shell Extension (B-block)

17A

16

15B

15

15A

14

13B 13A

13 12

11B

11

11A

10

9B 9A

09 08

Bit 15

17

Bit 14

16

Bit 13

15

Bit 12

14

Bit 11

13

Bit 10

12

Bit 9

11

Bit 8

10

Bit 7

09

Bit 6

08

7B

07

Bit 5

7A

06

Bit 4

05

Bit 3

05

04

Bit 2

04

03

Bit 1

03

3A

02

Bit 0

02

1B

01

5B 5A 3B

3/4 A

07 Load

06

01

1A Customer Connections Edge-connector

Internal Bus Strip

Figure 3-114. QBO Wiring Diagram

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3-15. QBO


CARD 1A

EDGE-CONNECTOR

A

A

B

1B

1

01

3A

2

02

02

2

3B

3

03

03

3

5A

4

04

04

4

5B

5

05

05

5

7A

6

06

06

6

7B

7

07

07

7

9A

8

08

08

8

9B

9

09

09

9

11A

10

10

10

10

11B

11

11

11

11

13A

12

12

12

12

13B

13

13

13

13

15A

14

14

14

14

15B

15

15

15

15

17A

16

16

16

16

17B

17

17

17

17

19A

18

19B

19

19

19

19

-

20

20

20

20

+

PE

PE

18

01

1

.75A External Power

Figure 3-115. QBO CE MARK Wiring Diagram

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3-16. QCA

3-16. QCA Current Amplifier (Style 3A99118G01 through G02)

3-16.1. Description Groups 01, 02 are applicable for use in the CE MARK Certified System The Q-Line Current Amplifier (QCA) card provides variable offset and current amplification stages for Q-line servo driver cards used to drive EH actuators. The card is strictly an analog card where the DPU does not interact with the card's function or status. Two channels are available on the QCA. The input to each channel is another Q-card's actuator position request (Coil Drive Output) wired into the front-edge connector. Two outputs are available for each QCA channel. For an actuator having redundant coils, both channel outputs (Coil Drive A and B) are used to drive the coils. Otherwise, only one of the channel outputs (Coil Drive A) is necessary to drive the actuator. Before a QCA channel can drive an actuator, it must be calibrated according to the actuator position request coming from a Q-line servo driver card that is to be amplified by the QCA. By adjusting potentiometers and selecting resistors, the appropriate offset and current amplification is applied to the input signal to produce the desired coil drive signal range. The current boosting stage for each channel of the QCA is powered by + 21V and - 21V on board DC-DC converters derived from the +13V backplane supply. The two on-board supplies are not isolated from DIOB ground. The QCA is assembled to provide two groups: Group 1

Group 2

Input Voltage

0 to -10V

0 to -10V

Output Voltage

0 to 12.5V

Maximum Output Current Drive (per coil drive)

400mA

250mA 50 ohms

Maximum Load Resistance (per coil drive) Maximum Total Current Drive (all channels combined)

800mA

500mA

Channel Configuration

voltage input, voltage output, two channels, redundant outputs on each channel

voltage input, true current output, two channels, nonredundant channel outputs

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3-16. QCA

3-16.2. Features The QCA card is available in two groups and provides the following features:

• • • •

Two channels configured as voltage inputs Redundant voltage outputs (Group 1) Non-redundant true current outputs (Group 2) Maximum current drive capability: — 400mA per Group 1 channel — 250mA per Group 2 channel — 800mA total, all channels combined

•

Outputs are NOT isolated from DIOB ground

3-16.3. Specifications Power Requirements DIOB Supply Voltage: +12.4 VDC to 13.1 VDC Current (supplied by DIOB): 2.5A typ 3.0A max for Groups 1 and 2 under maximum load conditions Input Stage (See Figure 3-116 and Figure 3-117) Actuator Position Request Range (Vin): -12V to +12V Range Adjustment Stage (See Figure 3-116 and Figure 3-118) Resistor Ladder: RA2 + RB ≥ 2KΩ Output Voltage Range: adjust V2 to fall within -12V to +12V. Offset Adjustment Stage (See Figure 3-116 and Figure 3-119) Resistor Ladder: RC2 + RD ≥ 2KΩ Offset Voltage Range: adjust V3 to fall within 0 to -12V Output Voltage Range: adjust V4 to fall within -12V to +12V

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3-16. QCA

Output Gain Stage (See Figure 3-116, Figure 3-120, and Figure 3-121) Output Voltage of Control Amp: adjust gain of booster amp so that V5 falls within - 12 to + 12V Output Voltage of Booster Amp: ±15V max Closed Loop Gain (Group 1 only): Choose Rf-B so that the overall loop gain (Vout/V4) is 1 to 5 V/V, keeping as close to unity gain as possible. When selecting Rf-B, use precision resistors: Westinghouse drawing number - 669A664. Output Coil Drives - Group 1 (See Figure 3-116 and Figure 3-120) Tolerance: may be adjusted to desired value initially Voltage Output Temperature Coefficient: ±200 ppm/oC (±0.02%/oC) over the temperature range 0-60oC Tracking Accuracy: ±0.3% between a channel's redundant outputs at room temperature Tracking Temperature Coefficient: 30 ppm/oC between redundant output over the temperature range 0 - 60oC Maximum Load Current: ±400mA per channel (If redundant drives are used, each coil drive can drive up to 200mA each.) Output Coil Drives - Group 2 (See Figure 3-116 and Figure 3-121) Tolerance: may be adjusted to desired value initially Current Output Temperature Coefficient: ±400 ppm/oC (±0.02%/oC) over the temperature range 0-60oC Maximum Load Current: ±250mA per channel

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3-16. QCA

3-16.4. Signal Interface DIOB Connector The QCA draws power from the DIOB bus through a 34 pin card-edge connector on the DIOB backplane. The card-edge DIOB signal assignments are given in Table 3-78. Table 3-78. QCA DIOB Card Edge Connector Pinout Signal Name Component Side

Signal Name Solder Side

Pin #

Pin #

PRIMARY +V

2

1

PRIMARY +V

BACKUP +V

4

3

BACKUP +V

GROUND

6

5

GROUND

No Connection

8

7

No Connection

No Connection

10

9

No Connection

No Connection

12

11

No Connection

No Connection

14

13

No Connection

No Connection

16

15

No Connection

No Connection

18

17

No Connection

No Connection

20

19

GROUND

No Connection

22

21

No Connection

No Connection

24

23

No Connection

No Connection

26

25

No Connection

No Connection

28

27

No Connection

No Connection

30

29

No Connection

No Connection

32

31

No Connection

GROUND

34

33

No Connection

Field/Addressing Connector The front card edge of the QCA provides the connections to the field devices. All wires to the front-edge connector must be of 18 AWG wiring to support potentially high current draw. There are no card addressing pins since the card is not accessed by the DPU. Note For the QCA, no points on the half-shell or in the field at the actuator coil should be tied to earth ground. All GROUND points in Table 3-79 are DIOB ground.

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3-16. QCA

Table 3-79. QCA Field Front Card Edge Connector Signal Name Component Side

Pin #

Pin #


No Connection

28B

28A

No Connection

No Connection

27B

27A

No Connection

No Connection

26B

26A

No Connection

No Connection

25B

25A

No Connection

No Connection

24B

24A

No Connection

No Connection

23B

23A

No Connection

No Connection

22B

22A

No Connection

No Connection

21B

21A

No Connection

No Connection

20B

20A

No Connection

No Connection

19B

19A

GROUND

No Connection

18B

18A

No Connection

No Connection

17B

17A

No Connection

No Connection

16B

16A

No Connection

COIL DRIVE 2B *

15B

15A

GROUND

No Connection

14B

14A

No Connection

GROUND

13B

13A

COIL DRIVE 2A

No Connection

12B

12A

No Connection

VIN2

11B

11A

GROUND

No Connection

10B

10A

No Connection

GROUND

9B

9A

COIL DRIVE 1B *

No Connection

8B

9A

No Connection

COIL DRIVE 1A

7B

7A

GROUND

No Connection

6B

6A

No Connection

GROUND

5B

5A

VIN1

No Connection

4B

4A

No Connection

No Connection

3B

3A

No Connection

No Connection

2B

2A

No Connection

GROUND

1B

1A

No Connection

* For Group 2 (True Current Output) these signals are No Connection. VIN = Actuator Position Request COIL DRIVE 1A, 1B = redundant outputs of channel 1 (1B available only on Group 1 boards) COIL DRIVE 2A, 2B = redundant outputs of channel 2 (2B available only on Group 1 boards)

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3-16. QCA

3-16.5. Operation QCA Channel

Input Stage

Vin

V1

Range Adjustment Stage

V2

Offset Adjustment Stage

V4

-10Vref Output Gain Stage

V4

Coil Drive A (voltage or current output) Coil Drive B (voltage output only)

Figure 3-116. QCA Channel

Figure 3-116 shows a block diagram of the stages in a QCA channel. The actuator position request (Vin) comes to the QCA from servo driver cards through the frontedge connector. Once the signal is adjusted to the voltage and current levels needed to drive the actuator, it is sent out to the field through the front-edge connector as the coil drive signal. Input Stage

Invert Input Jumper

-

Disable +

Vin

10K

10K Rin

Enable

V1

+ Unity Gain Inverter

Figure 3-117. QCA Channel Input Stage

Figure 3-117 shows the input stage in a QCA channel. For voltage level Vin signals, Rin is 20kΩ, drawing minimal current from the input and keeping the input from floating if Vin is not connected to the channel. Input inversion is used when the actuator position request range is unipolar and opposite in sign of the desired unipolar output drive range. For example, the actuator position request range may be 0 to -10V, and the desired output voltage range may be 0 to 12V. In this case, the input inverting jumper should be enabled to achieve an output of correct polarity (see Figure 3-122).

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3-16. QCA

Range Adjustment Stage

RA1

-

RA2

V2 +

V1 1K RB

Figure 3-118. QCA Channel Range Adjustment Stage

Figure 3-118 shows the range adjustment stage in a QCA channel. The range adjust stage sets the base range of the output drive signal and allows the input position signal range to be converted to meet any current driving range (within card specs) for a variety of actuators. An adjustable voltage divider determines the signal range. The final output signal range is a result of the range and gain stages combined, for the gain stage magnifies the base range by an adjustable gain multiplier. RA1 is a potentiometer which enables precise adjustment of signal range according to the following equation: V2 = V1 * (RB/(RA1 + RA2 + RB))

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3-16. QCA

Offset Adjustment Stage

RC1

-

RC2

+

-10Vref

10K

Offset Jumper V2 Disable

10K

Enable V3

10K

50K

V4 + 10K

RD

Unity Gain Differential Amplifier

Figure 3-119. QCA Channel Offset Adjustment Stage

Figure 3-119 shows the offset adjustment stage in a QCA channel. The offset adjust stage handles bipolar and unipolar signal adjustments. This stage adds an adjustable offset which can translate a bipolar input signal into a unipolar servo drive signal (required by certain valves). This stage may also be configured to add in small offsets to unipolar signals to ensure the signal does not cross over 0V to an undesired signal polarity. If no offset is required, offset addition to the signal is bypassed by installing the channel's Offset jumper in the DIS (disable) position (see Figure 3-122). Do NOT pull out RC1, RC2, or RD to disable offset. Adjustment of the potentiometer RC1 enables precise adjustment of the offset to be added to the signal according to the following equation: V3 = -10Vref * (RD/(RC1 + RC2 + RD)) The offset adjustment stage has unity gain resulting in the following equation: V4 = V3 - V2

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3-16. QCA

Output Gain Stage - Voltage Output Configuration (Group 1 only)

Rf Rf-A

Rf-B

10K 20K 10K Ri V4

-

-

Rout

+

2Ω

Coil Drive A

10K

V5

+

Control Amp

Vout

Booster Amp

To Coil Drive B Circuitry (same as Coil Drive A above)

Figure 3-120. QCA Output Gain Stage - Group 1

The following closed loop gain equation applies to the output stage of Group 1 boards illustrated in Figure 3-120: Vout = -V4 * Rf/Riwhere Rf= Rf-A + Rf-B

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3-16. QCA

Output Gain Stage - Current Output Configuration (Group 2 only) Rf 10K 20K

10K Ri V4

10K Ri’

V5

+

-

Rout

Iout

+

8.25Ω

Vout

Coil Drive A

10K

Control Amp

Booster Amp Rf’ 10K

Figure 3-121. QCA Output Gain Stage - Group 2

The following closed loop gain equation applies to the output stage of Group 2 boards illustrated in Figure 3-121: Iout = -(V4/Rout)*(Rf/Ri) = -V4/Rout Ri = closely matched input resistors Rf = closely matched feedback resistors Rout = 8.25 ohms Channel Configuration Examples

Unipolar Voltage In - Unipolar Voltage Out (Group 1) This section contains calculations for selecting resistors for the following channel specifications:

• • •

Input Voltage: 0 to -10V Output Voltage: 0 to 12.5V Load Resistance: 50 ohms

1. Enable the invert jumper (shown in Figure 3-122) since the input voltage sign is opposite from the output voltage sign.

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3-16. QCA

2. Since the magnitude of the input must be gained up to get the full output voltage range, the output gain stage will need a gain greater than 1. Set the output gain stage to a gain of 2. This means Rf-B is 10KΩ (see Figure 3-120). 3. Referring to Figure 3-120: Vout MAX = 12.5V Vout, booster amp MAX = 12.5V + (Rout)*(Iout) = 12.5V + (2Ω)*(250mA) = 13V

which is less than the maximum 15V allowed. 4. If the output stage has a gain of 2, V4 in Figure 3-119 has the range: 0 to -6.25V. Assume no offset is needed (Offset jumper in DIS position), so the offset adjustment stage is a unity gain inverting stage which means V2 = 0 to 6.25V. 5. Since V2 = 0 to 6.25V and V1 = 0 to 10V (after the actuator position request has been inverted), V2 = 0.625*V1. This implies that: RB/(RA1 + RA2 + RB) = 0.625

Let RA1 = 1k potentiometer, RA2 = 4.53K, and RB = 7.96k. By adjusting the 1k potentiometer, the ratio of resistors falls between 0.590 and 0.637 which includes the desired 0.625 ratio. 6. The offset adjustment stage may be used to add a small offset to the valve position request to make sure the output voltage is always positive. If a 10 to 50 mV offset is desired: RD/(RC1 + RC2 + RD) = 0.001 to 0.005

Let RC1 = 50k potentiometer, RC2 = 9.76k, and RD = 50 ohms. By adjusting the 50k potentiometer, the ratio of resistors falls between 0.0008 and 0.0051. When multiplied by 10Vref, the desired 10 to 50mV offset is added to the signal. Unipolar Voltage In - Unipolar Current Out (Group 2) This section contains calculations for selecting resistors for the following channel specifications:

• • •

Input Voltage: 0 to -10V Output Current: 0 to 250mA Load Resistance: 50Ω

1. Enable the invert jumper (shown in Figure 3-122) since the input voltage sign is opposite from the output current sign. 2. Referring to Figure 3-121:

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M0-0053

3-16. QCA

Vout (booster amp MAX) = (Rload + Rout)*(Iout) = (50Ω + 8.25Ω) * 250mA = 14.56V which is less than the maximum 15V allowed.

The output stage has unity gain where Rf = Ri. Since Rout is 8.25 ohms and Iout = 0 to 250mA: V4 = 0 to -2.06V

3. Assume no offset is needed (Offset jumper in DIS position), so the offset adjustment stage is a unity gain inverting stage which implies V2 = 0 to 2.06V. 4. Since V2 = 0 to 2.06V and V1 = 0 to 10V (after the valve position request has been inverted), V2 = 0.206*V1. This implies that: RB/(RA1 + RA2 + RB) = 0.206

Let RA1 = 1K potentiometer, RA2 = 7.5K, and RB = 2K. By adjusting the 1K potentiometer, the ratio of resistors ranges between 0.190 and 0.267, which includes the desired 0.625 ratio. Calibration To calibrate a QCA card, adjust the range and offset potentiometers on the front card edge while the output voltage or current is monitored. Since channel output drives cannot be disconnected on power-up and potentiometer settings may be unknown initially, it is suggested that outputs be disconnected from the actuators initially. Instead, a resistor (approximately equal to coil load resistance) of sufficient power rating may be connected to the output at the halfshell on power-up, and the potentiometers may be adjusted to safe operating values. Note Group 2 boards which have true current outputs, should have a load on the output when powered up. If no load is present and V4 (see Figure 3-119) has a slight voltage present due to the input voltage or the offset voltage, the output will saturate because the channel is trying to drive a preset current into an infinite load. The following calibration steps apply to unipolar voltage input to unipolar voltage or current output QCA boards. Steps are included to add in a small offset which keeps the output coil drive from crossing over the 0V or 0A boundary and switching polarities, if this is a necessary constraint. 1. Disable the offset jumper (see Figure 3-122).

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3-16. QCA

2. Send the full scale actuator position request, and adjust the range potentiometer on the front card edge for the channel being calibrated until Vout (Group 1) or Iout (Group 2) equals the desired full scale output for the channel. 3. Send the bottom of scale actuator position request and check if Vout (Group 1) or Iout (Group 2) is at the desired bottom of scale. If the output is satisfactory, then calibration is done. 4. If offset is needed, enable the offset jumper and adjust the offset potentiometer until Vout (Group 1) or Iout (Group 2) is acceptable and return to Step 2.

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M0-0053

R43

M0-0053 R54 R60

R50 R57

3-248

Westinghouse Proprietary Class 2C TP2

GND

TP1

GND

RANGE1

TP5

VBOOST1

TP6

RANGE2

TP3

TP8 JS1 JS2

VCOIL 1B

VCOIL 2B

DIS

EN INVERT2 INVERT1

JS3 JS4

TP10

GND

POWER(+) +VS

+15V

TP9

GND

-VS

-15V POWER(-)

RV4

RV3

RV2

RV1

R162 R159 R163 R160

DIS

EN

TP13 RG1

CHAN1

GND

CHAN2

OFFSET2 OFFSET1

-Vs

+Vs

OS1TP12

TP11

RG2

JS9 JS10

OS2

LE2

LE1

LEDS

VBOOST2

TP4

TP7

JS5 JS8

3-16. QCA


R47

R39 R44

Figure 3-122. QCA Card Outline and User Controls

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3-16. QCA

LED Indicators +VS: lit when +21V on-board supply is alive -VS: lit when -21V on-board supply is alive Plug-in Resistors Table 3-80. QCA Plug-in Scaling Resistor Reference Designators

Channel Range Adjust Resistors Offset Adjust Resistors *Gain Adjust Resistors (Rf-B) #1

RA2: R54 RB: R60

RC2: R160 RD: R163

DriveA - R44 DriveB - R47

#2

RA2: R50 RB: R57

RC2: R159 RD: R162

DriveA - R43 DriveB - R39

* Group 1 Only

Potentiometers Range Adjustment Potentiometer RA1: used to adjust the signal range of a channel during calibration. Channel 1 - Reference Designator RV4; Label RG1 Channel 2 - Reference Designator RV2; Label RG2 Offset Adjustment Potentiometer RC1: used to adjust the signal offset of a channel during calibration. Channel 1 - Reference Designator RV3; Label OS1 Channel 2 - Reference Designator RV1; Label OS2 Test Jacks CHANx - test jack providing Vcoil Drive A output voltage of channel x to be monitored during calibration. (x = 1,2) Reference Designators: TP13 (channel 1), TP11 (channel 2) GND - test jack providing signal ground. Reference Designator: TP12

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3-16. QCA

Jumpers POWER(+): Always set jumpers to +15V position. DEFAULT Group 1 and 2: +15V position POWER(-): Always set jumpers to -15V position. DEFAULT Group 1 and 2: -15V position OFFSET: If jumper set to EN (enable), offset is added to the channel’s actuator position request. When set to DIS (disable), no offset is added. DEFAULT Group 1 and 2: DIS position INVERT: If jumper is set to EN, the channel actuator position request is inverted in the input stage. DEFAULT Group 1 and 2: EN position

Table 3-81. Reference Designators for QCA Jumpers - Groups 1 and 2

Channel

Offset

Invert

*Power(+)

*Power(-)

#1

JS10

JS2

#2

JS9

JS1

JS3 JS4

JS5 JS8

* Note: Power (+) and (-) jumpers are not channel specific

Test Points Test points appear at the output of those stages denoted by V2, V4, and Coil Drives in Figure 3-116. These test points plus the ground test points with their reference designators are listed in Table 3-82 for each channel. Table 3-82. QCA Test Point Reference Designators

Channel

Range Adjust Stage Output

Offset Adjust Stage Output

Gain Adjust Stage Output

Ground

#1

TP5

TP6

DriveA: TP13 *DriveB: TP8

TP1, TP2, TP9, TP10, TP12

#2

TP3

TP4

DriveA: TP11 *DriveB: TP7

* Group 1 Only

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3-16. QCA

3-16.7. Installation Data Sheets 1 of 3

QCA Card TERMINAL BLOCK

19B 19A 17B 17A 15B 15A 13B 13A 11B 11A 9B 9A 7B 7A 5B 5A 3B 3A 1B 1A

Vcoil 2B

Vcoil 2A Vin 2

Vcoil 1B Vcoil 1A

Vin 1

18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

+ + + + + -

Channel 2 Redundant Voltage Output Coil Drive Channel 2 Primary Voltage Output Coil Drive Channel 2 Voltage Input Channel 1 Redundant Voltage Output Coil Drive Channel 1 Primary Voltage Output Coil Drive

+

Channel 1 Voltage Input

EDGE-CONNECTOR

Figure 3-123. QCA Wiring Diagram (Group 1) (Using AMP-18 conductor 18 AWG wiring) (3A99512)

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3-16. QCA


QCA Card TERMINAL BLOCK

Vcoil 2A Vin 2

Vcoil 1A

Vin 1

19B 19A 17B 17A 15B 15A 13B 13A 11B 11A 9B 9A 7B 7A 5B 5A 3B 3A 1B 1A

18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

+ + -

+ -

Channel 2 True Current Coil Drive Channel 2 Voltage Input

Channel 1 True Current Coil Drive

+

Channel 1 Voltage Input

EDGE-CONNECTOR

Figure 3-124. QCA Wiring Diagram (Group 2) (Using AMP-18 conductor 18 AWG wiring) (3A99512)

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3-16. QCA


CARD 1A

A

A

1B

1

1

3A

2

2

3B

3

3

5A

4

4

5B

5

5

Vin1 Ground

7A

6

6

Ground

7B

7

7

Coil drive 1A

9A

8

8

Coil drive 1B

9B

9

9

Ground

11A

10

10

Ground

11B

11

11

Vin2

13A

12

12

Coil drive 2A

13B

13

13

Ground

15A

14

14

Ground

15B

15

15

Coil drive 2B

17A

16

16

17B

17

17

19A

18

18

19B

PE

PE

EDGE-CONNECTOR

Notes 1. The A and B cabinets MUST be bolted together to use the QCA in CE Mark Certified Systems. 2. As shown, the shields and grounds must be connected together and to earth ground at the B cabinet.

Figure 3-125. QCA CE MARK Wiring Diagram

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3-17. QCI

3-17. QCI Contact Input (Style 7379A06G02)

3-17.1. Description Group 02 is applicable for use in the CE MARK Certified System The QCI provides 16 digital contact inputs and a +48 V contact-wetting supply voltage (see Figure 3-126). This contact-wetting voltage provides supply isolation and reduced current power consumption due to the current limiting capability of the supply. The QCI digitally filters the contact-input signals and provides the option of inverting the polarity of any data bit.

Figure 3-126. QCI Block Diagram

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3-17. QCI

3-17.2. Features The QCI card is available in two groups and provides the following features:

• • • • • •

Dual on-card contact-wetting power supply for low power consumption Separate status-indicating LEDs for each input Compatible with any DIOB controller IEEE surge-withstand protection Optical isolation for each input Optional digital switch selectable polarity of each bit

The Group 2 QCI provides 16 digitally-filtered contact inputs sharing a common return line with the ability to invert data-bit polarity (G01 does not have this option and is no longer manufactured).

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3-17. QCI

3-17.3. Specifications A functional block diagram of the QCI is shown in Figure 3-127.

GND POWER SUPPLY

POINT 15

POWER

SELECT HI-LO

16

8

DATA

ISOLATION

BUS DRIVERS

OPTICAL 2:1 MULTIPLEXER

•• •• •• •• •• •• •• (16) •• •• •

+10 +48

DIGITAL FILTERING

RET POINT 0

SIGNAL CONDITIONING

PWR ON LED

DIOB

+12

ENABLE RET

1 LOCAL OSCILLATOR

LED

CARD EDGE INDICATORS

16

UIOB GROUND

ADDRESS

ADDRESS COMPARATOR

DATA-DIR

JUMPER ADDRESS SELECTION

Figure 3-127. QCI Card Block Diagram

Input Requirements Digital Filter Delay:2.6 msec to 6.0 msec Input Signal Rejection Input signal duration <2.6 msec is always rejected. Input signal duration >6.0 msec is always passed.

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3-17. QCI

Note The elapsed time between the contact’s opening and its subsequent closure must be >15 msec. Contact leakage resistance:50 KΩ minimum. Table 3-83. QCI Contact Wetting Voltage Parameter

Minimum

Nominal

Maximum

Open Circuit Voltage

42V

48V

56V

Closed Contact Current

6mA

14mA

22mA

Input Capabilities The signal lines at the DIOB interface are specified by the DIOB specifications description. Power Supply Primary: +13 V +0.1 Vdc Backup: +12.6 V + 0.2 Vdc Current: 500 mA (maximum) supplied by DIOB Power Consumption: 6.3 W (maximum) Electrical Environment IEEE Surge withstand capability Common Mode Voltage: 500 Vdc or peak ac (line frequency)

Card Addressing and Data Output The QCI card address is established by eight jumpers on the front card-edge connector as shown in Figure 3-128. The insertion of a jumper encodes a “1” on the address line.

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3-17. QCI

DIOB CARD ADDRESS = 00100011 = 2316

BLANK:

A7 = 0

BLANK:

A6 = 0

JUMPER:

A5 = 1

BLANK:

A4 = 0

BLANK:

A3 = 0

BLANK:

A2 = 0

JUMPER:

A1 = 1

JUMPER:

A0 = 1

CARD-EDGE CONNECTOR (FRONT VIEW)

Figure 3-128. QCI Card Address Jumper Assembly

The binary data that is sent to the system controller over the DIOB are the 16 data bits from the 16 contact inputs divided into two eight-bit bytes. Connections and Field Cabling Refer to Figure 3-129 for details regarding the following discussion. Up to 1.2 mA may flow through any contact shunt resistance from the +48V supply (with open contacts, no current can flow from the +10V supply due to reverse-biased diodes). A resistance of 50 KΩ (minimum) is required to maintain the high-level contact-wetting voltage. However, the contacts are recognized as open with a shunt resistance of 10 KΩ (minimum). To ensure that closed contacts are always recognized as closed, the following equation must be applied: RC + RLINE + 16RR ≤ 60 Ω

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3-17. QCI

ONE OF 16 INPUTS

RC + RLINE + 16RR < 60 Ω

RC

RS RLINE

RR

COMMON RETURN PIN

FROM OTHER CONTACTS

RS = CONTACT SHUNT RESISTANCE RC = RESISTANCE ASSOCIATED WITH A CLOSED CONTACT RR = RESISTANCE OF A COMMON RETURN LINE (IF ANY) RLINE = RESISTANCE OF NON-COMMON CABLE LENGTH TO AND FROM CONTACTS

Figure 3-129. Cable Length Limitations for QCI Card

Contact Cycle Time If the maximum QCI on card generated voltage is to be applied to plant contacts that interface to the QCI card, the elapsed time between a contact opening and its subsequent closure must be greater than 15 msec.

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3-17. QCI

Table 3-84 gives the cable length limits for various gauges of wire. Table 3-84. Cable Length Limits for QCI Card

Gauge

Ohms/ thousand ft

16 Commons/Card (thousand ft) (maximum)1

1 Common/ Card (ft) (maximum)2

8

0.654

92

5,400

10

1.04

58

3,400

12

1.66

36

2,140

14

2.27

26

1,560

16

4.18

14

845

18

6.64

9.0

530

20

10.2

5.9

345

22

16.2

3.7

215

1The

maximum cable length for a 16-common/card assumes that RR = 0 and RC = 0. The length given is the sum of the lengths to and from the contacts. 2The

maximum cable length for a 1-common/card assumes that RC = 0. The length of the return is equal to the length of the cable to the contact. The length given is the length to the contact only.

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3-17. QCI

The QCI pin assignments are given in Table 3-85. These pins are located on the front-edge connector. Table 3-85. QCI Pin Assignments Connection Pins

B Side (Component Side)

A Side (Solder Side)

28

A7

GND

27

A6

GND

26

A5

GND

25

A4

GND

24

A3

GND

23

A2

GND

22

A1

GND

21

A0

GND

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

RET

RET

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

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3-17. QCI

Controls and Indicators QCI Group 2 (G02) provides the ability to reverse the polarity of the data bits depending on switch setting. Table 3-86 gives the data bit values for switch positions.

OSC PWR 15 14 13 12 10 11 9 8

LEDs

7 6 5 4 3 2 9 0

DIP Switches (Only on G02)

Figure 3-130. QCI Card Components

Separate status-indicating LEDs for each contact input are located at the front of the card (see Figure 3-130). Table 3-86. QCI G02 DIP Switch Positions

M0-0053

Switch Position

Contact State

Digital Value

OPEN

Open Closed

0 1

CLOSED

Open Closed

1 0


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3-17. QCI


+48VDC

CARD


20B


20A OPTO ISO

+10VDC

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 +V OPTO ISO

BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

19B

A

19A

18

17B

17

17A

16

15B

15

15A

14

13B

13

13A

12

11B

11

11A

10

9B

09

9A

08

7B

07

7A

06

5B

05

5A

04

3B

03

3A

02

1B

01

B 18 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

1A CUSTOMER CONNECTIONS EDGE-CONNECTOR

INTERNAL BUS STRIP

Figure 3-131. QCI Wiring Diagram

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3-17. QCI


CUSTOMER CONNECTIONS CARD 1A

A

A

B

1B

1

01

01

1

BIT 0

3A

2

02

02

2

BIT 1

3B

3

03

03

3

BIT 2

5A

4

04

04

4

BIT 3

5B

5

05

05

5

BIT 4

7A

6

06

06

6

BIT 5

7B

7

07

07

7

BIT 6

9A

8

08

08

8

BIT 7

9B

9

09

09

9

BIT 8

11A

10

10

10

10

BIT 9

11B

11

11

11

11

BIT 10

13A

12

12

12

12

BIT 11

13B

13

13

13

13

BIT 12

15A

14

14

14

14

BIT 13

15B

15

15

15

15

BIT 14

17A

16

16

16

16

BIT 15

17B

17

17

17

17

19A

18

18

18

18

PE

PE

19B

COMPRESSION-STYLE TERMINAL BLOCK EDGE-CONNECTOR

Figure 3-132. QCI CE MARK Wiring Diagram

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3-18. QDC

3-18. QDC Q-Line Digital Controller (Style 4256A15G01 through G11)

3-18.1. Description G01 and G02 are applicable for use in the CE MARK Certified System The Q-Line Digital Controller (QDC) printed circuit board provides an additional level of control capability, supplementing DPUs. The QDC has an on-board processor which controls outputs based on user-defined algorithms. Full details on the configuration and use of the QDC are contained in the “QDC User’s Guide” (U0-1105).

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3-19. QDI

3-19. QDI Digital Input (Style 2840A13G01 through G11)

3-19.1. Description The QDI card had been superseded by the QID card. For new applications, refer to the following table to determine the equivalence between QID and QDI cards: Table 3-87. QDI-QID Card Equivalents

QDI Group

Equivalent QID Group

Input Level

Inputs*

G02

G02

24 VAC/DC

8

G04

G04

48 VAC/DC

8

G06

G06

120 VAC/DC

8

G10

G10

48 VDC

16

G11

G11

120 VAC

8

* 16 means single-ended inputs, 8 means differential inputs. The QDI card provides signal conditioning for 16 digital voltage process inputs, and it interfaces these signals to the DIOB (see Figure 3-133). The QDI has two different kinds of voltage-sensing input circuits available. Cards can have eight two-wire (differential) inputs without electrical connections to other points, or sixteen single-ended inputs which share a common return line.

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3-19. QDI

Block Diagram

Figure 3-133. QDI Block Diagram

3-19.2. Features The QDI card is available in 11 groups and provides the following features:

• • • • • • • 5/99

G01 provides 16 single-ended 5 VDC inputs G02 provides eight 24 VAC/VDC differential inputs G03 provides 16 single-ended 24 VAC/VDC inputs G04 provides eight 48 VAC/VDC differential inputs G05 provides 16 single-ended 48 VAC/VDC inputs G06 provides eight 120 VAC/VDC differential inputs G07 provides 16 single-ended 120 VAC/VDC inputs


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3-19. QDI

• • •

G08 provides 16 single-ended logic-oriented, +12 VDC inputs

•

G11 provides eight 120 VAC/VDC differential inputs (high threshold)

G09 provides 16 single-ended non-logic (filtered), 12 VDC inputs G10 provides 16 single-ended 48 VDC inputs with filter circuitry for pulse input applications

3-19.3. Specifications Input Requirements Table 3-88. QDI Input Requirements

Group

ON Input Voltage (VDC or VAC rms) Min/Max

OFF Input Voltage ON (VDC or Input Current VAC rms) (mA) (max) Min/Max

Propagation Time (msec) Min/Max

Power In Front End with All Units On, (Nominal Voltage) (Watts)

G01

4

6

0.9

10

15

–

0.2

1.0

G02

20

30

3

10

15

5

21

2.3

G03

20

30

3

10

15

5

21

4.6

G04

40

60

4

10

15

5

21

4.6

G05

40

60

4

10

15

5

21

9.2

G06

100

150

6

10

15

5

21

11.5

G07

100

150

6

10

15

5

21

23.0

G08

10

15

2

10

15

–

0.2

2.3

G09

10

15

2

10

15

5

21

2.3

G10

40

60

4

10

15

5

2.1

9.2

G11

100

150 VDC 145 VAC (rms)

31 VDC 25 VAC (rms)

10

15

5

43

10.1

Power Supply Primary: +13.0 V +0.1 VDC/− 0.6 VDC Backup: +13.0 V + 0.1 VDC/− 0.6 VDC Current:

M0-0053

200 mA (maximum for single-ended cards) 100 mA (maximum for differential cards)


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3-19. QDI

Electrical Environment IEEE Surge withstand capability Common Mode Voltage: 500 VDC or peak AC (line frequency)

3-19.4. Card Addressing and Data Output The QDI card address is established by eight jumpers on the front card-edge connector as shown in Figure 3-134 and Figure 3-135. The insertion of a jumper encodes a “1” on the address line. The binary data that is sent to the system controller over the DIOB are the 8 or 16 data bits from the field inputs. For differential inputs, one byte of data is sent over the DIOB (Figure 3-134). For single-ended inputs, two bytes of data are sent over the DIOB (Figure 3-135). This parameter defines the color for the value when the point is in alarm.

JUMPER:

A7 = 1

JUMPER:

A6 = 1

BLANK:

A5 = 0

BLANK:

A4 = 0

JUMPER:

A3 = 1

BLANK:

A2 = 0

BLANK:

A1 = 0

BLANK:

A0 = 0

JUMPER:

HI-LO = 1 (i.e. HIGH BYTE


~

~

CARD ADDRESS = 1100 1000, (X ‘C8’ HIGH BYTE)

Figure 3-134. QDI Card Address Jumper Assembly (Differential Input)

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3-19. QDI

CARD ADDRESS = 00100011 (X ‘23’)

BLANK:

A7 = 0

BLANK:

A6 = 0

JUMPER:

A5 = 1

BLANK:

A4 = 0

BLANK:

A3 = 0

BLANK:

A2 = 0

JUMPER:

A1 = 1

JUMPER:

A0 = 1


Figure 3-135. QDI Card Address Jumper Assembly, Single Ended Input

Connections and Field Cabling The digital inputs enter to the QDI Card on the front-edge connector. The pin assignments for this connector are listed in Table 3-89. Figure 3-136 shows the wiring for point inputs to a G01. Figure 3-137 shows the typical wiring for the single-ended input groups.

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3-19. QDI

The cable length to field contacts is limited by cable capacitance when AC is used to wet contacts. See Table 3-90.

QDI G01

POINT 15

Up to 16 points

POINT 0 RETURN −

+

5 VOLTS

Figure 3-136. QDI G01 Point Wiring

QDI Single-Ended

Length Point 15

Field Contact

16 points Point 0

Field Contact

Return

Contact wetting voltage supply

Figure 3-137. QDI Typical Contact Input Point Wiring (G03, 05, 07, 08, 09, 10)

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3-19. QDI

Table 3-89. QDI Pin Allocations

(G01, G03, G05, G07, G08, G09, G10) Input Digital Bit

PC Card Edge Pin


Return

1A and 1B

1

M0-0053

Bit 15

17B

17

14

15A

14

13

13B

13

12

11A

10

11

9B

9

10

7A

6

9

5B

5

8

3A

2

7

17A

16

6

15B

15

5

13A

12

4

11B

11

3

9A

8

2

7B

7

1

5A

4

0

3B

3


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3-19. QDI

Table 3-89. QDI Pin Allocations (Cont’d)

(G02, G04, G06, G11) Input Digital Bit

PC Card Edge Pin


Return

1A and 1B

1

Bit 0

3A

2

3B

3

5A

4

5B

5

7A

6

7B

7

9A

8

9B

9

11A

10

11B

11

13A

12

13B

13

15A

14

15B

15

17A

16

17B

17

1 2 3 4 5 6 7

Table 3-90. Cable Length for QDI

Maximum Capacitance

At 50 pF/Ft typical capacitance Maximum Cable Length

G02 (24 VAC)

60,000 pF

1000 ft.

G04 (48 VAC)

30,000 pF

500 ft.

G06 (120 VAC)

15,000 pF

250 ft.

G11 (120 VAC)

15,000 pF

250 ft.

Group

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M0-0053

3-19. QDI

3-19.5. Controls and Indicators Separate status-indicating LED’s for each input are located at the front of the card (see Figure 3-138).

LEDs

LED Detail

PWR 15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

Figure 3-138. QDI Card Components

M0-0053


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3-19. QDI


Terminal block #8-32 Screw Card

19B

A

19A

18

17B

17

17A

16

15B

15

15A

14

13B

13

13A

12

11B

11

11A

10

9B

09

9A

08

7B

07

7A

06

5B

05

5A

04

3B

03

3A

02

1B

01

Bit 7

Bit 7

Bit 6

Bit 6

Bit 5

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1A

Edge-connector

Customer Connections

Figure 3-139. Wiring Diagram: QDI Groups 2, 4, 6, and 11

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M0-0053

3-20. QDT

3-20. QDT Diagnostic Test (Style 7379A29G01)

3-20.1. Description Applicable for use in the CE MARK Certified System The Q-line Diagnostic Test (QDT) card is a DIOB testing device which verifies that a system’s DIOB functions properly (see Figure 3-140). To do this, this card verifies the integrity of the DIOB data, address and control lines. Additionally, this card verifies that the DIOB controller can drive the DIOB and related point cards mounted on it. In a process control system, the Q-line point cards are used for signal conditioning. These point cards convert analog or digital field signals from a process into equivalent digital signals that are compatible with the supervising controller. Q-line point cards interface to a controller via the DIOB, which provides a byte oriented digital exchange of process information. The QDT card provides for diagnostic testing of this interface.

Data

DIOB

Address

Address Decoder & Select

Simulation Circuit

Display Control Circuit

Card-edge Displays

Figure 3-140. QDT Block Diagram

M0-0053


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3-20. QDT

3-20.2. Features The QDT card is available in one group and provides the following features:

• • •

Card-edge switches for mode selection and diagnostic testing.

• •

Card-edge LED’s for data display.

Simulates DC loading for 48 point cards. On-card 512 byte RAM to test the DIOB controller’s addressing and bus driving ability.

Automatic Display mode selection on power-up to protect an active DIOB from overloading.

Electrical connection to the QDT card is made through a 34-pin DIOB backpanel connector. The QDT card may be housed as follows:

• •

In the standard Q-line card crate Mounted to crate with a M4X6MM screw (not provided with QDT card)

Operation The QDT card provides two modes of operation:

•

Simulator Mode – used to test DIOB and controller Note All point cards must be removed from the DIOB prior to Simulator mode operation.

•

Display Mode – used to monitor a user selected DIOB address, displaying any data written to or read from the selected address. Note In the display mode, the user selects whether output or input data is to be displayed, via the card edge Data Direction switch.

3-20.3. Specifications Power Requirements

• 5/99

Voltage from DIOB: 3-277 Westinghouse Proprietary Class 2C

M0-0053

3-20. QDT

Primary: +12.4 VDC to +13.1 VDC Secondary: +12.4 VDC to +13.1 VDC

•

Current from DIOB: 750 mA maximum

•

5 VDC Power Supply: Derived internally on QDT card from 12 VDC supplied from DIOB Voltage: 4.8 VDC to 5.2 VDC Current: 400 mA maximum

Simulator Mode In the Simulator mode, the QDT card tests that the DIOB controller is able to drive a DIOB of maximum length and with the maximum number of point cards plugged in. Additionally, the QDT card checks that the controller is able to address all possible DIOB locations and can generate the basic DIOB control signals. The loading circuits, at the QDT card’s DIOB signal inputs, simulate the DC loading of the point cards and the capacitance of the longest permissible DIOB (50 feet). DIOB signals must drop below 3 VDC to be recognized as a logic 0 or rise above 9 VDC to be recognized as a logic 1. These QDT input circuits contain voltage comparators with hysteresis to reject input DIOB signals with voltage levels between 3 and a 9 VDC. In this mode, the QDT card (via the 512-bytes of RAM) tests the DIOB controller’s DIOB addressing capability and the controller’s ability to drive the DIOB. The QDT card’s 512-byte RAM simulates the entire DIOB address space. Due to the fact that the QDT card simulates every DIOB point card address and the loading of a DIOB full of point cards, no other point card should be present on the DIOB/ controller combination being tested. Therefore, to prevent any mishaps, when a QDT card is powered up or inserted into an active DIOB, it automatically powers up in the Display mode. The user then removes all other point cards from the DIOB before switching the QDT card into its Simulator mode. Two edge mounted LED’s are provided to inform the user as to which mode the QDT card is in.

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3-20. QDT

Caution Failure to remove all point cards from the DIOB, prior to switching to the Simulator mode, can cause DIOB loading, generating a failed condition. Also, in this mode, the QDT card generates a DEVICE BUSY pulse during every DIOB cycle. This DEVICE BUSY pulses generation may be disabled by the user via the card edge Device Busy enable switch. The DEVICE BUSY pulse is automatically disabled and not generated in the Display mode. Display Mode In the Display mode, the QDT card simply monitors the DIOB lines and displays data on sixteen card edge LED’s. In this mode, the QDT logic does not interact with the DIOB address, data or control signal transfers. Note The QDT card displays DIOB data, while in the Simulator mode. However, no other point cards are permitted on the DIOB. When the QDT card operates in the Display mode, it does not occupy any DIOB addresses and it appears to be transparent to the DIOB controller. All of the QDT logic, utilized for the Simulator mode, is isolated from the DIOB in the Display mode. Sixteen of the QDT card’s LED’s are used to display the contents of a 16-bit DIOB data latch on the QDT card. This latch’s contents are updated every time the selected DIOB address and direction of data (input or output) matches actual DIOB address and data direction. When this occurs, the appropriate LED’s flash for approximately 0.1 seconds. In this way, the exchange of digital data between the Q-line point cards and the DIOB is monitored.

3-20.4. Controls and Indicators The QDT card’s controls and indicators are shown in Figure 3-141. Table 3-91 gives a description of these controls and indicators.

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M0-0053

3-20. QDT

Power-On LED 15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

SIML

Data Display LEDs

Lamp Test Switch Simulator LED Mode Select Switch

DISP

Address Select Switch

High Byte ADR

Address LED Address Select Switch

Low Byte Dev. Busy Data Dir.

Display LED

DIS EN OUT IN

Device Busy Enable Switch Data Direction Switch

Figure 3-141. QDT Card Controls and Indicators Table 3-91. QDT Card Controls and Indicators

Control/Indicator Power-on LED Data Display LED’s

Simulator LED Display LED

M0-0053

Description Lights when QDT card is receiving power from DIOB. These sixteen LED’s are arranged in two rows of eight each. The row closest to the card edge displays the lower byte of DIOB data and the other row displays the higher byte of DIOB data. Lights when QDT card is operating in the Simulator mode. Lights when QDT card is operating in the Display mode.


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3-20. QDT

Table 3-91. QDT Card Controls and Indicators (Cont’d)

Control/Indicator Address LED

Description Lights for approximately 0.1 seconds each time the DIOB address and data direction matches the address and data direction selected on the QDT card. Note

When the addresses and data directions of the DIOB and QDT card repeatedly match, this LED appears to constantly light. Lamp Test Pushbutton Simultaneously tests all twenty QDT card LED’s. When pressed, all LED’s should light. Mode Select Toggle Selects the QDT card’s operating mode. Pressing this switch Switch (momentary toward DISP displaces the QDT card into the Display mode contact) and lights the Display LED. Pressing this switch toward SIML places the QDT card into the Simulator mode and lights the Simulator LED. Caution The Simulator mode should not be selected unless all point cards are removed from the DIOB and the appropriate DIOB controller diagnostic programming exits. Failure to remove all point cards, prior to switching to the Simulator mode, can cause DIOB loading, generating a failed condition. Additionally, the QDT card’s Simulator mode is of no use unless the necessary controller diagnostic programs are present. Address Select Rotary Selects the upper and lower bytes of the DIOB address that is to be Switches (hex) monitored by the QDT card’s display logic. Device Busy Toggle Enables or disables the generation of the DEVICE BUSY signal while Switch the QDT card is operating in the Simulator mode. Data Direction Toggle Selects the direction of DIOB data (input or output) that is to be Switch displayed by the QDT card’s Display LED’s. Pressing this switch to IN, displays data that is input to the DIOB controller. Pressing this switch to OUT, displays data that is written to a point card.

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M0-0053

3-21. QFR

3-21. QFR Remote I/O Fiber-Optic Interface (Style 4256A51G01)

3-21.1. Description Applicable for use in the CE MARK Certified System The QFR printed circuit board links master to remote nodes for long range communication (up to 5,280 feet or 1,609 meters). The card provides signal conversion from electrical to optical and optical to electrical (one unit sends and receives). Full details on the configuration and use of the QFR are contained in the “Remote Q-Line Installation Manual” (M0-0054).

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3-22. QIC

3-22. QIC Q-Line DIOB Monitor (Style 4256A83G01)

3-22.1. Description The Q-Line DIOB Monitor (QIC) card adds the capability to monitor DIOB operations. This function is often used in WDPF systems where DIOB operations driven by one DIOB controller must be monitored by a second computer, in addition to the normal DIOB controller. The second computer may be a WDPF DPU or a W2500 I/O subsystem. Monitoring is typically a requirement when upgrading from a W2500 system to a WDPF system. The card stores data transferred during read or write operations on the control DIOB and allows this data to be read by the second, monitor, DIOB. The data transferred over the bus is stored in shared memory on the card. Logic on the QIC card prevents memory contention from occurring. The QIC card contains a second (monitor) DIOB port which allows read-only operations of the shared memory. The monitor DIOB may originate from one of three connectors on the QIC. There are two types of connectors:

• •

One WDPF DPU connector. Two connectors for a W2500 I/O subsystem.

Control DIOB Connector

Monitor DIOB Connector1

Interface

Interface

Monitor DIOB Connector 2

Dual Port RAM

State Machine

State Machine

Figure 3-142. QIC Block Diagram

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M0-0053

3-22. QIC

3-22.2. Features DIOB 1 Operating Characteristics

•

A DIOB 1 Read or Write operation to any location in the 512-byte DIOB address space causes the data present on the DIOB 1 data lines to be written into the Dual Port RAM at the address specified by the DIOB 1 address lines.

•

The QIC will not drive the DIOB 1 data lines, regardless of whether a Read or Write operation is occurring.

•

Device-Busy is checked on DIOB Read operation. If Device-Busy is not present at the proper time, no Data will be written into the shared RAM. On DIOB Write operation, Device-Busy is ignored. On Q-Line I/O cards which do not support Device-Busy, there is a jumper which to allow the Data be written to shared Ram on DIOB Read operation without valid Device-Busy. The jumper is shown in Figure 3-142.

•

For double-byte (word) operations, the second (High) byte of data will be written to the RAM before the other (Read-only) port of the RAM may be accessed. This prevents data-tearing.

•

DIOB specification, double-byte (word) operations must be accessed Low byte, then High byte, in order to prevent data-tearing.

DIOB 2 Operating Characteristics

M0-0053

•

DIOB 2 Reads of any location in the 512-byte DIOB address space causes the data in the Dual Port RAM addressed by the DIOB 2 address lines to be driven onto the DIOB 2 data lines.

• • •

DIOB 2 Writes are ignored. Device-Busy is supported by the QIC. DIOB 2 cycles are NOT extended. In compliance with the DIOB specification, double-byte (word) operations must be accessed Low byte, then High byte, in order to prevent the possibility of datatearing.


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3-22. QIC

DIOB 2 Cable Restrictions Connector P2: WDPF-style Compatible with MBU, MSQ, MSX Maximum Length: 50 ft Connectors P3 or P4: W2500 -style Compatible with WIO Maximum Length: no longer than the present WIO-QPD or WIO-QPP cables System Grounding Restriction The 2 DIOB ports on the QIC are not isolated from each other. The DPU or W2500 computer power grounds (PG) of the cabinets that are connected to the QIC card must be connected together by a minimum 4 AWG wire. It is recommended that the cabinet containing the monitor DIOB controller be adjacent to the cabinet containing the QIC card. Note This current does not include the current drawn by an MBU, MSQ, or MSX card if it is connected to DIOB 2. There is no current drawn by the WIO, if one is connected to DIOB 2.

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M0-0053

3-22. QIC

Operating Restrictions The following restrictions apply when using the QIC card:

•

The power grounds (PG) of the cabinets containing the control and monitor DIOB controllers must be connected together by a minimum 4 AWG wire.

•

It is recommended that the cabinet containing the monitor DIOB controller be adjacent to the cabinet containing the QIC card.

•

The monitor DIOB cannot contain any other I/O cards that need to be read, because the QIC responds to Read operations of all DIOB addresses.

•

Double-byte (word) Read and Write operations of both the monitor and control DIOBs must be in Low byte, then High byte order to prevent data tearing. Note, the DPU DIOB controllers and the WIO both meet this requirement.

•

Although three connectors exist (one for a DPU, two for a W2500) for the monitor DIOB, only one connector may be connected to a DIOB controller at any one time.

Card Usage The QIC card contains four DIOB connectors P1, P2, P3, and P4 (see Figure 3-144). However, the signals coming from connectors P2, P3, P4 of DIOB 2 are tied together so that, essentially, there are two DIOB ports on the card. The signals from these ports are buffered and level-shifted to +5V levels. The two state machines (Figure 3-142) resolve any Shared RAM access contentions when two DIOB ports attempt to access the Shared Ram at the same time.

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3-22. QIC

The following occurs when a Read or Write operation occurs on DIOB 1: 1. The rising edge of DATA-GATE signals the Write State Machine that a DIOB operation is occurring. 2. The Write State Machine examines the output of the address comparator. If the address is the same as the previous (latched) address, HI,LO/ is high, and there is data in the low byte latch that still must be written to RAM, a word operation is occurring. Otherwise, a byte operation is occurring. 3. For a byte operation, the following occurs, depending on the state of HI,LO/, and whether there is data in the low byte latch that still must be written. If HI,LO/ is High, the Write State Machine immediately writes the data into the High Byte Dual Port RAM. If there is data in the low byte latch that still must be transferred to RAM, it will also be written at this time. If HI,LO/ is low and there is data in the low byte latch, the data in the low byte latch is transferred to RAM. Immediately afterward, the incoming data and address are latched. The data is not written to RAM in case this new low byte is part of a word operation. If there is no data in the latch to be written, the incoming data and address are latched immediately. For a word operation, the Write State Machine immediately writes both the low and high bytes to their respective Dual Port RAMs If there is data in the low byte latch that must be transferred to RAM and the 10 µs timer has expired, the data is written to the RAM. The 10 µs timer is used to determine whether a low byte operation is part of a word operation. The timer is turned on at the falling (inactive) edge of DATA-GATE. For a word operation, the maximum time between pulses is 10 µs. If the timer expires without another occurrence of DATA-GATE, the low byte operation must have been a byte operation. This ensures that a single low byte operation will be transferred to RAM as soon as possible, in case another DIOB operation does not occur. Note If more than 10 µs occurs between DATA-GATE pulses, the Write State Machine will write the low byte of data to the Dual Port RAM. Data tearing can occur for an assumed word operation if the DATA-GATE pulse of the high byte write follows the DATA-GATE pulse of the low byte write by more than 10 µs.

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M0-0053

3-22. QIC

The following occurs when a Read operation occurs on DIOB 2: 1.

The rising edge of DATA-GATE signals the Read State Machine that a DIOB operation is occurring.

2. If the operation is a write, no action takes place. Otherwise, the following action occurs. 3. If HI,LO/ is low, the Read State Machine latches the address. It then reads BOTH Dual port RAMs and latches the high byte of data. The low byte of data is transferred immediately to the DIOB drivers. 4. If HI,LO/ is high, the Read State Machine examines the output of the address comparator. If the address is the same as the previous (latched) address and the 10 µs timer has not expired, the high byte read is part of a word operation. Otherwise, the high byte read is a byte operation. 5. For a byte operation, the Read State Machine reads the High Byte Dual port RAM and transfers the data to the DIOB drivers. For a word operation, the Read State Machine reads the High Byte Latch and transfers the data to the DIOB drivers. Note, the latch is read in this case because it contains the data that was read at the same time as the low byte of the word was read. This prevents data tearing. 6. Similar to the 10 µs timer used with the Write State Machine, the 10 µs timer in the Read State Machine determines whether a High Byte Read may be part of a word operation or not. Note For a high byte read operation, if the DATA-GATE pulse occurs more than 10 µs after the previous DATA-GATE pulse, a single high byte Read operation is assumed and the data will be transferred from the RAM, regardless of whether the address matched the previous address. Therefore, to prevent data tearing from an assumed word Read operation, the DATA-GATE pulse of the high byte write should follow the DATA-GATE pulse of the low byte write by less than 10 µs.

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5/99 DIOB1 (Control) Port

3-289

Westinghouse Proprietary Class 2C DIOB Controls

Add. Match

Add. Comp.

Add. Latch

A

Arbitration State Machine

A

Shared RAM

Add. Match

Add. Comp.

Add. Latch

LB Data Latch

D

LB Data Latch

P1

D

HB Data Latch

HB Data Latch

Level Shift 12V → 5V

DIOB Controls

Level Shift 5V ←12V

Level Shift 5V ←12V

Level Shift 5V → 12V

DIOB2 (Monitor) Port

P4

P3

P2

3-22. QIC

3-22.3. Specifications

Figure 3-143. QIC Detailed Block Diagram

M0-0053

3-22. QIC

Power Supply Voltage Minimum

Nominal

Maximum

Primary Voltage

12.4V

13.0V

13.1V

Backup Voltage

12.4V

13.1V

Power Requirements DIOB 1 supply voltage: +12.4 VDC to 13.1 VDC Current: - supplied by DIOB 1 Typical 250 mA Maximum 550 mA

3-22.4. Controls and Indicators Power Connection

P1

JS1

Status LEDs Activity Flag Select Switch (SW1)

JS2

P2

P4

P3

JS3

Figure 3-144. QIC Card Outline

There are three jumpers on the card. Their approximate location is shown in Figure 3-144). JS1

Control-DIOB Watch-dog Timer. The settings are 1 or 20 Seconds. If activity ceases on the control DIOB bus longer than the setting time, bits 0 and 8 of the status word are reset.

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3-22. QIC

The address of the status word is set by DIP switch SW1. The Status word can be read in word or single byte operation from the Monitor DIOB 2. The address of the status word must be an unused Monitor (and control) DIOB address. JS2

Clock Enable. The JS2 jumper must be installed for normal operation of the QIC. This jumper is used for card production testing only.

JS3

Device-busy disabled. If installed, the QIC will write data from the Control DIOB Read operation to shared RAM with or without valid DeviceBusy. If not installed, data from Control DIOB Read operation will not be written to shared RAM without a valid Device-Busy.

Status LEDs There are three status LEDs. Their location is shown in Figure 3-144. Their meanings are as follows: LED1 OUTPUT PWR. If lit, there is +12VDC at TB1 connector of DIOB 2 port. This +12VDC is provided by DIOB 1 port. LED2 QIC PWR. If lit, there is +12VDC and +5VDC power on QIC board. The +12VDC is received from DIOB 1 port. The +5VDC is generated by a linear regulator on board. LED3 ALIVE. If lit, bit 0 and bit 8 of the status word is set. It indicates the DIOB controller connected to DIOB 1 port access the DIOB 1 at least once in 1 second or 20 second depending on the setting of JS1.

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M0-0053

3-22. QIC

3-22.5. Signal Interface DIOB P1 Connector The QIC interfaces to the control DIOB through a 34 pin card-edge connector on the DIOB backplane (P1 on Figure 3-144). The pinout and signal assignment are shown in Table 3-92 below. The QIC does not use the following signals from this connector: UCAL/, UCLOCK, UFLAG/, USYNC, UNIT, DEV-BUSY. Table 3-92. QIC DIOB1 Card Edge Connector

Signal Name (Component Side)

Signal Name (Solder Side)

Pin Number

Pin Number

PRIMARY +V

2

1

PRIMARY +V

BACKUP +V

4

3

BACKUP +V

GROUND

6

5

GROUND

UADD1

8

7

UADD0

UADD3

10

9

UADD2

Comp. UADD5

12

11

UADD4 Solder

Side UADD7

14

13

UADD6 Side

R,W/

16

15

HI,LO/

DATA-GATE

18

17

UNIT

DEV-BUSY

20

19

GROUND

UDAT1

22

21

UDAT0

UDAT3

24

23

UDAT2

UDAT5

26

25

UDAT4

UDAT7

28

27

UDAT6

UFLAG/

30

29

GROUND

USYNC

32

31

UCAL/

GROUND

34

33

UCLOCK

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3-22. QIC

DIOB 2 P2 Connector (WDPF style) The QIC interfaces to the WDPF monitor DIOB through a 50 pin card-edge connector (see P2 on Figure 3-144). This cable connects to the WDPF DPU that drives the DIOB signals. The pinout and signal assignment are shown in Table 3-93. The QIC does not use the following signals from this connector: UCAL/, UCLOCK, UFLAG/, USYNC, UNIT. Table 3-93. QIC DIOB2 for WDPF



Pin Number

Pin Number

GROUND

1

2

UADD0

GROUND

3

4

UADD1

GROUND

5

6

UADD2

GROUND

7

8

UADD3

GROUND

9

10

UADD4

GROUND

11

12

UADD5

GROUND

13

14

UADD6

GROUND

15

16

UADD7

GROUND

17

18

HI,LO/

GROUND

19

20

R,W/

GROUND

21

22

UNIT

GROUND

23

24

DATA-GATE

GROUND

25

26

DEV-BUSY

GROUND

27

28

UDAT0

GROUND

29

30

UDAT1

GROUND

31

32

UDAT2

GROUND

33

34

UDAT3

GROUND

35

36

UDAT4

GROUND

37

38

UDAT5

GROUND

39

40

UDAT6

GROUND

41

42

UDAT7

GROUND

43

44

UFLAG/

GROUND

45

46

UCAL/

GROUND

47

48

USYNC

GROUND

49

50

UCLOCK

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M0-0053

3-22. QIC

DIOB 2 P3 Connector The QIC interfaces to the W2500 monitor DIOB through a 34 pin card-edge connector P3 (WIO QPD style) or a 34-pin header connector P4 (WIO QPP style). A cable connects to the W2500 I/O subsystem’s WIO board, which drives the DIOB signals. The pinout and signal assignment for both connectors are shown in Table 3-94. Table 3-94. QIC DIOB2 (P4) for WIO



Pin Number

Pin Number

NC

1

2

NC

NC

3

4

NC

GROUND

5

6

GROUND

UADD0

7

8

UADD1

UADD2

9

10

UADD3

UADD4

11

12

UADD5

UADD6

13

14

UADD7

HI,LO/

15

16

R,W/

UNIT

17

18

DATA-GATE

GROUND

19

20

DEV-BUSY

UDAT0

21

22

UDAT1

UDAT2

23

24

UDAT3

UDAT4

25

26

UDAT5

UDAT6

27

28

UDAT7

GROUND

29

30

UFLAG/

UCAL/

31

32

USYNC

UCLOCK

33

34

GROUND

Note: The QIC does not use the following signals from this connector: PRIMARY +V, BACKUP +V, UCAL/, UCLOCK, UFLAG/, USYNC, UNIT

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3-22. QIC

DIOB 2 Power Connector The QIC card contains the same 2 position terminal block +12V connector that is on the QBE. This is used to power the DIOB interface circuitry on the MSQ or MSX card. DIOB 1 Addressing The QIC responds to any DIOB 1 Read or Write to any location in the 512-byte DIOB address space by writing the data present on the DIOB data lines into its Dual Port RAM at the address specified by the DIOB address lines. DIOB 2 Addressing The QIC responds to any DIOB 2 Read of any location in the 512-byte DIOB address space by driving the DIOB 2 data lines with the Dual Port RAM data addressed by the DIOB address lines. There is board status word. The location of this word is selected with the DIP switch SW1 (see Figure 3-144). Any Read by Monitor DIOB of this address will read the status word, not the shared RAM. The QIC ignores DIOB 2 Writes.

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M0-0053

3-23. QID

3-23. QID Style 4256A84G01 - G16 (through-hole PC boards) Style 3A99159G01 - G17 (surface mount PC boards)

3-23.1. Description Groups 4256A84G01-G05;G08-G10 are applicable for use in the CE MARK Certified System The Q-Line Digital Input Card (QID) provides an interface to 220 VAC and 220 VDC digital inputs. The QID can be used for up to 8 differential (Figure 3-145) or 16 single-ended (Figure 3-146) inputs. For some applications, the QID allows field wiring cable length of up to 2,000 ft. (see Table 3-101 for a list of allowable lengths). Because of the increased cable length, new systems should employ the QID cards for all digital input applications where QDI or QBI cards were formerly used. Table 3-96 provides a list of equivalent cards for QDI and QBI.

DIOB Data

Address

R/W

1

Bus Driver 8

HI-LO

Address Comparator

8

Opto-Couplers R-C Filters

LED Indicators


8 Signal Conditioning (8) Point 0

(A7) - (A8) - (A0)

HI-LO

Point 7

Figure 3-145. QID Block Diagram, Double Input

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3-23. QID

DIOB

Hi-Lo

Data

R/W

Address

1 1

Bus Driver

Address Comparator

8 2:1 Multiplex 16 16 Opto-Couplers R-C Filters

LED Indicators


16 Signal Conditioning (16) Point 0

Point 15

Common

(A7) - (8) - (A0)

Figure 3-146. QID Block Diagram, Single Input

3-23.2. Features

• • • • • • • • •

8 differential (two-wire) inputs or 16 single-ended inputs. 500 VDC common mode rating. 600 VDC on-card isolation between each differential input channel. * Inputs include: 5, 12, 24, 48, 120, or 220 Volts IEEE Surge Withstand Capability (except Groups 01, 08, and 17). Field inputs and DIOB bus isolation using optical couplers. 500KΩminimum leakage resistance of field wiring cable allowed. May be read by any DIOB compatible controller card. Status LED for each input.

* The type of field wiring and style of terminations may restrict the design limit of the card.

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3-23. QID

M0-0053

•

QID Field input voltages equal to or less than the maximum OFF INPUT VOLTAGE, or currents equal to or less than the maximum OFF INPUT CURRENT, guarantee a logic zero to be read via the card.

•

QID Field input voltages within the range of the ON INPUT VOLTAGE will guarantee a logic one to be read via the card.

•

ON INPUT CURRENT gives the range of input current for the specified ON INPUT VOLTAGE range.

•

Minimum ON INPUT CURRENT does not guarantee that a logic one will be transfer via the card.

•

500 VDC or peak AC (line frequency) common mode voltage.


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3-23. QID

Table 3-95. QID Card Summary

Group

Input Level

Inputs*

Surge**

Comments

Replaces

G01

5 VDC

16

No

No input filters Common line connected to 5VDC

QBI G01

G02

24 VAC/DC

8

Yes

QDI G02

G03

24 VAC/DC

16

Yes

QBI G04,10

G04

48 VAC/DC

8

Yes

QDI G04

G05

48 VAC/DC

16

Yes

QBI G05,06

G06

120 VAC/DC

8

Yes

500 ft cable

QDI G06

G07

120 VAC/DC

16

Yes

500 ft cable

QBI G07,08, 11

G08

12 VDC

16

No

No input filters

QBI G02

G09

12 VAC/DC

16

Yes

G10

48 VDC

16

Yes

Pulse Inputs

QDI G10

G11

120 VAC

8

Yes

1,000 ft cable

QDI G11

G12

120 VAC

16

Yes

1,000 ft cable

QBI G08,11

G13

220 VAC

8

Yes

1,000 ft cable

G14

220 VAC

16

Yes

1,000 ft cable

G15

220 VDC

8

Yes

G16

220 VDC

16

Yes

G17***

5VDC

16

No

QBI G03,09

No input filters Common line can be connected to +5V or 5V RTN.

QBI G01

* 16 means single-ended inputs, 8 means differential inputs. ** ANSI Std. C37.90A 1974 (or IEEE 472-1974) for surge withstand *** Style 3A99159 only.

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3-23. QID

3-23.3. Specifications Inputs/Outputs Table 3-96. QID Inputs

OFF ON Input Input Voltage Voltage ON OFF (VDC or VAC (VDC or Input Current Input Propagation Group RMS) VAC RMS) (mA) Current Time (msec)

Power In Front End, All Units On (Watts) Typical MIN MAX MAX MIN MAX (mA) MIN MAX (TYP) G01 2.4 7 0.9 2 10 0.5 --0.2 0.5 G02 20 30 7 5 10 3.0 1 14 1.5 G03 20 30 7 5 10 3.0 1 14 3.0 G04 40 60 17 7 12 5.0 1 14 3.8 G05 40 60 17 7 12 5.0 1 14 7.6 G06 100 150 40 6 10 3.8 1 14 7.1 G07 100 150 40 6 10 3.8 1 14 14.2 G08 10 15 3 5 10 2.0 --0.2 1.5 G09 10 15 3 5 10 2.0 1 14 1.5 G10 40 60 24 7 12 5.0 0.5 2.1 7.6 G11 95 150 60 16 27 8.4 1 14 10.0 G12 95 150 60 16 27 8.4 1 14 20.0 G13 190 264 120 30 43 11.4 1 14 23.2 G14 190 264 120 30 43 11.4 1 14 46.4* G15 180 264 110 6 10 3.8 1 14 12.4 G16 180 264 110 6 10 3.8 1 14 24.8 G17 2.8 7 0.9 2 10 0.5 --0.2 0.5 * Note: Due to high power in front end, the maximum number of the QID G14 that can be used in the DPU cabinet is 24 cards. Power Requirements Control DIOB supply voltage: +12.4 VDC to 13.1 VDC Current: - supplied by DIOB bus. Typical: 100 mA

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3-23. QID

Maximum: 200 mA DIOB Connector The QIC interfaces to the DIOB bus through a 34 pin card-edge connector on the DIOB backplane. The QID contains 17 gold fingers on the component and solder sides of the board, spaced 0.1” apart. The pinout and signal assignment are shown in Table 3-97. Table 3-97. QID Pinout

Signal Name PRIMARY +V BACKUP +V GROUND UADD1 UADD3 Comp. UADD5 Side UADD7 R,W/ DATA-GATE DEV-BUSY UDAT1 UDAT3 UDAT5 UDAT7

GROUND

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Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33


Signal Name PRIMARY +V BACKUP +V GROUND UADD0 UADD2 UADD4 Solder UADD6 Side HI,LO/ GROUND UDAT0 UDAT2 UDAT4 UDAT6 GROUND

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3-23. QID

There are three type of input signal interfaces selectable by groups:

•

Differential Input Interface-- provided in QID 8 differential input groups (QID G02, 04, 06, 11, 13, and 15) and is the same as that provided in any QDI 8 differential input cards. See Table 3-98.

•

Single Ended Input Interface --provided in QID 16 differential input groups (QID G01, 03, 05, 07-09, 12, 14, 16, and 17) and is the same as that provided in any QBI 16 Single-ended input cards. See Table 3-99.

•

Group 10 Input Interface -- equivalent to the QDI 16 single-ended input cards. See Table 3-100.

Table 3-98. QID Differential Input Interface

Input Digital Bit Number Chassis Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

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PC Card Edge Pin 1A and 1B 1A and 1B 3A 3B 5A 5B 7A 7B 9A 9B 11A 11B 13A 13B 15A 15B 17A 17B


Field Block Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

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3-23. QID

Table 3-99. QID Single-Ended Input Interface

Input Digital Bit Number Common Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15

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PC Card Edge Pin 1A and 1B 3A 3B 5A 5B 7A 7B 9A 9B 11A 11B 13A 13B 15A 15B 17A 17B



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3-23. QID

Table 3-100. QID G10 Input Interface

Input Digital Bit Number Common Bit 8 Bit 0 Bit 1 Bit 9 Bit 10 Bit 2 Bit 3 Bit 11 Bit 12 Bit 4 Bit 5 Bit 13 Bit 14 Bit 6 Bit 7 Bit 15

PC Card Edge Pin 1A and 1B 3A 3B 5A 5B 7A 7B 9A 9B 11A 11B 13A 13B 15A 15B 17A 17B


DIOB Control The QID Single-ended Input groups occupy a 16 bit word in the DIOB address field. The address of the QID is selected by jumpers at the top of the front-edge connector. Insertion of a jumper encodes a “one” on each address line. Absence of a jumper encodes a “zero”. The QID Differential Input groups occupy one byte (8 bits) in the DIOB address field. When selecting address of the QID, the HI-LOW address line at the front-edge connector must also be used.

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3-23. QID

Input Circuit Each input circuit of the QID is inherently a voltage input device. A two-wire differential input will produce a logic “one” at the DIOB if the voltage between the two wires is greater than the minimum ON INPUT VOLTAGE specified for that QID group. A Logic “zero” will be produced if the voltage between two wires is less than the maximum OFF INPUT VOLTAGE. Single-ended input cards operate in a similar manner except that voltage is sensed between the one input wire per bit and the common terminal. Contact inputs are provided by placing a field contact in series with the QID input voltage supply. Contact closure produces a logic “one” at the DIOB. Contact inputs may also be used on differential cards where isolation between two or more sets of wetting voltage supplies is required.

Card Address = 11001000 (Hex “C8” Low Byte)

Card Address = 00100011 (Hex “23”)

Jumper : A7 = 1

Blank

: A7 = 0

Jumper : A6 = 1

Blank

: A6 = 0

Blank

: A5 = 0

Jumper : A5 = 1

Blank

: A4 = 0

Blank

: A4 = 0

Jumper : A3 = 1

Blank

: A3 = 0

Blank

: A2 = 0

Blank

Blank

: A1 = 0

: A2 = 0 Jumper : A1 = 1 Jumper : A0 = 1

Blank

: A0 = 0 Jumper : HI-LO = 0

No Jumper required at HI-LO

Differential Inputs

Single-Ended Inputs

Figure 3-147. QID Card Address Jumper Example

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3-23. QID


LEDs

LED Detail

PWR 15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

Figure 3-148. QID Card Outline

Power LED POWER LED indicates whether there is +12VDC on the QID board. Input status LEDs For each input to the QID card, an LED indicates input status (ON for logic “one”, OFF for logic “zero”).

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3-23. QID

3-23.5. Wiring Field Wiring Cable Length When using AC supply voltage to wet contact inputs, some limits exist on cable lengths due to stray capacitance in the cables. The maximum capacitance which can be tolerated by the QID is listed below. Table 3-101. QID Allowable Cable Capacitance

Group Number Voltage Capacitance Maximum Length 1 G02 (24VAC) 100,000 PF 2,000 FT G03 (24VAC) 100,000 PF 2,000 FT G04 (48VAC) 75,000 PF 1,500 FT G05 (48VAC) 75,000 PF 1,500 FT G06 (120VAC) 25,000 PF 500 FT G07 (120VAC) 25,000 PF 500 FT G11 (120VAC) 50,000 PF 1,000 FT G12 (120VAC) 50,000 PF 1,000 FT G13 (220VAC) 50,000 PF 1,000 FT G14 (220VAC) 50,000 PF 1,000 FT 1 Based on standard cable with stray capacitance of 50 PF/FT. A longer length cable can be used if a cable with lower capacitance is used. Note For CE Mark certified systems, field wiring that carries the AC mains must have double insulation.

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3-23. QID

'

QID G01

Point 15 (16) Point 0 Common + Logic Voltage Figure 3-149. QID Group 1 Connections '

QID G08 and G17

Point 15 (16) Point 0 +

Common

Logic Voltage

Common line can be connected to Logic Voltage (+) or Logic Voltage (-).

Figure 3-150. QID Group 8 and Group 17 Connections

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3-23. QID

QID Single-Ended Inputs

Length (see Table 3-101) Point 15

Field Contact

16 points Point 0

Field Contact

Return


Figure 3-151. QID Single Ended Inputs

QID Differential Input

Length (see Table 3-101) Point 7

Field Contact

(8) 8 points Point 0

Field Contact

Return Chassis



Figure 3-152. QID Differential Inputs

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3-23. QID


Terminal Block

Card

19B 19A 17B 17A 15B 15A 13A 13A 11B 11A 9B 9A 7B 7A 5B 5A 3B 3A 1B 1A

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

Edge Connector

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Customer Connections

Note: For G13 (220 VAC) and G15 (220 VDC) used with #6 screw terminal blocks, all neutral returns of wetting voltages must be connected to even terminals of terminal blocks (terminals 2, 4, 6, 8, 10, 12, 14, 16).

Figure 3-153. QID Wiring for Groups 2, 4, 6, 11, 13, and 15

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3-23. QID


Figure 3-154. QID Card Connections

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3-23. QID


Figure 3-155. QID Card Connections

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3-23. QID


Figure 3-156. QID Card Connections (G10)

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3-23. QID


CARD

EDGE-CONNECTOR

1A

A

A

1B

1

1

3A

2

2

+

3B

3

3

-

5A

4

4

+

5B

5

5

-

7A

6

6

+

7B

7

7

-

9A

8

8

+

9B

9

9

-

11A

10

10

+

11B

11

11

-

13A

12

12

+

13B

13

13

-

15A

14

14

+

15B

15

15

-

17A

16

16

+

17B

17

17

-

19A

18

18

19B

19

19

20

20

PE

PE

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Figure 3-157. QID CE MARK Wiring Diagram (Groups 2, 4, 6, 11, 13 and 15)

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3-23. QID


CUSTOMER CONNECTIONS CARD A

1A

A

1B

1

01

B 01

BIT 0

3A

2

02

02

BIT 1

3B

3

03

03

BIT 1

3

BIT 2

5A

4

04

04

BIT 2

4

05

BIT 3

5

BIT 0

1 2

BIT 3

5B

5

05

BIT 4

7A

6

06

06

BIT 4

6

BIT 5

7B

7

07

07

BIT 5

7

BIT 6

9A

8

08

08

BIT 6

8

BIT 7

9B

9

09

09

BIT 7

9

BIT 8

11A

10

10

10

BIT 8

10

BIT 9

11B

11

11

11

BIT 9

11

BIT 10

13A

12

12

12

BIT 10

12

BIT 11

13B

13

13

13

BIT 11

13

BIT 12

15A

14

14

14

BIT 12

14

BIT 13

15B

15

15

15

BIT 13

15

BIT 14

17A

16

16

16

BIT 14

16

17

BIT 15

17

BIT 15

17B

17

19A

18

19B

19 20

EDGE-CONNECTOR

17 18

1A * 19

19

20

20

20

PE

PE

19

~ AC or DC +

* 2A in Groups 14 and 16

Figure 3-158. CE MARK Wiring Diagram (Groups 1, 3, 5, 7, 8, 9, 12, 14 and 16)

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3-23. QID


CUSTOMER CONNECTIONS CARD 1A

A

A

B

1B

1

01

01

BIT 0

3A

2

02

02

BIT 1

3B

3

03

03

BIT 0

3

BIT 2

5A

4

04

04

BIT 1

4

BIT 3

5B

5

05

05

BIT 9

5 6

BIT 8

1 2

BIT 4

7A

6

06

06

BIT 10

BIT 5

7B

7

07

07

BIT 2

7

BIT 6

9A

8

08

08

BIT 3

8

BIT 7

9B

9

09

09

BIT 11

9

BIT 8

11A

10

10

10

BIT 12

10

BIT 9

11B

11

11

11

BIT 4

11 12

BIT 10

13A

12

12

12

BIT 5

BIT 11

13B

13

13

13

BIT 13

13

BIT 12

15A

14

14

14

BIT 14

14

BIT 13

15B

15

15

15

BIT 6

15

BIT 14

17A

16

16

16

BIT 7

16

BIT 15

17B

17

17

17

BIT 15

17

19A

18

19B

EDGE-CONNECTOR

.75A 19

19

20

20

~ AC or DC +

PE

Figure 3-159. CE MARK Wiring Diagram (Group 10)

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3-24. QLC

3-24. QLC Q-Line Serial Link Controller (Style 4256A01G01)

3-24.1. Description Groups 01and 02 are applicable for use in the CE MARK Certified System The QLC printed circuit board is a single-board computer which interfaces to the WDPF DPU (Distributed Processing Unit). The QLC, installed in a Q-Crate communicates with the DPU through the DIOB. For additional information on the QLC, see “QLC User’s Guide” (U0-1100).

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3-25. QLI

3-25. QLI Q-Line Loop Interface Card (Style 7381A10G01 through G03)

3-25.1. Description Groups 01, 02, 03 are applicable for use in the CE MARK Certified System The Q-Line Loop Interface Card (QLI) handles the analog and digital inputs and outputs associated with a single or cascaded control loop executing in a Distributed Process Unit (DPU). The QLI’s I/O capability consists of three analog inputs, one analog output, two digital inputs, and two digital outputs. Communications to and from the card are through a Distributed Input/Output Bus (DIOB).

DIOB

DIOB Interface Timing Control Switches DIOB Bus Arbitration, Data Latches

Switches, Jumpers

Serial Port Circuit

MEMORY E E P R O M

R A M

E P R O M

RS 422 Serial Port

Processor

Isolation Barrier

Two Optical Isolators

TwoOPTICAL Optical TWO Isolators ISOLATORS

Two Drivers

Two Signal Conditioners

G03 40V A/D

A/D

(+)

(−)

(+)

(−)

Analog Inputs

A/D

(+)

(−)

D/A

(+)

(−)

-

+

or G01,02

RTN Two Digital Outputs

Analog Output

Two Digital Inputs

Figure 3-160. QLI Functional Block Diagram

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3-25. QLI

The QLI may be linked to a Loop Interface Module (LIM) or Small Loop Interface Module (SLIM), used for monitoring and manual control of the QLI’s control loop (see Figure 3-161).

TCP Data Highway

D P U

D P U

Q-Crate Q B E

Q T B

Q L I

Q L I

Q L I

Q L I

#1

#2

#3

#4

Flat Flex (Up to 12 QLI’s on chain)

Q L I

Q L I

Q L I

#28 #29 #30

Transition Panel Multiple QLIs (LIM or SLIM)

Twisted Pair (One QLI/LIM or SLIM)

Twisted Pair LIM or SLIM

LIM or SLIM

Figure 3-161. QLI Card Usage

Analog input voltages or currents are converted by the QLI to binary numbers at a rate of four times per second. They are stored by the QLI until they are read by the DPU. Binary numbers from the DPU are converted to output voltages or currents at a rate greater than 10 times/second. Digital inputs are read five times per second and digital outputs fixed at the same rate. Three versions of the QLI are available, distinguished by their analog input and output value ranges: Version

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Analog Input

Analog Output

Group 1

0 - 10 V

0 - 10 V

Group 2

0-5V

0 - 10 V

Group 3

0 - 20 mA

4 - 20 mA


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3-25. QLI

Group 3 QLIs may be modified to accept 10-50 mA input by changing a 250 ohm input resistor on the card to a 100 ohm resistor. Changing the resistor to 100 ohms introduces an error of 0.2%. Each QLI card must have an external power supply which delivers 500 mA at 24 VDC to the card edge connector. This power is for I/O functions. The Q crate delivers 13 VDC at the rear edge pin connectors. This is the power for all logic and communications on the card. The QLI automatically checks for 13-volt power supply malfunctions as well as many of its own malfunctions. Malfunctions are displayed by the program running in the DPU. Additional information related to the installation and operation of the QLI can be found in “Q-Line Loop Interface Module (QLI/LIM) User’s Guide” (NLAM-B200).

3-25.2. Features

M0-0053

•

Three analog input circuits and one analog output circuit. Also two digital input and two digital output circuits. Both analog and digital circuitry are isolated from the logic circuitry.

• •

Choice of analog input and output ranges.

• •

Digital scan rate of five times per second.

•

IEEE/SWC surge withstand protection for both digital and analog inputs and outputs.

• • •

Interfaces with the DPU through a Distributed Input/Output Bus (DIOB).

•

Automatic diagnostic program detects 13V power supply and QLI malfunctions.

•

Detects and flags over- and under-range conditions.

Analog-to-digital conversion rate of four times per second with an accuracy of 0.1%

Automatic adjustment for gain and offset temperature coefficients of analog inputs.

Configuration switches to customize operation. Serial port connection to Loop Interface Module (LIM) or Small Loop Interface Module (SLIM). RS-422 and up to 1000 feet long.


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3-25. QLI

3-25.3. Specifications Analog Input: Input ranges

A/D conversion type Conversion rate Accuracy Impedance Resolution

Group 1 0-10 VDC Group 2 0-5 VDC Group 3 0-20 mA* voltage-to-frequency 4/sec 0.1% 100 megohms/volt, 1000 ohms in overload 12 bits

Analog Output: Output ranges

Loading Resolution

Group 1 0-10 VDC Group 2 0-10 VDC Group 3 4-20 mA* 0-1000 Ohms for current, 500 Ohms minimum for voltage 12 bits, unipolar

Digital Input Ranges Min ON voltage – 18VDC Max ON voltage – 60VDC Max OFF voltage – 6VDC Max OFF current – 0.5mA Digital Output Ranges Min ON voltage 2VDC at 150mA, 3VDC at 200mA Max ON current 200mA Max OFF current 0.5mA at 60VDC Note Only Group 3 can be used for pulse digital outputs. *With Group 3 cards, the range can be changed to 10-50 mA by changing a resistor on the card. Accuracy will then be 0.2%.

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3-25. QLI

3-25.4. Interface Specifications Field wiring to the QLI is through the card edge connector. Prefabricated cable connections are made with the terminal blocks in the adjacent “B” cabinet. The QLI itself is grounded by a grounding screw at the bottom front corner of the card (see Figure 3-163). This not only grounds the card through its rack but also allows the IEEE Surge Protection circuitry to function and allows the LIM (Loop Interface Module) to function properly. The card edge connector contains the fuse for both the 24 VDC power supply and the digital inputs and outputs. Recommended ratings for replacement fuses are shown in the installation diagram. The terminal block itself is rated at 5A maximum, but most applications require a fuse of less than 1A. Analog inputs are protected up to 120 VDC continuous; digital, up to 150 VDC continuous. Both analog and digital input and output circuits meet IEEE/SWC Surge Withstand Standards.

3-25.5. Circuit Description The QLI contains three analog input channels, each of which has its own circuitry including an A/D converter. Analog inputs are converted to binary numbers. Negative inputs are flagged as an under-range condition. The QLI has one analog output with a D/A converter which converts binary numbers to an analog voltage or current value. The QLI also has two digital inputs and two digital outputs. Incoming analog and digital values to the DPU are stored in DIOB data latches on the QLI and accessed by the DPU for processing. Outgoing analog and digital values from the DPU are also stored in data latches on the QLI. Components Figure 3-160 shows a functional block diagram of the QLI. 1. Serial Port Control: An RS-422 serial port for communication with a Loop Interface Module (LIM). An on-board microprocessor sends and receives serial I/O data for manual loop control through this port. 2. A/D Converters: (Three converters: One for each analog channel) Convert incoming analog signals to a digital value. Incoming analog currents are first converted to a voltage signal and then to a frequency. 3. D/A Converter: Converts binary signals from the DPU to an analog voltage or current.

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3-25. QLI

4. Digital Input Circuits: Digital inputs pass through signal conditioners, filters, and optical isolators before being read by a microprocessor. 5. Digital Output Circuits: Digital outputs from the DPU go to the microprocessor and then through optical isolators, signal conditioners, and filters before leaving the circuit. These outputs are also powered through the card edge connector. 6. Switches: Settings of the configuration and EEPROM switches and the configuration jumper clips allow the microprocessor to follow the correct control procedures for the configuration chosen. 7. Microprocessor: Controls serial port communication, adjusts analog inputs for gain and offset error, stores configuration data, and performs control functions dictated by the configuration data. 8. Memory Controller: Allows the microprocessor to read configuration data from the on-board memories and to write configuration data sent to it from the DPU to the On-board EEPROM. This data will then be available for the microprocessor to read on the next power-up cycle. 9. Memories: Current configuration data is stored in the 1K EEPROM; default configuration data and control programming is stored in the 32K EPROM; and input, output, and calculation data is stored in the 2K Static RAM. 10. DIOB Bus Arbitration: Controls access to the DIOB data latches. Coordinates reading of new data by both the microprocessor and the DPU. 11. DIOB Data Latches: Store input data written by the microprocessor for the DPU to read via the DIOB interface, and output and configuration data written by the DPU via the DIOB interface for the microprocessor to read. 12. DIOB Interface: Places data from the output data latches onto the DIOB data lines and takes data from the DIOB data lines and stores it in the input data latches.

3-25.6. Card Addressing Card addressing is in hexadecimal. Addresses begin at 08 and end at F0 and follow the standard Q-Line addressing scheme. The last three bits are always zero; only the first five bits are set with jumpers.

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3-25. QLI

Note Installing a jumper encodes a DIOB address BIT = 1. Installing a jumper encodes a Card Configuration BIT = 0.

28

Jumper: A7=1

27

Jumper: A6=1

26

Blank

A5=0

25

Blank

A4=0

24

Jumper: A3=1

23

Jumper: 0

22

Jumper: 0

21

Jumper: 0

20

Jumper: Address Enabled

DIOB Address

Card Configuration

This jumper must be present for the QLI to respond to the DPU.

Figure 3-162. QLI Card Address Jumper Example

3-25.7. Controls and Indicators QLI card components are shown in Figure 3-163. EEPROM Switch Serial Port Connector Switches 1-3 POWER OK

LEDs

CALIBRATION

Figure 3-163. QLI Card Components

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3-25. QLI

Configuration Switches Switch No. 1

For all cards configuration types except Digital Positioning type: Digital Output Default: Controls whether to hold digital outputs at their current values during DPU timeout or to go to zero values. Open = Hold. For Digital Positioning type configurations only: Initial State Selection: Controls whether the output pulses start with the ON or OFF state. Open = ON state. This feature is available on QLI cards at sub X and later.

Switch No. 2

Power Line Frequency: Choose between 50 and 60 Hz power line frequency. Open = 50 Hz.

Switch No. 3

Disable DPU Timeout: Controls whether or not QLI will enter a timeout mode if DPU has not written to QLI for more than 3 seconds. Open = enable timeout.

EEPROM Switch Controls access to the on-board EEPROM (see Figure 3-163). If the switch is OFF, EEPROM is ignored on power-up and the configuration constants receive default values from EPROM. Also, any configuration data written to the QLI will not be stored in EEPROM. If the switch is ON, configuration constants previously written to the QLI (while the switch was ON) are read from EEPROM on power-up and any new configuration data written to the QLI will be stored in EEPROM for the next power-up.

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3-25. QLI

LED Indicators POWER OK -

LED is lit if proper power to the card is provided. It is ON in normal operation.

CALIBRATION - LED is lit if the card is calibrating or is initializing. It is OFF in normal operation.

Configuration Jumpers Slots on the card edge connector allow insertion of jumpers for card configuration and addressing (see Figure 3-162). Choices for card configuration are as follows: Table 3-102. Configuration Jumpers State

Jumper 23

Jumper 22

Jumper 21

NORMAL

In

In

In

NORMAL WITH RAISE/LOWER OVERRIDE

In

In

Out

MASSFLOW

In

Out

In

MASSFLOW WITH RAISE/ LOWER OVERRIDE

In

Out

Out

DIGITAL POSITIONING Digital positioning only available for group 3.

Out

In

In

DIGITAL POSITIONING WITH RAISE/LOWER OVERRIDE Digital positioning only available for group 3.

Out

In

Out

Not Used

Out

Out

In

Not Used

Out

Out

Out

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3-25. QLI


TERMINAL BLOCK



(+) ANALOG OUTPUT

20B

A

20A

20 B

19B

19

19A

18

17B

17

DIGITAL OUTPUT 1

17

17A

16

DIGITAL OUTPUT 2

16

FUSE 1/4A

15B

15

(+) ANALOG OUTPUT 1 (−)

15

FUSE 1/32A

I/O DEVICES

18 FUSE 1/4A

15A

14

(−)

13B

13

(+)

13A

12

11B

11

11A

10

9B

09

9A

08

7B

07

7A

06

5B

05

05

5A

04

04

3B

03

DIGITAL INPUT 1

3A

02

DIGITAL INPUT 1

02

FUSE 1/4A

DIGITAL INPUT 2

1B

01

DIGITAL INPUT 2

01

FUSE 1/4A

ANALOG SHIELD INPUT 1 (−) (+) ANALOG INPUT 2 SHIELD (−) (+) ANALOG INPUT 3 SHIELD (−)

14 13 (−)ANALOG INPUT 1(+)

12

FUSE 1/32A


09

FUSE 1/32A


06

FUSE 1/32A

03

1A (AT HALF-SHELL) EDGE-CONNECTOR

CUSTOMER CONNECTIONS 24 VDC Return (Customer grounding)

+24 VDC

Figure 3-164. QLI Wiring Diagram: WDPF Powered, Local Grounding

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M0-0053

3-25. QLI

Installation Data Sheet 2 of 4 TERMINAL BLOCK



(+) ANALOG OUTPUT

20B

A

20A

20

19B

19

19A

18

17B

17

17A 15B

B I/O DEVICES

18

DIGITAL OUTPUT 1

17

16

DIGITAL OUTPUT 2

16

FUSE 1/4A

15

(+)ANALOG OUTPUT 1(−)

15

FUSE 1/32A

FUSE 1/4A

15A

14

(−)

13B

13

(+)

13A

12

+

SHIELD

11B

11

S

(−)

11A

10

-

(+)

9B

09

+

SHIELD

9A

08

S

(−)

7B

07

-

07

(+)

7A

06

+

06

SHIELD

5B

05

S

(−)

5A

04

-

3B

03

DIGITAL INPUT 1

3A

02

DIGITAL INPUT 1

02

FUSE 1/4A

DIGITAL INPUT 2

1B

01

DIGITAL INPUT 2

01

FUSE 1/4A

ANALOG INPUT 1

ANALOG INPUT 2

ANALOG INPUT 3

14 13 12 ANALOG INPUT 1

11 10 09

ANALOG INPUT 2

ANALOG INPUT 3

08

05 04 03

1A

EDGE-CONNECTOR

CUSTOMER CONNECTIONS 24 VDC Return (Customer grounding)

+24 VDC

Figure 3-165. QLI Wiring Diagram: Digital I/O-WDPF Powered Analog I/O-Self Powered with Remote Grounding

Installation Notes (Refer to Figure 3-165) 1. For QLI cards at level 3QLI22 and higher (drawing number 7381A10 sub “L” or higher), the card is not connected to pin 15A and a jumper is present, connecting pin 1A to 3B. For earlier versions of the QLI, perform the following steps: a. Remove pin 15A from the card edge connector and tie back the wire.

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3-25. QLI

b. Add a jumper between pin 1A and pin 3B on the card edge connector. 2. Analog input devices should be connected with shielded twisted pair cables. Shield drains and negatives from QLI must be connected to DC power return. 3. DC power return must be grounded 4. Jumpers between terminal block screws 3, 4, 5, 7, 8, 10 and 11 must be added.

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M0-0053

3-25. QLI


CARD 1A

A

A

1B

1

1

3A

2

2

3B

3

3

5A

4

4

5B

5

5

7A

6

6

(+)

7B

7

7

(-)

9A

8

8

9B

9

9

(+)

11A

10

10

(-)

11B

11

11

13A

12

12

(+)

13B

13

13

(-)

15A

14

14

15B

15

15

17A

PE

PE

17B

BIT 2 BIT 1 (-) POINT 3

POINT 2

POINT 1

ANALOG OUTPUT (+)

R1

19A

R0 EDGE-CONNECTOR

18

18

19

19

(−)

20

20

(+)

1 2

24 VDC

.25A .25A

6 9 12 13 15 16

FUSE SIZE DEPENDENT ON RELAY AND APPLICATION

17

Figure 3-166. QLI CE MARK Wiring Diagram (Analog Inputs Powered at Field Side)

Installation Notes (Refer to Figure 3-166) 1. The digital outputs must use shielded cable, unless the cabinets are bolted together and interposing relays are used (as shown above). The actual relay wiring depends on the relay style used. 2. The analog output must NOT have the shield tied to the return. However, the shield must be connected to earth ground at the B cabinet, as shown. 3. The analog inputs may be grounded at the B cabinet or in the field, as shown.

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3-25. QLI


CARD 1A

A

A

1B

1

1

3A

2

2

3B

3

3

5A

4

4

5B

5

5

7A

6

6

(+)

7B

7

7

(-)

9A

8

8

9B

9

9

(+)

11A

10

10

(-)

11B

11

11

13A

12

12

(+)

13B

13

13

(-)

15A

14

14

15B

15

15

17A

PE

PE

17B

BIT 2 BIT 1 (-) POINT 3

POINT 2

POINT 1

ANALOG OUTPUT (+)

R1

19A

R0 EDGE-CONNECTOR

18

18

19

19

(−)

20

20

(+)

1

24 VDC

.25A

2

.25A

6

1/32A

9

1/32A

12 13 15 16

FUSE SIZE DEPENDENT ON RELAY AND APPLICATION

17

Figure 3-167. QLI CE MARK Wiring Diagram (Analog Inputs Powered at WDPF System Side)

Installation Notes (Refer to Figure 3-167) 1. The digital outputs must use shielded cable, unless the cabinets are bolted together and interposing relays are used (as shown above). The actual relay wiring depends on the relay style used. 2. The analog output must NOT have the shield tied to the return. However, the shield must be connected to earth ground at the B cabinet, as shown. 3. When powering the analog inputs at the WDPF side, the analog inputs should be grounded at the B cabinet or in the field, as shown.

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3-26. QLJ

3-26. QLJ Q-Line Loop Interface Card with Output Readback (Style 7381A76G01 through G03)

3-26.1. Description The Q-Line Loop Interface Card (QLJ) handles the analog inputs and outputs associated with a single or cascaded control loop executing in a Distributed Process Unit (DPU). The QLJ’s I/O capability consists of three analog inputs, and one analog output with readback. Communications to and from the card are through a Distributed Input/Output Bus (DIOB).

DIOB

DIOB Interface

DIOB Bus Arbitration, Data Latches RS 422 Serial Link Memory R A M

EE PROM

E P R O M

Processor

Timing Control

Jumpers, Switches

A/D

A/D

A/D

D/A (+)

(+)

(−)

(+)

(−)

Analog Inputs

(+)

(−)

(+)

Internal Readback

A/D (−)

(−)

Analog Output

Figure 3-168. QLJ Functional Block Diagram

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3-26. QLJ

The QLJ may be linked to a Loop Interface Module (LIM) used for monitoring and manual control of the QLJ’s control loop (see Figure 3-169).

TCP Data Highway

D P U

D P U

Q-Crate Q B E

Q T B

Q L J

Q L J

Q L J

Q L J

#1

#2

#3

#4

Flat Flex (Up to 12 QLJ’s on chain)

Q L J

Q L J

Q L J

#28 #29 #30

Twisted Pair (One QLJ/LIM or SLIM)

Transition Panel Multiple QLJs (LIM or SLIM)

Twisted Pair

LIM

LIM

Figure 3-169. QLJ Card Overview

Analog input voltages or currents are converted by the QLJ to binary numbers at a rate of four times per second. They are stored by the QLJ until they are read by the DPU. Binary numbers from the DPU are converted to output voltages or currents at a rate greater than 10 times/second.

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3-26. QLJ

Three versions of the QLJ are available, distinguished by their analog input and output value ranges: Version

Analog Input

Analog Output

Group 1

0 - 10 V

0 - 10 V

Group 2

0-5V

0 - 10 V

Group 3

0 - 20 mA

4 - 20 mA

Group 3 QLJs may be modified to accept 10-50 mA input by changing a 250 ohm input resistor on the card to a 100 ohm resistor. Changing the resistor to 100 ohms introduces an error of 0.2%. The Q crate delivers 13 VDC at the rear edge pin connectors. This is the power for all logic and communications on the card. The QLJ automatically checks for 13-volt power supply malfunctions as well as many of its own malfunctions. Malfunctions are displayed by the program running in the DPU. Additional information related to the installation and operation of the QLJ can be found in “Q-Line Loop Interface Card and Loop Interface Module (QLI/LIM) User’s Guide” (NLAM-B200).

3-26.2. Features

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•

Three analog input circuits and one analog output circuit with internal readback and range checking. Analog circuitry is isolated from the logic circuitry.

• • •

Choice of analog input and output ranges.

• • • •

IEEE/SWC surge withstand protection for analog inputs and outputs.

•

Automatic diagnostic program detects 13V power supply and QLJ malfunctions.

Analog-to-digital conversion rate of 4 times per second with an accuracy of 0.1% Automatic adjustment for gain and offset temperature coefficients of analog inputs.

Interfaces with the DPU through a Distributed Input/Output Bus (DIOB). Configuration switches to customize operation. Serial port connection to Loop Interface Module (LIM). RS-422 and up to 1000 feet long.


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3-26. QLJ

•

Detects and flags over- and under-range conditions.

3-26.3. Specifications Analog Input Input ranges

Group 1 0-10 VDC Group 2 0-5 VDC Group 3 0-20 mA * A/D conversion type voltage-to-frequency Conversion rate 4/sec Accuracy 0.1% Impedance 100 megohms/volt, 1000 ohms in overload Resolution 12 bits Analog Output Output ranges

Loading Resolution Accuracy AO Readback

Group 1 0-10 VDC Group 2 0-10 VDC Group 3 4-20 mA ** 0-1000 Ohms for current 500 Ohms minimum for voltage 12 bits, unipolar 0.1% A/D resolution 8 bits Accuracy of readback 3.125% (5 bits)

Circuit Specifications Field wiring to the QLJ is through the front card edge connector. Prefabricated cable connections are made with the terminal blocks in the adjacent “B” cabinet. The QLJ itself is grounded by a grounding screw at the bottom front corner of the card (see Figure 3-171). This not only grounds the card through its rack but also allows the IEEE Surge Protection circuitry to function and allows the LIM (Loop Interface Module) to function properly. Analog inputs are protected up to 120 VDC continuous; digital, up to 150 VDC continuous. Analog input and output circuits meet IEEE/SWC Surge Withstand Standards.With Group 3 cards

*With Group 3 cards, the range can be changed to 10-50mA by changing a resistor on the card. Accuracy will then be 0.2%. ** AO is totally isolated from the rest of the card. The shield can be connected to earth ground in the field.

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3-26. QLJ

3-26.4. Circuit Description The QLJ contains three analog input channels, each of which has its own circuitry including an A/D converter. Analog inputs are converted to binary numbers. Negative inputs are flagged as an under-range condition. The QLJ has one analog output with a D/A converter which converts binary numbers to an analog voltage or current value. This analog output is read back and converted to linear numbers, and can be read by the DPU. Incoming analog values to the DPU are stored in DIOB data latches on the QLJ and accessed by the DPU for processing. Outgoing analog values from the DPU are also stored in data latches on the QLJ. Components Figure 3-168 shows a functional block diagram of the QLJ. 1. Serial Port Control: An RS-422 serial port for communication with a Loop Interface Module (LIM). An on-board microprocessor sends and receives serial I/O data for manual loop control through this port. 2. A/D Converters: (Three converters: One for each analog channel) Convert incoming analog signals to a digital value. Incoming analog currents are first converted to a voltage signal and then to a frequency. 3. AO Readback: A/D converts analog output signal directly to a digital value. 4. D/A Converter: Converts binary signals from the DPU to an analog voltage or current. 5. Switches: Settings of the configuration and EEPROM switches and the configuration jumper clips allow the microprocessor to follow the correct control procedures for the configuration chosen. 6. Microprocessor: Controls serial port communication, adjusts analog inputs for gain and offset error, stores configuration data, and performs control functions dictated by the configuration data. 7. Timing and Control Circuitry: Generates the signals needed for the input and output circuits and the microprocessor. Based on an 11.0592-MHz clock. 8. Memories: Current configuration data is stored in the 1K EEPROM; default configuration data and control programming is stored in the 32K EPROM; and input, output, and calculation data is stored in the 2K Static RAM. 9. DIOB Bus Arbitration: Controls access to the DIOB data latches. Coordinates reading of new data by both the microprocessor and the DPU. M0-0053


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3-26. QLJ

10. DIOB Data Latches: Store input data written by the microprocessor for the DPU to read via the DIOB interface, and output and configuration data written by the DPU via the DIOB interface for the microprocessor to read. 11. DIOB Interface: Places data from the output data latches onto the DIOB data lines and takes data from the DIOB data lines and stores it in the input data latches.

3-26.5. Card Addressing Card addressing is in hexadecimal. Addresses begin at 08 and end at F0 and follow the standard Q-Line addressing scheme. The last three bits are always zero; only the first five bits are set with jumpers. Note Installing a jumper encodes a DIOB address BIT = 1. Installing a jumper encodes a Card Configuration BIT = 0

28

Jumper: A7=1

27

Jumper: A6=1

26

Blank

A5=0

25

Blank

A4=0

24

Jumper: A3=1

23

Jumper: 0

22

Jumper: 0

21

Jumper: 0

20

Jumper: Address Enabled

DIOB Address

Card Configuration

This jumper must be present for the QLJ to respond to the DPU.

Figure 3-170. QLJ Card Address Jumper Example

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3-26. QLJ

3-26.6. Controls and Indicators QLJ card components are shown in Figure 3-171.

EEPROM Switch POK CAL

Switches 1-3

LEDs Serial Port Error Jumper

Figure 3-171. QLJ Card Components

Configuration Switches (Four Position DIP Switch) Switch Pos. No. 1

Not used.

Switch Pos. No. 2

Power Line Frequency: Choose between 50 and 60 Hz power line frequency. Open = 50 Hz.

Switch Pos. No. 3

Disable DPU Timeout: Controls whether or not QLJ will enter a timeout mode if DPU has not written to QLJ for more than 3 seconds. Open = enable timeout.

Switch Pos. No. 4

Not used.

EEPROM Toggle Switch Controls access to the on-board EEPROM. If the switch is OFF, EEPROM is ignored on power-up and the configuration constants receive default values from EPROM. Also, any configuration data written to the QLJ will not be stored in EEPROM. If the switch is ON, configuration constants previously written to the QLJ (while the switch was ON) are read from EEPROM on power-up and any new configuration data written to the QLJ will be stored in EEPROM for the next power-up.

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3-26. QLJ

Serial Port Error Jumper Determines how the absence of a serial port is reported to the DPU. Position 1-2 installed jumper – Report serial port errors Position 2-3 installed jumper – Do not report serial port connector off as an error to the DPU. Configuration Jumper Clips Slots on the card edge connector allow insertion of jumper clips for card configuration and addressing. Choices for card configuration are as follow: Table 3-103. Configuration Jumpers State

Jumper 23

Jumper 22

Jumper 21

NORMAL

In

In

In

MASSFLOW

In

Out

In

All other configurations are invalid.

LED Indicators POWER OK -

LED is lit if proper power to the card is provided. It is ON in normal operation.

CALIBRATION - LED is lit if the card is calibrating or is initializing. It is OFF in normal operation.

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3-26. QLJ

3-26.7. Installation Data Sheet 1of 2


CARD

ANALOG OUTPUT

ANALOG INPUT 1

ANALOG INPUT 2

ANALOG INPUT 3

TERMINAL BLOCK

20B

A

20A

20

19B

19

19A

18

17B

17

17A

16

(+)

15B

15

(+)

(SHIELD)

15A

14

(SHIELD)

(−)

13B

13

(−)

(+)

13A

12

(+)

(SHIELD)

11B

11

(SHIELD)

(−)

11A

10

(−)

(+)

9B

09

(+)

(SHIELD)

9A

08

(SHIELD)

(−)

7B

07

(−)

(+)

7A

06

(+)

(SHIELD)

5B

05

(SHIELD)

(−)

5A

04

(−)

3B

03

3A

02

1B

01

ANALOG OUTPUT 1

ANALOG INPUT 1

ANALOG INPUT 2

ANALOG INPUT 3

1A

EDGE CONNECTOR

Figure 3-172. QLJ Wiring Diagram

Installation Notes (Refer to Figure 3-172) A. If inputs are to be grounded at the system end, insert a #6 screw and nut in the hole located near the shield terminal on Terminal Block A. Then add two jumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 14, & 17, have been drilled for this purpose.

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3-26. QLJ

A (+)

(+) TRANSDUCER

S (−)

(−) #6 SCREW

Figure 3-173. QLJ Ground Inputs at System End

B. If inputs are to be grounded at the signal source, ground both the (−) side of the signal and the cable shield as shown below.

A (+)

(+) TRANSDUCER

S (−)

(−)

Figure 3-174. QLJ Ground Inputs at Signal Source

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3-26. QLJ

Installation Data Sheet 2 of 2 TERMINAL BLOCK



(+) ANALOG OUTPUT

ANALOG INPUT 1

ANALOG INPUT 2

ANALOG INPUT 3

20B

A

B

20A

20

20

19B

19

19A

18

17B

17

17A

16

15B

15

19 I/O DEVICES

18 17

(+)ANALOG OUTPUT 1(−)

FUSE 1/4A

16

FUSE 1/4A

15

FUSE 1/32A

15A

14

(−)

13B

13

14

(+)

13A

12

SHIELD

11B

11

(−)

11A

10

(+)

9B

09

SHIELD

9A

08

(−)

7B

07

(+)

7A

06

SHIELD

5B

05

05

(−)

5A

04

04

3B

03

03

3A

02

02

1B

01

01

13 (−)ANALOG INPUT 1(+)

12

FUSE 1/32A


09

FUSE 1/32A


06

FUSE 1/32A

1A

EDGE-CONNECTOR


Figure 3-175. QLJ Fused Half-Shell Extension Wiring

Installation Notes (Refer to Figure 3-175) 1. Jumper 1A - 3B is connected only for QLJ’s sub D and later. For earlier versions, this jumper should be added. 2. Analog input devices should be connected with shielded twisted pair cables. Shield drains and negatives from QLJ must be connected to DC power return. 3. DC power return must be grounded. 4. Jumpers between terminal block screws 3, 4, 5, 7, 8, 10, and 11 must be added.

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3-27. LIM

3-27. LIM Loop Interface Module (Style 1D54561G01 through G02)

3-27.1. Description The Loop Interface Module (LIM) provides the displays, keyboards inputs, and accompanying logic needed for the operator to monitor and control the I/O functions of a QLI (Q-Line Loop Interface). Information is presented to the operator by various bargraphs, LEDs, numeric displays and alphanumeric displays on the front panel of the LIM. The keyboard allows the operator to send control information to the QLI to control the process (see Figure 3-176).

Figure 3-176. Loop Interface Module

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3-27. LIM

Keyboard Interface

Bargraph Display

MicroProcessor

7 Display Controller

1

Status Leds 8

6 Numeric Display Serial Port Input/ Output

To/from Qli

9

Alpha Numeric Display

2

10 Timing And Control

4

3

From User Supply

User Power Interface

Power Ok To All Components

5

Figure 3-177. LIM Functional Block Diagram

3-27.2. Features Through keys on the front of the LIM panel, the operator has the following capabilities:

• • • • • • • • • M0-0053

Raise output Lower output Raise setpoint Lower setpoint Change LIM mode (Group 1 only) Change alphanumeric and numeric displays Change to different QLI (with different loop number) (Group 1 only) Change QLI mode to Cascade (Group 1 only) Change QLI mode to Auto


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3-27. LIM

• • •

Change QLI mode to Manual Change QLI mode to Local Change QLI tuning constants (Group 1 only)

Additional information on the installation and use of the LIM can be found in “Q-Line Loop Interface Card and Loop Interface Module (QLI/LIM) User’s Guide” (NLAM-B200).

Additional Features

•

Runs bargraphs, LEDs, and alphanumeric and numeric displays to monitor QLI I/O activities.

• • •

Scans keypad to control QLIs

• • • •

Sends and receives information to and from the QLI through a serial port.

Monitors and communicates with up to 12 QLIs Group 1 LIMs operate in four modes: CONTROL, MONITOR, TUNING, LOOP. Group 2 operates in CONTROL mode only.

Flags a break in the communication link with the QLI Allows loop control even if DPU is down Displays: two 40-segment bargraphs one 30-segment bargraph one 4-digit numeric one 4-digit alphanumeric thirteen status LEDs

•

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Control keys:


M0-0053

3-27. LIM

four keys to raise and lower setpoint and outputs seven function keys

Groups The LIM card is packaged in one of two assemblies (see Figure 3-178). The card is the same for both assemblies, although the PROMs will have been burned differently. They keyboards are the same except Group 2 does not have the LOOP, CASC, and MODE buttons. Group 1

Allows the operator to choose from among four modes of operation for the LIM and four for the QLI.

Group 2

Offers no choice of modes for the LIM; it always operates in the CONTROL mode. Offers three choices of operation of the QLI.

The four modes of operation for the LIM are as follows:

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CONTROL MODE:

Allows the operator to send control information to the QLI through a keyboard; displays the process variable, the setpoint, and output value for the QLI on a bargraph, and displays PV, SP, or OUT with proper engineering units on an alphanumeric display.

MONITOR MODE: (Group 1 only)

Displays the process variable, the setpoint, and output values for the QLI on a bargraph and displays the analog input values on an alphanumeric display.

TUNING MODE: (Group 1 only)

Displays the gain, reset, rate, and derivative gain values for the QLI it is communicating with and enables the operator to change the values. Requires a password.

LOOP MODE: (Group 1 only)

Displays the Loop Number of the QLI the LIM is currently communicating with and allows the operator to change to another QLI.


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3-27. LIM

DISP

LOOP

MODE

CASC

DISP

AUTO

AUTO

MAN

MAN

LOC

LOC

GROUP 1

GROUP 2

Figure 3-178. Keyboards for Group 1 and Group 2 LIMs

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3-27. LIM

3-27.3. Specifications Power cables to the LIM must be single stranded #16 AWG copper conductors with ring lugs on both ends. Power required at the black terminal block of the LIM is 1.5A at 12 VDC (see Table 3-104). No shielding is required. A backup power supply is optional.

+12V A (8) +12V B Signal “-” Signal “-”

(1)

Serial Port

Figure 3-179. LIM Wiring Table 3-104. LIM Power Card-Edge Terminal Block Connector

Component Side Pin

Description

1

Chassis (Earth) Ground

2


3


4


5

Signal (“–”)

6

Signal (“–”)

7

+12V B

8

+12V A

In installations with more than one LIM, each LIM should have its own pair of conductors directly from the power supply. If LIMs are connected in parallel, conductors must be able to accommodate the total current requirement for all LIMs; voltage must measure 12 VDC at the last LIM in the line.

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3-27. LIM

3-27.4. Circuit Description The LIM card contains the logic to send and receive information from the QLI to allow the operator to monitor and control the QLI’s I/O activities. The operator can monitor the activities on three bargraphs, a 4-digit numeric display, a 4-character alphanumeric display, and 13 status LEDs. The I/O activities can be controlled through an 11-key keyboard for Group 1 assemblies or an 11-key keyboard for Group 2 assemblies.

3-27.5. Components A functional block diagram of the LIM card is shown in Figure 3-177. 1. Keyboard Interface: Allows the operator to control the I/O activities of the QLI. 2. Serial Port (see Table 3-105): Receives display and status data from the QLI. Also sends operator inputs from the keyboard to the QLI. Can communicate with only one QLI at a time. The LIM must enter Loop Mode to change the QLI with which it is communicating. Table 3-105. LIM Serial Port Card-Edge Connector

Component Side Pin

Description

1

Transmit +

2

Transmit −

3

Shield (Signal Ground)

4

Receive +

5

Receive −

6 through 10

Not Used

3. Timing and Control: Generates the signals needed to coordinate the serial port, keyboard scans, displays, and microprocessor. Based on a 11.0592-MHz-clock. 4. Microprocessor: Scans the keyboard and determines what action (if any) should be taken, formats outgoing serial port messages, interprets incoming serial port messages, and maintains the various displays. 5. User Power Interface: Provides the regulated voltages needed by the logic circuitry and provides the POWER OK signal for the microprocessor. Also provides the voltages needed by the various displays.

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3-27. LIM

6. Display Controller: Provides multiplexing control for the status LEDs, bargraphs, and the numeric display. The alphanumeric display has its own multiplexing circuitry. 7. Bargraph Displays: Can display either the setpoint, process variable, and output values. The setpoint and process variable are on 40-segment bargraphs, the output is on a 30-segment bargraph. 8. Status LEDs: Thirteen status LEDs display the LIM mode, the QLI mode, which value is currently being displayed by the numeric display, and high-limit and low-limit alarm conditions. 9. Numeric Displays: Shows a numeric value for the setpoint, output, process variable, or analog inputs. This value will be scaled to the appropriate engineering units for the value of the numeric display. 10. Alphanumeric Display: Can give the name of the engineering units for the value of the numeric display, or can give status or mode information.

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3-28. SLIM

3-28. SLIM Small Lop Interface Module (Style 4D33741G01 through G02)

3-28.1. Description Applicable for use in the CE MARK Certified System The Small Loop Interface Module (SLIM) provides the displays, keyboards inputs, and accompanying logic needed for the operator to monitor and control the I/O functions of a QLI (Q-Line Loop Interface). Information is presented to the operator by various bargraphs, LEDs, numeric displays and alphanumeric displays on the front panel of the SLIM. The keyboard allows the operator to send control information to the QLI to control the process (see Figure 3-180).

WDPF II

PV

SP

Out

Reject to Local

100 Disp 80

60 Auto SP/Bias 40

Man

Loc

20 Out

SLIM Enclosure 0

0 20

40

60

80

100

SLIM

Figure 3-180. SLIM Small Loop Interface Module

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3-28. SLIM

Block Diagram Keyboard Interface

Bargraph Display

MicroProcessor

7 Display Controller

1

Status Leds 8

6 Numeric Display Serial Port Input/ Output

To/from QLI

9

Alpha Numeric Display

2

10 Timing And Control

4

3 From User Supply

User Power Interface

Power Ok To All Components

5

Figure 3-181. SLIM Functional Block Diagram

3-28.2. Features Through keys on the front of the SLIM panel, the operator has the following capabilities:

• • • • • • • •

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Raise output Lower output Raise setpoint Lower setpoint Change SLIM mode (Group 1 only) Change alphanumeric and numeric displays Change to different QLI (with different loop number) (Group 1 only) Change QLI mode to Cascade (Group 1 only)


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3-28. SLIM

• • • •

Change QLI mode to Auto Change QLI mode to Manual Change QLI mode to Local Change QLI turning constants (Group 1 only)

Additional information on the installation and use of the SLIM can be found in “Q-Line Loop Interface Card and Loop Interface Module (QLI/LIM) User’s Guide” (NLAM-B200).

•

Runs bargraphs, LEDs, and alphanumeric and numeric displays to monitor QLI I/O activities.

• • •

Scans keypad to control QLIs

• • • •

Sends and receives information to and from the QLI through a serial port.

Monitors and communicates with up to 12 QLIs Group 1 SLIMs operate in four modes: CONTROL, MONITOR, TUNING, LOOP. Group 2 operates in CONTROL mode only.

Flags a break in the communication link with the QLI Allows loop control even if DPU is down Displays: two 40-segment bargraphs one 30-segment bargraph one 4-digit numeric one 4-digit alphanumeric thirteen status LEDs

•

Control keys: four keys to raise and lower setpoint and outputs seven function keys

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3-28. SLIM

Groups The SLIM card is packaged in one of the two assemblies (see Figure 3-178). The card is the same for both assemblies, although the PROMs will have been burned differently. They keyboards are the same except Group 2 does not have the LOOP, CASC, and MODE buttons. Group 1

Allows the operator to choose from among four modes of operation for the SLIM and four for the QLI.

Group 2

Offers no choice of modes for the SLIM; it always operates in the CONTROL mode. Offers three choices of operation of the QLI.

The four modes of operation for the SLIM are as follows:

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CONTROL MODE:

Allows the operator to send control information to the QLI through a keyboard; displays the process variable, the setpoint, and output value for the QLI on a bargraph, and displays PV, SP, or OUT with proper engineering units on an alphanumeric display.

MONITOR MODE: (Group 1 only)

Displays the process variable, the setpoint, and output values for the QLI on a bargraph and displays the analog input values on an alphanumeric display.

TUNING MODE: (Group 1 only)

Displays the gain, reset, rate, and derivative gain values for the QLI it is communicating with and enables the operator to change the values. Requires a password.

LOOP MODE: (Group 1 only)

Displays the Loop Number of the QLI the SLIM is currently communicating with and allows the operator to change to another QLI.


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3-28. SLIM

WDPF II AI1

AI2

AI3

PV SP 100

Out

WDPF II

PV

Reject to Local

Disp

Loop

Mode

M C T

80

SP 100

Out

Reject to Local

Disp 80 Casc

60

60 Auto

Auto SP/Bias 40

20

SP/Bias Man

40

Man

Loc

20

Loc

Out

0

0 20

40

60

Out

80

100

0

0 20

40

60

80

100

Figure 3-182. Keyboards for Group 1 and Group 2 SLIMs

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3-28. SLIM

3-28.3. Specifications Power cables to the SLIM must be single stranded #16 AWG copper conductors with ring lugs on both ends. Power required at the black terminal block of the SLIM is 0.5A at 12 VDC (see Figure 3-183). No shielding is required. A backup power supply is optional.

+12A +12B RTN RTN

Serial Port

Figure 3-183. SLIM Wiring

In installations with more than one SLIM, each SLIM should have its own pair of conductors directly from the power supply. If SLIMs are connected in parallel, conductors must be able to accommodate the total current requirement for all SLIMs; voltage must measure 12 VDC at the last SLIM in the line.

3-28.4. Circuit Description The SLIM card contains the logic to send and receive information from the QLI to allow the operator to monitor and control the QLI’s I/O activities. The operator can monitor the activities on three bargraphs, a 4-digit numeric display, a 4-character alphanumeric display, and 13 status LEDs. The I/O activities can be controlled through an 11-key keyboard for Group 1 assemblies or an 11-key keyboard for Group 2 assemblies.

3-28.5. Components A functional block diagram of the SLIM card is shown in Figure 3-181. 1. Keyboard Interface: Allows the operator to control the I/O activities of the QLI.

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3-28. SLIM

2. Serial Port (see Table 3-106): Receives display and status data from the QLI. Also sends operator inputs from the keyboard to the QLI. Can communicate with only one QLI at a time. The SLIM must enter Loop Mode to change the QLI with which it is communicating. Table 3-106. SLIM Serial Port Card-Edge Connector

Component Side Pin

Description

1

Transmit +

2

Transmit −

3

Shield (Signal Ground)

4

Receive +

5

Receive −

6 through 10

Not Used

3. Timing and Control: Generates the signals needed to coordinate the serial port, keyboard scans, displays, and microprocessor. Based on a 11.0592-MHz-clock. 4. Microprocessor: Scans the keyboard and determines what action (if any) should be taken, formats outgoing serial port messages, interprets incoming serial port messages, and maintains the various displays. 5. User Power Interface: Provides the regulated voltages needed by the logic circuitry and provides the POWER OK signal for the microprocessor. Also provides the voltages needed by the various displays. 6. Display Controller: Provides multiplexing control for the status LEDs, bargraphs, and the numeric display. The alphanumeric display has its own multiplexing circuitry. 7. Bargraph Displays: Can display the setpoint, process variable, or output values. The setpoint and process variable are on 30-segment bargraphs, the output is on a 20-segment bargraph. 8. Status LEDs: Thirteen status LEDs display the SLIM mode, the QLI mode, which value is currently being displayed by the numeric display, and high-limit and low-limit alarm conditions. 9. Numeric Displays: Shows a numeric value for the setpoint, output, process variable, or analog inputs. This value will be scaled to the appropriate engineering units for the value of the numeric display. 10. Alphanumeric Display: Can give the name of the engineering units for the value of the numeric display, or can give status or mode information.

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3-28. SLIM

SLIM use in the CE MARK Certified System The SLIM is applicable for use in the CE MARK certified system. The following rules apply:

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•

A transition panel kit (Westinghouse drawing number 3A59353) is used inside the DPU to provide an earth grounding point for the shields of the QLI/SLIM cable (Westinghouse drawing number 5A26130) and the internal QLI transition panel cable (Westinghouse drawing number 5A26127).

•

Cable 5A26130 (SLIM to transition panel) provides the connection between the SLIM and the transition panel. It is connected to (internal) cable 5A26127.

•

Cable 5A26127 (QLI/SLIM transition panel) provides the connection from the transition panel to the QLI. It is connected to cable 5A26130.


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3-29. QMT

3-29. QMT M-Bus Terminator Card (Style 7379A79G01 through G03)

3-29.1. Description The QMT card provides a variety of support functions for the Q-line Memory Bus (M-bus) and Distributed Input/Output Bus (DIOB) (see Figure 3-184). The QMT card is available in three design groups (G01, G02, and G03).

DIOB

120Ω Terminators Bus Discharge and Clamp

Read, Write, and DMA Interrupt Recovery

On-Card Power Supplies

Dead Computer Recovery

UIOB or DIOB Power Status Monitor

Power Supply Monitor

Optional Q-line M-bus DIOB Bus Extension

Figure 3-184. QMT Block Diagram

3-29.2. Features All QMT cards (G03, G02, and G01) provide the following Q-line support functions:

•

Voltage threshold selection for the following power supplies: — +V Primary (+13V)

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3-29. QMT

— +V Backup (+13V)

• • •

All DIOB signals are diode clamped to +15 VDC and 0 VDC DIOB extension through two front-edge connector Two form-C, dry-circuit relays indicating primary and secondary DIOB power status

The G02 QMT cards add the following Q-line support functions:

•

Voltage threshold detection for the following power supplies: — +12 Auctioneered (+12 VDC) — +5 Internal (+5 VDC) — +15 (+15 VDC DIOB clamp supply)

•

DIOB discharge

The G01 QMT cards include all of the G02 functions and add the following Q-line support functions:

• • •

120 Ω termination to +5 VDC for 33 M-bus signals +5 VDC at 2A for microcomputer termination and bus transceiver power Voltage threshold detection for the following power supply: — +5T (M-bus) (+5 VDC)

•

Time-out detection and recovery for the following M-bus conditions: — Missing READY on READ cycle — Missing READY on WRITE cycle — Incomplete Direct Memory Access (DMA) cycle — Missing READY on INTERRUPT OPCODE cycle — “Dead Computer” reset (optional) — Sequence fault (READY•REL↑) — All DIOB signals are diode clamped to +15 VDC and 0 VDC

The QMT card is designed to be installed in a standard Q-line card cage in the vertical position and it occupies card slot number 25 in all M-bus card cages.

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3-29. QMT

Block Diagram

J1 CONNECTOR (DIOB)

J3 CONNECTOR DIOB EXTENSION (WITHOUT POWER)

DIOB DISCHARGE AND CLAMP

J4 CONNECTOR

MBUS TERMINATION (120 Ω 5 V) J2 CONNECTOR (M-BUS)

READ WRITE DMA INTERRUPT RECOVERY

+5 VDC AT 2A

DEAD COMPUTER RECOVERY

POWER SUPPLY MONITOR

INTERNAL LOGIC (VCC) POWER SUPPLY J5 CONNECTOR

+5 VDC AT 2A

M-BUS TERMINATION POWER SUPPLY

+15 VDC AT 10 MA

DIOB CLAMP POWER SUPPLY

CHASSIS POWER MONITOR RELAYS

Figure 3-185. QMT Card Functional Block Diagram

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3-29. QMT

Power Requirements

Minimum

Nominal

Maximum

Primary Voltage

12.4 VDC

+ 13.0 VDC

13.1 VDC

Backup

12.4 VDC

--

13.1 VDC

Current

2A

3A

Power Consumption

26 watts

39.3 watts

Signal Interface The QMT card interfaces with the Q-line system through five electrical connectors. The connector names and locations are shown in Figure 3-186. Descriptions of individual connector functions are provided following Figure 3-186:

J5

J1

J3

J2

J4

Figure 3-186. QMT Card Connectors

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•

J1 Connector: The J1 connector is a 34-pin DIOB signal interface to the QMT card. The J1 connector plugs into the backplane of a standard 19 inch Q-line card cage.

•

J2 Connector: The J2 connector is a 50-pin M-bus signal interface to the QMT card. The J2 connector plugs into the backplane of a standard 19 inch, Q-line card cage.


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3-29. QMT

•

J3 and J4 Connectors: The J3 and J4 34-pin connectors are used to extend the DIOB signals to other card crates. Female front-edge connectors with flat-flex ribbon cable are used to transfer the DIOB signals.

•

J5 Connector: The J5 connector is a 9-pin connector that is used as an application interface for the QMT card power monitor relays. The J5 connector is a board mounted connector that transfers the relay signals to any desired location. Table 3-107 shows the pin connections and signal names for the J5 connector.

Table 3-107. QMT J5 (Power Monitor Relay) Pin Connections and Signal Names

Pin No.

Signal Name

1

PCOM

2

BCOM

3

+12 AX

4

BNC

5

GROUND

6

PNO

7

BNO

8

PNC

9

(Not Connected)

3-29.3. Input/Output Signal Requirements M-bus signals: Complies with M-bus interface requirements DIOB signals: Complies with DIOB interface requirements

Fuses The QMT card uses six fuses for over current protection. Table 3-108 shows the name, rating and function of each fuse. Table 3-108. QMT Card Fuse Ratings and Locations

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Fuse Name

Rating (Amperes)

Function

M192-1

1

+12V Auctioneered Out to J5-3

M196-1

2

+5T Power Supply Output

M196-2

2

+5 Power Supply Output


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3-29. QMT

Table 3-108. QMT Card Fuse Ratings and Locations

Fuse Name

Rating (Amperes)

Function

M272-1

3

+12 Auctioneered Main Input

H60-1

.25

+V Primary Comparator Input

H60-2

.25

+V Backup Comparator Input

Wiring Electrical connection to the Q-line system is made by two backplane plug-in connectors (J1 and J2), two front-edge connectors (J3 and J4) and a side mounted (component side) connector (J5) (see Figure 3-186). The J1 and J2 connectors are, respectively, the DIOB and M-bus connectors while the J3 and J4 connectors provide for DIOB cable extension. The J5 connector provides connection to the primary and backup power monitor relay contacts.

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3-30. QPA

3-30. QPA Pulse Accumulator (Style 7379A13G01 through G04)

3-30.1. Description Groups 01 through 04 are Applicable for use in the CE MARK Certified System The QPA card accumulates the pulse inputs that are normally counted by the system controller. This configuration allows the system controller to perform other control and data acquisition tasks and permits higher rates of pulse inputs. These pulse inputs may originate from devices such as position encoders, tachometers and flow-rate meters. The QPA performs average speed measurements, average inverse speed measurements, elapsed time measurements and speed ratio measurements (see Figure 3-187).

DIOB

Data

Data

2:1 MUX

Register MSB

G04 Only

Latch

DIOB Data

Compare 2:1 MUX Latch Control Up/Down Counter

Up/Down Counter

Status Read

PHA Field Control Logic

PHA Status

PHB

Field Clock Inputs

PHB

Field Clock Field Control Inputs Inputs

Figure 3-187. QPA Block Diagram

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3-30. QPA

The QPA interfaces with the Distributed Input Output Bus (DIOB) through a rear-edge connector, J1. Ten field inputs are brought onto the card via a front-edge connector, J3. A 25-pin “D” type connector is located on the top front-edge of the card (J2). The J2 connector is used to interface QPA comparator register output signals to QPA counter control inputs. It also permits various options to be selected.

3-30.2. Definitions Frozen – This signal indicates that the counter is still counting, but the last counter value before freezing is stored in the latch that is read by the DIOB. FLAG – This signal is set by an exact comparison of the counter and the compare register. It is reset by a power-up or a status read command. Compare – This signal is active only when a comparison is valid. It will deactivate on the next counter clock, counter reset or write command to the compare register. Running – This signal indicates that the counter has been enabled to recognize clock inputs and may increment/decrement accordingly. Its state is affected by the START and STOP inputs and the START/STOP bit in the command word. Snap-Shot – This signal takes an instantaneous sample of the counter’s value by unfreezing the bus input latch, then immediately refreezing it. By insertion of a jumper from a J2 connector pin, RESET OPTION, to one of its ground pins, counter reset will immediately follow the snap-shot of the counter value. DIOB – (DISTRIBUTED INPUT/OUTPUT BUS) – This bus interfaces Q-Line I/O point cards to a multiplexing bus controller and permits a byte-oriented digital exchange of information between the bus controller and the point cards. The data, address and control signals on the DIOB are twelve volt CMOS logic level signals. The DIOB also supplies power to the Q-Line point cards.

3-30.3. Features There are four QPA card groups available. The G01 through G04 QPA cards contain two separate counter/comparators circuits. The pulse inputs (process or time base) are fed into one of two counter/comparators. Each counter/comparator consists of a 15-bit bidirectional counter, a start/stop bit, a snap-shot bit, and a comparator. The counter’s value may be read at any time and the comparator’s output is available to the bus as status. For the G01 through G03 cards, both counters may be reset to zero, started or stopped, and snap-shot or released from snap-shot by a command word. The command may be sent to one specific card (jumper selected address) or to many cards (jumper selected group address). Group addressing gives the system the ability to perform a plant snap-shot. Groups are described below:

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3-30. QPA

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•

G01 provides Phase A and Phase B inputs that are optically coupled, +48 VDC differential voltage inputs that employ on-card digital filtering (Figure 3-188). The SNAP-SHOT, START, and STOP inputs are single-ended, 48 VDC, optically coupled inputs with digital filters (identical to that of Phase A and Phase B inputs). The common return line may be tied to a positive or negative polarity (+48 VDC). See Figure 3-189.

•

G02 provides Phase A and Phase B inputs that are optically coupled, +5 VDC differential inputs (with no filtering). The clock plus input should be tied to a +5 VDC +5% voltage source and the clock minus input to the output of a +5 VDC line driver. The line driver must be capable of sinking 40 mA while maintaining an output voltage (VOL) of +0.5 VDC or less. See Figure 3-190 and Figure 3191. The SNAP-SHOT, START and STOP inputs are +48 VDC, single-ended inputs as stated in G01. See Figure 3-189.

•

G03 provides Phase A and Phase B inputs that are +5 VDC differential inputs as described in G02. The control inputs of SNAP-SHOT, START and STOP are +5 VDC, single-ended, optically-coupled inputs without filtering. The common return line must be tied to +5 VDC +5% voltage source. See Figure 3-192.

•

G04 provides Phase A and Phase B inputs that are identical to Group one inputs (Figure 3-188). The control signals and the J2 connector are absent.


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Two methods of wiring the contact wetting voltage supply to the field contacts and the QPA clock inputs are shown.

Field Contacts

Field Contacts

Contact Wetting Voltage Supply

Each clock signal should be transmitted over a twisted conductor pair as shown. The cable containing the twisted pair should only carry QPA field signals. An outer shield should surround all the cable’s twisted pair conductors.

- + PH(+)

PH(-)

PH(-)

Contact Wetting Voltage Supply

48VDC

PH(+)

+

48VDC

QPA Group One or Four

Clock Inputs

PH.B0(+),PH.B0(-)

PH.A0(+),PH.A0(-)

PH.B1(+),PH.B1(-)

PH.A1(+),PH.A1(-)

3-30. QPA

Figure 3-188. QPA +48 VDC Clock Input Signal Wiring (G01, G04)

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3-30. QPA

Figure 3-189. QPA Control Signal (+48 VDC) Input Wiring (G01, G02)

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+5VDC ±5%

3-30. QPA

Figure 3-190. QPA +5 VDC Clock Input Signal Wiring (G02, G03)

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QPA-4

QPA-4

+5VDC ±5%

3-30. QPA

Figure 3-191. QPA Clock Signal Wiring (Differential Line Driver) G02 and G03

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THE OPEN COLLECTOR TRANSISTOR MAY BE REPLACED BY TTL OPEN COLLECTOR GATES OR STANDARD TTL GATES CAPABLE OF SINKING 16 MA OR CURRENT

+ 5 VOLTS D.C. +5%

SINGLE ENDED INPUTS

WIRING IS RESTRICTED TO WITHIN THE CABINET IN WHICH THE QPA IS LOCATED.

QPA CONTROL INPUTS START 0, 1 STOP 0,1 SNAPSHOT 0,1

COMMON

CONTROL INPUT

J3 CONNECTOR

QPA GROUP THREE

3-30. QPA

Figure 3-192. QPA +5 VDC Control Input Wiring (G03)

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3-30. QPA

3-30.4. Specifications A functional block diagram of the QPA card is shown in Figure 3-193. The counter/ comparator is shown in Figure 3-194 and Figure 3-195. .

J1 Bus Interface

Counter/Comparator #1 (CC1)

J2 (G01,2,3)

25 pin “D” Connector

Power On 1 MHz Osc. Time Base

Counter/Comparator #0 (CC0)

Field Signals from Terminal Block

Figure 3-193. QPA Functional Block Diagram

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3-30. QPA

DIOB 1

“FLAG”

UFLAG

P.U.

8

UFLAG R STATUS

Q

FLAG

DATA

READ

RESET ON P.U.

REGISTER S

COMPARE

15

MSB

AND

DIRECTION BIT (1=DOWN)

(=)

COMPARE

CLOCK SELECT

MSB 15

TIME BASE

8 DATA

UP/DOWN COUNTER

START

OR

START

S

R

OR

BUS COMMAND P.U.

AND

Q

STOP

RESET

COUNT

X4

“RUNNING”

STOP BUS COMMAND

SNAP-SHOT OROR

FREEZE

MUX 4:1 BUS COMMAND OR P.U.

RESET OPTION

MUX 2:1

BUS COMMAND

100 KHZ 10 KHZ

ENABLE

External Clocks

L A T C H

15

HIGH SPEED

Internal Timebase + PHB − + PHA −

15

S LOGIC

“FROZEN” Q

R

SNAP-SHOT SNAP-SHOT BUS COMMAND OR P.U.

LEGEND J3 CONNECTION J2 CONNECTION P.U. = POWER UP

UNFREEZE LATCH, THEN FREEZE LATCH. RESET COUNTER IF RESET OPTION INPUT IS GROUNDED.

= STATUS BIT = OPTICAL ISOLATION

Figure 3-194. QPA Card Counter/Comparator (1 of 2) (G01, 2, 3)

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3-30. QPA

DIOB

DIRECTION BIT

MSB

L A T C H

15

PHB +

MUX 2:1

8

DATA

(DIRECTION)

EXTERNAL CLOCKS CLOCK

PHA +

R

UP/DOWN COUNTER

(X1)

CE BUS COMMAND OR P.U. S

BUS COMMAND

Q

OR P.U. BUS COMMAND

R BUS COMMAND

“RUNNING” S Q

“FROZEN”

R BUS COMMAND OR P.U. LEGEND J3 CONNECTION P.U. = POWER UP = STATUS BIT = OPTICAL ISOLATION

Figure 3-195. QPA Card Counter/Comparator (2 of 2) (G04)

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3-30. QPA

Internal Timebase Clocks and External Inputs’ Digital Filter Clock Frequency Internal Low Speed Time Base Clock

10 kHz + 1%

Internal High Speed Time Base Clock

100 kHz + 1% 1.953 kHz + 2%

Digital Filter Clock

Vin is measured directly across the QPA input pins for external clock inputs (see Table 3-109). Vin is measured directly between the specified QPA input pin and the common return pin for control inputs. Iin is the current measured at the QPA input pin that flows into the input circuit. Table 3-109. QPA Field Signal (J3) Specifications

VDC

mA(DC)

External Phase A & Phase B

Vin OFF

Clock Inputs

Max.

Min.

Nom.

Max.

Max.

Min.

Nom.

Max

G01, 4

2.0

40

48

60

0.35

8.0

11.9

15.25

G02, 3

0.8

3.9

–

5.0

3.0

25.0

–

42.0

G01, 2

2.0

40

48

60

0.35

8.5

11.7

16.6

G03

0.7

4.1

–

5.3

0.2

8.3

–

15.45

Vin ON

Iin OFF

Iin ON

Control Inputs

QPA field input voltages equal to or less than the maximum OFF voltage will guarantee a logic zero to be transferred to the QPA logic circuitry via the optical isolator. QPA field input voltages equal to or greater than the minimum ON voltage will guarantee a logic one to be transferred to the QPA logic circuitry via the optical isolator.

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3-30. QPA

Iin OFF (MAX) is the maximum leakage current allowed to flow into a QPA field input (J3) that still ensures that a logic zero will be transferred to the QPA logic circuitry via the optical isolator (see Table 3-110). When Vin OFF(MAX) is applied to a QPA field input, the resulting input current may exceed Iin OFF (MAX) but the input current will still transfer a logic zero to the logic circuitry. IinOFF may be due to driver/cable leakage or coupling capacitance between cables. Table 3-110. Field Signal Times (J3)

msec External Clock On Time Inputs (Min.)

Off Time (Min)

msec

Max. Count Rate CLKX1 CLKX41

Digital Filter Delay Min.

Nom.

Max.

G01, 4

2.5

2.5

200 kHz

800 kHz

1.7

2.0

2.36

G02, 3

0.005

0.005

100 kHz

400 kHz

–

None

–

G01, 2

2.5

2.5

–

–

1.7

2.0

2.36

G03

0.1

0.1

–

–

–

None

–

Control Inputs

1

Assumes a two-phase (quadrature) input clock. The maximum clock frequencies are still 200 KHz for G01 and G04 or 100 KHz for G02 and G03.

Power Supply Voltage (VDC) Minimum

Nominal

Maximum

+12.4

+13.0

+13.1

Primary Voltage:

Current: 100 mA (max), limited with a 0.5 Amp fuse

3-30.5. Addressing and Field Pins J2 Connector signals (Figure 3-196)

•

5/99

INPUTS: the TIME BASE, HIGH SPEED and RESET OPTION are select lines which may be tied to ground at the connector or left open (inactive). The START, STOP and SNAP-SHOT inputs may be tied to a QPA output (COMPARE) or left open (inactive). SNAP-SHOT is available on two separate pins to aid in daisy chaining. See Figure 3-196 for pin locations of J2. The UFLAG (pin #1) of the J2 connector is tied directly to the QPA card-DIOB pin 30 (UFLAG).


M0-0053

3-30. QPA

•

OUTPUTS: The COMPARE output may be used to drive the QPA inputs described in the above section. FLAG is an open collector output which may be wired into an interrupt subsystem or similar receiver. To clear the FLAG, a status read should be part of an interrupt service routine. The FLAG output may also be used to drive the UFLAG input if the DIOB Controller uses UFLAG.

FLAG0 TIME-BASE0 HIGH-SPEED0 RESET-OPTION0 START0 STOP0 FLAG1 TIME-BASE1 HIGH-SPEED1 RESET-OPTION1 START1 STOP1 DIOB UFLAG

13 12 11 10 9 8 7 6 5 4 3 2 1

25 24 23 22 21 20 19 18 17 16 15 14

COMPARE0 GND GND

Counter/Comparator 0

GND SNAP-SHOT0 SNAP-SHOT0 COMPARE1 GND GND

Counter/Comparator 1

GND SNAP-SHOT1 SNAP-SHOT1

4260A10G02

Figure 3-196. QPA J2 Pin Connector (G01, 2 and 3) (Front View)

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3-30. QPA

J3 Connector Signals (Figure 3-197)

•

CONTROL INPUTS: THE SNAP-SHOT, STOP and START inputs may be either the +48 volt wetted contacts (external supply required) type or the +5 volt TTL current sinking type. The selection is to be by group. Each of the six signals will be single wire sharing a common with the other five inputs (see Figure 3-197).

(SLOT) PHB1 (+)

17B 17A

PHB1 (−)

PHA1 (+)

15B 15A

PHA1 (−)

13B

(OPEN)

POINT 1 SNAP-SHOT 1

START1 11B 11A

STOP1

PHB0 (+)

9B 9A

PHB0 (−)

PHA0 (+)

7B 7A

PHA0 (−)

5B

(OPEN)

START 0

3B 3A

STOP 0

CONTROL RETURN

1B 1A

CONTROL RETURN

(GROUPS 1, 2, 3, ONLY) POINT 0 SNAP-SHOT 0

0 404A037H01 (CARD EDGE)

A = CIRCUIT SIDE B = COMP. SIDE

Figure 3-197. QPA J3 Pin Connector (G01, 2, 3, and 4) (Front View)

•

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CLOCK INPUTS: Phase A and Phase B are both two wire inputs with either +48 volt wetted contacts (external supply required) or +5 VDC line driver compatible.


M0-0053

3-30. QPA

QPA card connectors are shown in Figure 3-198. Table 3-111 shows the clock select jumper connections (see Figure 3-196).

J1

Power On LED

J2

J3

Figure 3-198. QPA Card Connectors

Table 3-111. QPA Clock Select Jumper Connections

Jumper

Counter Clock

TIMEBASE

HIGH SPEED

N

N

1 count per external clock cycle*

N

J

4 counts per external clock cycle**

J

N

1 count per 100 µs (internal 10kHz timebase)

J

J

1 count per 10 µs (internal 100kHz timebase)

J = Jumper Inserted; N = No Jumper *When the X1 external clock is selected, a one or two phase clock may be used. If Phase B is left open, the counter will only up-count. **If the X4 clock is selected, a two-phase clock must be used.

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3-30. QPA

DIOB Addressing and Field Pins A QPA card occupies four successive DIOB addresses (Figure 3-199). The lowest of the four DIOB addresses (XX) is occupied by the Counter/Comparator 0 word while the next higher DIOB address (XX + 1) is occupied by Counter Comparator 1 word. A DIOB write operation is performed to one of the two comparator registers, where a double type operation is required. The two upper QPA DIOB addresses (which address four data bytes) are used to address the QPA card Status or Command byte (Figure 3-199). Either of the upper or lower bytes of the QPA addresses (XX + 2, XX + 3) may be read to obtain the QPA status byte. If double byte DIOB Read operations are required, the Status byte appears in the lower data byte and is repeated in the upper data byte. If single byte data transfers are used, the card command byte may be written into the upper or lower byte of the QPA addresses (XX + 2, XX + 3). When double byte data transfers are used, the Command byte must be in the lower data byte and be repeated in the upper data byte. Refer to Figure 3-200 for QPA Data Formats, Figure 3-201 for Card Address Bit Positions and Figure 3-202 for Card Address Selection.

DIOB ADDRESS

HIGH BYTE

LOW BYTE

XX16

COUNTER 0 WORD OR COMPARATOR 0 WORD (XX + 1)16

COUNTER1 WORD OR COMPARATOR1 WORD (XX + 2)16

COMMAND BYTE OR STATUS BYTE




(XX + 3)16

Figure 3-199. QPA Card Address Format

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M0-0053

3-30. QPA

High Byte

Low Byte

D LSB

MSB

Input Data from QPA (Read Counter)

15 Bit Counter Value D= Direction Bit: 0 = Last Count Was Up 1 = Last Count Was Down -AHigh Byte

Low Byte

Output Data to QPA (Set Comparator)

E LSB

MSB 15 Bit Comparator E= Enable Bit: 0 = Comparator Disarmed 1 = Comparator Armed -BMSB

High Byte

X

Counter 1

Low Byte

X

X

LSB Input Data from QPA (Read Status Byte(S))

X

Flag 1 Running 1 Frozen 1

Counter 0

Flag 0 Running 0 Frozen 0

-CMSB

High Byte X

Counter 1

Low Byte X

X

X

LSB Output Data to QPA (Write Command Byte(S))

Reset 1 Start/Stop 1 Freeze/Unfreeze 1

Counter 0

Reset 0 Start/Stop 0 Freeze/Unfreeze 0 X = Don’t Care

-D-

Figure 3-200. QPA Card Data Format

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3-30. QPA

UADD2-7

UADD1

UADD0

HI-LO

0

0

0

0

0

1

0

1

0

0

1

1

1

X

X

Card DIOB Address* (CA2-CA7)

**111111

S2

S1

S0

***111111

CA6

CA5

CA4

OR

Read counter 0 low byte: Write comparator 0 low byte.

OR

Read counter 0 high byte: Write comparator 0 high byte.

OR

Read counter 1 low byte: Write comparator 1 low byte.

OR

Read counter 1 high byte: Write comparator 1 high byte.

OR

Read card status byte(s) Write command byte(s)

Same Data Format

Write command byte Read flags on bits determined by CA2, CA3.

(X) = Don’t care *

The card address bits are jumper selectable on the front connector, J3. See Figure 3-202. The Pulse Accumulator Card Occupies Four Addresses In The DIOB.

**Address bits S0, S1, S2 are jumper selectable (see Figure 3-202). These bits determine the QPA’S group write byte address. *** Bits CA2 through CA6 are the card address bits described above (*). Bits CA5 and CA6 determine the QPA’s particular DIOB group read address. The DIOB group read address contains two bytes of data which contain the status of eight QPA’s flags. CA4 determines which byte (upper or lower) a QPA’s flags are located in. Bits CA2 and CA3 determine the flag bit positions within that byte. (Individual QPA cards cannot be assigned DIOB addresses FC16 to FF16). Group reads and writes are not available with Group 4 QPA’s.

Figure 3-201. QPA Card Address Selection (Example)

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M0-0053

3-30. QPA

J3 Card Edge Connector

28B, A

CA7 = 1

27B, A

CA6 = 0

26B, A

CA5 = 1

25B, A

CA4 = 1

24B, A

CA3 = 0

23B, A

CA2 = 1

22B, A

S2 = 1

21B, A

S1 = 0

20B, A

S0 = 1

Select Card DIOB Address for example. 101101XX (B416-B716)

Select Group Write Byte Address 10 High Byte 111111 FIxed

Selected by S2, S1, S0

[FE16(High Byte)] Jumper Inserted = Logic One

Figure 3-202. QPA Card Address Selection (Example)

QPA DIOB Group Read Bit Format The upper half of the DIOB address range (80-FF) is mapped into 64 Group Read bits that occupy four DIOB addresses (FC-FF; no point card may occupy these addresses) (Figure 3-203). Each Group Read bit has two successive DIOB addresses mapped into it. A QPA card occupies four successive DIOB addresses which means that two successive DIOB Group Read bits are available to each QPA card. The QPA card DIOB address determines which two Group Read bits are assigned to it. Figure 3-203 may be used to determine the bit positions of a particular QPA card’s FLAGS within the eight bytes of Group Read data (DIOB Group Read Address, high or low byte and bit positions within the particular byte). Example: Bits 0 and 1 of the low bytes of DIOB address FF16 contain the status of FLAGS 0 and 1 of QPA card that is occupying DIOB addresses E016 to E316.

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5/99 3-385

Westinghouse Proprietary Class 2C FC

9C-9F

FLAG 0 #8

BC-BF

FLAG 1 QPA

FD

FLAG 0 #16

DC-DF

FLAG 1 QPA

FE

FLAG 1 QPA FLAG 0 #24

OPEN

OPEN DIOB FF ADDRESS

6(F)

7(F) FLAG 0 #31

FLAG 1 QPA

FLAG 0 #23

FLAG 0 #15

FLAG 0 #7

98-9B

FLAG 1 QPA

B8-BB

FLAG 1 QPA

D8-DB

FLAG 1 QPA

F8-FB

4(C)

HIGH BYTE 5(D) FLAG 1 QPA

FLAG 0 #30

FLAG 0 #22

FLAG 0 #14

FLAG 0 #6

94-97

FLAG 1 QPA

B4-B7

FLAG 1 QPA

D4-D7

FLAG 1 QPA

FLAG 0 #21

FLAG 0 #13

FLAG 0 #5

90-93

FLAG 1 QPA

B0-B3

FLAG 1 QPA

D0-D3

FLAG 1 QPA

0(8) FLAG 0 #29

F0-F3

1(9)

2(A)

F4-F7

FLAG 1 QPA

3(B)

FLAG 0 #20

FLAG 0 #12

FLAG 0 #4

8C-8F

FLAG 1 QPA

AC-AF

FLAG 1 QPA

CC-CF

FLAG 1 QPA

6 FLAG 0 #28

EC-EF

FLAG 1 QPA

7

FLAG 0 #27

FLAG 0 #19

FLAG 0 #11

FLAG 0 #3

88-8B

FLAG 1 QPA

A8-AB

FLAG 1 QPA

C8-CB

FLAG 1 QPA

4

LOW BYTE

E8-EB

FLAG 1 QPA

5

3

FLAG 0 #18

FLAG 0 #10

FLAG 0 #2

84-87

FLAG 1 QPA

A4-A7

FLAG 1 QPA

C4-C7

FLAG 1 QPA

2 FLAG 0 #26

E4-E7

FLAG 1 QPA

1

FLAG 0 #17

FLAG 0 #9

FLAG 0 #1

80-83

FLAG 1 QPA

A0-A3

FLAG 1 QPA

C0-C3

FLAG 1 QPA

0 FLAG 0 #25

E0-E3

FLAG 1 QPA

3-30. QPA

Figure 3-203. QPA Card Group Read Bit Format

M0-0053

3-30. QPA

QPA Applications By using the control signals on the J2 and J3 connectors, several derived QPA functions are possible. The most straight forward use of the QPA card is pulse accumulation. With the field input wired to PHASE A (PHA +) and PHASE A (PHA −) (and PHASE B and PHASE B if necessary) and the control pins left open, the bus controller may read the counter value at any time. Devices included in this category are position encoders (where rotation in one direction increments the counter and rotation in the opposite direction decrements the counter). This allows the counter to contain a value that is proportional to rotary position. Shown in the following figures (Figure 3-204 through Figure 3-207) are four circuit configurations utilizing the QPA card.

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J3 Connection

J2 Connection

3-30. QPA

Figure 3-204. QPA Card Used for Speed Measurement

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M0-0053

M0-0053 E.G. SELECT 10 KHZ CLOCK

E.G. SELECT 100 KHZ CLOCK

+

+

48V

48V

B

A

LIMIT SWITCHES

3-388

Westinghouse Proprietary Class 2C TIME BASE

HIGH SPEED

RESET OPTION

RTN

SNAP-SHOT

TIME BASE

HIGH SPEED

RTN

STOP

START

COUNTER/COMPARATOR 1

OR

COUNTER/COMPARATOR 0

J3 Connection

J2 Connection

READ VALUE (AT ANY TIME)

READ VALUE (WHEN STOPPED)

3-30. QPA

Figure 3-205. QPA Card Used for Elapsed Time Measurement

5/99

J3 Connection

J2 Connection

3-30. QPA

Figure 3-206. QPA Used for Speed Ratio Measurement (For example, estimate stretch of materials between two rollers

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M0-0053

J3 Connection

J2 Connection

3-30. QPA

Figure 3-207. QPA Used for Average Inverse Speed Measurement

3-30.6. Implementation Example In the following example, a QPA card is set up as a counter for one pulsed input. The parameter being counted in this case is a POWER VALUE (MWH): contact closures from a megawatt meter. The number of megawatts per pulse will be accounted for in the coefficients that have to be calculated.

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3-30. QPA

The QPA card is located in the first slot of crate 1 in a DPU (zone/halfshell = A1) and its address is 80H. Care should be taken when selecting hardware addresses for QPA cards, since they require 4 consecutive addresses each, even though there are only 2 inputs per card. (The remaining two addresses are used for control and status word transfer). In this example, EW1 is point 1 on the card. This is the second point on the card. The first point is point 0. The QPA point must be initialized as an analog input point in the DPU. An example follows: INIT/EW1, AI, 1.0, IV = 0, FM = 0, DG = 2500, TB = 0, BB = 0, ED = ‘MWH TO PHOS 1E − ACB NO1 ‘, EU = ‘MWH ‘, EV = 0.0, CD = 36, HW = 258, AP = 0, LC = 0, HL = 0.0, LL = 0.0, IL = 0.0, DB = 0.0, HS = 0.0, LS = 0.0, CV = 1, CJ = 0, CI = 2

CHARST/EW1 , ‘A

‘

(OPTIONAL)

INIT/HOURS, DM, 1.0 INIT/PMIN, DM, 1.0 INIT/SECND, DM, 1.0 INIT, EWIR, AM, 1.0 INIT/EW1TOT, AM, 1.0 This point may have non-zero values for parameters such as TOPBAR, BOTBAR and LIMITS as desired, just as any other analog process input point. As an example, if 1 pulse from a KWH meter is equal to 10 KW, and EW1 is to be equivalent to MEGAWATTS PER HOUR; the conversion coefficients for this point would be: COEF/LT. 2 = (0.600, 0.00) This means, if 3 pulses came in a one minute period, the coefficient would give a value of 3 * 10 KW * 0.60 + 0.00 = 1.80 MWH. If the CI and CV fields are left blank, the value of EW1 will be the actual pulse count from the QPA card. A gain can then be used in the RESETSUM algorithm to get MW per hour. The algorithms required to control the QPA card are as follows: TIMECHG/110, HCHG = HOURS, MCHG = PMIN, SCHG = SECND QPACMD/111, CNTR = EW1, GADR = 0, FRZ0 = 0, STRO = 0, RST0 = 0, FRZ1 = 0, STR1 = 1, RST1 = 0, RUN = DX1PASS QPACMD/112, CNTR = EW1, GADR = 0, FRZ0 = 0, STRO = 0, RST0 = 0, FRZ1 = 2, STR1 = 0, RST1 = 0, RUN = PMIN

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M0-0053

3-30. QPA

QPACMD/113, CNTR = EW1, GADR = 0, FRZ0 = 0, STRO = 0, RST0 = 0, FRZ1 = 1, STR1 = 0, RST1 = 1, RUN = PMIN

AIN/114, AREC = EW1 RESETSUM/115, IN1 = EW1, FFLG = HOURS(F), RSET = HOURS(F), RUN = PMIN, RCNT = 0.0, GAIN = 1.0, OUT = EW1R, FOUT = EW1TOT

Algorithm 110 (TIMECHG) generates PMIN, which is a flag denoting a change in minutes, and HOURS, which is a flag denoting a change in hours, to be used by the QPACMD and RESETSUM algorithms. HOURS, PMIN and SECND must be initialized as digital points (for example, DM record type). Algorithm 111 sends a control command of START to channel 1 of the QPA when the digital input DX1PASS is set. DX1PASS is a point generated by the standard system in every DPU which is set to 1 only during the first pass through the DPU control program. These algorithms, therefore, start the QPA data collection (that is, count upon DPU startup). The two algorithm pairs (112 and 113) provide for the reading of data from the QPA channel 1. This is accomplished by first freezing the counter to get the new value from the QPA, and resetting the counter once that reading has been obtained. Only the reset operation will affect the actual QPA count; the freeze/unfreeze operation only causes the current value to be placed on the DIOB or removed from the DIOB. These 4 algorithms will only run when the digital flag PMIN is true. PMIN may be generated any number of ways, but in this system, PMIN is set as an output flag from the algorithm TIMECHG every minute. By unfreezing the QPA value only on the next 1-minute pass after freezing, rather than immediately, a valid QPA reading is present on the DIOB during the entire 1-minute period. AIN (algorithm 114) is used to convert the value EW1 to engineering units as required by RESETSUM. RESETSUM (algorithm 115) is used to totalize the value read from the QPA. The values are summed based on the state the out flags PMIN and HOURS generated by TIMECHG. In this example the output EW1R is an hours accumulation of MW. Output EW1TOT which is triggered by HOURS will be an hourly total. A description of each individual algorithm and required parameters can be found in “Control Algorithms” (U0-0106). The command words as described here may be field-wired if the availability of the QPA count is to be controlled by hardware rather than software.

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3-30. QPA


TERMINAL BLOCK 20B

CARD


20A 19B

CLOCK 1

PHB

COUNTER 1

* PHA

18

(+)

17B

17

(−)

17A

16

(+)

15B

15

(−)

15A

14

SNAP-SHOT

CLOCK 0

13B

13

13A

12

START

11B

11

STOP

11A

10

PHB

* COUNTER 2

3/4 A

19A

(+)

9B

09

(−)

9A

08

18 PHB

*

PHA

*

17 16 15 14

SNAP-SHOT

13 12

START

11

STOP

10

PHB

*

PHA

*

09 08

(+)

7B

07

(−)

7A

06

SNAP-SHOT

5B

05

5A

04

3B

03

START

03

3A

02

STOP

02

1B

01

PHA

START STOP

07 06

SNAP-SHOT

05 04

01

1A

EDGE-CONNECTOR

CUSTOMER CONNECTIONS BLACK

INTERNAL BUS STRIP

RED

TP BUS RETURN

(+)

48 VOLT POWER

Figure 3-208. QPA Wiring Diagram, Groups 1 and 4

Installation Note: Group 4 consists of counters only and no control signals. Group 1 contains all signals and circuits shown.

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M0-0053

3-30. QPA

Installation Data Sheet 2 of 5 Terminal Block 20B

Card

Half Shell Extension (B-Block)

20A 19B

Counter 1

Clock 1

19A

18

(+)

17B

17

(−)

17A

16

(−)

(+)

15B

15

(+)

(−)

15A

14

(−)

SNAP-SHOT

13B

13

13

13A

12

12

11B

11

11

PHB

PHA

Start

17 PHB

16 15

PHA

14

11A

10

9B

09

(+)

(−)

9A

08

(−)

(+)

7B

07

(+)

(−)

7A

06

(−)

5B

05

05

5A

04

04

Start

3B

03

03

Stop

3A

02

02

1B

01

PHB

PHA

Counter 2

18 (+)

(+)

Stop

Clock 0

*

Snap-shot

10 09 PHB

08 07

PHA

06

01 *

1A

Edge-connector

Customer Connections BLack

Red

Return

(+)

* TP BUS

Internal Bus Strip

48 Volt Power (Group 2)

(+)

(−)

Customer 5V POWER (Group 3)

Figure 3-209. QPA Wiring Diagram, Groups 2 and 3

Installation Notes: Group 3 uses customer supplied 5V power. This cards TP Bus will be live when customer 5V is on. * Group 2 utilizes standard 48V supply.

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3-30. QPA

For CE MARK Certified System 3 of 5 CUSTOMER CONNECTIONS CARD

EDGE-CONNECTOR

A

1A

A

B

1B

1

01

01

3A

2

02

02

3B

3

03

03

5A

4

04

04

STOP 0

1 2

START 0

3 4

SNAP SHOT 0

5B

5

05

05

7A

6

06

06

7B

7

07

07

9A

8

08

08

9B

9

09

09

PHB 0

9

11A

10

10

10

STOP 1

10

11B

11

11

11

START 1

11

13A

12

12

12

5 6

PHA 0

7 8

12 SNAP SHOT 1

13

13B

13

13

13

15A

14

14

14

15B

15

15

15

17A

16

16

16

17B

17

17

17

19A

18

19B

19

19

19

19

-

20

20

20

20

+

PE

PE

18

14 PHA 1

15 16

PHB 1

17

.75A 48 VDC

Figure 3-210. QPA CE MARK Wiring Diagram (Groups 1 and 4)

Installation Notes: 1. All field wiring must use shielded cables. Individually-shielded cables are not mandatory. A single overall shield is acceptable. The shield may be connected to earth ground at the B cabinet or in the field. Figure 3-210 shows two shielded cables with shields connected at the B cabinet. 2. The control signals are absent from the Group 4 QPA.

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M0-0053

3-30. QPA


EDGE-CONNECTOR

A

1A

A

B

1B

1

01

01

3A

2

02

02

3B

3

03

03

5A

4

04

04

STOP 0

1 2

START 0

3

PLANT EARTH GROUND

4 SNAP SHOT 0

5B

5

05

05

7A

6

06

06

6

-

7B

7

07

07

7

+

9A

8

08

08

8

-

9B

9

09

09

9

+

11A

10

10

10

STOP 1

10

11B

11

11

11

START 1

11

13A

12

12

12

5 PHA 0

PHB 0

PLANT EARTH GROUND

12 SNAP SHOT 1

13

13B

13

13

13

15A

14

14

14

14

-

15B

15

15

15

15

+

17A

16

16

16

16

-

17B

17

17

17

17

+

19A

18

19B

19

19

19

19

-

20

20

20

20

+

PE

PE

18

PHA 1

PHB 1

.75A 48 VDC

Figure 3-211. QPA CE MARK Wiring Diagram (Group 2)

Installation Notes: 1. All field wiring must use shielded cables. Individually-shielded cables are not mandatory. A single overall shield is acceptable. The shield may be connected to earth ground at the B cabinet or in the field. Figure 3-211 shows the shields connected to earth ground in the field. 2. Twisted-pair wiring is recommended for the clock inputs (PHA and PHB) due to the high frequencies.

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3-30. QPA


EDGE-CONNECTOR

A

1A

A

B

1B

1

01

01

3A

2

02

02

3B

3

03

03

5A

4

04

04

STOP 0

1 2

START 0

3 4

SNAP SHOT 0

5B

5

05

05

7A

6

06

06

6

-

7B

7

07

07

7

+

9A

8

08

08

8

-

9B

9

09

09

9

+

11A

10

10

10

STOP 1

10

11B

11

11

11

START 1

11

13A

12

12

12

5 PHA 0

PHB 0

12 SNAP SHOT 1

13

13B

13

13

13

15A

14

14

14

14

-

15B

15

15

15

15

+

17A

16

16

16

16

-

17B

17

17

17

17

+

19A

18

19B

19

19

19

19

-

20

20

20

20

+

PE

PE

18

PHA 1

PHB 1

.75A 5 VDC

Figure 3-212. QPA CE MARK Wiring Diagram (Group 3)

Installation Notes: 1. All field wiring must use shielded cables. Individually-shielded cables are not mandatory. A single overall shield is acceptable. The shield may be connected to earth ground at the B cabinet or in the field. Figure 3-212 shows all shields connected to earth ground at the B cabinet. 2. Twisted-pair wiring is recommended for the clock inputs (PHA and PHB) due to the high frequencies.

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M0-0053

3-31. QRC

3-31. QRC Remote Q-Line Controller (Style 4256A26G01)

3-31.1. Description Applicable for use in the CE MARK Certified System The QRC (Remote Q-Line Controller) printed circuit board serves as a DIOB controller in the WDPF Remote Q-Line I/O subsystem. Located in the remote stations, the QRC handles the communications between the remote station and the MRC (which is housed in the master station (DPU)). Full details on the configuration and use of the QRC are contained in the “Remote Q-Line Installation Manual” (M0-0054).

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3-32. QRF

3-32. QRF Four-Wire RTD Input Amplifier (Style 3A99109G01)

3-32.1. Description Applicable for use in the CE MARK Certified System The QRF card provides an addition to the family of Q-line I/O cards. It provides an integrated solution to measure temperature, using four-wire Resistance Temperature Detectors (RTD's) (see Figure 3-213). Six isolated analog input channels are provided along with six isolated reference current sources to accommodate six four-wire RTD's. To provide electrical (transformer) isolation for the analog input channels, individual (one per channel), on-card power supplies are used. In addition to providing power to each channel, precise timing is also transmitted by using a stable frequency to drive the power supplies. The input analog signals on each channel are converted to digital data and transferred to the on-board microcontroller. The data is processed to compensate for offset and gain errors, to provide filtering for 50/60 Hz. noise, and to convert the result to a percent of the full scale input voltage. The resulting data is formatted to conform to the data package used on the QAV, QAW, QAX, and QRT cards. The formatted data is read via the Distributed Input/ Output Bus (DIOB). Periodic calibration is performed by the microcontroller to obtain offset and gain errors from each input channel. As part of the calibration, reasonability checks are performed on the errors to monitor the integrity of the hardware.

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3-32. QRF

DIOB Data

Address

Data Buffer RAM

Control

Address Decoder

µController, Counter and Control Circuits

(+)





(-)

S O U R C E

R E T U R N

... S H I E L D

(+)

(-)

...

S O U R C E

R E T U R N

S H I E L D

Six Sets of 4-wire RTD Analog Field Inputs

Figure 3-213. QRF Block Diagram

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3-32. QRF

3-32.2. Features The QRF card provides the following features:

• • • • • • • •

IEEE Surge Withstand Capability

• • •

Reasonability test.

Auto Offset Auto Gain corrections Electrical Isolation (all channels) On-Card Digital Memory (buffer) 50 or 60 Hz time-base using a QTB card or internal time-base without a QTB. Auto Conversion Check Both Normal and Common-Mode Rejection are provided Low power consumption is achieved by the extensive use of CMOS circuitry and the use of a switching regulator to generate the +5V (Vcc).

RTD operational range monitoring. Open Input and Current Loop Detection

Four groups provided as follows:

Group

Temperature Range

Plug-on QRD Module

G01

0 oC to 370 oC using a 200 ohm Platinum RTD at 0 oC

3A99114G01

G02


3A99114G02

G03


3A99114G03

G04


3A99114G04

Note The groups are determined by the group of the Plug-on QRD Module (3A99114).

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3-32. QRF

3-32.3. Specifications Ratings

• • • •

Number of Analog Inputs: 6

•

Input Channel Sample Period (four cycles of the power line frequency): 0.066 sec. for 60 Hz. 0.080 sec. for50 Hz.

•

Current: 0.8 A typical, 1.0 A maximum

Point Sampling Rate (Rate/Second): 10, 5 during auto calibration Resolution: 12 bits Input Impedance: 107 Ohm 6000 Ohms in Overload or power-down

Power Supply Minimum

Nominal

Maximum

Primary Voltage

12.4 VDC

+ 13.0 VDC

13.1 VDC

Optional Backup

12.4 VDC

--

13.1 VDC

Input Signal Temperature Ranges Group Temperature Range

Platinum RTD’s Value

Excitation Current

Vspan*

G01

0 oC to 370 oC

200 ohm at 0 oC

1mA+5%

273.3mV

G02

180 oC to 230 oC

100 ohm at 0 oC

2mA+5%

36.72mV

G03

268 oC to 342 oC

200 ohm at 0 oC

1mA+5%

54.04mV

G04

0 oC to 290 oC

100 ohm at 0 oC

2mA+5%

216.92mV

* The actual Vspan values are the function of the excitation current.

Normal Mode Voltage The IEEE surge may be applied without permanent damage to the QRF card. Reduced accuracy is to be expected if reading are taken during the surge and up to 10 seconds following the surge, or until the next calibration.

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3-32. QRF

A continuous over-range input up to 10 VAC or 10 VDC can be sustained without damaging the QRF card. However, readings taken following sustained over-range can be affected for several seconds. Common Mode Voltage The IEEE surge may be applied without permanent damage to the QRF card. Reduced accuracy is to be expected if readings are taken during the surge and up to 10 seconds following the surge, or until the next calibration. A continuous maximum of + 500 VDC or peak AC with respect to system ground is allowable. The common mode reject ratio is not applicable if the AC peak value exceeds 200,000 percent of the full-scale input scan (20 VAC maximum for G01; 67 VAC maximum for G02). A continuous over-range input up to 10 VAC or 10 VDC can be sustained without damaging the QRF card. However, readings taken following sustained over-range can be affected for several seconds. Normal Mode Rejection

• •

60 dB at exactly 50 and 60 Hz (and harmonics) with line frequency tracking 30 dB at 50 and 60 Hz + 5% without line frequency tracking

For specified accuracy and normal mode rejection, the input peak-to-peak AC is not to exceed 50% of the input span (136.65 mV for G01, 18.36 mV for G02, 27.02mV for G03 and 108.46mV for G04). Common Mode Rejection

•

120 dB at DC and the power line frequency and its harmonics with line frequency tracking

•

100 dB (typical) for nominal line frequency +5% and harmonics without line frequency tracking Note Common mode rejection is not applicable if peak value of AC exceeds 200,000% of the input span

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3-32. QRF

Temperatures Stability For accuracy specifications to apply, the QRT card’s temperature rate of change must not exceed + 10°C per hour.

Other Applicable Specifications Once every 80 conversions (8 seconds apart) auto gain and auto offset calibration is performed. Calibration and input conversion cycles are alternated, thus the data is never more than 0.2 second old. Reference Accuracy - Analog Inputs: +0.20% of span +10 uV +1/2 LSB @ 99.7 confidence. Reference Conditions: 25oC +1oC Ambient Temperature 50% +1% RH. 0 V Common Mode 0 V Normal Mode (ac) Temperature Coefficient: Maximum variation of reading is + 0.25% of span, over the temperature range of 0oC to 60oC. Note The temperature characteristics of the instrument are determined mainly by the characteristics of the reference resistors. Long Term Stability: 0.02%

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3-32. QRF

Operating and storage temperature: Operating: From 0oC through +60oC as measured approximately 1/2 inch from any point on the printed circuit card while it is mounted in its normal vertical position and while subject to the air movements which result from natural convection only (that is, no forced air movement). Storage:

From 0 oC through +70 oC.

Humidity: From 10 to 90% relative humidity through an ambient temperature range of 0oC through 60oC, but with maximum wet bulb temperature not over 35oC (95oF).

3-32.4. Card Addressing The card address is programmed by five jumpers on the top of the front card-edge connector. Insertion of a jumper encodes a “1” on each address line (Add 3-7). When the pattern of the jumpers matches the bit pattern of the DIOB (UADD 3-7), the card is selected. Since there are only six analog channels on the card, two addresses (4 bytes) are used to obtain diagnostic data from the QRF card. As an option, the two addresses are disabled on the QRF and can be used by other cards. Bit patterns on UADD 0-2 determine which of the eight (or six using the option) channels on the card is selected. In order to keep the address recognition circuit to a minimum size, card addresses will be programmed in groups of 8 (16 bytes). Since the all-zero card address is excluded, 8 addresses (16 bytes) are lost. The “DIOB” can address 31 cards (186 channels). To provide address protection during card-pull and still retain the full address range, an unused “finger” (20B) is shortened on the card. An “address” jumper must be in this position on the I/O connector. Half of the address range is usable when the QRF is mixed on the same DIOB with other cards that use the short “MSB” finger.

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3-32. QRF

The QRF will use the feature where the DEV-BUSY line is pulsed (-when addressed-) to detect card presence. The DIOB cycle is extended during a valid card address. Table 3-112. QRF DIOB Address Selection ADDRESS LINE

ADDRESS PIN

GROUND PIN

A7 A6 A5 A4 A3

28B 27B 26B 25B 24B

28A 27A 26A 25A 24A

Address Protect

20A

20B

A - Solder Side B - Component Side

Table 3-113. Field Signal Pins

Input

Excitation Current

(+)

(-)

Shield

Source

Return

Shield

Point 1

1A

2A

3A

1B

2B

3B

Point 2

5A

6A

7A

5B

6B

7B

Point 3

9A

10A

11A

9B

10B

11B

Point 4

13A

14A

15A

13B

14B

15B

Point 5

17A

18A

19A

17B

18B

19B

Point 6

21A

22A

23A

21B

22B

23B

A - Solder Side B - Component Side

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3-32. QRF

3-32.5. Controls and Indicators User configurable QRF card jumpers are shown in Figure 3-214.

Jumper JS3

Jumper JS2 Figure 3-214. QRF Card Jumpers

Jumpers JS1 (Three Pos.) - used for other RAM sizes - not installed. JS2 (Three Pos.) - used to set the 50/60 hz operation according to the following table: JS2 (1-2) JS2 (3-4) Function OFF

OFF

60 HZ operation, No QTB (internal time-base)

OFF

ON

50 HZ operation, No QTB (internal time-base) (Default)

ON

OFF

60 HZ operation, With QTB

ON

ON

60 HZ operation, With QTB

JS3 (Three Pos.) - used to select the number of addresses used by the QRF card as follows: JS3 (1-2) JS3 (3-4)

Function

ON

OFF

All eight addresses are used by the QRF. (Default)

OFF

ON

The first six addresses are used by the QRF.

JS4 - JS9 (Three Pos.) - only the first position (on each channel) is used to connect the shields for all six channels. This is an option used to facilitate the grounding of the shields on some Jobs.

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3-32. QRF

LEDs LE1: POK - module receiving power from backplane


Point 6

Point 5

Point 4

Point 3

Point 2

Point 1

sh Return Source sh + sh Return Source sh + sh Return Source sh +

24A 24B 23B 22B 21B 23A 22A 21A 19B 18B 17B 19A 18A 17A 15B 14B 13B 15A 14A 13A

17 16 18 14 “B” 13 Block 15 Halfshell 11 10 12 8 7 9 5 4 6 2 1 3

sh Return Source sh + sh Return Source sh + sh Return Source sh +

11B 10B 9B 11A 10A 9A 7B 6B 5B 7A 6A 5A 3B 2B 1B 3A 2A 1A

17 16 18 “A” 14 Block 13 Halfshell 15 11 10 12 8 7 9 5 4 6 2 1 3

Figure 3-215. QRF Wiring Diagram

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3-32. QRF

For CE MARK Certified System 2 of 2 A

CARD

1

A (-)

2A

1

1

3A

2

2

1A

3

3

(+)

2B

4

4

(Return)

3B

5

5

1B

6

6

(Source)

6A

7

7

(-)

8

8

7A 5A

9

9

(+)

6B

10

10

(Return)

7B

11

11

5B

12

12

(Source)

10A

13

13

(-)

11A

14

14

9A

15

15

(+) (Return)

10B

16

16

11B

17

17

9B

18

18

PE

PE

POINT 1

POINT 2

POINT 3

(Source)

EDGE-CONNECTOR A

2

A (-)

14A

1

1

15A

2

2

13A

3

3

(+)

14B

4

4

(Return)

15B

5

5

13B

6

6

(Source)

18A

7

7

(-)

19A

8

8

17A

9

9

(+)

18B

10

10

(Return)

19B

11

11

17B

12

12

(Source)

22A

13

13

(-)

23A

14

14

21A

15

15

(+)

22B

16

16

(Return)

23B

17

17

21B

18

18

PE

PE

POINT 4

POINT 5

POINT 6

(Source)

NOTE: MOVs (Westinghouse Part # 4258A79H06) must be connected from the cable shields to earth ground at the B cabinet.

Figure 3-216. QRF CE MARK Wiring Diagram

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3-33. QRO

3-33. QRO Relay Output (Style 2840A18G01 through G04)

3-33.1. Description The QRO Card provides a method of interfacing DIOB controllers with field process points that require relay switching within the plant environment (see Figure 3-217). This card consists of eight mercury-wetted relays energized under DIOB control, providing normally-open or normally-closed relay contact operations to field processes. An on-card read/write latch provides an 8-bit memory function. This card also contains a switch-selectable dead-computer time-out circuit to reset the card when not periodically updated by the controller.

Data

DIOB

Data Latch

Bus Drivers

On-Card Relays

Address

Address Decoder

Card-Edge LED Indicators

Field Process Relay Contact Outputs

Figure 3-217. QRO Block Diagram

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3-33. QRO

3-33.2. Features The QRO card groups provides the following features:

•

G01 provides eight contacts (SPST) which may drive resistive or inductive loads. All G01 contacts are factory shipped as Form A (normally open).

•

G02 provides eight contacts (SPST) which may drive resistive or inductive loads. All G02 contacts are factory shipped as Form B (normally closed).

•

G03 provides eight contacts (SPST) which are limited to resistive loads. (Inductive loads cannot be driven). All G03 contacts are factory shipped as Form A (normally open).

•

G04 provides eight contacts (SPST) which are limited to resistive loads. (Inductive loads cannot be driven). All G04 contacts are factory shipped as Form B (normally closed).

Features common to all cards include:

•

Contacts may be individually jumper selected to be Form A (normally open) or Form B (normally closed).

• • • • • • •

IEEE surge-withstand protection 330 VDC common mode rating On-card power-up, bus, and dead-computer time-out resets Switch-selectable time-out periods Read/write output data operation Card-edge LED indicator for each relay‘s state Compatible with any DIOB controller

During a write operation, the QRO card receives and latches data from the DIOB into an on-card read/write register. This latched write data energizes or de-energizes the appropriate relays via transistor relay drivers, depending on user applications. During a read operation, the state of each of the eight relays is read from the read/ write register and driven to the DIOB, for use by the system controller. The read/write register may be reset by the DIOB controller, or by on-card resets from the power-up and time-out circuits. Additionally, card-edge LED’s indicate the state of each relay, where “ON” is energized and “OFF” is de-energized. The card should not be mounted more than 30 degrees from vertical.

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3-33. QRO

3-33.3. Specifications A functional block diagram of the QRO is shown in Figure 3-218.

Address

DIOB

Data

Unit

Power Up

8 9

~

~

Card Time Out 8-bit Latch

Compare

DRIVERS

Or 8

9

Relay Coils Reset Latch

LED’s

Front Connector Jumpers 8 Identical Relays

MOV

N.O.

68Ω .5w

.1µF

MOV

N.C.

On-Card Jumper *0.1µF AT 60 Hz = 26 KΩ Impedance 0.1µF AT 50 Hz = 31 KΩ Impedance

Figure 3-218. QRO Functional Block Diagram

Output Capabilities

M0-0053

Voltage:

330 VDC (maximum) 250 VAC (maximum) RMS at line frequency

Current:

0.5 Adc at peak AC (maximum)

Power:

100 VA (maximum) DC at peak AC


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3-33. QRO

Speed:

2ms typical (operate) 10ms typical (release)

Contact

Closed – 6Ω (maximum)

Impedance:

Open (G01, G02) – 25 kΩ (minimum) Open (G03, G04) – 300 kΩ (minimum)

Duty Cycle:

The contact should not open more than once every 10 ms (at rated voltage)

Power Supply Primary:

+13V + 0.1 VDC

Backup:

+12.6V + 0.2 VDC

Current:

400 mA (maximum) supplied by DIOB

Electrical Environment IEEE Surge withstand capability (G01 and G02 only) Common Mode Voltage:

330 VDC 250 VAC (rms)

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3-33. QRO

Safe Operating Area Figure 3-219 shows graphs for both DC and AC operation. These graphs may be referenced for safe operation specifications.

.5 100 VA .4 Closed Circuit Current (Amps)

DC Safe Operating Area

.3

.2

.1

100

200

300

Open Circuit Voltage (VDC)

100 VA

.3 Closed Circuit Current (Amps RMS)

.2

AC Safe Operating Area

.1

100

200

250

300

Open Circuit Voltage (VAC RMS)

Figure 3-219. QRO Safe Operating Area Diagrams

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3-33. QRO

3-33.4. Card Addressing The QRO card address is established by eight jumpers on the top, front, card-edge connector. The insertion of a jumper encodes a “1” on the address line (Figure 3-220).

Address Selection Example

Card Address = 1100 1000 (C8 High Byte)

Jumper:

A7 = 1

Jumper:

A6 = 1

Blank:

A5 = 0

Blank:

A4 = 0

Jumper:

A3 = 1

Blank:

A2 = 0

Blank:

A1 = 0

Blank:

A0 = 0

Jumper:

HI-LO = 1 (i.e., High byte)

Card-edge Connector (Front View)

Figure 3-220. QRO Card Address Jumper Assembly

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3-33. QRO

3-33.5. Controls and Indicators The location of the QRO LEDs and DIP switches are shown in Figure 3-221. If the QRO card is not periodically updated, the card resets. The update period is set by four DIP switches as given in Table 3-114. Separate LED’s for each output are located at the front of the card to indicate the status of each output. Eight jumpers are provided to select the form of each contact (normally open or normally closed). G01 and G03 are factory shipped with all jumpers in the normally open position. G02 and G04 are factory shipped with all jumpers in the normally closed position.

LEDs

DIP Switches

Figure 3-221. QRO Card Components

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3-33. QRO

Table 3-114. QRO Card Reset Switch Position Dip Switch

Reset Time

A

B

C

D

0

0

0

0

62 ms + 20%

0

0

1

0

125 ms + 20%

0

1

0

0

250 ms + 20%

0

1

1

0

500 ms + 20%

1

0

0

0

1 sec + 20%

1

0

1

0

2 sec + 20%

1

1

0

0

4 sec + 20%

1

1

1

0

8 sec + 20%

X

X

X

1

No time out, data latched (X = 0 or 1)

3-33.6. Installation The relay outputs are brought out on the front edge of the card. The contact allocations are listed in Table 3-115. Table 3-115. QRO Digital Output Contact Allocations Output Digital Bit No.

PC Card Edge Pin No.


B7

17B

17

17A

16

15B

15

15A

14

13B

13

13A

12

11B

11

11A

10

9B

9

9A

8

7B

7

7A

6

B6

B5

B4

B3

B2

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3-33. QRO

Table 3-115. QRO Digital Output Contact Allocations (Cont’d) Field Terminal Block Terminal No.

Output Digital Bit No.


B1

5B

5

5A

4

3B

3

3A

2

B0

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3-33. QRO

3-33.7. Installation Data Sheet 1 of 1 TERMINAL BLOCK SCREW HI/LO JUMPER CARD

TYPICAL

5A BIT 7

250 V

G01

20B

A

20A

20

19B

19

19A

18

17B

17

17A

16

15B

15

15A

14

13B

13

13A

12

11B

11

11A

10

9B

09

9A

08

7B

07

7A

06

5B

05

5A

04

3B

03

3A

02

1B

01

BIT 7

BIT 6

BIT 6

BIT 5

G02

BIT 5

BIT 4

BIT 3

250 V

COMMON

BIT 2

BIT 1

BIT 0

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

1A

EDGE-CONNECTOR


Figure 3-222. QRO Wiring Diagram

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3-34. QRS

3-34. QRS Redundant Station Interface (Style 3A99108G01 through G06)

3-34.1. Description Groups G01 through G06 (Must be revision F or later) are applicable for use in the CE MARK Certified System The QRS is designed to provide a redundant interface to the DPU, a Manual/ Automatic (M/A) station and a field device. The M/A station interface consist of 6 digital outputs, 8 digital inputs, 3 analog outputs, 1 fixed analog output and 1 analog input. The M/A station interface is referenced to the DIOB ground. The field interface consists of a single analog output which is electrically isolated from DIOB ground. All analog outputs have readback circuits which are monitored by the on-board microcontroller. In addition to the readback circuits, the microcontroller monitors several other functions to determine if the card is operating properly. The QRS card can be configured to operate as part of a redundant pair or as a stand alone card. When two QRS cards are configured as a redundant pair, one of the cards will be the controller and the other will be the backup. If a problem occurs on the controller and the quality of the backup is good, then control is automatically passed to the backup QRS. The transfer of control could take up to 30 milliseconds. Contact your Westinghouse representative for additional information.

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3-35. QRT

3-35. QRT Q-Line RTD Input Amplifier (Style 7379A62 G01 and G02)

3-35.1. Description Applicable for use in the CE MARK Certified System The QRT card converts an analog field signal to digital data. The digital data is the summation of a frequency counted for a time period; this time period is a multiple of the power line frequency (50 or 60 Hz). Each QRT card contains four individually isolated voltage-to-frequency converter circuits (channels). The output of each input circuit is processed by a common microcomputer, and the resulting digital data is multiplexed to the Distributed Input/Output bus (DIOB) as a 13-bit word (see Figure 3-223).

DIOB Data

Address

Data Buffer RAM

Control

Address Comparator and Data Selection

mP and Control Circuits


R T D

(+)

... ...

(-)


R T D

(+)

COM

(-)

COM

Four Sets of 3-wire RTD Field Pick-ups

Figure 3-223. QRT Block Diagram

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3-35. QRT

3-35.2. Definition of Terms

• • • • • • • • •

RCOLD = Resistance at bottom of span RHOT = Resistance at top of span RSUPP = Equivalent resistance to RCOLD on card IPROBE = Current through RTD VFS = Full scale input voltage RSPAN = RHOT minus RCOLD R = Current limiting resistors on the bridge Calculated Output = Output stripped of indicator bits (bits 15, 14) Output = Output including indicator bits (bits 15, 14)

3-35.3. Features The QRT card uses an electrical isolation circuit (transformer) to separate the analog input from the digital counting circuits. The isolation circuit provides power for each analog input channel in addition to providing precise timing from a stable frequency. This timing is generated on the digital side of the QRT card circuits. Each analog input circuit contains circuitry for signal conditioning, biasing, auto-zero and auto-gain correction, and a clocked voltage-to-frequency converter. Offset and gain correction factors are calculated periodically by the QRT card microcomputer. The frequency of the offset and gain calibration cycle is determined by a constant which has been programmed into the memory of the system controller.

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3-35. QRT

Figure 3-224 shows a typical control system configuration using QRT cards.

DIOB CONTROLLER

QTB CARD

POWER LINE INPUTS

QRT CARD NUMBER 1

FIELD INPUTS

QRT CARD NUMBER 35

FIELD INPUTS

DIOB

NOTE THE QTB CARD OBTAINS A HIGH NORMAL MODE REJECTION IN APPLICATIONS WHERE LARGE POWER LINE FREQUENCY VARIATIONS OCCUR.

Figure 3-224. Typical Control System Using QRT Cards

In process control and monitoring applications where temperature must be measured in various locations, a three-wire Resistance Temperature Detector (RTD) input signal is connected to bridge the amplifier circuits. The QRT card provides the bridges, converters, and multiplexers to interface four isolated RTD inputs asynchronously to a process control or monitoring system. Copper, platinum, or nickel RTDs can be interfaced to the QRT card. The QRT card includes an on-board 8039 microcomputer which, in addition to supervising voltage-to-frequency conversion, converts the digitized voltage reading to a percent span of the full scale input voltage, and also performs periodic QRT card calibration. The QRT card is a voltage input card with four individually-isolated analog input channels. The front end is designed to convert field signals to a proportional frequency. There are two QRT card groups:

•

G01–Full Scale 10 mV Nominal 10 VDC ref ---------------------------- Actual 1000

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3-35. QRT

•

G02–Full Scale 33-1/3 mV Nominal 10 VDC ref ---------------------------- Actual 300

where:

10 VDC ref = 10 VDC + 1 Percent The on-card controller is common to all four input channels and converts the variable frequencies to a parallel, 12-bit word. It also provides offset and gain correction and controls the interfacing to the DIOB. Both QRT card groups include the following features: • IEEE surge withstand capability

M0-0053

• •

Auto-zero, auto-gain corrections

• •

On-card memory (buffer) for storing conversion results

Each channel is electrically isolated from the other channels and the UIOB or DIOB ground. If a twisted pair cable must be used, every two analog channels will have a common ground. Normal and common-mode rejection


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3-35. QRT

Figure 3-225 shows QRT card percentage accuracy versus RCOLD/RSPAN.

1

0.5%

0.425% 2

0.4%

3

0.3% 4 0.225% 0.2% 0.16%

5

NORMAL RANGE

0.1%

1

2

3

4 RCOLD RSPAN

WHERE: RSPAN = RHOT − RCOLD (STANDARD CALIBRATION) 1

GROUP 1 ACCURACY INCLUDING BRIDGE (4 Ω SPAN)

2

GROUP 2 ACCURACY INCLUDING BRIDGE WITH LOW RTD SPAN (10 Ω SPAN)

3

GROUP 2 ACCURACY INCLUDING BRIDGE

4

GROUP 2 ACCURACY EXCLUDING BRIDGE

5

GROUP 2 ACCURACY INCLUDING BRIDGE (CUSTOM CALIBRATION)

Figure 3-225. QRT Card Accuracy

The range of the valid input voltages to the QRT card extends from -10% to +110% of the defined full scale voltage (that is, −0.1 VFS ≤ Vin ≤ VFS). The dynamic linear range of the output is shown in Figure 3-226. If the output exceeds 11FFH, such as an open RTD, the output is set to 1200H. Below 3E00H, such as a shorted RTD, the output is set to 3DFFH.

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3-35. QRT

CALCULATED OUTPUT 1200H 1000H

OUTPUT D200H D000H

(−)0.125VFS

VFS

1.125 VFS VIN

OUTPUT FDFFH

CALCULATED OUTPUT 3DFFH

Figure 3-226. QRT Card Output Dynamic Linear Range

Four different measurements are taken for each channel. One reading is the bridge input; the other three readings are the calibration readings, taken when a calibration cycle occurs (period of approximately 8 sec). During a calibration cycle, the calibration readings are monitored to ensure that they are within acceptable ranges. If they are not, bit 14 is set to Logic 0. At the end of the calibration cycle, the QRT card checks for the presence of the USYNC jumper. If the jumper is installed, the controller tests for the USYNC signal’s presence and its limits. A failure here sets bit 15 to Logic 0. Bit 15 is also set to Logic 0 during the power up routine of the QRT card. The QRT microcomputer is then reset, and conversion of data begins when the reset control is removed and the QRT card buffer memory is updated. Bit 15 is reset to Logic 1 after a warm-up pause is complete. The length of the warm-up pause is determined by another constant which is programmed into the memory of the system controller. The calibration readings plus bits 14 and 15 are stored in QRT card memory and remain unchanged until the next calibration cycle, at which time they are updated. The result of the conversion is a 12-bit binary word. Table 3-116 lists the interpretations of QRT card hexadecimal output data. Table 3-116. QRT Card Conversion Results

Hexadecimal Output Data C000

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Interpretation Zero Input


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3-35. QRT

Table 3-116. QRT Card Conversion Results (Cont’d)

Hexadecimal Output Data

Interpretation

C001

Zero + 1

D000

+ FS

D001-D1FF

+ Over range

D1FF

Maximum operational range

D200

Above the operational range (or RTD open)

FFFF

Zero − 1

FFFF-FE00

− Over Range

FE00

Minimum operational range

FDFF

Below the operational range (or RTD shorted)

8000-BFFF

Calibration readings not within acceptable range

0000-7FFF

Warm-up or USYNC failure (USYNC not present or present but not within specifications)

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Block Diagram Figure 3-227 and Figure 3-228 show functional block diagrams of the QRT card. 200 KΩ

10 VDC REF

100 Ω GO(1) 167 Ω GO(2)

100 KΩ GO(1) 50 KΩ GO(2)

+ INPUT (2)

− +

INPUT (3) R FRONT EDGE CONNECTOR

I OFFSET

R

−

FULL SCALE REF

+

GROUND REF

−

0-4 VDC RANGE 75 KΩ

RGAIN + INPUT (1)

RSUPP

RTD

INPUT (4)

−

VBRIDGE 500 Ω

+ COMMON MODE − GROUND

+ −

MULTIPLEXER

500 Ω

MUX CONTROLLER

I TO F INPUT SIGNAL +12 VDC −12 VDC POWER SUPPLY

(−)

INTEGRATOR SWITCHING LOGIC


CLOCK

+ 12 VDC

CURRENT SOURCE IREF

PSD (250 KHZ) FREQUENCY INPUT F11 T1

D1 C2

CAPACITOR DISCHARGE LOGIC

R5

Figure 3-227. QRT Card Bridge and I to F Circuits Block Diagram

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3-35. QRT

ADDRESS JUMPERS

(250 KHZ) PSD

ANALOG POWER CONTROL CL

P15

6 MHZ

AOK

RAM LOAD ENABLE

UADD (0-7) DATA DIR

ADDRESS DECODER


TADD (0-2) THI-LO

DOUT LEVEL SHIFT AND BUFFER

I/O

P17

UDAT (0-7) DEV BUSY)

P16 60 HZ

TUSYNC 50 HZ CL WR JU 3-1

8039 MICROCOMPUTER


MWR, WHI-LO

BUFFER RAM

SS

WD(0-7)

LEN

PROGRAM MEMORY

ADDRESS LATCH

DIOB

BUS (DB0-7)

BUFFER LATCH

CONTROL ADDRESS I/O

P10-12

P14 RESET

COUNTER (5)

POWER UP AND RESET

COUNTERS (1 TO 4)

+5V

5 VOLT REGULATOR

+12V ALE/4 F1 (0 THROUGH 3)

Figure 3-228. QRT Card Digital Circuits Block Diagram

3-35.4. Specifications Ratings

• • • 5/99

Number of Analog Inputs: 4 Point Sampling Rate: 500 msec Auto Calibration Rate: 9 sec


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3-35. QRT

•

Sampling Rate During Calibration: 1 sec


Nominal

Maximum

Primary Voltage

12.4 VDC

+ 13.0 VDC

13.1 VDC

Optional Backup

12.4 VDC

--

13.1 VDC

–

1.0 A

1.2 A

Current Normal Mode Voltage Input

Table 3-117 lists the input signal ranges and input spans for both QRT card groups. The QRT card signal input can be open or short circuited without damaging the card. Table 3-117. Normal Mode Voltage Input

G01

G02

Nominal

Actual

Nominal

Actual

Input Signal Range

0 through 10 mV

0 through Vref -----------------------------------1000

0 through 33-1/3 mV

0 through Vref -----------------------------------1000

Input Span

10 mV

Vref -----------1000

33-1/3 mV

Vref -----------300

Vref ≈ 10 VDC

Normal Mode Rejection

• • •

60 dB at exactly 50 and 60 Hz (and harmonics) without line frequency tracking 25 dB at 50 and 60 Hz + 5% without tracking Optional 60 dB at power line frequency (and harmonics) + 5% with line frequency tracing

Temperatures Stability For accuracy specifications to apply, the QRT card’s temperature rate of change must not exceed + 10°C per hour.

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Amplifier Offset Temperature Drift Compensation The QRT card features automatic compensation for amplifier offset temperature drift. Bridge Supply

• • •

Accuracy: 10.0 + 0.1 VDC Bridge Current: 10 mA Maximum Temperature Coefficient: 40 ppm/degree C

AC normal mode rejection does not apply if peak AC exceeds 50 percent of the input span (5 mV maximum for G01; 17 mV maximum for G02). QTB Tracking Ranges (Optional) 58 Hz to 62 Hz or 45 Hz to 55 Hz Input Channel Sampling Period 0.4 seconds Common Mode Input The IEEE surge may be applied without permanent damage to the QRT card. Reduced accuracy is to be expected if reading are taken during the surge and up to 10 seconds following the surge, or until the next calibration. A continuous maximum of + 500 VDC or peak AC with respect to system ground is allowable. The common mode reject ratio is not applicable if the AC peak value exceeds 200,000 percent of the full-scale input scan (20 VAC maximum for G01; 67 VAC maximum for G02). A continuous over-range input up to 10 VAC or 10 VDC can be sustained without damaging the QRT card. However, readings taken following sustained over-range can be affected for several seconds. Common Mode Rejection

• • 5/99

120 dB at DC 100 dB at exactly 50 and 60 Hz (and harmonics) without tracking


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3-35. QRT

• •

80 dB at 50 and 60 Hz + 5% without tracking Optional 100 dB at power line frequency (and harmonics) + 5% with line frequency tracking

DIOB Interface The QRT card plugs into a standard DIOB backplane connector.

3-35.5. Field Input Connection Figure 3-229 shows the QRT card-edge connectors. Backplane Connector

Front Edge Connector (RTD Input)

Figure 3-229. QRT Card Connectors

A standard Q-Line series front-edge connector is used on the QRT card. Each of the four analog channels has four contacts:

• • • • M0-0053

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3-35. QRT

Table 3-118 lists QRT card front-edge connector pin numbers and signals. Table 3-118. QRT Front Edge Connector Pin Assignments Pin Number (Solder Side)

1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 13A 14A 15A 16A 17A 18A 19A 20A 21A 22A 23A 24A 25A 26A 27A 28A

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Signal


(−) INPUT (POINT 0) UNUSED SHIELD (POINT 0) UNUSED COMMON (POINT 0) UNUSED COMMON (POINT 1) UNUSED SHIELD (POINT 1) UNUSED (−) INPUT (POINT 2) UNUSED (+) INPUT (POINT 2) UNUSED SHIELD (POINT 2) UNUSED (−) INPUT (POINT 3) UNUSED (+) INPUT (POINT 3) GROUND UNUSED UNUSED GROUND GROUND GROUND GROUND GROUND GROUND

1B 2B 3B 4B 5B 6B 7B 8B 9B 10B 11B 12B 13B 14B 15B 16B 17B 18B 19B 20B 21B 22B 23B 24B 25B 26B 27B 28B


Signal

(−) INPUT (POINT 0) UNUSED (+) INPUT (POINT 0) UNUSED SHIELD (POINT 0) (−) INPUT (POINT 1) (−) INPUT (POINT 1) UNUSED (+) INPUT (POINT 1) UNUSED SHIELD (POINT 2) UNUSED COMMON (POINT 3) UNUSED SHIELD (POINT 3) UNUSED SHIELD (POINT 3) UNUSED (+) INPUT (POINT 3) ENABLE UNUSED UNUSED UADD 2 UADD 3 UADD 4 UADD 5 UADD 6 UADD 7

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3-35.6. Card Addressing As shown in Table 3-119, the QRT card uses DIOB address bits UADD 7 through UADD 2 for address selection of the card, and uses UADD 1 and UADD 0 to select channels 1 through 4 on the card. A7

A6

A5

A4

A3

A2

A1

Possible Card Address

A0

Channels 1 through 4

To set a DIOB address, a jumper is inserted at the terminal pair(s) corresponding to the UADD bit(s) which is (are) Logic 1. A jumper to tie 20A to 20B on the front edge must always be inserted. This feature removes the card from its DIOB address when the front-edge connector is removed. Table 3-119 lists the DIOB address bits’ corresponding front-edge connector pairs. Table 3-119. Front Edge Pairs for QRT Card Address Bits

UIOB or DIOB Address Bit

Corresponding Front Edge Pairs

UADD 7

28A, B

UADD 6

27A, B

UADD 5

26A, B

UADD 4

25A, B

UADD 3

24A, B

UADD 2

23A, B

Selection of RTD Bridges Table 3-120 lists the six standard groups of bridge modules which are available for the QRT card. Custom RTD bridges are available to the user. For ordering details, contact your Westinghouse representative. Table 3-120. QRT Card RTD Bridge Modules (7380A92) Module Group

Full Scale Voltage

R

Rsup

Rspan

1

10 mV or 33-1/3 mV

--

--

--

2

33-1/3 mV

60 KΩ

100 Ω

200 Ω

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3-35. QRT

Table 3-120. QRT Card RTD Bridge Modules (7380A92) (Cont’d) Module Group

Full Scale Voltage

R

Rsup

Rspan

3

33-1/3 mV

15 KΩ

120 Ω

50 Ω

4

33-1/3 mV

30 KΩ

100 Ω

100 Ω

5

33-1/3 mV

30 KΩ

400 Ω

100 Ω

6

10 mV

8 KΩ

8.5 Ω

8Ω

3-35.7. Controls and Indicators User configurable QRT card components are shown in Figure 3-230. Jumper JU3-1 is installed in order to perform line frequency tracking. At the end of each calibration cycle, the controller checks whether this jumper is installed. If it is not installed, then the controller will use its own internal clock as a time base for voltage-to-frequency conversion. If jumper JU3 is installed, the controller will use the QTB board’s USYNC signal for that time base (50 or 60 Hz according to jumper location). Four stranded jumpers may be installed to tie together the ground and shield of channels 1 and 2 to the ground and shield of channels 3 and 4.

Stranded Jumpers (4)

Jumper JU3-1

Figure 3-230. QRT Card Components

3-35.8. Application Information As noted previously, the QRT card provides an interface to four individual resistance temperature detector (RTD) sensors. These RTDs can provide cold junction compensation for thermocouple (QAV) inputs. The following sections provide information intended to clarify the application of QRT cards.

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3-35. QRT

Bridge Resistor Calculation Each of the four channels on the QRT card contains a resistance bridge, located on a small daughter card. These four daughter cards, called the bridge modules, are each connected to the QRT by a row of nine 25-mil square posts. Each voltage input channel provides its bridge with a precision 10 V source voltage. Three of four resistance arms that form each bridge (R, R, and RSUPP) are located on the daughter card (see Figure 3-231). The fourth resistance arm is the RTD. The bridge is said to be balanced when the resistance of the RTD equals the resistance of the bridge resistor arm that contains RSUPP. The resulting bridge voltage is zero. +10 V (RA-2)

R R (RA-1) +

+

(−) VBRIDGE (RB-1)

RTD

RSUPP (−)

(RC-1)

COM

Figure 3-231. Bridge Resistance

If the resistance of the RTD increases, the bridge is no longer balanced, and a net positive bridge voltage exists. This bridge voltage is input to the QRT card. Group 1 QRT cards accept a full scale bridge voltage input of 10 mV, and would typically be specified to interface copper RTDs with very low resistance values (for example, 10 Ohm). Group 2 QRT cards accept a full scale bridge voltage input of 33.3333 mV, and would typically be specified to interface platinum or nickel RTDs.

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The formulas used to specify the bridge resistors are shown below: RSUPP – This bridge arm resistance is normally set equal to RCOLD. The two bridge arm resistors (RB-1) and RC-1) must be precision resistors (as specified on the applicable system drawing). Typically, only resistor RB-1 is used. Resistor RC-1 may also be used if it is necessary to parallel two of the available resistors to obtain the desired RSUPP. Formula 1a.

RSUPP = RCOLD

OR Formula 1b.

RSUPP = RB-1

OR Formula 1c.

RB-1 ∗ RC-1 RSUPP = -------------------------------RB-1 + RC-1

R – Two bridge resistance arms contain resistor R (RA-1 and RA-2). These two resistors are used to limit the RTD probe current (which minimizes the RTD self-heating error). In conjunction with RSUPP, R is used to select the RTD resistance (that is, RHOT) that corresponds to a full scale bridge voltage output. If RHOT and RSUPP are known, then R is selected. To simplify the task of selecting a value for R, once RHOT and RSUPP have been determined, a first order approximation of the bridge voltage is used: Formula 2a. 10V V Bridge = ---------- × ( R RTD – R Supp ) R

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A full scale bridge output voltage is desired when RRTD = RHOT: Formula 2b.

10 V R = ----------------------------------------------------------------------------------------- ∗ ( R HOT – R SUPP ) FULL SCALE BRIDGE VOLTAGE

If the value of R that is calculated from Formula 2 cannot be obtained by selecting a resistor from the standard drawing, the user may select a resistor from the drawing with a slightly higher resistance. Using such a resistor for RA-1 and RA-2 causes the span of resistance that can be measured by the QRT card to be slightly wider that RSPAN: Formula 3. Full Scale Bridge Voltage QRT Resistance Measurement Span = -------------------------------------------------------------- × R 10V

Card Output Calculation Formulas The QRT card provides a sixteen bit digital output for each of its four voltage input channels. The analog voltage to digital code conversion circuit in each QRT input channel produces a signed 14-bit output (sign bit plus 13 data bits), of which values of 0 to 4096 represent the normal full-scale operating range. These fourteen bits (bits 13 through 0) are the fourteen least significant bits of the QRT card channel’s digital output. Bits 15 and 14 are status bits and will be set to 1 if the QRT card is functioning properly. The sixteen bit QRT digital output is typically expressed in hexadecimal form. The QRT card is calibrated so that when a full scale bridge voltage is applied to an input channel, the channel’s digital output code is D000H. A digital output of C000H indicates that the QRT card input channel is measuring a bridge voltage which is zero (that is, RRTD = RSUPP). Bridge voltages that lie between zero and full scale result in digital output codes that range from C000H (0 counts) to D000H (4096 counts). The following two formulas will be required to convert a bridge voltage into counts:

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3-35. QRT

Formula 4.

FULL SCALE BRIDGE VOLTAGE VLSB = ----------------------------------------------------------------------------------------4096

Formula 5.

V BRIDGE COUNTS = ---------------------V LSB

As described previously, when the bridge module resistors are chosen, a first order approximation for the bridge voltage (Formula 2a) is used to derive the equation for calculating the value of R (Formula 2b). However, since Formula 2 is only an approximation of the actual bridge voltage equation (Formula 6, shown below), using Formula 2b to calculate R results in a resistance value that is not precisely correct. If bridge resistors RA-1 and RA-2 are selected to equal the calculated value of R, the actual bridge voltage will not equal the bridge voltage expected (from Formula 2). In addition, there is a non-linear relationship between RRTD and VBRIDGE (see Formula 6). As a result, for a given value of RRTD, there is a difference between the expected output (calculated from Formula 2) and the actual output (calculated from Formula 6): 10 V * R RTD 10 V * R SUPP – ---------------------------------VBRIDGE = ------------------------------R + R RTD R + R SUPP

Formula 6.

Bridge Resistor Selection and Output Examples The following examples illustrate how using a first order approximation of the bridge voltage to calculate R affects the expected (ideal) hexadecimal output code, as does the inherent non-linearity of the bridge. For each example, the values for bridge resistors R and RSUPP are calculated. Then, five values for RRTD, ranging in equal increments from RCOLD to RHOT will be used to calculate bridge voltages, first using Formula 2, and then using Formula 6. The two resulting bridge voltage values will be used to calculate counts and hexadecimal output codes. Example A. Given the following values: =120 Ω RCOLD RHOT =170 Ω RSUPP is set equal to RCOLD (120 Ω) From the values given for RCOLD and RHOT, the RTD is obviously not a copper RTD, so a Group 2 QRT card is selected. This provides a full scale bridge voltage of 33.3333 mV.

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3-35. QRT

Since a 120 Ω resistor is available on the standard drawing (651A129), bridge resistor RB-1 will be 120 Ω (RC-1 is not required). Formula 2b is used to calculate the value of R (bridge resistors RA-1 and RA-2): 10 V R = ------------------- ∗ ( 170Ω – 120Ω ) = 15 KΩ 33.3mV A 15 KΩ resistor is available from the standard drawing, so bridge resistors RA-1 and RA-2 will have this value. With all three bridge resistors selected, the bridge voltages, counts, and hexadecimal output codes can be calculated. For the following RTD resistance values: 120 Ω

132.5 Ω

145 Ω

157.5 Ω

170 Ω

Formulas 2 and 6 can be used to calculate bridge voltages (first order approximation and actual): Formula 2a. 10 V V BRIDGE ( Expected ) = --------------------- * ( R RTD – 120 Ω ) 15000 Ω OR Formula 6. 10 V * R RTD 10 V * 120Ω V BRIDGE ( Actual ) = --------------------------------- – -------------------------------15KΩ + R RTD 15.120KΩ

The voltage weight of one count (or LSB) is calculated using Formula 4. Formula 4.

33.333 mV VLSB = --------------------------- = 8.138 µV 4096

Using the bridge voltage figures calculated for each RTD resistance value, Formula 5 can be used to calculate the corresponding ideal number of counts:

Formula 5.

V BRIDGE COUNTS = ---------------------8.138 µV

The hexadecimal output codes are determined by converting the decimal count number into hexadecimal and adding C000H. The results are shown in Table 3-121.

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Table 3-121. Bridge, Count, and Output Values (Example A)

RTD

Expected Bridge V

Expected Counts

Expected Output

Actual Bridge V

Actual Counts

Actual Output

170 Ω

33.333 mV

4096

D000H

32.698 mV

4018

CFB2H

157.5 Ω

25.000 mV

3072

CC00H

24.544 mV

3016

CBC8H

145 Ω

16.666 mV

2048

C800H

16.376 mV

2012

C7DCH

132.5 Ω

8.333 mV

1024

C400H

8.195 mV

1007

C3EFH

120 Ω

0.000 mV

0

C000H

0.000 mV

0

C000H

Example B. Given the following values: = 8.5 Ω RHOT = 14.5 Ω RSUPP is set equal to RCOLD (8.5 Ω) From the values given for RCOLD and RHOT, the RTD must be a copper RTD, so a Group 1 QRT card is selected. This provides a full scale bridge voltage of 10.000 mV. RCOLD

Since an 8.5 Ω resistor is not available on the standard drawing, bridge resistors RC-1 and RB-1 will both be required. If two 17Ω resistors are placed in parallel (as will be the case with RC-1 and RB-1), the resulting resistance is 8.5Ω. The standard drawing does include a 17Ω resistor, so both RC-1 and RB-1 will be set equal to 17 Ω. Formula 2b is used to calculate the value of R (bridge resistors RA-1 and RA-2): 10 V R = --------------------------- ∗ ( 14.5Ω – 8.5Ω ) = 6000Ω 10.000 mV A 6000 Ω resistor is available from the standard drawing, so bridge resistors RA-1 and RA-2 will have this value. With all three bridge resistors selected, the bridge voltages, counts, and hexadecimal output codes can be calculated. For the following RTD resistance values: 8.5 Ω

10 Ω

11.5 Ω

13.0 Ω

14.5 Ω

Formulas 2 and 6 can be used to calculate bridge voltages (first order approximation and actual): 5/99


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Formula 2a. 10 V V BRIDGE ( Expected ) = ------------------ * ( R RTD – 8.5 Ω ) 6000 Ω OR Formula 6. 10 V * R RTD 10 V ∗ 8.5Ω V BRIDGE ( Actual ) = ----------------------------------- – ------------------------------6000Ω + R RTD 6008.5Ω

The voltage weight of one count (or LSB) is calculated using Formula 4. Formula 4.

VLSB =

10.000 mV ---------------------------- = 2.44 µV 4096

Using the bridge voltage figures calculated for each RTD resistance value, Formula 5 can be used to calculate the corresponding ideal number of counts:

Formula 5.

COUNTS = V BRIDGE ---------------------2.44 µV

The hexadecimal output codes are determined by converting the decimal count number into hexadecimal and adding C000H. The results are shown in Table 3-122. Table 3-122. Bridge, Count, and Output Values (Example B)

RTD

Expected Bridge V

Expected Counts

Expected Output

Actual Bridge V

Actual Counts

Actual Output

14.5 Ω

10.000 mV

4096

D000H

9.962 mV

4080

CFF0H

13.0 Ω

7.500 mV

3072

CC00H

7.473 mV

3061

CBF5H

11.5 Ω

5.000 mV

2048

C800H

4.983 mV

2041

C7F9H

10.0 Ω

2.500 mV

1024

C400H

2.492 mV

1021

C3FDH

8.5 Ω

0.000 mV

0

C000H

0.000 mV

0

C000H

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3-35. QRT

Use of RTDs and Segments The DPU’s cold junction compensation approach allows two separate temperature zones, called segments, to be defined in each cabinet. For each segment, two temperature readings can be averaged. Any thermocouple points terminated in a given segment will use the segment’s (averaged) temperature reading. This permits very accurate compensation when required. Segments are defined by the addresses assigned to the RTDs. The QRT card always uses the block of four hardware addresses beginning at F8. The first two addresses (F8 and F9) are dedicated to the first segment, and the second two addresses (FA and FB) are dedicated to the second segment. If only addresses F8 and F9 are assigned, only one segment will be defined. If temperature averaging is not to be used, only one address in each segment can be assigned (for example, F8 in segment 1 and FA in segment 2). Figure 3-232 illustrates two of the possible combinations of RTD(s) and segment(s). Each segment uses two QRT inputs, whether or not two RTDs are used. The second QRT input cannot be used for customer RTD inputs, since it would be averaged into the cold junction temperature. Also, two bridges must be installed for each segment, even if the second input is not used. Note If RTDs are mounted in a separate termination (B) cabinet, a half-shell extension and baffle kit are required to prevent fan cooling from affecting the temperature reading.

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RTD 1 (Address F8)

One Segment RTD 1 and RTD 2 Values Are Averaged

RTD 2 (Address F9)

RTD 1 (Address F8) Segment 1 RTD 1 and RTD 2 Values Are Averaged RTD 2 (Address F9)

RTD 3 (Address FA) Segment 2 RTD 3 and RTD 4 Values Are Averaged

RTD 4 (Address FB)

Figure 3-232. RTDs and Segments

For additional information on cold junction compensation (CJ record field, software addressing, etc.), refer to “Record Types User’s Guide” (U0-0131) and “MAC Utilities User’s Guide” (U0-0136). Values for Sample RTDs The following sample provides specific values for the Westinghouse standard RTD:

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3-35. QRT

120Ω - Nickel RTD

Westinghouse Part No.: 774A759H01 Manufacturer: Minco Products (No. S4-60) Alpha =.0081 For linear conversion: Gain = 3780.378 Bias = 32.0 For 5th order polynomial conversion: C0 = 32.000C3 = 0.0000 C1 = 3835.6311C4 = 0.0000 C2 = −8044.8691C5 = 0.0000

If used with a G02 QRT card and a G03 bridge module, the following is true: Span = 0 to 3.33 mVDC for a range of 0 to 70°C (32 to 158°F), 120 to 170 Ω Temperature Range Information

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mV in VDC

Temperature in °F

Temperature in °C

Ohms

0.0000000

32.0

0.0

120.00

0.0060386

57.0

13.89

130.01

0.0118357

81.0

27.22

139.95

0.0173913

104.0

40.00

149.79

0.0176328

105.0

52.78

159.99

0.0229468

127.0

52.78

159.99

0.0333333

158.0

70.00

170.17


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The following sample provides specific values for another common RTD:

100Ω - Platinum RTD Manufacturer: Tempro Alpha =0.00385 For linear conversion: Gain = 30120.00 Bias = 32.0 For 5th order polynomial conversion: C0 = 32.0000

C3 = 80864.00

C1 = 27634.00

C4 = 20502.0E + 003

C2 = 61050.00

C5 = −31987.0E + 004

If used with a G02 QRT card and a G03 bridge module, the following is true: Span = 0 to 3.33 mVDC for a range of 0 to 558°C (32 to 1036°F), 100 to 300 Ω Temperature Range Information mV in VDC

Temperature in °F

Temperature in °C

Ohms

0.0000000

32.00

0.0

100.00

0.0062151

219.20

104.0

140.01

0.0094422

316.40

158.0

160.30

0.0126693

413.60

212.0

180.24

0.0159562

512.60

267.0

200.22

0.0196614

624.20

329.0

222.31

0.0227092

716.00

380.0

240.15

0.0261753

820.40

438.0

260.07

0.0297610

928.40

498.0

280.26

0.0333333

1036.00

558.0

300.00

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3-35. QRT



TERMINAL BLOCK #8-32 SCREW 20B

CARD Channel Shield (1 of 4)

2

20A

PLUG-IN BRIDGE (−)

10 V POWER

A

19A

18

17B

17

17A

16

15B

15

15A

14

(+)

(+)

Power Supply Return CHANNEL 4

13

13A

12


11B

11

11A

10

(−)

9B

09

9A

08

7B

07

7A

06

5B

05

5A

04

3B

03

3A

02

1B

01

10 V POWER

10 V POWER

(+)

(+)


(−)

10 V POWER

SHIELD

RTD4

(−)

13B (−)

4

1

19B

(+)


RETURN 5 RETURN (+)

PLANT GROUND

RTD3

SHIELD (−) + SHIELD

RTD2

(−) RETURN PLANT GROUND

RETURN (+)

RTD1

SHIELD (−)

1A

EDGE-CONNECTOR

FOR PLANT GROUNDED RTDS

Figure 3-233. QRT Wiring Diagram: Plant Grounding

Installation Notes (Refer to Figure 3-233): 1. Use three-conductor shielded cable to interface the RTDs to the terminal block. 2. Group 1 QRT – 10 mV full scale (low-range bridge and 10 Ω RTD) Group 2 QRT – 33.3 mV full scale (high-range bridge and 100 Ω RTD)

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3-35. QRT

3. Move the QRT line frequency jumper (located at the lower left hand corner of the QRT printed circuit card assembly) to the 50 Hz position if 50 Hz operation is desired. 4. One pair of QRT printed circuit card jumpers is used to connect Channel 1 and Channel 2’s power supply return and channel shield together. Therefore, Channel 1 and Channel 2 share a common power supply return and a channel shield. A second pair of QRT printed circuit card jumpers is used to connect Channel 3 and Channel 4’s power supply return and channel shield together. Therefore, Channel 3 and Channel 4 share a common power supply and a channel shield. 5. Since Channel 1 and Channel 2’s power supply return are connected together at the QRT, RTD1 and RTD2 must have their power supply return and shield connections tied together and grounded to a single point. Since Channel 3 and Channel 4’s power supply return are connected together at the QRT, RTD3 and RTD4 must have their power supply return and shield connections tied together and grounded to a single point. 6. If a QRT is to interface to both plant grounded and cabinet grounded RTDs, the following rules apply: Channel 1 and Channel 2 must interface to similarly grounded RTDs (that is, both RTDs must be cabinet grounded or both RTDs must be grounded to the same plant ground). Channel 3 and Channel 4 must interface to similarly grounded RTDs (that is, both RTDs must be cabinet grounded or both RTDs must be grounded to the same plant ground).

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3-35. QRT

IInstallation Data Sheet 2 of 4


TERMINAL BLOCK #8-32 SCREW 20B

CARD Channel Shield (1 of 4)

2

20A

PLUG-IN BRIDGE (−)

10 V POWER

1

19B

A

19A

18

17B

17

17A

16

15B

15

15A

14

(+)

(+)


RTD4

SHIELD (−) RETURN SHIELD

13B

13

13A

12


11B

11

11A

10

(−)

9B

09

9A

08

7B

07

7A

06

5B

05

5A

04

3B

03

3A

02

1B

01

(−)

4

10 V POWER

10 V POWER

(+)

(+)


(−)

10 V POWER

(+)


5 RETURN

5 RTD3

(+) SHIELD (−) +

RTD2

SHIELD (−) RETURN SHIELD RETURN (+)

5 RTD1

SHIELD (−)

1A

EDGE-CONNECTOR

FOR CABINET GROUNDED RTDS

Figure 3-234. QRT Wiring Diagram: Cabinet Grounding

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3-35. QRT

Installation Notes (Refer to Figure 3-234): 1. Use three-conductor shielded cable to interface the RTDs to the terminal block. 2. Group 1 QRT – 10 mV full scale (low-range bridge and 10 Ω RTD) Group 2 QRT – 33.3 mV full scale (high-range bridge and 100 Ω RTD) 3. Move the QRT line frequency jumper (located at the lower left hand corner of the QRT printed circuit card assembly) to the 50 Hz position if 50 Hz operation is desired. 4. One pair of QRT printed circuit card jumpers is used to connect Channel 1 and Channel 2’s power supply return and channel shield together. Therefore, Channel 1 and Channel 2 share a common power supply return and a channel shield. A second pair of QRT printed circuit card jumpers is used to connect Channel 3 and Channel 4’s power supply return and channel shield together. Therefore, Channel 3 and Channel 4 share a common power supply and a channel shield. 5. Since Channel 1 and Channel 2’s power supply return are connected together at the QRT, RTD1 and RTD2 must have their power supply return and shield connections tied together and grounded to a single point. Terminal block terminal number 5 allows RTD1 and RTD2 to be grounded at the cabinet halfshell. A hole is provided in the half-shell for the RTD cabinet grounding. Use a Number 6 screw and a Number 6 nut for this purpose. Since Channel 3 and Channel 4’s power supply return are connected together at the QRT, RTD3 and RTD4 must have their power supply return and shield connections tied together and grounded to a single point. Terminal block terminal number 14 allows RTD3 and RTD4 to be grounded at the cabinet halfshell. A hole is provided in the half-shell for the RTD cabinet grounding. Use a Number 6 screw and a Number 6 nut for this purpose. 6. If a QRT is to interface to both plant grounded and cabinet grounded RTDs, the following rules apply: Channel 1 and Channel 2 must interface to similarly grounded RTDs (that is, both RTDs must be cabinet grounded or both RTDs must be grounded to the same plant ground). Channel 3 and Channel 4 must interface to similarly grounded RTDs (that is, both RTDs must be cabinet grounded or both RTDs must be grounded to the same plant ground).

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3-35. QRT


CARD 1A

A

A

1B

1

1

3A

2

2

3B

3

3

(−) SHIELD (+)

5A

4

4

5B

5

5

7A

6

6

7B

7

7

9A

8

8

9B

9

9

11A

10

10

11B

11

11

13A

12

12

RTD 1

RETURN

RETURN (−) SHIELD

RTD 2

(+) (−) SHIELD (+)

13B

13

13

15A

14

14

15B

15

15

17A

16

16

17B

17

17

19A

18

18

19B

PE

PE

RTD 3

RETURN

RETURN (−) SHIELD

RTD 4

(+)

EDGE-CONNECTOR

Figure 3-235. QRT CE MARK Wiring Diagram (Grounded at the B Cabinet)

Installation Notes (Refer to Figure 3-235): 1. Use 3/C Shielded Cable. 2. Group 1 – 10 mV full scale (low-range bridge and 10 Ω RTD) Group 2 – 33.3 mV full scale (high-range bridge and 100 Ω RTD) 3. Move frequency jumper for 50 Hz operation. 4. When using standard A-B cabinet wiring (twisted pairs), jumpers on the QRT card tying the grounds and shields of channels 1 and 2 together, and the grounds and shields of channels 3 and 4 together, must be installed. When these jumpers are installed, only one ground wire of each pair should be connected. 5. The power supply return and shield of the RTD channel must both be grounded to a single point.

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3-35. QRT


CARD 1A

A

A

1B

1

1

3A

2

2

3B

3

3

(−) SHIELD (+)

5A

4

4

5B

5

5

7A

6

6

7B

7

7

9A

8

8

9B

9

9

11A

10

10

11B

11

11

13A

12

12

RTD 1

RETURN

RETURN (−) SHIELD

RTD 2

(+) (−) SHIELD (+)

13B

13

13

15A

14

14

15B

15

15

17A

16

16

17B

17

17

RTD 3

RETURN

RETURN (−) SHIELD

19A

18

18

19B

PE

PE

RTD 4

(+)

EDGE-CONNECTOR

Figure 3-236. QRT CE MARK Wiring Diagram (Grounded in the Field)

Installation Notes (Refer to Figure 3-236): 1. Use 3/C Shielded Cable. 2. Group 1 – 10 mV full scale (low-range bridge and 10 Ω RTD) Group 2 – 33.3 mV full scale (high-range bridge and 100 Ω RTD) 3. Move frequency jumper for 50 Hz operation. 4. When using standard A-B cabinet wiring (twisted pairs), jumpers on the QRT card tying the grounds and shields of channels 1 and 2 together, and the grounds and shields of channels 3 and 4 together, must be installed. When these jumpers are installed, only one ground wire of each pair should be connected. 5. The power supply return and shield of the RTD channel must both be grounded to a single point.

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3-36. QSC

3-36. QSC Speed Channel Card (Style 2840A75G01 and G02)

3-36.1. Description The Speed Channel Card (QSC) converts tachometer signal pulses directly into a 14-bit binary speed number (see Figure 3-237). This binary number can be read by a software program via the DIOB bus interface. The card also contains an analog output that is proportional to the input frequency. (For new applications, the QSS card is recommended).

Figure 3-237. QSC Block Diagram

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3-36. QSC

Block Diagram

PULSE TO VOLTAGE CONVERTER

ZERO CROSSING DETECTOR

JUMPER SELECTED RANGE 0-1500 RPM TO 0-6670 RPM

SETABLE PULSE CIRCUIT

+V

VREF

DELAY TO PREVENT SKEWING

LATCH UP COUNTER

INPUT

CLOCK

TIMING & CONTROL

LATCH

ADDRESS SELECT JUMPERS

READ ENABLE

ADDRESS COMPARE

ANALOG OUTPUT 0-10V

DIOB DATA

DIOB ADDRESS

A functional block diagram of the QSC is shown in Figure 3-238.

Figure 3-238. QSC Card Functional Block Diagram

3-36.2. Features The card counts zero crossing of the input signal for a sampling period and then latches the value to allow reading from the DIOB interface. This value consists of a 14-bit binary number that is simultaneously displayed on the cards front edge via 16 LEDs. To allow missing card detection, one bit (#15) is always high (“1”) and the other bit (#14) is always low (“0”). There are two groups of QSC cards.

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3-36. QSC

•

Group 1 has a sampling period of 1/8 second and the 14-bit binary output is equal to 1/4 of the input frequency.

•

Group 2 cards have a sampling period of 1/2 second and the 14-bit binary output is equal to the input frequency.

In addition, the card contains a 0 to 10 volt analog output that is proportional to 0% to 125% of the nominal input frequency. The nominal input ranges are 1.5, 1.8, 3.0, 4.0 and 6.67 kHz. These ranges are selected via jumpers which are located on the card (see Table 3-123 and Figure 3-239). Table 3-123. QSC Input Frequency Selection

Nominal Speed (Hz)

1 A

2 B

4 C

1.5K

8 D

16 E

32 F

64 G

128 H

X

1.8K

X

3.0K

X

3.6K

X

4.0K

X

6.67K

X

X

X

X X

X

X

X

X X

X

X

X

X

X

X

X

X

X

X = Jumpers to be installed for desired nominal speed

3-36.3. Specifications Inputs The Speed Channel (QSC) card accepts a sine wave input. The input may be connected to 120 Vac RMS without damage. Sensitivity:

0.5V P-P @ 36 Hz 5.0V P-P @ 4.5 kHz

Common Mode Voltage: 20V P-P (Max.) Nominal Input Speeds:

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1.5 kHz (90,000 RPM) 1.8 kHz (108,000 RPM) 3.0 kHz (180,000 RPM) 3.6 kHz (216,000 RPM) 4.0 kHz (240,000 RPM) 6.67 kHz (400,200 RPM)


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3-36. QSC

Input Impedance: 20 k ohms DIOB Output Data word: 16 Bits (Bits 0-13 = data, Bit 14 = 0, Bit 15 = 1, Bit 0 = LSB, Bit 13 = MSB) Update Rate1/8 second for Group 1 1/2 second for Group 2 Output:

Binary value that is 1/4 of the input frequency for Group1. Binary value equals the input frequency for Group2.

Accuracy 0.03% with one bit resolution (min,) over temperature range Analog Output Isolated Output Span10V Nominal Input Speeds1.5, 1.8, 3.0, 3.6, 4.0 and 6.67 kHz Output

0 to +10V proportional to 0 to 125% of nomina speed setting

Accuracy: 0.06% of span for 3.0, 3.6, 4.0 and 6.67 kHz ranges 0.09% of span for 1.5 and 1.8 kHz ranges Output Noise<5 mV P-P Output Load500 ohms or greater. Short circuit protection provided Output Limits−0.7V + 0.3V to +11V + 0.6V Reference Condition25 degrees C ambient, 13.0 V supply Temperature Coefficient+ 0.005% per degree F. Supply Coefficient0.02%/ volt

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3-36. QSC

3-36.4. Controls/Indicators The LEDs indicate the output value (see Figure 3-239)

LEDs

Speed Selection Jumpers

Figure 3-239. QSC Card Components

3-36.5. Wiring The QSC card employs the standard Q-Series front-edge connector. Eight jumpers are used to determine the DIOB address. Contacts supplied include two contacts for the speed input and two contacts for the analog output signal. See table below:

Pin #

Field Signals

15A

Speed input signal

17A

Speed input return

7B

Analog output source (+)

5B

Analog output return (−)

Power Supply Voltage

Minimum

Nominal

Maximum

Primary

12.4 V

+ 13.0 V

13.1 V

Optional Backup:

12.4 V

--

13.1 V

Current (Supplied by DIOB)

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400 mA


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3-37. QSD

3-37. QSD Servo Driver Card (Style 2840A78G01 through G04)

3-37.1. Description Group 01 is applicable for use in the CE MARK Certified System The Servo Driver (QSD) card is a position controller which interfaces the electronic control system via the UIOB to either two EH or two MH actuators. The QSD card positions the two EH or MH actuators, which operate the turbine steam valves of the BFPT and MSR systems. Figure 3-240 shows a typical application of a QSD card.

QSD Card

OB

UI

Position and Indicators

Drive Feedback Pushbuttons

Pos A

Pos B

A M

Drive Feedback

Valve “A”

Valve “B”

Field

M/A Station

Figure 3-240. QSD Typical QSD Card Application

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3-37. QSD

3-37.2. Features The QSD card has two modes of operation, which are:

•

AUTO – where the QSD card converts a 12-bit binary number from the UIOB into a position control signal to the EH or MH actuators

•

MANUAL – where the QSD works with a manual station to produce the position control signal to the EH or MH actuators

In Auto mode, the QSD card can be configured to control either EH or MH actuators with the insertion of on-card jumpers and resistors (see Table 3-125 and Figure 3245). When the EH actuator type is selected, the output control signal to the EH actuator is determined by applying a proportional plus integral control action to the error between the desired and actual values of the actuator position. The EH actuator position is determined by a Schaevitz DC-DC LVDT at the actuator. When the MH actuator type is selected, the output control signal to the MH actuator is determined by applying an adjustable gain to the converted 12-bit binary number. The output control signal to the MH actuator is adjustable from 0 to 5 VDC or 0 to 10 VDC. In Manual mode, the QSD card works with a manual station (M/A). The M/A Station increases or decreases the output control signal through the RAISE and LOWER pushbuttons. Indicator lamps on the M/A Station display the valve position. The QSD card contains a two-speed manual clock and the control logic used during Manual mode operations. Operating mode selection is made from the UIOB. Auto mode selection is prevented when the UIOB controller is not ready. Additionally, a watchdog timer switches the card from Auto to Manual mode if the QSD card is not periodically serviced by the UIOB controller. The QSD card is available in one group (G01). Electrical connection to the QSD card is made through a 34-pin rear-edge connector (UIOB) and a 56-pin front-edge connector (M/A Station and Field Connections).

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3-37. QSD

3-37.3. Specifications Block Diagram

Offset TP4 JDA MASTER CLEAR FAST LOWER RAISE AUTO MANUAL

U I O B

UIOB Interface

P+I

MANUAL AUTO READY ALIVE

Control Logic

JDA

Span RFA

Up/Down Counter

D/A Output D/A

TP3

(-)

TJ Common TJ

+24 VDC

Direct

LVDT Gain

LVDT Zero

LVDT Drive TJ

Jumpers

P+I

Valve Coil Drives

Position Output

(-)

Position Feedback

Output A Offset TP2 JDB P+I

TP1

(-) Span

TJ: Test Jack TP: Test Point

JDB

+24 VDC

Direct

RFB P+I LVDT Gain

Jumpers LVDT Zero

(-)

Valve Coil Drives

LVDT Drive TJ Position Output Position Feedback

Output B

Figure 3-241. QSD Block Diagram

Block Diagram Description The following block diagram descriptions apply to Figure 3-241 through Figure 3-244.

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3-37. QSD

Power-Up and Master Clear When power is applied, the power-up control logic initializes the card to Manual mode and initiates RESET and CLEAR signals which set up the QSD card’s logic. Additionally, this logic provides a CLEAR to the up/down counter on receipt of a MASTER CLEAR from either actuator. Up/Down Counter and D/A Converter The up/down counter holds the 12-bit data count for control of either EH or MH actuators through the D/A converter. In Auto mode, the counter is loaded with a 12bit actuator demand from the UIOB controller. Figure 3-242 shows the data word coming from the UIOB which contains the 12-bit demand for the up/down counter. In Manual mode, the counter is incremented or decremented by the M/A Station’s RAISE or LOWER push-button. Manual Mode In Manual mode, the up/down counter driving the D/A converter is clocked up or down when the RAISE or LOWER push-button is pressed on the M/A Station’s front panel. The rate at which the up/down counter is clocked is determined by whether the FAST push-button on the M/A Station’s front panel is pressed and by separate plug-in resistors for the fast and slow clocks (see Controls and Indicators). The clock (fast or slow) operates at a constant rate when enabled. As a result, the output of the D/A converter is a linear ramp while the RAISE or LOWER pushbutton remains depressed, causing the up/down counter to count. When jumper A is not installed, the up/down counter holds its last value if neither RAISE nor LOWER is pressed. In this case, when both are pressed, LOWER takes precedence over RAISE. If jumper A is in place, the counter holds if both buttons are pressed or neither button is pressed. Except for the KEEP ALIVE, GO TO ALIVE, and GO TO MAN bits (Figure 3-242), the output from the UIOB controller is ignored in Manual mode.

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3-37. QSD

Input and Output Bit Patterns

Bits 15 14 13 12 11 10

9

8

7

6

5

High Byte

4

3

2

1

0

Low Byte L S B

M S B Up/Down Counter Data Not Used 1 = Go to Manual 1 = Go to Auto 1 = Keep Alive

Figure 3-242. QSD Card Input Data

Bits 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

L S B

M S B Up/Down Counter Data 1 = Card in Place 1 = Ready 1 = Manual, 0 = Auto 1 = Auto Push-button

Figure 3-243. QSD Card Output Data

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3-37. QSD

Manual to Auto Transfer Sequence To initiate a transfer from Manual to Auto mode, the operator must press the AUTO push-button at the M/A Station’s front panel. If jumper C is installed, the AUTO push-button signal generates an AUTO REQUEST, announcing the operator’s request. If jumper C is not installed, the UIOB controller must determine if the operator pressed the AUTO push-button. When the AUTO push-button is pressed, its status is latched and is available in the QSD’s output data word (shown in Figure 3-243) for the UIOB controller to read.The UIOB controller sends back a GO TO AUTO bit (shown in Figure 3-242) when it sees that the operator pressed the AUTO push-button. If jumper B is in place, the GO TO AUTO bit generates an AUTO REQUEST. If jumper G is installed, the QSD must be READY before an AUTO REQUEST is granted. To be READY, the QSD must be in Manual mode and be ALIVE (watchdog not timed-out), and the UIOB controller must output the same value already contained in the upper 8 bits of the up/down counter. The KEEP ALIVE bit, GO TO AUTO bit, and the correct data can all be contained in the same output from the UIOB controller (Figure 3-242) if desired. The QSD card grants the AUTO REQUEST and switches to Auto mode if the above conditions are satisfied and a MANUAL REQUEST has not been initiated. Auto Mode In Auto mode, data from the UIOB controller is loaded into the up/down counter which drives the D/A converter. The QSD card’s UIOB interface logic latches the two byte input data (Figure 3-242) from the UIOB and transfers the 12-bit demand to the up/down counter. RAISE, LOWER, and FAST inputs to the QSD from the M/ A Station are ignored in Auto mode.

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3-37. QSD

Auto to Manual Transfer Sequence Several events can generate a MANUAL REQUEST which initiates a transfer from Auto to Manual mode. These events are:

• •

An operator pressing the MANUAL push-button at the M/A Station’s front panel. RESET signal due to low power supply voltage.

If appropriate enabling jumpers are installed, three other events can also cause MANUAL REQUESTS:

• • •

Card not ALIVE (jumper D is installed). GO TO MAN bit from UIOB controller (jumper E is installed). RAISE or LOWER push-button pressed on M/A Station’s front panel (jumper F is installed).

If a MANUAL REQUEST is made, it immediately transfers the QSD to Manual mode even if an AUTO REQUEST is present. A MANUAL REQUEST also prevents an AUTO REQUEST from being granted if the QSD is already in Manual mode. Input Data to QSD from UIOB When data is written to the QSD from the UIOB, it has a two byte format as pictured in Figure 3-242. The 12-bit digital valve position is loaded into the up/down counter and used to control the EH or MH actuators. The GO TO AUTO and GO TO MANUAL bits of the input data cause continuous AUTO or MANUAL REQUESTS, respectively, when they are set, for they are latched by the QSD card. The KEEP ALIVE bit is not latched when received by the QSD. To keep the watchdog timer from timing out, a high KEEP ALIVE bit must be written to the card within the watchdog time-out period (Table 3-126). Output Data from QSD to UIOB The format for QSD card output data transfers to the UIOB controller is shown in Figure 3-243 with the up/down counter data contained in bits 0 through 11 and the QSD card’s status contained in bits 12 through 15. CAUTION The QSD card should not be read continuously at a rate faster than 100 times per second.

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3-37. QSD

Watchdog Timer The watchdog timer is started on receipt of a high KEEP ALIVE bit from the UIOB (see Figure 3-242). If the UIOB does not write another KEEP ALIVE bit to the QSD within the timer’s selected time-out period, the timer times-out and ALIVE goes high. The ALIVE = high signal resets the card to Manual mode. A switch provides user selection of watchdog time-out periods as listed in Table 3-126 under Controls and Indicators. Valve Actuator Drive Circuits The operating characteristics of these circuits (A and B, which are identical) are determined by the plug-in resistors, potentiometers and jumpers JDA or JDB. The block diagram of Figure 3-244 shows both the EH and MH actuator applications of these circuits. See Controls and Indicators for a detailed description of the plug-in resistors, potentiometer adjustments, and jumper installations. When this circuit is set up for EH actuator operation, the plug-in resistors and jumpers are set up for a closed-loop operation as follows:

• • •

RFA (or RFB) installed JDA (or JDB) removed RDA (or RDB) removed

For EH actuator application, both outputs (COIL1 and COIL2) are used to drive the EH valve actuator. The D/A OUT signal from the D/A converter (Figure 3-244) drives the actuator via the summing amp and the P + I amp. With resistor RDA (or RDB) removed, the linear amp provides P + I amplification. The resulting drive to the actuator is determined by the error signal and indicates the desired new actuator position. The actual valve position is fed back to this circuit as the LVDT differential signal. This signal is presented to the LVDT calibration circuit. The output of the LVDT calibration circuit is presented to the summing amp as a 0 to (−)10 VDC level equivalent to the actual position of the valve. This actual position signal is summed with the desired position signal (D/A OUT), producing the error drive signal to the valve actuator coils. As the difference between the desired and actual valve position decreases, the error drive signal decreases, until it is equal to zero (actual position = desired position). Additionally, the output of the LVDT calibration circuit is displayed on a position meter on the M/A Station indicating the actual valve position.

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3-37. QSD

D/A Out Setpoint 0 to + 10 V

Coil 1

P+ I

Error K

(

1+TS TS

EH Valve Actuator

)

LVDT Calibration Gain & Offset

1/TES Coil 2

Position 0 to (-)10 V

Position Meter M/A Station

0 to + 10 V

DC LVDT Position Indication

D/A Out

MH Valve Actuator (Torque Motor)

Gain and Offset Amp.

LVDT Calibration

0 to + 10 V

Position Meter M/A Station

DC LVDT Position Indication

Figure 3-244. EH and MH Actuator Applications

When this circuit is set up for MH actuator operation, the plug-in resistors and jumpers are set up for an open-loop operation as follows:

• • •

RFA (or RFB) removed JDA (or JDB) installed RDA (or RDB) installed

Power Requirements

•

Primary Voltage:

12.4 VDC minimum 13.0 VDC nominal 13.1 VDC maximum

•

Backup Voltage:

12.4 VDC minimum 13.1 VDC maximum

•

Current: With EH actuator – 1.2 A maximum With MH actuator – 1.6 A maximum

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3-37. QSD

Field Interface As shown in the block diagram of Figure 3-241, the control circuitry for each actuator is identical. The only exceptions are the provisions for individual calibration of the various circuit parameters which depend on selected resistor values (see Table 3-129). Valve Coil Drive (Two Circuits)

• •

EH actuator: two current outputs of +24 mA each into 80Ω MH actuator: a single output, adjustable from 0 VDC through (-)10 VDC full scale across 100 Ω minimum. (MH output is negative with respect to common).

Position Feedback (Two Circuits) A high impedance differential input receives the position signal from a demodulating Linear Variable Differential Transformer (DC LVDT), where:

• •

Input Scan: +1.5 VDC to +15.0 VDC depending on LVDT type and stroke

•

Common Mode Voltage: +10 VDC maximum

Input Impedance:

Differential (with floating source), 400KΩ Inputs (tied together) to common, 150 KΩ

LVDT Drive (Two Circuits)

• • •

+24 VDC +1.2 V at 25 mA Supply Voltage Coefficient: +0.4%/volt Average Temperature Coefficient: +0.025%/°C

Master Clear The Master Clear is a self-powered differential input connected to a field contact. Closing the field contact clears the up/down counter but does not switch the QSD card to Manual mode. Specifications include:

• • • •

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Open Circuit Voltage: 42 VDC +8 V Closed Circuit Current: 15 mA maximum Contact and Wiring Resistance: 100Ω maximum Delay: 6 msec. maximum (The delay is from the time of contact closure to the appearance of 0.0 VDC at the D/A output.)


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3-37. QSD

3-37.4. Operator Interface DIM Inputs DIM inputs are typically connected to operator pushbuttons. Specifications include:

• • • •

Input Voltage Range: (−)0.5 V to +30 VDC maximum Low Input Voltage: 2.0 VDC maximum High Input Voltage: 10.0 VDC minimum Delay: 0.75 msec. maximum

DIM Outputs DIM outputs are typically connected to operator panel lamps. Specifications include:

• • • •

High Output Voltage: Open Collector, 30 VDC maximum High Output Leakage Current: 0.5 mA maximum Low Output Voltage: 1.0 VDC maximum Low Output Current: 250 mA maximum

Position Output (Two Circuits)

•

Output Span: 0 through 10 VDC which corresponds to 0 through 100% of actuator position

• •

Load Resistance: 2 KΩ minimum

•

Temperature Coefficient: +0.02% of span/°C

Accuracy: Adjustable to within 0.1% of span, measured by comparing the position output with the position feedback input

Analog Controller Each of the two QSD card controllers is jumper programmed as either a Direct Output or a P + I controller. Direct Output Controller (MH Actuator)

• • M0-0053

Offset: (−)1.0 VDC to +1.0 VDC Span: 1.0 VDC to 10 VDC 3-468 Westinghouse Proprietary Class 2C

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3-37. QSD

• • •

Accuracy: +0.1% of span Temperature Coefficient: +0.02% of span/°C Output: Single output adjustable from 0 to (-)10V full scale across 100 Ω minimum. (Output is negative with respect to common).

P + I Controller (EH Actuator)

• • • • • •

Offset: (−)10% to +10% of demand Span: Actuator position from 25% to 200% for 100% demand Accuracy: Position Feedback within 0.1% of span for adjusted demand Temperature Coefficient: +0.02% of span/°C Gain: 1.22 to 122* Reset Time Constant: 0.5 sec to 10 sec* Note* The gain and reset time constants are interrelated and controlled by the resistors. The relationships are detailed in Table 3-131.

Signal Interface The standard front-edge connector interfaces the QSD to the M/A Station and the field. Table 3-124 lists the connector’s pin designations. Table 3-124. QSD Front-Edge M/A Station and Field Connector

Pin # Signal Name 1A Ground (System Common) 2A -Master Clear Contact Input 3A +Master Clear Contact Input 4A Ground (Return to pins 12A, 13A) 5A Ground (Return in pins 8A, 9A) 6A Ground (Return to pin 10A) 7A Ground (Return to pin 11A)

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Pin # 1B Ground 2B Ground

Signal Name

3B

Ground

4B 5B 6B 7B

Ground (Return to pin 16B) Ground (Return to pin 17B) AUTO IN FAST


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3-37. QSD

Table 3-124. QSD Front-Edge M/A Station and Field Connector (Cont’d)

Pin # 8A 9A 10A 11A 12A 13A 14A 15A 16A 17A 18A 19A 20A 21A 22A 23A 24A 25A 26A 27A 28A

Signal Name COIL 1 -- “A” actuator valve coils COIL 2 -- “A” actuator valve coils LVDT Drive “B” actuator LVDT Drive “A” actuator COIL 1 -- “B” actuator valve coils COIL 2 -- “B” actuator valve coils -LVDT Feedback “B” actuator +LVDT Feedback “B” actuator -LVDT Feedback “A” actuator +LVDT Feedback “A” actuator SLOT (NO PIN) Unused Unused UIOB Grounds UIOB Grounds UIOB Grounds UIOB Grounds UIOB Grounds UIOB Grounds UIOB Grounds UIOB Grounds

Pin # 8B RAISE 9B

Signal Name

LOWER

10B MAN IN 11B READY 12B AUTO 13B

ALIVE

14B

MAN 2

15B

MAN 1

16B

0 - 10 V Position Ind. (“B”)

17B

0 - 10 V Position Ind. (“A”)

18B SLOT (NO PIN) 19B Unused 20B Unused 21B ASEL0 22B ASEL1 23B ASEL2 24B ASEL3 25B ASEL4 26B ASEL5 27B ASEL6 28B ASEL7

In Table 3-124: pins 1A through 17A are Field connections, pins 1B through 17B are M/A Station connections, pins 21A through 28A and 21B through 28B are UIOB Address Selection connections. The following front connector pins are tied together on the QSD: 1A, 4A, 5A, 6A, 7A, 1B, 2B, 3B, 4B, and 5B. Pins 1A and 1B should also be tied to the System UIOB Ground at one point in the system.

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3-37. QSD

3-37.5. Card Addressing The QSD card address is determined by the eight jumpers detailed in Appendix B. Inserting a jumper between an ASELX pin on the B side and the corresponding pin on the A side encodes a “1” on the address line. The QSD may be read from or written to via the UIOB only if the address from the UIOB is the same as that selected by the A and B pins on the front-edge connector.


RZA, RGA

RF, RS

RZB, RGB

LEDs

RFB, ROB, RSB, RTB,

Watchdog Timeout

RDB Gain and Zero Pots.

Auto/Manual Selection Jumpers

JDB

Span B Pot.

Test Jacks

Span A Pot.

Offset B Pot.

ABCDEFG

TP1 - 4

RFA, ROA, D/A Invert RSA, RTA, Buffers RDA

Offset A Pot. JDA

Figure 3-245. QSD Card Outline and User Controls

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3-37. QSD

Front Edge Potentiometers (total of 8):

• • • •

LVDT ZERO (One each circuit A and B) LVDT GAIN (One each circuit A and B) OFFSET (One each circuit A and B) SPAN (One each circuit A and B)

Test Jacks (total of 4):

• • • •

POSITION A POSITION B D/A OUTPUT COMMON

Test Point Pins:

• • • • • •

TP1 (Coil 2, circuit B) TP2 (OFFSET, circuit B) TP3 (Coil 2, circuit A) TP4 (OFFSET, circuit A) JDA (Coil 1, circuit A) JDB (Coil 1, circuit B)

LED Indicators

• • • • M0-0053

POWER ON MANUAL READY ALIVE


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3-37. QSD

Jumpers Table 3-125 provides a list of QSD card jumpers and the selected operational card characteristic produced when each is installed. The location of these jumpers is shown on Figure 3-245. Table 3-125. QSD Card Jumpers

Jumper

Description

JDA

Installed for direct configuration of circuit A.

JDB

Installed for direct configuration of circuit B.

A

When installed, simultaneous RAISE and LOWER signals from M/A Station cause the output to hold.

B

When installed, the GO TO AUTO bit from the UIOB Controller produces an AUTO REQUEST (Auto mode).

C

When installed, pressing the AUTO push-button at the M/A Station produces an AUTO REQUEST.

D

When installed, a timeout (ALIVE = high) from the Watchdog Timer causes the card to switch to Manual mode.

E

When installed, the GO TO MAN bit from the UIOB Controller places card in Manual mode.

F

When installed, a RAISE or LOWER signal from the M/A Station places card in Manual mode.

G

When installed, a READY state must be latched before an AUTO REQUEST is granted, placing card in Auto mode.

Watchdog Timeout Select Switch The Watchdog Timeout switch (Figure 3-245) sets timeout periods as listed in Table 3-126. Table 3-126. QSD Watchdog Timeout Selections

Switch Segments

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H

J

K

0

0

0

0

0

1

Watchdog Timeout All times +25% 1/16 second (62 msec) 1/8 second (125 msec)


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3-37. QSD

Table 3-126. QSD Watchdog Timeout Selections (Cont’d)

Switch Segments

Watchdog Timeout All times +25%

H

J

K

0

1

0

1/4 second (250 msec)

0

1

1

1/2 second (500 msec.)

1

0

0

1 second

1

0

1

2 seconds

1

1

0

4 seconds

1

1

1

8 seconds

D/A Converter Input Buffer Selection Under normal conditions non-inverting buffers (Figure 3-245) are used as inputs to the D/A converter. However, these can be replaced by inverting buffers, which cause the D/A converter to behave inversely. With the inverting buffers installed, input data of 000 (hexadecimal) produces +10 VDC at the output from the D/A converter output, and input data of FFF (hexadecimal) produces 0 VDC at the output.

Up/Down Counter Clock Rate Selection, Manual Mode Selection of which clock (FAST or SLOW) is made by the FAST push-button at the M/A Station. The FAST clock’s rate is determined by selecting values for plug-in resistor RF, while the SLOW clock’s rate is determined by selecting values for plug-in resistor RS (Figure 3-245). These clocks, by stepping the counter in the Manual mode, produce a linear ramp analog level to the valve actuator at rates that are adjusted by changing the resistor value. Table 3-127 indicates the time for full scale ramp generation and percent of change per minute for plug-in resistor values in both fast and slow applications. Table 3-127. QSD Clock Rate Selection

Full Scale Ramp

Percent/Minute

RF or RS Value

Fast

Slow

2 KΩ

15 sec.

30 sec.

400

200

5 KΩ

25 sec.

50 sec.

240

120

10 KΩ

37 sec.

74 sec.

162

81

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Fast

Slow

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3-37. QSD

Table 3-127. QSD Clock Rate Selection (Cont’d)

Full Scale Ramp

Percent/Minute

RF or RS Value

Fast

Slow

Fast

Slow

20 KΩ

70 sec.

140 sec.

86

43

50 KΩ

175 sec.

350 sec.

34

17

100 KΩ

330 sec.

660 sec.

18

9

Analog Output State Plug-in Resistor Selection Figure 3-246 shows an equivalent circuit for the Analog Output Circuits (A and B). Each circuit contains up to seven plug-in resistors determining specific characteristics per application needs. Table 3-128 lists each resistor, its function, and typical values for both Direct Output or P + I controller applications. Additionally, operating equations are provided as an aid in determining the specific parameters for each application.

RIN D/A Out 0 to 10 VDC

SPAN RSX

V1

RDX EH Valve Coils

ROS Bias ± 1.2 VDC

50K

V2

ROX

RTX

JDX

1µf

RLP Position V3 Feedback 0 to (-) 10 VDC

RFX

330

80

330

80

50K +

VO IO

Figure 3-246. QSD Analog Output Stage

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3-37. QSD

Resistor locations are illustrated in Figure 3-245. Table 3-128. QSD Analog Output Stage Plug-in Resistors

Typical Values*

Resistor

Function Controlled

Direct Output

P + I Controller

RZA or RZB

LVDT Zero

10 KΩ

10 KΩ

RGA or RGB

LVDT Gain

2 KΩ to 20 KΩ

2 KΩ to 20 KΩ

RFA or RFB

Position Feedback

open

0 to 500 KΩ

ROA or ROB

Offset

0 to 200 KΩ

0 to 500 KΩ

RSA or RSB

Span

24.9 KΩ

0 to 500 KΩ

RTA or RTB

Time Constant

open

500 KΩ to 10 MΩ

RDA or RDB

Direct Output

10 KΩ to 200 KΩ

open

Note The presence or absence of these resistors, as well as the resistor values varies greatly from one application to the next. Therefore, the information provided here is of a general nature. (*See calibration notes to select the resistor for the desired system performance.)

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3-37. QSD

Direct Output Operating Equations

•

Voltage Gain: * RD x Vo 1 ------ = ( − )  ----------  --------------------------------------------  R IN   1 + ( RD x × 1µf )S VI

Note* Filter Term when RTx = jumper

•

Span: RD x SPAN = 10VDC  ----------  R IN 

•

Offset (referred to D/A OUT): R IN OFFSET = ± 1.2VDC  ---------  R OS

•

Filter Time Constant (when RTx= jumper): TC = ( RD x )1 µf

P + I Controller Operating Equations

•

Gain: ∆I 1 500Ω RT x ---------o- = -------------  ----------  -------------------------------------------    410Ω R LP 1 + ( RT x × 1µf )S ∆V 2 where: 500Ω = Scale Factor = V2 10 VDC ------ = --------------------Io 20 mA

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3-37. QSD

•

Proportional Gain: RT x 500 RT x K = ---------  ---------- = 1.22  ----------  R LP  410  R LP 

•

Reset Time Constant: TC = ( RT x )1 µf

•

Offset: R IN OFFSET = ± 1.2VDC  ---------  R OS

•

Span (Position Feedback vs. D/A OUT): R IN SPAN =  ---------  R LP

Calibration Notes This description provides general QSD calibration information. LVDT Calibration Plug-in resistors RZA and RZB should be 10KΩ. Plug-in resistors RGA and RGB should be selected to meet position feedback requirements as follows: Table 3-129. LVDT Calibration resistor Selection

Position Feedback from LVDT

RGA or RGB Value

+1 VDC to +2.5 VDC

2KΩ

+2.5 VDC to +6.0 VDC

5KΩ

+5.0 VDC to +12.5 VDC

10KΩ

+10.0 VDC to +20 VDC

20KΩ

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3-37. QSD

The LVDT ZERO potentiometer of each analog output circuit (A and B) is adjusted for 0 VDC at the POSITION output, with the LVDT in its minimum position. The LVDT GAIN potentiometer is adjusted for 10 VDC at the POSITION output, with the LVDT in its maximum position. Direct Output Calibration The A and B Analog Output Circuits are identical and independently configured and calibrated. The plug-in resistor configuration is selected as indicated in Table 3-130. Table 3-130. QSD Direct Output Resistors

Resistor

Range

Recommendation

ROA and ROB

0 to 200 KΩ

As desired

RSA and RSB

0 to 200 KΩ

24.9 Ω

RTA and RTB

jumper or open

As desired

RDA and RDB

10KΩ to 200KΩ

Where: Desired Span 1 to 3 VDC 3 to 6 VDC 6 to 10 VDC

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RD Value 10KΩ 20KΩ 50KΩ

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3-37. QSD

P + I Controller Calibration The A and B Analog Output Circuits are identical and independently configured and calibrated. The plug-in resistor configuration is selected as indicated in Table 3-131. Table 3-131. QSD P + I Controller Resistors

Resistor

Range

Recommendation

RFA and RFB

0 to 500 KΩ

ROA and ROB

0 to 500 KΩ

RSA and RSB

0 to 500 KΩ

RTA and RTB

500KΩ to 10MΩ

Use the lowest possible values

Where the Gain Range vs. Reset Time Constant is as follows: TC/GAIN 1 sec/2.44 to 24.4 10 sec/24.4 to 122

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3-37. QSD

3-37.7. Installation Data Sheet For CE MARK Certified System A

CARD

1

A Master Clear (-)

1

1

2

2

10B

3

3

Manual IN/

8B

4

4

Raise IN/

7B

5

5

Fast IN/

9B

6

6

Lower IN/

5A

7

7

(−)

8

8

9

9

(SHIELD) A-Servo Coll #1 (+)

10

10

(−)

11

11

9A

12

12

(SHIELD) A-Servo Coll #2 (+)

16A

13

13

(−)

14

14

17A

15

15

(SHIELD) A-LVDT Feedback (+)

5B

16

16

(−)

17

17

18

18

(SHIELD) A-Position (+)

PE

PE

2A

8A

17B EDGE-CONNECTOR

A 3A

2

A Master Clear (+)

1

1

2

2

3

3

4

4

(-)

5

5

11A

6

6

(SHIELD) 24 VDC (+)

4A

7

7

(−)

8

8

9

9

(SHIELD) B-Servo Coll #1 (+)

10

10

(−)

11

11

13A

12

12

(SHIELD) B-Servo Coll # 2 (+)

14A

13

13

(−)

14

14

15A

15

15

(SHIELD) B-LVDT Feedback (+)

4B

16

16

(−)

17

17

18

18

(SHIELD) B-Position (+)

PE

PE

7A

12A

16B

Figure 3-247. QSD CE MARK Wiring Diagram

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3-37. QSD

Installation Notes (Refer to Figure 3-247): 1. Analog inputs and outputs must use individually-shielded twisted pair cables, with the shields connected to earth ground at the B cabinet, as shown. 2. Digital inputs must use shielded cable (an overall shield is acceptable), with the shield connected to earth ground at the B cabinet.

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3-38. QSE

3-38. QSE Sequence of Events Recorder (Style 7380A36G01 and G02)

3-38.1. Description Groups 01 and 02 are applicable for use in the CE MARK Certified System The QSE Card is a DIOB-compatible single-card sequence of events subsystem which provides monitoring of field status points, recording, and time tagging of changes in plant status (see Figure 3-248). Through a rear-edge connector, the QSE interfaces with the Distributed I/O Bus (DIOB), a collection of parallel wires (signal, power, and ground), into which point cards are inserted. The digital inputs are brought onto the card via a front-edge connector. The QSE interfaces to sixteen field contacts using a common return line. On-card contact-wetting supply, signal conditioning, and optical isolation are provided. Digital filtering is used to reject input signal changes with less than a minimum predetermined time interval (3.5 msec. for Group1 and 3 msec. for Group2). The outputs of the digital filters can be read at any time by the DIOB controller as “current status.” The card contains a “mask register” which can be both read or written by the DIOB controller. The mask register content determines which bits are checked for change of state and cause entries in the Event Buffer. During the power-up the mask register is set to all “ones.” On Group 2 QSE cards, the mask bits have the additional function of holding the corresponding Chattering Flag and Chattering Counter in the reset condition, as long as the mask bit is set to zero. The monitoring for chattering starts at the time the mask bit is set to 1. Dual Event Buffers are used to permit reading of one Event Buffer, while events are entered into the other Event Buffer. The Group 2 QSE card has the additional feature of recognizing “chattering” on any of its sixteen inputs. “Chattering” is defined as a condition when the number of input changes exceed four within a specified time interval. This time interval can be set from 20 to 255 msec. in firmware only. After the PROMs are “burned” in the time interval is constant.

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3-38. QSE

Time Tagging of the status changes is accomplished with the aid of the on-card clock. The clock has a one-minute range, a resolution of 1/8 millisecond for Group1 and 1 msec. for Group2, and an accuracy of +0.01 percent. The clock can be synchronized by a “Group DIOB Write.”

DIOB Bus Data

Address

Control

Address Decoder

Data Interface

Buffer #1

Buffer #2 DEMUX

Mask Status Curr. Inp

Real Time Clock

Reg

Events Storage Memory

Control Logic P07

Digital Debouncer 0

... 8

2: 1 MUX 0

...15

16 Optical Isolators and Signal Conditioners

RTN

0

Oscillator

On-Card Isolated Power Sply. +10VDC +48VDC

...15

Figure 3-248. QSE Block Diagram

The frequency of the synchronization is controlled by the DIOB controller and it should occur at least once per second.

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3-38. QSE

To facilitate QSE-DIOB controller communication, status and control words are used. The status register can be read by the DIOB controller at any time. It contains the Enable Stack Operation (freeze) bit (Bit 7), QSE Card OK bit (Bit 6), the Event Buffer Overflow bit (Bit 5) and the Number of Events in Buffer field (Bits 0-4). Bit 4 in this field indicates that the Event Buffer is full. The control word is used to set or reset the Enable Stack Operation (freeze) bit. When the “freeze” bit is set, new events will be entered into the second Event Buffer. The status word is read by the DIOB controller to determine the number of events (N) in the first Event Buffer. The DIOB controller performs 2N reads from the Event Stack location to collect all entries. (Event Buffer and Event Stack are the same.) After the Event Buffer is read, the control word is used to reset the “freeze” bit. The first Event Buffer is now reset and is available for storing new events.

3-38.2. Features The QSE card is available in groups (G01 and G02) and has the following features:

• • • • • • • • • • • • •

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DIOB-compatible, single card sequence of events subsystem. Sixteen inputs that also can be read directly. On-card 48 V contact-wetting supply. IEEE surge withstand capability. 500 VDC isolation from DIOB. Optical coupling. Optical isolation for each input. Mask register for flexible sequence of event recording. Dual event storage memory. LED power supply operating indicators. Resolution event recording of 1/8 msec. for Group 1 and 1 msec. for Group2. On-card one-minute range synchronizable clock. Recognize, mark and inhibit chattering inputs (Group 2 only)


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3-38. QSE

3-38.3. Specifications Contact-Wetting Voltage Supplied by QSE All inputs are optically isolated. Minimum

Nominal

Maximum

Open Circuit Voltage (Volts)

42

48

56

Closed Contact Current (mA)

7

14

21

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3-38. QSE

Input Requirements Field Cable and Contact: Minimum

Nominal

Maximum

Leakage Resistance (KΩ)

50

--

--

Group 1 Propagation Delay (msec.)

3.5

4

4.5

Group 2 Propagation Delay (msec.)

3

--

4

Input Signal Rejection Group 1 Input Signal Duration Group 2 Input Signal Duration Always Rejected

< 3.5 msec.

< 3.0 msec.

Always Passed

> 4.5 msec.

> 4.0 msec.


Nominal

Maximum

Primary Voltage

12.4 V

13.0 V

13.1 V

Optional Backup

12.4 V

--

13.1 V

--

1A

--

Current

Electrical Environment IEEE surge withstand capability (Ref. IEEE 472-1974) (Ref. ANSI C37.902-1974). 500 VDC or peak AC between input command and DIOB ground.

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3-38. QSE

Cabling Limitations Since up to 1.2 mA could flow through any open contact shunt resistance (RS), from the +48 volt supply (with open contacts, no current can flow from the +10 voltage supply due to reverse biased diodes), 50K ohms is required as a minimum shunt resistance in order to maintain the high level contact-wetting voltage. As an example, if the open contact shunt resistance was 25K ohms, the nominal voltage present across the open contacts would only be 25 volts. However, the minimum open contact shunt resistance that would permit open contacts to be recognized by the QSE card as open contacts is 10K ohms. In order to ensure that closed contacts will always be recognized as closed by the QSE card, the sum total of the contact series resistance and cable resistance must be less that 60 ohms. See Figure 3-249. Table 3-132 shows cable length limitations. Table 3-132. Maximum Cable Lengths (Assume RC = 0) for QSE Card

Cable Wire Gauge

For 16 Commons/Card (RR = 0) Length given is the distance from contacts to termination

For 1 Common/Card Length of return = length of cables to contacts

12 AWG

15,000 feet

1,800 feet

14 AWG

10,000 feet

1,200 feet

16 AWG

6,000 feet

700 feet

18 AWG

4,000 feet

500 feet

20 AWG

2,500 feet

300 feet

22 AWG

1,500 feet

200 feet

Contact Cycle Time If the maximum QSE on-card generated contact-wetting voltage is to be applied to plant contacts that interface to the QSE card, the elapsed time between the contact’s opening and its subsequent closure must be greater than 15 msec.

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3-38. QSE

ONE OF SIXTEEN QSE CONTACT INPUTS

RLINE CONTACT

RS

COMMON RC

RR

FROM OTHER CONTACTS

FOR A CLOSED CONTACT: RC + RLINE + 16RR < 60 OHMS RS = OPEN CONTACT SHUNT RESISTANCE RC = CLOSED CONTACT SERIES RESISTANCE RR = RESISTANCE OF THE COMMON RETURN LINE (IF ANY) RLINE = RESISTANCE OF NON-COMMON LINE LENGTH TO AND FROM CONTACTS

Figure 3-249. Contact Wiring

Event Buffer Capacity Two Event Buffers are used, each having a capacity of 32 16-bit words. Since each event requires two 16-bit words, the total capacity of the two buffers is 32 events.

Resolution Event time tagging resolution is 1/8 msec. for Group 1, and 1 msec. for Group 2.

Accuracy One millisecond, relative to synchronizing.

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3-38. QSE

Rate of Input Change Monitor (Group 2 Only) In order to recognize “Chattering”, the Group 2 QSE card has an additional counter for each input channel to accumulate the number of changes, and a common counter to measure the time interval (Ti). Every time the input is scanned, the corresponding mask bit is tested. If the mask bit is 0, then the Chattering Flag and Chattering Counter assigned to the input is reset. Monitoring for chatter starts when the mask bit is set to one. At the time of an input change, the corresponding input counter is checked for a count of four. If the counter is set to four, the Chattering Flag is set and the change is entered into the Event Register with Bit 7 in the Point ID set to a 1. If the corresponding input counter is less than four, it is incremented and the change is entered to the Event Register. No entry is made to the Event Register if the Chattering Flag (corresponding to the input channel) is set. At the end of each time interval (Ti), all the input counters are decremented by one count. When an input counter reaches the zero count, the corresponding Chattering Flag is reset allowing future changes to enter the Event Register. The input counters will not “underflow” or exceed the count of four. Time Interval (Ti) Ti = 100 msec. Input rates higher than 1/Ti will set the Chattering Flag. Rates lower than 1/Ti will reset it.

3-38.4. Signal Interface DIOB Interface The QSE card is interfaced to the DIOB via the QSE’s pin J1 connector. See Table 3-133 for a list of the DIOB signals used by the QSE card. Table 3-133. QSE J1 Connector DIOB Pin Out

Solder Side Signals

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Card-Edge Pins


PRIMARY

1

2

PRIMARY

BACKUP

3

4

BACKUP

GROUND

5

6

GROUND


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3-38. QSE

Table 3-133. QSE J1 Connector DIOB Pin Out (Cont’d)

Solder Side Signals

Card-Edge Pins


UADD 0

7

8

UADD 1

UADD 2

9

10

UADD 3

UADD 4

11

12

UADD 5

UADD 6

13

14

UADD 7

HI-LO/

15

16

R/W1

UNIT

17

18

DATA-GATE

GROUND

19

20

DEV-BUSY

UDAT 0

21

22

UDAT 1

USAT 2

23

24

UDAT 3

UDAT4

25

26

UDAT 5

USAT6

27

28

UDAT 7

GROUND

29

30

*

*

31

32

*

33

34

GROUND

*These pins are open. The QSE card does not interface to the following DIOB signal: UFLAG

UCAL

USYNC

UCLOCK

When the card is addressed by the DIOB controller (read cycles only) and the DIOB control signal “Data Gate” is received, the QSE card will activate the “Device-Busy” DIOB signal line. The appearance of the “Device-Busy” signal indicates to the DIOB controller that the QSE is on the DIOB and is powered up. If the “Device Busy” pulse is missing, the DIOB controller can assume that there is no point card capable of recognizing that particular DIOB address. Card address assignment is accomplished via the front-edge 56-pin J2 connector. See Table 3-134 for the signal list. Table 3-134. QSE J2 Connector Pin Out for Address Jumpers

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Signal

Card Edge Pin Number

CA7

28B

CA6

27B

CA5

26B

CA4

25B


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3-38. QSE

Table 3-134. QSE J2 Connector Pin Out for Address Jumpers

Signal


CA3

24B

CA2

23B

CA1

22B

CA0

21B

Hi/Lo (Address Protect)

20B

Logic Common

21A-28A

Contact Inputs The 16 QSE card contact inputs are interfaced to the field contact via the 56-pin (J2) front-edge connector. Each contact input is single-ended and shares a common return connection with the other contact inputs. Since the QSE has an internally generated, isolated dual voltage supply, there is no need for an external contact-wetting voltage supply. Each contact can thus be wired directly between the QSE card’s field common pin and one of the sixteen contact input pints. See Table 3-135 for the J2 connector signal pin out.

3-38.5. Circuit Description A functional block diagram of the QSE card is shown in Figure 3-248.

Power-Up The power-up circuit performs the following functions:

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• •

Maintains reset as long as the power supply is below 9 volts.

•

After the reset is terminated it, provides a delay of 125 msec. for Group 1 and 1 second for Group 2 before it enables the setting of the status bit ST6. During this delay, the on-board microcontroller completes over a thousand cycles, providing stable data before the status bit ST6 is set. Thus, status bit ST6 indicates both power-up and “card ok” conditions.

Extends the reset for a nominal 250 msec. for Group 1 and 2 seconds for Group 2 after the power supply is above 9 volts.


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3-38. QSE

•

Continuously monitors the processor cycle time and clears the status bit ST6 if the cycle is shorter than 100 µsec.for Group 1 and 700 µsec for Group 2, or longer than 150 µsec. for Group 1 and 1700 µsec for Group 2. To perform this “Watchdog timer” function, the power-up circuit timing is independent of the processor clock.

Reset During reset, the following circuits are cleared:

• • •

Real time clock. The clock begins at “0” time after the reset is terminated.

• • •

The Event Buffer is cleared of all entries.

Memory load latch. All mask-bits are set to “one.” This enables entries to the Event Buffer when the change of state of any input bits is recognized.

The processor is reset. The contact-wetting voltage supply is shut down.

Input Circuit The card handles 16 contact inputs with common return. The input signals are digitally filtered (debounced). Contact closure produces a “1” at the DIOB, while an open contact produces a “0.” For field input connector pin out, see Table 3-135. Table 3-135. QSE J2 Connector Pin Out for Field Inputs

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Contact Input Bit Number


DB15

17B

DB14

17A

DB13

15B

DB12

15A

DB11

13B

DB10

13A

DB9

11B

DB8

11A


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3-38. QSE

Table 3-135. QSE J2 Connector Pin Out for Field Inputs

Contact Input Bit Number


DB7

9B

DB6

9A

DB5

7B

DB4

7A

DB3

5B

DB2

5A

DB1

3B

DB0

3A

COMMON

1A and 1B Notes

1. B = Component Side A = Solder Side 2. Pins 19A and 19B are internally tied together on the QSE Card.

DIOB Control The card is addressed by means of the six most significant DIOB address lines (UADD7-UADD2). This address is referred to as “Base Address.” The Base Address is selected by jumpers at the top of the front card-edge connector. Insertion of a jumper encodes a “one” on that address line, absence of a jumper encodes a “zero.” When this pattern of jumpers matches that on the bus, the card has been selected by the bus controller. Because the DIOB has eight data lines, the HI/LO line of the DIOB is used to determine whether the high or the low half of the 16-bit data word is to be transferred. Data protection during the removal of the front connector is implemented via a short front-edge pin in the location of the HI/LO jumper (front connector Pins 20A-20B). Note The jumper must be installed.

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3-38. QSE

If the connector is removed, this contact opens first and removes the card from its DIOB address. This allows use of the full DIOB address while allowing removal and insertion of the cards in an operating DIOB. However, this feature does not allow these cards in the lower half of the DIOB address while using cards with a short A7 pin type address protection in the DIOB upper half address. The two least significant DIOB address lines are used as described in the following sections.

Current Input (UADD0 = “zero”, UADD1 = “zero”) This word can be read any time. Each bit indicates the state of the corresponding input as shown in Table 3-136. Table 3-136. QSE Current Input

Input Bit Number

J2 Card Edge Pin Number

DIOB Data Lines

DIOB HI/LO

DB15

17B

UDAT7

“one”

DB14

17A

UDAT6

“one”

DB13

15B

UDAT5

“one”

DB12

15A

UDAT4

“one”

DB11

13B

UDAT3

“one”

DB10

13A

UDAT2

“one”

DB9

11B

UDAT1

“one”

DB8

11A

UDAT0

“one”

DB7

9B

UDAT7

“zero”

DB6

9A

UDAT6

“zero”

DB5

7B

UDAT5

“zero”

DB4

7A

UDAT4

“zero”

DB3

5B

UDAT3

“zero”

DB2

5A

UDAT2

“zero”

DB1

3B

UDAT1

“zero”

DB0

3A

UDAT0

“zero”

Note The “Current Input” word is unaffected by the “Mask” word.

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QSE Mask (UADD0 = “one,” UADD1 = “zero”) The word determines which bits are checked for change of state to cause entries in the Event Buffer (See Table 3-137). This word can be both read and written. A “one” in any bit position causes the corresponding input to be checked for change of state every 125 µsec. for Group 1 and 1msec. for Group 2, and, in case of change of state, to enter the change (with corresponding time) to the Event Buffer. For Group 2 QSE cards, a zero in any bit position of the Mask Word resets the corresponding Chattering Counter and Chattering Flag in order to disable monitoring for chatter. Monitoring will start at the time the mask bit is set to 1. Upon power-up, all QSE Mask bits are set to “one.” Table 3-137. QSE Status Word Bit Assignment

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QSE Mask Bit

DIOB Data Lines

DIOB HI/LO

MB15

UDAT7

“one”

MB14

UDAT6

“one”

MB13

UDAT5

“one”

MB12

UDAT4

“one”

MB11

UDAT3

“one”

MB10

UDAT2

“one”

MB9

UDAT1

“one”

MB8

UDAT0

“one”

MB7

UDAT7

“zero”

MB6

UDAT6

“zero”

MB5

UDAT5

“zero”

MB4

UDAT4

“zero”

MB3

UDAT3

“zero”

MB2

UDAT2

“zero”

MB1

UDAT1

“zero”

MB0

UDAT0

“zero”


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3-38. QSE

Status Word (UADD0 = “one,” UADD1 = “one”) The Status word indicates the condition of the QSE Card (power is up, watchdog timer is OK), and the status of the Event Buffer. The two bytes of the Status Word (HI/LO) are identical; thus, a byte read operation is sufficient to obtain status information. Table 3-138 lists the assignment of the bits within the Status Word: Table 3-138. QSE Status Word Bit Assignment

DIOB Data Line

Status Bit Number

Function

UDAT7

ST7

Freeze bit

UDAT6

ST6

Card “OK” flag

UDAT5

ST5

Buffer overflow

UDAT4

ST4

UDAT3

ST3

UDAT2

ST2

UDAT1

ST1

UDAT0

ST0

Number of events in the Buffer (ST 4 = “one” means Buffer-full).

The “freeze” bit (ST7 = “one”) indicates that the “Enable Stack Operation” was initiated by the DIOB controller. The Card OK flag (ST6 = “one”) means that the card is operating. Buffer overflow (ST5 = “one”) warns that no more entries are allowed to either buffer; thus information may be lost. Status bits ST0 to ST4 are meaningful only after the DIOB controller initiates an “Enable Stack Operation” (ST7 is set on “one”). Under this condition, bits ST0 to ST4 indicate the number of events entered to the buffer prior to when it was frozen. Bit ST4 = “one” if the buffer is full.

Control Word (UADD0 = “one,” UADD1 = “one”) The control word is used by the DIOB controller to enable stack operations, and to reset the Event Buffers. The following procedure is used to empty (read) Event Buffer.

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1. The DIOB controller sets the Enable Stack Operation (freeze) bit to “one” by writing a word (with the most significant bit = “one”) to the card’s “Base Address” + 3. (Only the most significant bit is used in the control word; the other bits can be in any state.) 2. The status word (byte) is read next, so that the number of entries (N) to the Event Buffer can be determined. 3. The DIOB controller now reads 2N words from the card’s “Base Address” + 2 in order to collect all information. 4. To eliminate the stack operation (unfreeze), the DIOB controller clears the freeze bit by writing a word (with the most significant bit = “zero”) to the card’s “Base Address” + 3. This action also clears the Event Buffer (the one just read from) so that it is free to record new events. 5. The DIOB controller repeats the freeze/status read procedure to check for entries to the second buffer. If additional entries are detected, then the read/ unfreeze operations are repeated. With no entries, only the unfreeze (reset) procedure is required.

Events Buffer (UADD0 = “zero,” UADD1 = “one”) The word is active only when the Enable Stack Operation (freeze) bit is set to “one.” Otherwise, read operations return all zero data words. Write operations are not used with this address. If the Enable Stack Operation (freeze) bit = “one,” then the reads from this address (Card Base Address + 2) are treated as pop operations from the Event Buffer stack. In case the number of reads exceeds 2N words (where N = the number of entries in the Event Buffer at the time of the freeze command), all zero data words are returned. Entries to the Event Buffer All 16 field-input bits are sampled every 125 µsec. for Group 1 and 1msec. for Group 2 to detect change of states. If a change is detected for 32 continuous sample cycles (4 msec.) for Group 1 or 4 continuous sample cycles for Group 2, then the mask bit (that corresponds to the bit that registered the change) is tested. For each registered change that has the corresponding mask bit set, an entry is made to the Event Buffer.

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For Group 2 QSE cards additional tests are made to determine if the new change causes a chattering condition. If it does the change is entered with the Chattering Flag set. If the chattering condition already exists, then no entry is made to the Events Buffer. An entry consists of two 16-bit words. The first word is referred to as the Point ID. The bit assignment of the Point ID is shown in Table 3-139. The second half of the entry is the 16-bit representation of the time-tag (LSB = 1 msec.). Table 3-139. QSE Point ID Bit Assignment

Bit Position

Description

15

New Point Value

14

Always “one”

13

Always “zero”

12

Always “zero”

10

Always “zero”

9

Always “zero”

8

Always “zero”

7

Always “zero” for Group 1, Chattering Flag for Group 2.

6

Time Tag extension bits, used to provide 1/8 msec. resolution

5

(LSB [Bit Position 4] = 1/8 msec.) for Group 1. Always “zero” for Group 2.

4 3

Bit Identification Code. Binary representation of the bit causing the entry

2

(MSB = Bit 3, LSB = Bit 0)

1 0

Event Buffer Stack Each Event Buffer has a capacity of 16 entries (32 15-bit words). Event 1 is the first change of state (oldest event) since the buffer was last emptied. The first read from location Base Address + 2 returns Event 1 Point ID. The next read from the same location returns Event 1 Time-Tag. This sequence continues for 2N reads required to empty the buffer stack through location Base Address + 2. Event 1

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Point ID


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3-38. QSE

Event 1

Time-Tag

Event 2

Point ID

Event 2

Time-Tag

Event 3

Point ID

Event 3

Time-Tag

• • • Event N

Point ID

Event N

Time-Tag

Clock Synchronizing Clock synchronizing is accomplished by periodic DIOB write operations. One of four Group Write Addresses can be selected by jumpers J1 and J2 (see “Group Write Address Selection Jumpers”). Double byte transfer (word transfer) should be used on the DIOB, low byte first, high byte second. The QSE clock is synchronized when the high byte is transferred. If the two writes (bytes) are more than 200 µsec apart, the QSE aborts the synchronization attempt.

3-38.6. Firmware Considerations The 8031 microcontroller is used to perform the following functions:

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Sample the status information from the isolated contact inputs, and compare it to the previous state of inputs called “Current Input” (Current Input is stored in the 8031’s internal registers and cleared during reset). The result is stored as “alarm bits” in internal registers.

•

Increment the corresponding counter(s) for each alarm bit. (The 8031’s internal registers are used as counters.)

• • •

Reset all the counters that have no corresponding alarm bits set.

•

Calculate the new “Current Input” based on “surviving” alarm bits and the old “Current Input.”

Test each counter for a terminal count (32 for Group 1 and 4 for Group 2). Reset the corresponding alarm bits for each counter that did not reach the terminal count.


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3-38. QSE

• •

Output new “Current Input” to registers that can be read by the DIOB controller. Repeat the cycle.

In order for the debounce algorithm to be accomplished within the time restriction in Group 1 QSE cards, the code is written in-line (no loops). In addition, the code-map is segregated to two separate areas. The program executes from the “low” map area until it detects an alarm bit, then jumps to the “high” map area to increment and test the corresponding counter. If the test indicates that the counter reaches the terminal count, the program jumps back to the “low” map area, resets the counter, and proceeds to test the next alarm bit. If the counter did not reach terminal count, the program will stay in the “high” area, reset the alarm bit just processed, and test the next alarm bit. The program is written so that it completes the processing of each bit in exactly the same time, regardless of the jumps. Thus, the area from which the program is executed indicates the bit being processed and the result. An additional “shadow PROM” is used to generate “marker” bits to translate the code address for the control logic. This approach enables the 8031 to complete each cycle in exactly 125µsec, and with the shadow PROM supplying the pulses to advance the QSE’s real time clock, there is no contention between events recording, and the advancing of the real-time clock. For the Group 2 QSE card, the firmware was written in a more conventional form in order to fit the code into the 512x8 PROM. The sampling rate was lowered to 1 KHz. in order to accomplish the additional algorithms. These algorithms recognize the chattering condition, mark the Event Buffer entry using the Chattering Flag and prevent additional entries to the Event Buffer while the chattering condition exists. In order to minimize hardware changes, The Group 2 firmware also uses the “Shadow PROM” to communicate the changes to the control logic that is external to the microcontroller.

Event Memory Arbitration Timing Clock The Event Memory is accessed by both the microcontroller (to record new events) and the DIOB controller (to read the recorded data).

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To avoid contention, arbitration logic is used. The principal signals are shown on Figure 3-250. The designators T1 through T12 refer to the microcontroller’s oscillation periods (states).

T1

T12

T1

T12

T1

CLOCK ALE PSEN/ PSEN.DLD ADD.OK U63-A U63-B MUC SY1 STR

Figure 3-250. QSE Event Buffer Memory Arbitration Timing Chart

The CLOCK is generated by a precision oscillator and used by the microcontroller. The CLOCK’s frequency is 12 MHz. The ALE and PSEN/ are generated by the microcontroller and used to strobe addresses and enable external program memory. The PSEN.DLD is generated by delaying the inverted PSEN/ signal. ADD.OK is derived from the DIOB address and control signals, and it is asynchronous, relative to the timing of the microcontroller. The signal SY1 is generated, using two flip-flops as synchronizers (U56-A and U56-B); to replace the strobe (STR) that is normally used to access the Event Buffer by the on-card microcontroller. The signal MUC is also generated to control the memory address multiplexer in advance of the strobe SY1. In Figure 3-250 the timing of the signal ADD.OK is such that it just missed setting the synchronizers; thus, synchronization is delayed by a full cycle of the signal PSEN.DLD. Under this worst-case condition, the data will be strobed to the DIOB in less than 625 nsec after the DIOB signal “Data Gate” is valid.

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3-38. QSE

3-38.7. Controls and Indicators Figure 3-251 shows the LED card components.

Power LED I/O Power LED

Figure 3-251. QSE LED Card Components

Light Emitting Diodes When lit, the Power LED indicates the card is receiving DIOB power. When lit, the I/O Power LED indicates the card is generating +10 VDC and 48 VDC.

3-38.8. Card Addressing Group Write Address Selection Jumpers One of the four group write words (16 bit wide) can be selected with the aid of four jumpers. Jumper Inserted

Group Write Word Selected

J1

J3

FC

J2

J3

FD

J1

J4

FE

J2

J4

FF

Addressing The QSE card occupies four DIOB addresses. These addresses are described below:

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3-38. QSE

•

The first DIOB address is used for reading the current input word, which can be read at any time. Each bit of the current input word indicates the state of the corresponding input. The mask word has no effect on the current input word.

•

The second DIOB address is used to set/reset the bits in the mask word. The mask word determines which inputs are checked for changes of state, and causes entries in the event buffer. All bits in the mask word are set to 1 upon power-up.

•

The third DIOB address is used for reading the event data from the event stack buffer. This word is only active when the enable stack operation bit (described below) is set to 1 (FREEZE). Otherwise, it returns to 0000 when read.

•

The event data read through this DIOB address is treated as a “POP” operation from the event stack buffer. As noted previously, each event is made up of 2 words of information (see Figure 3-252).

•

The fourth DIOB address is used to set/reset (FREEZE/UNFREEZE) the enable stack operation bit, and to read the status (byte) (see Figure 3-253). The state of the bits on the following page can be read at any time: — Enable stack operation — QSE card OK — Buffer overflow — Buffer full The number of events in the event stack buffer can be read only when the enable stack operation bit is set (FREEZE).

F

E

D

C

B

A

9

8

7

D

6

5

4

1/8 DIV

3

2

1

0

BIT POSITION

TIME TAG IN msec. (0 TO EA60H)

D 1/8 DIV BIT POSITION TIME TAG IN msec.

= = = =

DIGITAL VALUE TIME TAG IN 1/8 msec. (RANGE 0 TO 7) BIT POSITION OF DIGITAL VALUE IN THE CURRENT INPUT WORD NUMBER OF msec. (RANGE 0 TO 60000)

Figure 3-252. QSE Event Data Format

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3-38. QSE

7

6

5

4

3

2

1

0

NO. OF EVENTS

NUMBER OF EVENTS (0 TO 15)

BUFFER FULL BIT (WHEN SET, INDICATES THAT THE CURRENTLY USED BUFFER CONTAINS 16 EVENTS) BUFFER OVERFLOW BIT (WHEN SET, INDICATES THAT THERE ARE 32 EVENTS ENTERED INTO THE QSE CARD) QSE OK BIT (WHEN SET, INDICATES NORMAL OPERATION)

ENABLE STACK OPERATIONS BIT (SET = FREEZE, RESET = UNFREEZE)

Figure 3-253. QSE Status Byte Format

3-38.9. Application Information The QSE card is one element of the WDPF Sequence of Events (SOE) subsystem, which provides a means of determining the order in which a set of preselected contact inputs change state. In addition to the QSE, the SOE subsystem contains the following elements:

•

DPU software to synchronize the QSE with the Data Highway clock, scan the QSE for events, buffer the events, and send General Purpose Messages to one or two designated drops

•

Logger, HSR, or HDR software to process event messages (from multiple DPUs), sort the events by time, and print them in chronological order

The resolution of the SOE is 1/8 msec. (within a single DPU). In an SOE subsystem with multiple DPUs, the overall accuracy (between drops) is calculated to be better than 1.5 msec.

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QSE Capacity The QSE performs a high-speed scan of its 16 digital inputs, storing event data in one of its dual event stack buffers. This dual buffer allows accumulated events to be read from one event stack, while the other continues to accept event data as it occurs. Each event stack buffer has a 32 word capacity. Since each event requires 2 words, the total combined capacity of the event buffers is 32 events. When this maximum is exceeded, an overflow condition occurs and the card stops collecting information. Input Conditioning The QSE card includes a digital filter for each input, which is used to reject signal changes within a predetermined time interval (3.5 to 4.5 msec.). Time Tagging Time tagging of status changes is accomplished using the QSE clock. This clock has a 1 minute range, resolution of 1/8 msec., and accuracy of + 0.01%. To determine the relative real time of the events to the system, this onboard clock can be synchronized by a group DIOB offset (1FEH). DPU Configuration The user can configure a DPU to monitor up to 576 SOE points; these points correspond to a maximum of 36 QSE cards, each with 16 inputs. For the DPU to collect event information, the user must do the following:

• •

Connect the appropriate field input signals to the QSE cards. Initialize the appropriate process point record fields. In general, the SOE points will be initialized as standard digital inputs (DI type), with the following exceptions: — The EQ record field must be set to 1. — The HW field must be a multiple of 8H (allowing four DIOB word addresses per QSE). — Optionally, the user may specify a value for the RL field (relay close delay time). Each event read from the QSE card will have this value (in msec.) subtracted from the reported time before it is sent to the Logger.

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3-38. QSE

•

Initialize the drop number(s) of the drop(s) to receive SOE data from the DPU (using the DPU configuration diagram).

Operation At restart, a DPU configured for SOE handling searches through all DI records for the SOE points, and builds a table which it will use to expedite event recording. The DPU’s functional processor then resets each QSE card, and subsequently writes a value to each card (mask) that indicates which of the QSE’s 16 inputs are to be monitored for SOE. Note QSE input points which are not event monitored may be used as ordinary contact or digital input points.

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Each time the functional processor executes its overall loop, it synchronizes the QSE cards with the real time from the Data Highway Controller clock. In addition, during each scan, the DPU functional processor does the following:

•

Checks the number of events contained in both event stack buffers on each QSE card. If the number is greater than 0, the event data is read and temporarily stored in RAM (until it can be sent to the designated drop(s)).

•

Checks for buffer overflow condition (Buffer Overflow bit set) and verifies correct operation of the QSE card (QSE OK bit set, and Enable Stack Operation bit set/reset properly). If QSE hardware failure is detected, the card’s input points are put into alarm. (When the card is repaired or replaced, the DPU will automatically initialize the new card, reset the mask bit, and remove the points from alarm.) Note Removing a point from digital input scan will also remove it from SOE scan.

Once the event data is recorded into the DPU’s RAM buffer, it is sent to the user-specified drop (or drops). Typically, the target drop will be a Logger, which has the capability of receiving, sorting, and printing SOE data from multiple DPUs. If one target drop is specified by the user, the DPU will send the event data to that drop one message at a time. That is, each message requires the receiving drop to acknowledge, before the DPU will send the next one. If the target drop fails to acknowledge a message, the DPU will periodically repeat the message, until the target drop responds. If the target drop continues to fail to respond, the DPU will continue to collect data until the RAM buffer is full. Once the RAM buffer is full, new events will not be saved. Note that if the target drop fails, the RAM buffer will continue to fill and can contain a minimum of 790 events. If two target drops are specified, the DPU will send the event messages to both drops simultaneously. Each message requires the receiver to acknowledge it within a pre-determined period of time. If neither drop acknowledged its message, the DPU will periodically re-transmit the same message to both drops until at least one of them responds. If only one drop responds, the DPU will re-attempt the message to the non-responding drop, up to three times. If this fails, the non-responding drop will be considered “dead.” Subsequent messages will still be sent to both target drops; however, the DPU will not repeat the messages to the “dead” drop. Once the “dead” drop acknowledges a message, it will be considered “alive”, and the DPU will once again attempt to re-transmit any unacknowledged messages.

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3-38.10. SOE Event and Error Messages When certain error conditions occur, an error message will be sent to the designated drop(s). The SOE error messages are listed below:

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•

QSE BUFFER OVERFLOW – Indicates that the number of events stored on the QSE card has reached 32. When this occurs, any additional events (exceeding 32) will be lost. The oldest 32 events will be saved.

•

DPU DHC CLOCK DISABLE – Indicates that the Data Highway clock is disabled, although the SOE is otherwise operational. Events entering the QSE cards’ Event Stack Buffers will not be collected while this condition exists.

•

DPU DHC CLOCK ENABLE – Indicates that the Data highway clock is re-enabled after a disabled condition. When the clock is re-enabled, the DPU resets all the QSE cards and sets their masks. The DPU’s RAM event buffer is initialized, and the status of the target drop(s) is set to “alive”.

•

DPU SOE RAM BUFFER FILLED – Indicates that the DPU’s RAM event buffer is full. In this case, all events (in all QSEs’ FROZEN Event Stack Buffers) are slowly dumped into the DPU’s RAM buffer, as event messages are sent to the remote drops (creating space in the buffer). Any event data entering the second (UNFROZEN) Event Stack Buffers (in all QSE cards) will be considered bad data, and will not be collected, because the base time will not have been updated.

•

INITIALIZING SOE DATA BASE – Indicates that the SOE subsystem is being initialized. This message will appear after restart and when a redundant DPU is switched from Backup to Control mode.


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3-38. QSE



CARD

OPTO ISO

+10VDC

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 +V OPTO ISO


20B

+V

BIT 4 BIT 3 BIT 2 BIT 1 BIT 0


20A 19B

A

B

19A

18

18

17B

17

17A

16

15B

15

15A

14

13B

13

13A

12

11B

11

11A

10

9B

09

9A

08

7B

07

7A

06

5B

05

5A

04

3B

03

3A

02

1B

01

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

1A CUSTOMER CONNECTIONS EDGE-CONNECTOR

INTERNAL BUS STRIP

Figure 3-254. QSE Wiring Diagram

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3-38. QSE

For CE MARK Certified System 2 of 2 CUSTOMER CONNECTIONS CARD 1A

A

A

B

1B

1

01

01

1

BIT 0

3A

2

02

02

2

BIT 1

3B

3

03

03

3

BIT 2

5A

4

04

04

4

BIT 3

5B

5

05

05

5

BIT 4

7A

6

06

06

6

BIT 5

7B

7

07

07

7

BIT 6

9A

8

08

08

8

BIT 7

9B

9

09

09

9

BIT 8

11A

10

10

10

10

BIT 9

11B

11

11

11

11

BIT 10

13A

12

12

12

12

BIT 11

13B

13

13

13

13

BIT 12

15A

14

14

14

14

BIT 13

15B

15

15

15

15

BIT 14

17A

16

16

16

16

BIT 15

17B

17

17

17

17

19A

18

18

18

18

PE

PE

19B

EDGE-CONNECTOR

Figure 3-255. QSE CE MARK Wiring Diagram

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3-39. QSR

3-39. QSR Servo Driver with Positional Readback (Stlye 3A99101G01 through G04)

3-39.1. Description G01 through G04 (Must be revision L or later) are applicable for use in the CE MARK Certified System The Q-Line Servo Driver with Position Readback (QSR) card is a valve position controller I/O card that interfaces to the WDPF DPU through the DIOB in order to control Electro-Hydraulic (EH) actuators in the field. Group 1 and 3 boards have four channels and control up to four DC actuators. The only difference between groups 1 and 3 is that the DPU demand and readback codes are inverted. The group 2 and 4 boards have two channels and control up to two AC actuators. The only difference between groups 2 and 4 is that the DPU demand and readback codes are inverted. The QSR is similar in function to the Q-Line Servo Driver Card (QSD) but has independent outputs and provides more features. Some features are DPU readback of the valve position for each channel, valve shutdown options, autocalibration of the channels, and electrically isolated channels. A microcontroller provides the interface function between the DIOB and the channels. It also handles the auto-calibration function for the card. The demand Digital to Analog (D/A) converter in each channel of the QSR card converts a 12 bit binary number (the demand code from the DPU) into a desired position analog signal. This signal is summed with an Linear Variable Differential Transformer (LVDT) feedback signal to produce an error signal. A gain D/A converter located in each channel scales the channel's feedback voltage before it is summed with the demand signal. The output signal which drives the actuator is determined by applying proportional plus integral (analog) control action to the error between the desired demand and actual feedback values of the actuator position. The actuator position is determined by an LVDT at the actuator. To monitor the feedback or position voltage of the actuator, a 12 bit value representing the actuator position from the LVDT is available for readback by the DPU for each channel. This allows the DPU to digitally compare the actual position with the desired output position. The valve shutdown function on the QSR is used to either fully open or fully close the actuators (independent of the position feedback or the demand output). Each channel has a jumper to select an overdriven positive or overdriven negative output coil drive level during shutdown. This drives the actuator to its fully open or closed state. Shutdown is activated by command from the DPU (one channel at a time), by a card reset, or by a watchdog timer timeout.

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3-39.2. Features The QSR card provides the following features:

• • •

Channel shutdown capability.

• • • •

High impedance differential inputs for feedback.

•

Resistor programmable 1kHZ or 3kHZ modulated LVDT power supply (Group 2 and 4 only).

•

Microprocessor and hardware watchdog timers.

Configurable valve coil drive levels. Electrical isolation between channels and between field and digital control circuitry.

Diode protected feedback inputs. Position readback of AC and DC feedback voltage. Selectable magnitude (+15V or +16V) bipolar DC LVDT power supply (Group 1 and 3 only).

3-39.3. Specifications Channel Valve Types A QSR channel may be configured to drive 1 of 3 valve types which include bipolar, unipolar1, and unipolar2. To configure a channel for a specific valve type, install the Valve Type Select jumper and Bipolar Select Resistor (RBP) as follows: 1. Bipolar:

Valve Type Select jumper set to N-normal position and RBP is installed.

2. Unipolar1: Valve Type Select jumper set to N-normal position and RBP is NOT installed. 3. Unipolar2: Valve Type Select jumper set to I-inverted position and RBP is DON'T CARE. See Figure 3-260 and Table 3-145 through Table 3-148 for location of RBP and Valve Type Select jumper for each channel of the QSR. The four QSR groups define bipolar, unipolar1, and unipolar2 as follows:

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Group 1 - DC LVDT Unipolar1 DPU Demand: 0% = negative coil drive output; 100% = positive coil drive output LVDT Feedback: 0VDC = 100%; -10VDC = 0% NOTE: Invert leads of the LVDT feedback so feedback range is 0VDC to -10VDC Unipolar2 DPU Demand: 0% = positive coil drive output; 100% = negative coil drive output LVDT Feedback: 0VDC = 100%; +10VDC = 0% NOTE: Do NOT invert leads of the LVDT feedback. Bipolar

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DPU Demand: 0% = negative coil drive output; 100% = positive coil drive output LVDT Feedback: -10VDC = 0%; +10VDC = 100% NOTE: Adjust feedback leads so above feedback polarities are true.


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3-39. QSR

Group 2 - AC LVDT Unipolar1 DPU Demand: 0% = negative coil drive output; 100% = positive coil drive output LVDT Feedback: 0VAC = 100%; ±10VAC = 0% NOTE: Connect LVDT feedback leads to feedback B of channel. Unipolar2 DPU Demand: 0% = positive coil drive output; 100% = negative coil drive output LVDT Feedback: 0VAC = 100%; ±10VAC = 0% NOTE: Connect LVDT feedback leads to feedback A of channel. Bipolar

DPU Demand: 0% = negative coil drive output; 100% = positive coil drive output LVDT Feedback: ±10VAC on feedback A, 0VAC on feedback B = 100%, ±10VAC on feedback B, 0VAC on feedback A = 0% NOTE: Adjust feedback leads so above feedback conditions are true.

Group 3 - DC LVDT Unipolar1 DPU Demand: 0% = positive coil drive output; 100% = negative coil drive output LVDT Feedback: 0VDC = 0%; −10VDC = 100% NOTE: Invert leads of the LVDT feedback so feedback range is 0VDC to -10VDC. Unipolar2 DPU Demand: 0% = negative coil drive output; 100% = positive coil drive output LVDT Feedback: 0VDC = 0%; +10VDC = 100% NOTE: Do NOT invert leads of the LVDT feedback. Bipolar

DPU Demand: 0% = positive coil drive output; 100% = negative coil drive output LVDT Feedback: −10VDC = 100%, +10VDC = 0% NOTE: Adjust feedback leads so above feedback polarities are true.

Group 4 - AC LVDT Unipolar1 DPU Demand: 0% = positive coil drive output; 100% = negative coil drive output LVDT Feedback: 0VAC = 0%; ±10VAC = 100% NOTE: Connect LVDT feedback leads to feedback B of channel.

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Unipolar2 DPU Demand: 0% = negative coil drive output; 100% = positive coil drive output LVDT Feedback: 0VAC = 0%; ±10VAC = 100% NOTE: Connect LVDT feedback leads to feedback A of channel. Bipolar

DPU Demand: 0% = positive coil drive output; 100% = negative coil drive output LVDT Feedback: ±10VAC on feedback A, 0VAC on feedback B = 0%, ±10VAC on feedback B, 0VAC on feedback A = 100% NOTE: Adjust feedback leads so above feedback conditions are true.

Valve Coil Drive QSR boards are assembled for ±40mA into 40 ohms. The resistor which sets this current (Rout) is installed in spring sockets to allow other drive levels/loads (see Figure 3-260, Table 3-145, and Table 3-146 for location of Rout on board). Configurable drive levels are as follows: Resistor

Level

Load

210 ohms

±40mA

40 ohms

100 ohms

±60mA

60 ohms

158 ohms

±40mA

80 ohms

Resolution: 11 BitAccuracy: 10 Bit LVDT Position Feedback Groups 1 and 3 - DC LVDT Input Span: depends upon LVDT type and stroke. Unipolar LVDT Type: ±1.5V to ±15V Bipolar LVDT Type: ±1.5V to ±10V See Per Channel Jumper description under Controls and Indicators for necessary LVDT Input Level Jumper positions which are dependent on the input span. See Figure 3-260 and Table 3-147 for location of LVDT Input Level Jumpers. Input Impedance: Differential (with floating source): 400 Kohms Inputs (tied together) to common: 150 Kohms

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Common mode rejection: 55 dB with LVDT Input Level Jumpers in “<10V” position 50 dB with LVDT Input Level Jumpers in “>10V” position Inputs are diode protected against common mode and differential overvoltages. Resolution: 11 BitAccuracy: 9 Bit Groups 2 and 4 - AC LVDT See Figure 3-260 and Table 3-148 for location of LVDT Input Level Jumpers. Signal Span:20Vp-p max Common mode voltage:±10V max Input Impedance:10K ohm with input floating Common mode rejection: 55 dB with LVDT Input Level Jumpers in “<10V” position 50 dB with LVDT Input Level Jumpers in “>10V” position Voltage applied:±30V max Resolution: 11 BitAccuracy: 9 Bit

3-39.4. LVDT Power Supply Groups 1 and 3 - DC LVDT Supply Adjustable: Jumper selectable per channel for +15V and -15V or +16V and -16V outputs each at ±5% tolerance, 30mA max. See Figure 3-260 and Table 3-147 for location of DC LVDT Supply Level Jumpers. Average Change Over Temperature: ±1% max from 0 to 60oC Tracking accuracy: ±1.5% max from 0 to 60oC Groups 2 and 4 - AC LVDT Supply Signal:

Sine wave 2.8 to 3.3 kHz (May be set to 1.0 kHz - see AC LVDT Drive Resistors under Controls and Indicators for location of resistor which set the frequency.)

Frequency Stability:1.5% ppm per oC Amplitude:19Vp-p max ±11%

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Load resistance:500 ohm min

3-39.5. Power Requirements DIOB supply voltage: +12.4 VDC to 13.1 VDC Current (supplied by DIOB):1.0A typ 1.5A max - Groups 1 and 3 0.9A typ 1.4A max - Groups 2 and 4

3-39.6. Watchdog Timers The Microprocessor watchdog timer puts all channels in shutdown mode if the onboard microprocessor fails to service the QSR within 0.5 seconds. The hardware watchdog timer causes the Alive LED to blink if the DPU has not communicated with the QSR within three seconds. If the Shutdown jumper JS1 is enabled, a timeout will put all channels in shutdown.

3-39.7. Signal Interface DIOB Connector The QSR interfaces to the DIOB bus through a 34 pin card-edge connector on the DIOB backplane. The card-edge DIOB signal assignments are given in Table 3-140 below. Table 3-140. QSR DIOB Card Edge Connector Pinout

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Signal Name Component Side

Pin #

Pin #


PRIMARY +V

2

1

PRIMARY +V

BACKUP +V

4

3

BACKUP +V

GROUND

6

5

GROUND

UADD1

8

7

UADD0

UADD3

10

9

UADD2

UADD5

12

11

UADD4

UADD7

14

13

UADD6

DATA-DIR

16

15

HI,LO

DATAGATE

18

17

No Connection


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3-39. QSR

Table 3-140. QSR DIOB Card Edge Connector Pinout

Signal Name Component Side

Pin #

Pin #


DEVBUSY

20

19

GROUND

UDAT1

22

21

UDAT0

UDAT3

24

23

UDAT2

UDAT5

26

25

UDAT4

UDAT7

28

27

UDAT6

No Connection

30

29

Ground

No Connection

32

31

No Connection

Ground

34

33

No Connection

3-39.8. Field/Addressing Connector The front card edge of the QSR card provides for both the card DIOB address assignment and for the connections to the field devices. The field device connection points are different for Group 1,3 cards and Group 2,4 cards as shown in Table 3-141 and Table 3-142. Table 3-141. Groups 1 and 3 (DC LVDT) Field/Addressing Front Card Edge Connector Signal Name Component Side

Pin #

Pin #


ADD7

28B

28A

+13V

ADD6

27B

27A

+13V

ADD5

26B

26A

+13V

ADD4

25B

25A

+13V

ADD3

24B

24A

+13V

Shield

23B

23A

Shield

LVDT 2 (+)Feedback

22B

22A

LVDT 4 (+)Feedback

LVDT 2 (-)Feedback

21B

21A

LVDT 4 (-)Feedback

20B

20A

No connection

Shield

19B

19A

Shield

LVDT 2 (+)Supply

18B

18A

LVDT 4 (+)Supply

LVDT 2 (-)Supply

17B

17A

LVDT 4 (-)Supply

No connection

16B

16A

No connection

Shield

15B

15A

Shield

COIL DRIVE 2

14B

14A

COIL DRIVE 4

GROUND 2

13B

13A

GROUND 4

No connection

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Table 3-141. Groups 1 and 3 (DC LVDT) Field/Addressing Front Card Edge Connector Signal Name Component Side

Pin #

Pin #


No connection

12B

12A

No connection

Shield

11B

11A

Shield

LVDT 1 (+)Feedback

10B

10A

LVDT 3 (+)Feedback

LVDT 1 (-)Feedback

9B

9A

LVDT 3 (-)Feedback

No connection

8B

8A

No connection

Shield

7B

7A

Shield

LVDT 1 (+)Supply

6B

6A

LVDT 3 (+)Supply

LVDT 1 (-)Supply

5B

5A

LVDT 3 (-)Supply

No connection

4B

4A

No connection

Shield

3B

3A

Shield

COIL DRIVE 1

2B

2A

COIL DRIVE 3

GROUND 1

1B

1A

GROUND 3

Note LVDT (+) and (-) Supply signals are referenced to channel ground. Table 3-142. Groups 2 and 4 (AC LVDT) Field/Addressing Front Card Edge Connector Signal Name Component Side

Pin #

Pin #


ADD7

28B

28A

+13V

ADD6

27B

27A

+13V

ADD5

26B

26A

+13V

ADD4

25B

25A

+13V

ADD3

24B

24A

+13V

Shield

23B

23A

Shield

LVDT 1B (+)Feedback

22B

22A

LVDT 2B (+)Feedback

LVDT 1B (-)Feedback

21B

21A

LVDT 2B (-)Feedback

20B

20A

No connection

Shield

19B

19A

Shield

No connection

18B

18A

No connection

No connection

17B

17A

No connection

No connection

16B

16A

No connection

Shield

15B

15A

Shield

COIL DRIVE 1B

14B

14A

COIL DRIVE 2B

GROUND 1

13B

13A

GROUND 2

No connection

12B

12A

No connection

Shield

11B

11A

Shield

No connection

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Table 3-142. Groups 2 and 4 (AC LVDT) Field/Addressing Front Card Edge Connector Signal Name Component Side

Pin #

Pin #


LVDT 1A (+)Feedback

10B

10A

LVDT 2A (+)Feedback

LVDT 1A (-)Feedback

9B

9A

LVDT 2A (-)Feedback

No connection

8B

8A

No connection

Shield

7B

7A

Shield

LVDT 1 (+)Supply

6B

6A

LVDT 2 (+)Supply

GROUND 1

5B

5A

GROUND 2

No connection

4B

4A

No connection

Shield

3B

3A

Shield

COIL DRIVE 1A

2B

2A

COIL DRIVE 2A

GROUND 1

1B

1A

GROUND 2

The QSR card address is established by five jumpers on the front card edge connector as show in Figure 3-256. Addressing is identical for all groups of the card.

DIOB CARD ADDRESS = 10011xxx = 9816 - 9F16

See Table 3-143 for valid addresses represented

JUMPER:

A7 = 1

BLANK:

A6 = 0

BLANK:

A5 = 0

JUMPER:

A4 = 1

JUMPER:

A3 = 1


Figure 3-256. QSR Card Address Jumper Assembly

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3-39.9. Operation DIOB Data Format The DPU has access to all channels of the QSR card. The QSR card occupies eight DIOB address locations which are assigned as shown in Table 3-143. where aaaaa is the DIOB address set on the front card edge connector (see Figure 3-256) Table 3-143. QSR DIOB Address Assignments

DIOB Address

Register

aaaaa000

Read Address Request Register

aaaaa001

not used

aaaaa010

not used

aaaaa011

not used

aaaaa100

Channel 1 Demand - Write only

aaaaa101


aaaaa110


aaaaa111


To write a demand to a channel of the QSR, the DPU writes the 12-bit demand to one of the last four addresses listed in Table 3-143. A read operation of a channel requires two steps. First the DPU must write a register number to the first address listed in Table 3-143. Register numbers identify from which QSR register the DPU is requesting data. See Table 3-144 for register numbers. The QSR processor then retrieves the desired data from its memory and places it in the QSR's DIOB read registers. The DPU can then read the latches to obtain the information. A read of any of the eight DIOB address locations provides the same data since there is only one set (two bytes) of DIOB read registers on the QSR. Only double byte (that is, word) DIOB read and write operations are allowed.

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3-39. QSR

Table 3-144. QSR Read Register Assignments Register Number

Assignment

00

Channel 1 Demand

01

Channel 1 Feedback

02

Channel 2 Demand

03

Channel 2 Feedback

04

Channel 3 Demand

05

Channel 3 Feedback

06

Channel 4 Demand

07

Channel 4 Feedback

08

Channel 1 Min Scale Factor

09

Channel 1 Max Scale Factor

0A


0B


0C


0D


0E


0F


10

Valve calibration type for each channel

For each channel, the demand position can be both read and written, and the LVDT feedback position can be read where command and status bits are embedded within the read/write data value. Maximum and minimum scale factors may be read for each channel where valid scale factors only appear for calibrated channels (DATA VALID status bit=1). The valve type that each channel is currently calibrated to drive may also be read from the card. The formats of these data types are given in Figure 3-257, Figure 3-258, and Figure 3-259. When reading the feedback position, a Data Valid status bit of 1 indicates that the feedback position value has been determined by the QSR processor. A status of 0 indicates that the QSR has not yet determined the feedback position value or that there is an on-card or LVDT problem (such as an uncalibrated channel) in determining that value.

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HI Byte 15 14 13 12 11 10 9

8

7

6

5

LO Byte 4 3 2

1

0

L S B

M S B 12 Bit Data Data Valid (1=Valid 0=Invalid)

Shutdown Direction (1=Positive 0=Negative) Shutdown Active (1=Active 0=Inactive) Card OK (1=OK)

Figure 3-257. Read Data Format for Reading Demand, Feedback, and Scale Factors

HI Byte 15 14 13 12 11 10 9

Chan4

ChanX =

0 Hex: 1 Hex: 2 Hex: 3 Hex: F Hex:

Chan3

8

7

6

5

LO Byte 4 3 2

Chan2

1

0

Chan1

not yet calibrated for a valve type set up for unipolar1 valve type * set up for unipolar2 valve type * set up for bipolar valve type * non-existent channel (used for AC Groups 2 and 4 channels 3 and 4 which do not exist)

* Valve types are listed and explained in the Specifications section above.

Figure 3-258. Read Data Format for Reading Channel Valve-Type Assignments

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HI Byte 15 14 13 12 11 10 9

8

7

6

5

LO Byte 4 3 2

1

0

L S B

M S B 12 Bit Data Not Used Not Used Activate Shutdown (1=Activate) Not Used

Figure 3-259. Write Data Format for Sending Demands to a Channel

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Westinghouse Proprietary Class 2C JS1

CAL

JS3

INT VALVE

TP2

TP6

JS8

R45 TP14 N I

JS11

R53

NEG POS

R55

DIS EN

RV1 R58

15V 16V

JS15

R115

TP15

TP5

R98 R99

15V 16V

JS14

R113

JS2

CT CAL

JS4

N I

JS12

R67 R68

JS6

NEG POS

TP13 N I

R52

TP11

R40 JS10

RV3

TP8

TP7

JS7

R61

NEG POS

TP16

TP17

JS16

JS26 JS27 JS28 JS29

EN CAL

TP20 JS30

TP19

<10V

R160

<10V

JS19

>10V

R148

TP18

<10V

JS22 JS23 JS24 JS25

>10V

JS17

RV2 JS18 >10V

R126

R125

R119

<10V

JS21

RV4 JS20 >10V

R162

EN DIS

DPU CTRL

TP4

TP3

TP10

JS9

NEG POS

TP12

R107 R108

R167

SHDN

TP1

TP9

N I

R118

15V 16V

LE5

LE4

LE3

LE2

LE1

CAL

STRT

CH4

CH3

CH2

CH1

STP

SP

UP2

UP1

CAL4 CAL3 CAL2 CAL1 ALIVE

LEDS

15V 16V

JS13

3-39. QSR

3-39.10. Controls and Indicators SW2

SW1

R105 R106

R75 R76

R59

Figure 3-260. QSR Card Outline and User Controls

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1 2 3 4 5 6 7 8

3-39. QSR

LED Indicators The following LEDs are located near the card edge (see Figure 3-260): ALIVE:

• •

Stays lit when DPU is communicating with the microcontroller. Blinks when the DPU fails to interrupt the microcontroller at least once every 3 seconds.

CALx (x = 1,2,3,4 for Groups 1 and 3; x = 1,2 for Groups 2 and 4):

• • • •

Flashes every 0.25 sec when channel x requires internal calibration. Blinks every 0.5 sec when channel x requires valve calibration. Stays lit when channel x undergoes internal or valve calibration. Remains off when channel x has been calibrated and is able to send demand positions to valve and readback valve positions.

Switches

8

UP1

Valve-calibrate channel for unipolar1 valve type

7

UP2

Valve-calibrate channel for unipolar2 valve type

6

BP

Valve-calibrate channel for bipolar valve type

5

SSTEP

Single-step through valve calibration

4

CH1

Calibrate channel 1

3

CH2

Calibrate channel 2

2

CH3

Calibrate channel 3

1

An 8-position DIP switch (SW1) located near the card edge (see Figure 3-260) has the following switch configuration:

CH4

Calibrate channel 4

The start calibration push-button switch (SW2) is also located near the card edge. The DIP switch settings are read by the QSR only when this button is pressed.

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Internal Calibration Internal calibration is performed only by the factory, and is done to set internal voltage ranges for each channel. A channel's calibration LED flashes every 0.25 seconds if the channel has not been internally calibrated. If this occurs in the field, the card should be sent back to the factory. Valve Calibration Valve calibration is required of every channel on the QSR each time the channel is wired to drive a new valve and LVDT. If a channel is already calibrated and power is removed from the card, the channel does not require re-calibration on power-up if it is wired to drive the same valve and LVDT for which it was most recently calibrated to drive. If a channel has never been valve calibrated or if the channel is between valve calibration steps, its calibration LED will blink every 0.5 sec. Before valve calibration begins, configure the QSR Card as follows (see Figure 3-260 for locations): 1. Install the Enable Calibration jumper (JS30). 2. Set the DPU Control jumper to the disable (DIS) position (JS4). 3. Set the Calibration Select jumper to the VALVE position (JS3). 4. Set the Valve Type selection jumper to normal (N) or inverted (I) mode based on the valve type (see Channel Valve Types under Specifications to determine valve type and Table 3-147 and Table 3-148 to locate jumpers). 5. Select the channel to be calibrated using the front card-edge DIP switch (SW1) (CH1, CH2, CH3, or CH4). 6. Select the valve type being driven using the front card-edge DIP switch (SW1) (UP1, UP2, or BP). 7. Remove RBP for all channels driving Unipolar1 type valves (see Table 3-145 and Table 3-146 to locate RBP for each channel). 8. Check that feedback wires are installed properly for valve type being driven (see Channel Valve Types under Specifications to determine valve type). To begin valve calibration, press the start calibration button (SW2) on the front card edge. The Calibration LED (CAL1, CAL2, CAL3, or CAL4) for the channel being calibrated will remain lit during calibration. For channels driving bipolar valves, valve calibration consists of four steps.

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1. Channel coil drive is overdriven in the negative direction which drives the valve to its fully driven negative position. An auto-gain coefficient which scales the fully driven LVDT feedback voltage is determined on the card. 2. Channel coil drive is overdriven in the positive direction which drives the valve to its fully driven positive position. An auto-gain coefficient which scales the fully driven LVDT feedback voltage is determined on the card. The lesser of the above two auto-gain coefficients is chosen. 3. Channel coil drive is overdriven in the negative direction and a successive approximation is done of the LVDT feedback voltage being scaled by the chosen autogain coefficient. This determines the MAX_SCALE factor. 4. Channel coil drive is overdriven in the positive direction and a successive approximation is done of the LVDT feedback voltage being scaled by the autogain coefficient. This determines the MIN_SCALE factor. Note MAX_SCALE and MIN_SCALE factors are used to translate DPU demand codes to coil drive demand voltages and to translate LVDT feedback voltages to DPU feedback codes. For channels driving unipolar valves, valve calibration consists of two steps: 1. Channel coil drive is overdriven in the positive or negative direction (depending on whether the valve is unipolar1 or unipolar2 type) which drives the valve to its fully driven positive or negative position. An auto-gain coefficient which scales the fully driven LVDT feedback voltage is determined on the card. A successive approximation is done of the scaled LVDT feedback voltage to determine MAX_SCALE factor. 2. Channel coil drive is driven with 0V, and a successive approximation of the LVDT feedback is performed to calculate the MIN_SCALE factor. Once a channel is calibrated, the channel's calibration LED (CAL1, CAL2, CAL3, or CAL4) is turned off and the microcontroller puts the channel in shutdown. Note When all channels driving valves are calibrated, the DPU Control jumper (JS4) must be set to the enable (EN) position so that the DPU may communicate with the channels.

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If a calibration step fails, any remaining steps are skipped, and calibration terminates by forcing the channel into its shutdown state. A failure also sets the channel's Calibration LED (CAL1, CAL2, CAL3, or CAL4) back to its blinking state to indicate that the channel still needs valve calibration. If power is cycled to the QSR, the channel's LED will stop blinking if previous successful valve calibration data was stored for the channel. To aid in diagnostics, an additional switch setting is provided to allow single stepping through the calibration routines outlined above. By setting the SSTEP switch on the front card edge DIP switch (SW1) before starting the calibration routine, the microprocessor will pause between each step of calibration until the calibration button is pressed to proceed on to the next step. The channel's Calibration LED will be illuminated while a calibration step is executing and will blink between calibration steps.

3-39.11. Plug-in Resistors Analog Output P/I Loop Circuitry The output stage of each channel is an analog proportional plus integral (P/I) loop circuit as shown in Figure 3-261. Figure 3-260 and Table 3-145 and Table 3-146 show the location of the resistors used to locate them on the board.

RD

1µf

RT RIN V1

RS

Feedback V2 Position

RF

D/A Out

+

RLP

ROUT

Valve Coil

210 Ω or 100 Ω or 158 Ω

40 Ω or 60 Ω or 80 Ω

Figure 3-261. QSR Analog Output Stage

Bipolar Resistor (RBP) See Channel Valve Types section under Specifications above to determine what valve types require RBP to be installed. Table 3-145 and Table 3-146 list the location for RBP in each channel and Figure 3-260 illustrates the location.

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3-39. QSR

AC LVDT Drive Resistors Two resistors per channel are used to set the AC LVDT Supply frequency. This applies only to Group 2 and 4 boards. Channel 1 resistor locations are R105 and R106. Channel 2 resistor locations are R125 and R126. Frequency

Resistor

1K Hz

33K Ohms

3K Hz

11K Ohms

Table 3-145. Plug in Resistor Reference Designators (Groups 1 and 3)

Channel

RF

RS

RT

RD

ROUT

RBP

1

R75

R58

R59

R76

R160

R45

2

R99

R98

R115

R113

R162

R55

3

R67

R52

R53

R68

R148

R40

4

R108

R107

R119

R118

R167

R61

Table 3-146. Plug in Resistor Reference Designators (Groups 2 and 4)

Channel

RF

RS

RT

RD

ROUT

RBP

1

R75

R58

R59

R76

R160

R45

2

R67

R52

R53

R68

R148

R40

3-39.12. Jumpers Per Card Enable Calibration (EN CAL): When installed, card may be calibrated. (See JS30 on Figure 3-260) Card Test Calibration (CT CAL): When installed, internal calibration is enabled, only if EN CAL is also installed. (See JS2 on Figure 3-260)

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M0-0053

3-39. QSR

Calibration Select (CAL INT/VALVE): In the INT position, pressing the start calibration button begins internal calibration. In the VALVE position, pressing the button begins valve calibration. (See JS3 on Figure 3-260) DPU Control Enable/Disable (DPU CTRL EN/DIS): In DIS position, the DPU cannot communicate with the channels. The jumper should be in DIS position on initial power up and during calibration. In EN position, communication is permitted between the DPU and QSR. (See JS4 on Figure 3-260) Shutdown Enable/Disable (SHDN EN/DIS): In DIS position, channels maintain demand positions if the DPU breaks communication with the microcontroller. In the EN position, communication breakdown drives the channels to their shutdown positions. (See JS1 on Figure 3-260) Per Channel (see Table 3-147 and Table 3-148 for reference designators) Valve Shutdown Direction (POS/NEG): In POS position, channel shutdown state overdrives channel coil drive to approximately +13V. In NEG position, shutdown state is approximately -13V. DC LVDT Power Supply Level (15V/16V): In 15V position, LVDT Supply levels are +15V and -15V referenced to channel ground. In 16V position, LVDT Supply levels are +16V and -16V referenced to channel ground. These jumpers are found on Group 1 and 3 boards only. LVDT Input Level (>10V/<10V): For Unipolar Valves - feedback span between ±1.5V and ±7.5V, install jumper in “>10V” position. Feedback span between ±7.5V and ±15V, install jumper in “<10V” position. For Bipolar Valves - feedback span between ±1.5V and ±4V, install jumper in “>10V” position. Feedback span between ±4V and ±10V, install jumper in “<10V” position. Valve Type Select (N/I): In N position, Normal valve type is selected. In I position, Inverted valve type is selected (see Valve Type section under Specifications above).

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3-39. QSR

Table 3-147. Channel Jumper Reference Designators (Groups 1 and 3)

Channel

Valve Shutdown

DC LVDT Supply Level

LVDT Input Level

Valve Type Select

1

JS8

JS15

JS26, JS27

JS11

2

JS6

JS16

JS18, JS19

JS12

3

JS7

JS14

JS22, JS23

JS10

4

JS9

JS17

JS20, JS21

JS13

Table 3-148. Channel Jumper Reference Designators (Groups 2 and 4)

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Channel

Valve Shutdown

LVDT Input Level

Valve Type Select

1

JS8

JS26 - JS29

JS11

2

JS7

JS22 - JS25

JS10


M0-0053

3-39. QSR

3-39.13. Test Points Digital Ground: TP1, TP2 Channel Test Points: Table 3-149. Channel Test Point Reference Designators (Groups 1 and 3)

P/I Loop Test

Probe for Int.

Channel

GND

Tie to GND

Inject Signal

Calibration

1

TP17

TP5

TP6

TP14

2

TP8, TP19

TP7

TP15

TP11

3

TP18

TP3

TP4

TP13

4

TP10, TP20

TP9

TP16

TP12

Table 3-150. Channel Test Point Reference Designators (Groups 2 and 4)

P/I Loop Test

Probe for Int.

Channel

GND

Tie to GND

Inject Signal

Calibration

1

TP17

TP5

TP6

TP14

2

TP18

TP3

TP4

TP13

3-39.14. Potentiometers for DC LVDT Drive (Groups 1 and 3 only) These potentiometers are used during internal calibration to adjust the DC LVDT supply output levels. Channel 1: RV1 Channel 2: RV2 Channel 3: RV3 Channel 4: RV4

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3-39. QSR

3-39.15. Installation Data Sheet 1 of 5 QSR CARD



A

B

QSR CARD

Coil Drive 1

2B

01

01

2A

Coil Drive 3

Shield

3B

02

02

3A

Shield

Ground 1

1B

03

03

1A

Ground 3

LVDT 1 (+) Supply

6B

04

04

6A

LVDT 3 (+) Supply

Shield

7B

05

05

7A

Shield

LVDT 1 (-) Supply

5B

06

06

5A

LVDT 3 (-) Supply

LVDT 1 (+) FB

10B

07

07

10A

LVDT 3 (+) FB

Shield

11B

08

08

11A

Shield

LVDT 1 (-) FB

9B

09

09

9A

LVDT 3 (-) FB

Coil Drive 2

14B

10

10

14A

Coil Drive 4

Shield

15B

11

11

15A

Shield

Ground 2

13B

12

12

13A

Ground 4

LVDT 2 (+) Supply

18B

13

13

18A

LVDT 4 (+) Supply

Shield

19B

14

14

19A

Shield

LVDT 2 (-) Supply

17B

15

15

17A

LVDT 4 (-) Supply

LVDT 2 (+) FB

22B

16

16

22A

LVDT 4 (+) FB

Shield

23B

17

17

23A

Shield

LVDT 2 (-) FB

21B

18

18

21A

LVDT 4 (-) FB

QSR Card Edge-Connector Component Side

QSR Card Edge-Connector Solder Side

Figure 3-262. QSR Wiring Diagram (Groups 1 and 3)

Installation Notes: 1. Jumpers from A3, A12, B3, and B12 shown above may be jumpered to the (+) Feedback signal instead of the (-) Feedback signal depending on the valve type. The jumper should always correspond with the return or COM signal of the LVDT in the field. 2. Although not shown above, jumpers are required from each WDPF shield Terminal (A2, A5, A8, ..) to ground screw or half shell.

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M0-0053

3-39. QSR

Installation Data Sheet 2 of 5 QSR CARD



A

B

QSR CARD

Coil Drive 1A

2B

01

01

2A

Coil Drive 2A

Shield

3B

02

02

3A

Shield

Ground 1

1B

03

03

1A

Ground 2

LVDT 1 (+) Supply

6B

04

04

6A

LVDT 2 (+) Supply

Shield

7B

05

05

7A

Shield

Ground 1

5B

06

06

5A

Ground 2

LVDT 1A (+) FB

10B

07

07

10A

LVDT 2A (+) FB

Shield

11B

08

08

11A

Shield

LVDT 1A (-) FB

9B

09

09

9A

LVDT 2A (-) FB

Coil Drive 1B

14B

10

10

14A

Coil Drive 2B

Shield

15B

11

11

15A

Shield

Ground 1

13B

12

12

13A

Ground 2

NC

18B

13

13

18A

NC

19B

14

14

19A

NC

17B

15

15

17A

NC

LVDT 1B (+) FB

22B

16

16

22A

LVDT 2B (+) FB

Shield

23B

17

17

23A

Shield

LVDT 1B (-) FB

21B

18

18

21A

LVDT 2B (-) FB

QSR Card Edge-Connector Component Side

QSR Card Edge-Connector Solder Side

Figure 3-263. QSR Wiring Diagram (Groups 2 and 4)

Installation Note: 1. Although not shown above, jumpers are required from each WDPF shield Terminal (A2, A5, A8, ..) to ground screw or half shell.

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3-39. QSR


CARD

1

A

2A

1

1

3A

2

2

1A

3

3

2B

4

4

3B

5

5

1B

6

6

6A

7

7

7A

8

8

5A

9

9

6B

10

10

7B

11

11

5B

12

12

10A

13

13

11A

14

14

9A

15

15

10B

16

16

11B

17

17

9B

18

18

PE

PE

Coil Drive 3 Ground 3 Coil Drive 1 Ground 1 (+) LVDT 3 Supply (−) LVDT 3 Supply (+) LVDT 1 Supply (−) LVDT 1 Supply (+) LVDT 3 Feedback

-16V

+16V

LVDT (-) LVDT 3 Feedback

Output

COM

-16V

+16V

(+) LVDT 1 Feedback (-) LVDT 1 Feedback

EDGE-CONNECTOR A

2

A

14A

1

1

15A

2

2

13A

3

3

14B

4

4

15B

5

5

13B

6

6

18A

7

7

19A

8

8

17A

9

9

18B

10

10

19B

11

11

17B

12

12

22A

13

13

23A

14

14

21A

15

15

22B

16

16

23B

17

17

21B

18

18

PE

PE

Coil Drive 4 Ground 4 Coil Drive 2 Ground 2 (+) LVDT 4 Supply (−) LVDT 4 Supply (+) LVDT 2 Supply (−) LVDT 2 Supply (+) LVDT 4 Feedback

LVDT (-) LVDT 4 Feedback

Output

COM

(+) LVDT 2 Feedback (-) LVDT 2 Feedback

Figure 3-264. QSR CE MARK Wiring Diagram (Groups 1 & 3)

Installation Notes (Groups 1 & 3) (Refer to Figure 3-264): 1. Valve interfaces for channels 1 and 3 are shown with the shields connected to earth ground at the B cabinet. 2. Valve interfaces for channels 2 and 4 are shown with the shields connected to earth ground in the field.

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3-39. QSR

3. Based on the valve type (unipolar1, unipolar2, or bipolar), the feedback leads (Output and COM) from the LVDT in the field may have to be swapped when connected to a channel’s feedback inputs. Whichever feedback lead polarity is wired in the B cabinet, the earth ground tie should always correspond to the COM lead not the Output lead.

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3-39. QSR


CARD

1

A

2A

1

1

3A

2

2

1A

3

3

2B

4

4

3B

5

5

1B

6

6

6A

7

7

7A

8

8

5A

9

9

6B

10

10

7B

11

11

5B

12

12

10A

13

13

11A

14

14

9A

15

15

10B

16

16

11B

17

17

9B

18

18

PE

PE

Coil Drive 2A Ground 2 Coil Drive 1A Ground 1 (+) LVDT 2 AC Supply Ground 2 (+) LVDT 1 AC Supply Ground 1 (+) LVDT 2A Feedback (-) LVDT 2A Feedback (+) LVDT 1A Feedback (-) LVDT 1A Feedback

EDGE-CONNECTOR A

2

A Coil Drive 2B

14A

1

1

15A

2

2

13A

3

3

Ground 2

14B

4

4

Coil Drive 1B

15B

5

5

13B

6

6

18A

7

7

19A

8

8

17A

9

9

18B

10

10

19B

11

11

17B

12

12

22A

13

13

23A

14

14

21A

15

15

22B

16

16

23B

17

17

21B

18

18

PE

PE

Ground 1

(+) LVDT 2B Feedback (-) LVDT 2B Feedback (+) LVDT 1B Feedback (-) LVDT 1B Feedback

Figure 3-265. QSR CE MARK Wiring Diagram (Groups 2 & 4 with B Cabinet Earth Grounding)

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3-39. QSR


CARD

1

A Coil Drive 2A

2A

1

1

3A

2

2

1A

3

3

2B

4

4

3B

5

5

1B

6

6

6A

7

7

7A

8

8

5A

9

9

6B

10

10

7B

11

11

5B

12

12

10A

13

13

11A

14

14

9A

15

15

10B

16

16

11B

17

17

9B

18

18

PE

PE

Ground 2 Coil Drive 1A Ground 1 (+) LVDT 2 AC Supply Ground 2 (+) LVDT 1 AC Supply Ground 1 (+) LVDT 2A Feedback (-) LVDT 2A Feedback (+) LVDT 1A Feedback (-) LVDT 1A Feedback

EDGE-CONNECTOR A

2

A Coil Drive 2B

14A

1

1

15A

2

2

13A

3

3

Ground 2

14B

4

4

Coil Drive 1B

15B

5

5

13B

6

6

18A

7

7

19A

8

8

17A

9

9

18B

10

10

19B

11

11

17B

12

12

22A

13

13

23A

14

14

21A

15

15

22B

16

16

23B

17

17

21B

18

18

PE

PE

Ground 1

(+) LVDT 2B Feedback (-) LVDT 2B Feedback (+) LVDT 1B Feedback (-) LVDT 1B Feedback

Figure 3-266. QSR CE MARK Wiring Diagram (Groups 2 & 4 with Field Earth Grounding)

M0-0053


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3-40. QSS

3-40. QSS Speed Sensor Card (Style 7381A73G01)

3-40.1. Description Must be sub E or later to be applicable for use in the CE MARK Certified System The Speed Sensor Card (QSS) converts tachometer signal pulses directly into a 15-bit binary speed number (see Figure 3-267). This binary number can be read by a software program via the DIOB bus interface. The card also contains an Analog output that is proportional to the input frequency.

Address

DIOB

Data

DIOB Interface

Buffer

Latch

Update Rate Speed Range Select Micro Controller

Timer

D/A Converter

Zero Crossing Detector

Analog Output

Input Signal

Figure 3-267. QSS Block Diagram

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M0-0053

DIOB Address

DIOB Control DIOB Data Latch

Buffer LEDs

Input Sine Wave Signal

Zero Crossing Detector

Timer Control

Micro Controller

Timer

D/A Converter

Speed Range And Update Rate Selects

Analog Output 0 - 10 V

3-40. QSS

3-542


Figure 3-268. QSS Card Functional Block Diagram

Address Compare

Block Diagram, Detail

M0-0053 Address Select Jumper

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3-40. QSS

The QSR card counts zero crossing of the input signal over an update period +/− 0.5 T (T is period of the input sine-wave). The update period is selected by jumper to be either 50 ms or 25 ms. The Micro Controller (with timer) on the card will determine the “2 x frequency” of the input signal. The “2 x frequency” will be represented by bits 0-14 in a 16 bit output word which can be read via the DIOB interface. Bit 15 of the output word is high (“1”) to indicate the presence of a functional QSS card. This output word is also displayed on the front card edge with 16 LEDs. In addition, the card contains a 0 to 10 volt analog output that is proportional to 0% to 125% of the nominal input frequency. The nominal input ranges are 1.5, 1.8, 3.0, 3.6, 6.0, 7.2 kHz. These ranges are selected via a switch located on the card (see Figure 3-269 for an illustration of the speed selection switch and Figure 3-270 for the location of this component.) ON

OFF

SPARE1

1500

1800

3000

3600

6000

7200

SPARE2

(NOMINAL SPEED = 3600 HZ, AS SHOWN ABOVE)

Figure 3-269. QSS Speed Selection Switch

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3-40. QSS

3-40.2. Specifications Inputs/Outputs Power Supply Voltage Minimum

Nominal

Maximum

Primary

12.4 V

13.0 V

13.1 V

Optional Backup

12.4 V

--

13.1 V

-

500mA

650mA

Current (supplied by DIOB) Inputs

The Speed Channel (QSS) card accepts a sine wave input. The input may be connected to 120 Vac RMS without damage. Sensitivity:

0.5 V P-P @ 36 Hz 8.0 V P-P @ 7.2 kHz

Common Mode: Voltage: 20V P-P (Max.) Nominal Input Speeds:

1.5 kHz 1.8 kHz 3.0 kHz 3.6 kHz 6.0 kHz 7.2 kHz

Input Impedance: 40 k ohms

DIOB Output Data word:16 Bits (Bits 0-14 = two times the input frequency, Bit 15 = 1, Bit 0 = LSB, Bit 14 = MSB) Update Rate:Selectable by jumper to be either one of the following: 50 ms ±0.5 T for speeds greater than or equal to 20 Hz, 1.0 T for speeds less than 20 Hz. 25 ms ±0.5 T for speeds greater than or equal to 40 Hz, 1.0 T for speeds less than 40 Hz.

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3-40. QSS

where: T = period of input sine-wave. Output:

Binary value equal to two times the input frequency.

Accuracy: Minimum one LSB resolution (± 0.5 Hz) over temperature range for low update rate (50 ms); minimum two LSB resolution (±1 Hz) over temperature range for High update rate (25 ms) Output value indication:16 LEDs (see Figure 3-270).

Analog Output Isolated

Output Span: 10V Nominal Input Speeds: 1.5 kHz 1.8 kHz 3.0 kHz 3.6 kHz 6.0 kHz 7.2 kHz Output: 0 to +10V proportional to 0 to 125% of nominal speed setting Accuracy: 0.1% of span at 25 C Output Load: 500 ohms or greater short circuit protection provided Output Limits: -0.1V to +10.1V

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M0-0053

3-40. QSS


LEDs

Error Mode (Watchdog Timer) Jumper Speed Selection Switch

Reset Switch

Update Period Jumper

LED Detail

D07 D06 D05 D04 D03 D02 D01 D00

D14 D13 D12 D11 D10 D09 D08

POK COK

Figure 3-270. QSS Card Components

LED Errors In normal operation, the QSS maintains a self test. If an error is detected, the card will enter the error mode.

•

If the watchdog timer is enabled via a jumper (see Figure 3-270) the watchdog timer will time out to reset the card until the error is corrected.

•

If the watchdog timer is disabled, errors can be read via flashing LEDs (see LED Detail in Figure 3-270). The meaning of the patterns is described in Table 3-151: Table 3-151. QSS Watchdog Timer

Bit Number

Mnemonic

0 1 2 3 4

ANALOG ERROR CALIB ERROR TIMER ERROR DIPSWITCH PULSE ERROR

M0-0053

Description

Error in Analog output circuitry Analog output below 10V Error in Timer control circuit Invalid setting of DIP switch Pulse generator malfunction


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3-40. QSS

Table 3-151. QSS Watchdog Timer Bit Number

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Mnemonic

5 6

TIMER FLAGS AO OVF

7 8 9 10 11 12 13 14 15 16

AO AVERAGE TIMER DATA SPI ERROR T2I ERROR FPNEG FPOVF FPUNF FPNAN COK POK

Description

Error in two second loop Speed is greater than 125% of nominal. (This error will cause the QSS to enter error mode, however the error is saved for display if another error occurs). Analog calibration data too high Invalid data received from timers, three consecutive times. Invalid serial port interrupt Invalid Timer 2 Interrupt Negative floating point number Floating point overflow Floating point underflow Number not a floating point value Card OK bit Power OK


M0-0053

3-40. QSS


QSS Card

20B

Input Circuit A1

Output Circuit

A2

A

20A

20

19B

19

19A

18

17B

17

17A

16

15B

15

15A

14

13B

13

13A

12

11B

11

11A

10

9B

9

9A

8

7B

7

7A

6

5B

5

5A

4

3B

3

3A

2

1B

1

Input Return Input Signal Input Earth Ground

+ Output Source - Output Return

1A

This configuration is for maximum common mode rejection and is recommended. Other options are shown on the following pages.

Figure 3-271. QSS Wiring Diagram (Recommended)

Field Input Connections (Refer to Figure 3-271) The QSS card employs the standard Q-Series front-edge connector. Eight jumpers are used to determine the DIOB address. Contacts supplied include two contacts for the speed input and two contacts for the analog output signal. See Table 3-152 below. Table 3-152. QSS Field Inputs

Pin Number

M0-0053

Field Signals

1A

Earth ground from card clamp

3A

Analog output shield


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3-40. QSS

Table 3-152. QSS Field Inputs

Pin Number 5A

5/99

Field Signals Analog output shield

13A


15A

Speed input signal

17A

Speed input return

1B


3B


5B


7B

Analog output source (+)

13B

Speed input shield

15B

Speed input shield


M0-0053

3-40. QSS


A 20

QSS Card Input Circuit

19B

19

19A

18

17B

17

17A

16

15B

15

15A

14

13B

13

13A

12

11B

11

A1

Input Return Output Return

This configuration has the speed input cable’s shield at the DPU chassis.

QSS Card 09

Output Circuit

A2

09A

08

07B

07

07A

06

05B

05

05A

04

03B

03

03A

02

01B

01

+ Output Source - Output Return Output Earth Ground

01A

This configuration has the output shield terminated at the Field.

Figure 3-272. QSS Wiring Diagram

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3-40. QSS


CARD 1A

A

A

1B

1

1

3A

2

2

3B

3

3

5A

4

4

5B

5

5

7A

6

6

7B

7

7

9A

8

8

9B

9

9

11A

10

10

11B

11

11

13A

12

12

13B

13

13

15A

14

14

15B

15

15

17A

16

16

17B

17

17

Output - Return Output + Source

Input Signal Input Return

19A

18

18

19B

PE

PE

EDGE-CONNECTOR

Figure 3-273. QSS CE MARK Wiring Diagram

Installation Notes: 1. The output shield must be connected to the output return, with both connected to earth ground at the B cabinet as shown. 2. The input shield may be connected to earth ground in the field or at the B cabinet.

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M0-0053

3-41. QST

3-41. QST Smart Transmitter Interface (Style 4256A76G01 and G02)

3-41.1. Description There are many field devices (known as “smart” transmitters) that transmit their values over a digital link. The HART (Highway Addressable Remote Transducer) protocol is one such link specification. Communication via this interface to WDPF is provided through the Smart Transmitter Interface. Complete details on the installation and use of this interface are found in“ Smart Transmitter Interface (STI) User’s Guide” (U0-1115). In brief, the interface consists of three separate printed circuit cards:

• • •

Q-Line Smart Transmitter (QST) SBX Smart Transmitter link (SST) Q-Line Serial Link Controller (QLC)

The QLC card with one SST card may be connected to up to four QST cards to provide a hardware interface for up to 24 smart transmitter current loops. However, the QLC software limits the actual number of QSTs to three, providing an interface to a maximum of 18 smart transmitter loops. For additional detail on the QLC card, see “QLC User’s Guide” (U0-1100).

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3-42. QTB

3-42. QTB Time Base (Style 2840A20G01 through G04)

3-42.1. Description Groups 03 and 04 are applicable for use in the CE MARK Certified System The QTB card is the source of DIOB analog control timing signals (see Figure 3-274). The card generates precise analog control timing signals for use by analog point cards within a process control system. The QTB (by digitally tracking the power line frequency) generates integration, clock, and offset conversion command signals to the analog input cards via the DIOB.

Figure 3-274. QTB Block Diagram

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M0-0053

3-42. QTB

3-42.2. Features The QTB provides the following features:

• • • • • • • • • •

Calibration not affected when integration period is varied to match line period. Provides command to signal analog point card to obtain offset value. Variable time-base clock. Digital power line frequency tracking. Optional crystal oscillator controlled timing. Compatible with any DIOB controller. Optional redundant configuration with primary and backup QTB cards. 50 Hz or 60 Hz operation. Auto-zeroing. Real time clock circuit.

The QTB card has card-edge jumper-selectable options for either normally enabled or disabled QTB operation following power up or system initialization. The QTB may also be enabled or disabled at any time by the bus controller via the DIOB. A command on the DIOB overrides the initially jumpered set-up. Four QTB groups are available:

•

G01 compatible with 60 Hz systems; provides frequency tracking for a 60 Hz, input-voltage frequency.

•

G02 compatible with 50 Hz systems; provides frequency tracking for a 50 Hz, input-voltage frequency.

•

G03 compatible with 60 Hz systems; has no frequency tracking for the 60 Hz frequency.

•

G04 compatible with 50 Hz systems; has no frequency tracking for the 50 Hz frequency.

The QTB Card complies with the DIOB interface design specifications. This card may be used in a Q-crate assembly.

3-42.3. Specifications Figure 3-275 shows a functional block diagram of the card.

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3-42. QTB

Input Voltage (G01 and G02) 120 VAC + 10 percent (rms) Sourcing Current: 20 mA Input Voltage Frequency G01 – 60 Hz + 2 Hz G02 – 50 Hz + 2 Hz G03 and G04 – None (internal crystal oscillator) Maximum Change: + 0.06 percent/sec Input Common Mode Voltage Surge: IEEE Surge Withstand Capability Continuous: + 500 VDC (maximum) Input Normal Mode Voltage Surge: IEEE Surge Withstand Capability

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M0-0053

M0-0053 (G01 AND G02 ONLY)

AC INPUT fL DIGITAL TRACKER

ENABLE/DISABLE CARD-EDGE JUMPER

CLOCK

SYNC

COUNTER

LATCH

3-556


START

RESET

SET

DISABLE

TRI-STATE BUFFER

UIOB INTERFACE

+12V

+12V

HI/LO

DATA DIR

UNIT

DATA GATE

UDAT

UADD

UCLOCK

USYNC

UCAL

D I O B

3-42. QTB

Figure 3-275. QTB Card Functional Block Diagram

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3-42. QTB

Output Signal UCLOCK +2.0V (minimum)

Logic 1:

+3V (nominal) +4.5V (maximum) −0.6V (minimum)

Logic 0:

0.0V (nominal) +0.5V (maximum)

UCLOCK is a pulse train with varying ON/OFF time. The time-averaged frequency is equal to 10,240 times the input-voltage frequency. Output Signal USYNC Logic 0:

0V to +3V

Logic 1:

+8V to +12V

Output Signal UCAL Logic 0:

+12V (nominal)

Logic 1:

0V (nominal)

UCAL is low true for one pulse every 512 line-frequency cycles. The pulse width is longer than the USYNC high time by 500 UCLOCK periods. Power Supply +12.4V (minimum)

Primary:

+13.0V (nominal) +13.1V (maximum) Optional Backup:

+12.4V (minimum) +13.1V (maximum)

Current:

100 mA

3-42.4. Real Time Clock The QTB Card, Real Time Clock is two five-stage counters clocked by the SYNC signal. The resulting outputs are:

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16, 8, 4, 2, and 1 Hz


M0-0053

3-42. QTB

The counter outputs are gated and jumpered for reset circuitry. The jumpers (i.e., JU5-2 for G01 and G03; JU5-1 for G02 and G04) ensures that the outputs are the same regardless of group type. However, the counter outputs do not have 50 percent duty cycles and the duty cycle is not the same on 50 Hz and 60 Hz cards. The Real Time Clock can be read with a normal DIOB Read operation. The Data format is shown in Figure 3-276. Note The Real Time Clock stability is excellent for G01 and G02 since these groups are synchronized with the line frequency. However, G03 and G04 have no line tracking and long term stability of the Real Time Clock is slightly lower.

7

6

5

4

3

2

1

0

BIT

USYNC 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz ENABLED 0.5 Hz (50 PERCENT DUTY CYCLE

Figure 3-276. QTB Real Time Clock Data Format

3-42.5. QTB Timing Requirements The QTB output signals are closely related in timing requirements. As the AC input frequency changes, the USYNC signal must also change since USYNC is tracking the line frequency. During the time USYNC is high, signal integration occurs on analog input cards. The UCAL signal may be pulled low by the bus controller at any time, but a QTB-initiated UCAL occurs on the rising edge of the USYNC pulse 255. The UCLOCK signal occurs very rapidly compared to USYNC and UCAL. UCLOCK also varies with the AC input frequency as shown in Figure 3-277. The UCLOCK signal in Figure 3-277 is magnified for clarity. Normally, UCLOCK occurs approximately 40,960 times during a USYNC pulse.

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3-42. QTB

NORMAL INPUT FREQUENCY

UCLOCK

LOW INPUT FREQUENCY

HIGH INPUT FREQUENCY

USYNC PULSE

0

1

2

0

1

255

UCAL

QTB INITIATED

LOCK-OUT BY CONTROLLER

Figure 3-277. QTB Output Signal Timing Diagrams

Note The USYNC signal occurs on the rising edge of the squared-up AC input signal. However, USYNC ends 40,960 clock pulses later and this pulse width may vary with input frequency.

3-42.6. Control and Indicators Figure 3-278 shows the card outline.

Figure 3-278. QTB Card Outline

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M0-0053

3-42. QTB

Note There are no user-configurable jumpers on this card. All user jumpering is done at the front cardedge connector.

3-42.7. Connectors and Terminations The QTB uses a standard Q-line front connector. The front connector, in addition to the nine address jumpers, uses the following pins:

• • • • • •

Pins 2B and 8B for the 117 VAC line and neutral, respectively. Pin 5A for AC ground. Pins 12A and 12B for PRIMARY. Pins 14A and 14B for a one-card system jumper. Pins 16A and 16B for ENABLE. Pins 19A and 19B for INHIBIT UCAL.

The ENABLE jumper must be in place for proper QTB Card operation. The jumper in pins 14A and 14B is in place for systems using one QTB Card. There is no backup QTB. In redundant configurations where a backup QTB is used, this jumper must be omitted. The PRIMARY jumper is used in redundant configurations to identify the primary card in a two-QTB system. The INHIBIT CAL jumper is used in special applications to defeat the auto-calibration feature. This jumper must be removed for a DIOB which has QAI cards. Note For CE Mark certified systems, field wiring that carries the AC mains must have double insulation.

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3-42. QTB

3-42.8. Redundant QTB Configurations The QTB Card can be configured in a primary-backup connection controlled by the jumper selection on the front-edge connector. The active card is selected as either a primary or backup using a DIOB output cycle. The active card always drives the USYNC, UCAL and UCLOCK lines. Both the primary and backup cards are given the same address. The primary card uses the low byte while the secondary card uses the high byte when reading the Real Time Clock. Both cards respond to the same output cycle (Lo Byte) for active card selection.

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M0-0053

3-43. QTO

3-43. QTO 3-43.1. Description The QTO card receives DIOB signals and provides solid-state AC switching to the field processes within a plant environment (see Figure 3-279). This card contains eight identical solid state relays (TRIAC’s) capable of 120 VAC line frequency switching. An on-card read/write latch provides an 8-bit memory function. This card also contains a switch selectable dead-computer time-out.

Figure 3-279. QTO Block Diagram

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3-43. QTO

3-43.2. Features The QTO card is available in one group only. This card provides the following features:

• • • • • • • •

IEEE surge-withstand protection. 500 VDC common mode rating. Read/write output data operation. On-card power-up, bus, and dead-computer time-out resets. Card-edge LED indicator for each TRIAC output. Switch-selectable dead computer time-out periods. Compatible with any DIOB controller. Zero voltage switching for reducing inductive load surges (see Figure 3-280).

The QTO interfaces the DIOB through a rear-edge connector. The DIOB signals at this interface are defined by DIOB standards. The TRIAC outputs are brought out to the front edge of the card.

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M0-0053

3-43. QTO

Vtrigger = 15 V Maximum Von = 1.5 V Maximum

Voff (Peak) Voff (RMS)

Voltage across triac (Resistive load)

tdelay (On) QTO Latch bit status

0=Off

tdelay(Off) 10=On 0=Off

Where tdelay (On) and tdelay(Off) = 5/8 line cycle maximum

Figure 3-280. TRIAC Zero Voltage Switching

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3-43. QTO

Voff (Peak)

Voff Voltage across solid state switch

1=On QTO Latch bit status

0=Off

0=Off

Figure 3-281. TRIAC Operation with Load Current Below 75 mA

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M0-0053

3-43. QTO

3-43.3. Specifications A functional block diagram of the QTO is shown in Figure 3-282.

DIOB ADDRESS

DATA

9

8

UNIT POWER UP

EIGHT-BIT LATCH

COMPARE

OR

~

~

CARD REFRESH

DRIVERS

9 8

TO JUMPER ADDRESS

OPTICAL ISOLATORS

RESET LATCH

SSR

SSR

+

+

POINT 0

POINT 7

Figure 3-282. QTO Functional Block Diagram

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3-43. QTO

Power Requirements Minimum

Nominal

Primary Voltage

12.4 VDC

+ 13.0 VDC

13.1 VDC

Optional Backup

12.4 VDC

--

13.1 VDC

Current

Maximum

150mA

250mA

Output Capabilities Characteristic

Minimum

Typical

Maximum Units

80

115

140 VAC

0.075*

--

1.8 A RMS (continuous) 10A RMS (T ≤ 5 cycles)

Frequency

47

--

63 HZ

Common Mode Voltage

--

--

500 VDC (Peak) 300 VAC (RMS) (line frequency

Current (OFF)

--

--

8 mA (RMS)

Voltage (RMS) Current (ON)

* The load current must be above 75 mA to fire the TRIAC (see Figure 3-281).

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M0-0053

3-43. QTO

3-43.4. Card Addressing The QTO card address is selected by eight jumpers on the top, front, card-edge connector (see Figure 3-283). Insertion of a jumper encodes a 1 in the address line.

CARD ADDRESS = 1100 1000 (X ‘C8’ HIGH BYTE)

JUMPER:

A7 = 1

JUMPER:

A6 = 1

BLANK:

A5 = 0

BLANK:

A4 = 0

JUMPER:

A3 = 1

BLANK:

A2 = 0

BLANK:

A1 = 0

BLANK:

A0 = 0

JUMPER:

HI-LO = 1 (i.e., HIGH BYTE)


Figure 3-283. QTO Card Address Jumper Assembly Example

3-43.5. Controls and Indicators QTO card components are shown in Figure 3-284. The LEDs indicate which Triac output is active.

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3-43. QTO

If the QTO Card is not periodically updated, the card resets. The update period is set by four DIP switches as given in Table 3-153.

LEDs

Update Period DIP Switches

7 6 5 4 3 2 1 0

LED Detail

Figure 3-284. QTO Card Components

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M0-0053

3-43. QTO

Table 3-153. QTO Card Reset Switch Position DIP Switch

Reset Time

A

B

C

D

0

0

0

0

62 ms + 20%

0

0

1

0

125 ms + 20%

0

1

0

0

250 ms + 20%

0

1

1

0

500 ms + 20%

1

0

0

0

1 sec + 20%

1

0

1

0

2 sec + 20%

1

1

0

0

4 sec + 20%

1

1

1

0

8 sec + 20%

X

X

X

1

No time out, data Latched (X = don’t care)

3-43.6. Connectors and Terminations The QTO Card interfaces to the DIOB via a standard DIOB, rear, card-edge connector. The Solid-State Relay (SSR) outputs are brought to the front edge of the card. These two-wire outputs have the contact pin allocations listed in Table 3-154. R-C snubbing networks are provided on the card across the SSR terminals to minimize inductive load surges on TRIAC turnoff, and to protect the SSR from damage. Table 3-154. QTO Digital Output Contact Allocations

Output Digital Bit Number



B0

3A

2

3B

3

5A

4

5B

5

7A

6

7B

7

9A

8

9B

9

11A

10

B1 B2 B3 B4

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3-43. QTO

Table 3-154. QTO Digital Output Contact Allocations (Cont’d)

Output Digital Bit Number B5 B6 B7

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11B

11

13A

12

13B

13

15A

14

15B

15

17A

16

17B

17


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3-43. QTO


HI/LO JUMPER 20B

CARD

TYPICAL

TERMINAL BLOCK

5A

20A

20

19B

19

19A

18

17B

17

17A

16

15B

15

15A

14

13B

13

13A

12

11B

11

11A

10

9B

09

9A

08

7B

07

7A

06

5B

05

5A

04

3B

03

3A

02

BIT 7

BIT 6

BIT 6

BIT 5

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

01

EDGE-CONNECTOR


Figure 3-285. QTO Wiring Diagram

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3-44. QVP

3-44. QVP Servo Valve Position Controller (Style 4256A94G01 through G04)

3-44.1. Description Groups 01, 02, 03, and 04 are applicable for use in the CE MARK Certified System The QVP is the interface between a WDPF DPU drop’s DIOB controller, an OIM (M/A station), a hydraulic servo valve positioner, and a linear variable differential transformer (LVDT) attached to the stem of the controlled valve. The QVP is available in four groups:

• • •

Group 1

LVDT interface, 80 ohm (+/-24 mA) servo-valve coils

Group 2

LVDT interface, 280 ohm (+/-50 mA) servo-valve coils

Group 3

4 to 20 mA current loop interface, 80 ohm (+/-24 mA) servo-valve coils

•

Group 4

4 to 20 mA current loop interface, 280 ohm (+/-50 mA) servo-valve coils

Consult the “Q-Line Valve Position (QVP) Servo Controller User’s Guide” (U0-1125), or contact your Westinghouse representative for additional information.

3-44.2. Features

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• •

Computer (Automatic) or PB Manual mode operation.

• • • •

Simplified valve calibration procedures that do not require trim-pots.

Computer or PB Manual mode selection via external OIM signals or the WDPF drop’s DIOB controller.

Automatic valve closing bias. Servo valve contingency setpoint LVDT feedback position rate of change monitoring.


M0-0053

3-44. QVP

3-44.3. Functional Description An on-card 80C32 microcontroller provides a link between the QVP card’s DIOB interface circuit, the hydraulic servo valve coil drive circuit, and the LVDT primary coil excitation and LVDT secondary coil demodulation circuit. A valve position setpoint is maintained by the QVP. The setpoint may normally be altered by the OIM’s Raise/Lower pushbuttons or by the WDPF drop via the DIOB interface. The QVP’s microcontroller provides closed loop proportional-plus-integral (PI) control for real time servo valve position control. The valve position setpoint causes the QVP card to generate redundant control output signals which drive the hydraulic servo valve actuator coils. The feedback loop is closed with the valve position measurement obtained from a LVDT that is mounted on the valve stem at the actuator.

3-44.4. Specifications Table 3-155. LVDT Coil Drive Outputs

Signal

1.00 kHz +/-10% sine wave or 3.00 kHz +/-10% sine wave (user selectable via jumpers)

Amplitude: Group 1 Group 2

17.00 Vp-p +/-5%, adjustable 23.75 Vp-p +/-5%, adjustable

Gain Change

0.5% maximum (0 to 60 C)

Offset

25 mV maximum (0 to 60 C)

Total Harmonic Content

1% maximum

Protection

The QVP card Primary Coil Drive circuit may be short circuited without damage to the circuit. Short circuit current is limited to 80 mA nominal.

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3-44. QVP

Table 3-156. LVDT Secondary Inputs

Signal span

25 Vp-p maximum

Common mode voltage

+/- 10 volts maximum

Common mode rejection

55 dB maximum

Voltage applied

+/-30 volts maximum

Differential Input Impedance

10 k ohm with input open-circuited

Table 3-157. QVP Valve Coil Drive Outputs

Signal span: Groups 1 and 3 Groups 2 and 4

+/-2.00 V (+/-25 mA maximum into 80 ohm coils) +/-14.2 V (+/-50.7 mA maximum into 280 ohm coils)

Load resistance: Groups 1 and 3 Groups 2 and 4

80 ohm +/-12% 280 ohm +/-10%

Protection

Any output will function correctly if the other output(s) are short circuited to common. All outputs may be short circuited to +10 V or to -10 V without suffering damage.

Table 3-158. QVP Setpoint Output

Signal span

0.0 to +10.0 volts nominal

Load resistance

5 k ohm minimum

Gain error

50 mV maximum (0 to 60 C) 25 mV maximum (25 C)

Offset

25 mV maximum (0 to 60 C) 4 mV maximum (25 C)

Protection

The QVP card Setpoint Voltage circuit output terminals may be short circuited without damage to the circuit. Short circuit current is limited to 80 mA nominal.

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3-44. QVP

Table 3-159. QVP Valve Position Output

Signal span

0.0 to +10.0 volts at 25 C

Load resistance

500 ohm minimum

Gain error: CPU alive CPU dead Offset: CPU alive CPU dead Protection

50 mV maximum (0 to 60 C) 25 mV maximum (25 C) 200 mV maximum (0 to 60 C) 25 mV maximum (0 to 60 C) 4 mV maximum (25 C) 100 mV maximum (0 to 60 C) The QVP card Position Voltage circuit output terminals may be short circuited without damage to the circuit. Short circuit current is limited to 80 mA nominal.

Table 3-160. QVP Current Loop Input (Groups 3 and 4)

Signal

Unipolar DC current

Input range

4 to 20 mA 20 mA = 0% (fully closed) 4 mA = 100% (fully open)

Input Impedance

250 ohms +/-2% The inpedance converts the 4 to 20 mA input current into a 1 to 5 V input voltage.

Input Circuit

A differential input stage is used to reject common mode voltages present at the QVP card inputs.

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3-44. QVP

Table 3-161. QVP Digital Outputs

Quantity

2 (Manual and Servo-Bad)

Power Supply

21.6 to 30 Volts maximum 24 Volts nominal This voltage must be supplied from an external isolated power supply.

Minimum on voltage

2 VDC sinking 150 mA 3 VDC sinking 200mA

Maximum on current

200 mA

Maximum off voltage

30 VDC

Maximum off current

0.5 mA at 30 VDC

Table 3-162. QVP Digital Inputs

Quantity

6 (Man-Sel, Raise, Lower, Prty-Raise, Prty-Lower, Man-Shtdwn)

Power Supply

21.6 to 30 Volts maximum 24 Volts nominal This voltage must be supplied from an external isolated power supply.

Minimum on voltage

20 Volts

Maximum on voltage

30 Volts

Maximum off voltage

6 Volts

Minimum on current

4.5 mA

Maximum on current

11.5 mA

Maximum off current

3 mA

Table 3-163. QVP Watchdog Timer

Time-out period

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45 msec +/-33%


M0-0053

3-44. QVP

3-44.5. Interface The QVP card occupies a block of eight consecutive DIOB word addresses. All eight of these DIOB addresses can be written to, but reading any of the eight addresses will get the same data. Before data transfer to and from the QVP card can occur, the DIOB address lines must contain an address that has been assigned to the QVP card. The QVP card’s base DIOB address is selected by the installation of jumpers on the QVP card’s P2 connector’s mating front card edge connector (see example in Figure 3-286). Five jumpers may be used to select the base address which will always end in a 0 or an 8. A sixth jumper, CARD-ENA/, must always be installed to enable QVP card access by the DIOB controller. The QVP card interfaces the DIOB controller using sixteen bit data words. Since the DIOB is a byte oriented data bus, two DIOB data transfers are required to transfer DIOB data to or from a QVP card. The order of data transfer must always be low byte first, followed by the high byte. Byte data transfers are not permitted.

QVP P2 card edge connector’s mating hood (front view) Up

CA7 = 1 CA6 = 0

QVP card DIOB Base Address = B8 DIOB Addresses B8 through BF are assigned to this QVP card

CA5 = 1 CA4 = 1 CA3 = 1 CARD-ENA = 1

Jumper installed - Address Bit = Logic 1 Jumper removed - Address Bit = Logic 0

Figure 3-286. Example of QVP DIOB Base Address Selection

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3-44. QVP

3-44.6. Manual Controls Testpoints The QVP card contains 12 testjacks mounted at the front edge of the card. These testjacks permit a voltmeter to be used to measure specific voltage levels on the QVP card or to provide contact inputs in parallel with three of the external isolated contact inputs. Four additional three-position header are used as test points on the QVP card. Table 3-164. QVP Testjacks

Testjack Number

Name

TP1

AGND

Analog power supply common

TP2

VPCAL

Bipolar DC output voltage of the LVDT demodulator circuit (Groups 1 and 2)

TP3

VSET

Setpoint Meter Drive voltage

TP4

VPOS

Position Meter Drive voltage

TP5

VC1

Servo-valve coil 1 voltage

TP6

VC2


TP7

VC3


TP8

C-COM

TP9

ISO-COM

TP10

LMAN-SEL/

TP11

R/

Isolated Local Manual mode valve Raise contact input

TP12

L/

Isolated Local Manual mode valve Lower contact input

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Function

Servo-valve coil drive circuit power supply common Isolated power supply common Isolated Local Manual mode select contact input

JS1

Digital Common

JS7

Analog Common

JS10

Analog Common

JS11

+10 V Reference voltage


M0-0053

3-44. QVP

QVP Card Figure 3-287 illustrates the manual controls and LEDs on a QVP card. These controls are described in the following sections.

Switches

SW1

LE1

SW2 LE2 LE3

Jumpers

123 JS2

123

123 123

123

123

JS8

JS9

POK SRVO OK MAN

LEDs

JS3

JS5 JS6

Figure 3-287. QVP Card

Switches The QVP card contains two switches (SW1 and SW2) that are located near the front edge of the card (see Figure 3-287).

•

SW1 is a pushbutton switch. Pressing and releasing this switch will cause a hard reset of the QVP.

•

SW2 is an SPST toggle switch. The two positions of this switch are test and online. The test, or up position of this switch will disconnect the servo drive from the servo coils and isolate the servo drive amplifiers from the P2 front edge connector.

The on-line, or down position of this switch will connect the servo drive to the servo coils. SW2 must be in the on-line, or down position for normal operation of the QVP card

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3-44. QVP

LEDs The QVP card contains three LED indicators that are mounted near the front edge of the card (see Figure 3-287). Table 3-165describes what the LEDs indicate when they are lit or unlit. Table 3-165. QVP LEDs

LED

Lit

Unlit

LE1

The QVP DIOB power fuse is intact The QVP DIOB power fuse is open or and at least one DIOB supply voltage neither DIOB supply voltage is present. is present.

LE2

If the QVP card is powered, there is There is a problem with the QVP card’s no detected problem with the QVP servo-valve control operation. card’s servo-valve control operation.

LE3

The QVP card is operating in PB MANUAL mode.

The QVP card is currently not in PB MANUAL mode, and may be in any other mode.

Jumpers The QVP card (Groups 1 and 2) contain six three-position single row headers with plug-in jumpers installed (see Figure 3-287). The QVP card (Groups 3 and 4) contain four three-position single row headers with plug-in jumpers installed. Table 3-166. QVP Option Select Headers

Header

Posts Shorted

Function

JS2

1 -2 2-3

Enable Alive watchdog timer Disable Alive watchdog timer

JS3

1 -2 2 -3

Normal running mode Test mode

JS5

1 -2 2 -3

Disable DIOB watchdog timer Enable DIOB watchdog timer

* JS6

1 -2 2 -3

Configure from QVP algorithm Configure from on-board EEPROM

**JS8 **JS9

1 -2 2 -3

Selects LVDT Excitation Oscillator sinewave frequency of 1 KHz. Selects LVDT Excitation Oscillator sinewave frequency of 3 KHz.

* See the Calibration section in “QVP” Servo Controller User’s Guide” (U0-1125). ** Groups 1 and 2 only.

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3-44. QVP

3-44.7. Installation Data Sheet A (QHS)

CARD 8A

1

LVDT A(+)

9A

2

10A

3

LVDT A(-)

8B

4

LVDT B(+)

9B

5

10B

6

LVDT B(-)

16A

7

VOSC (+)

17A

8

18A

9

VOSC (-)

20B

10

Coil 1 Out (+)

21B

11

22B

12

Coil 1 Out (-)

20A

13

Coil 2 Out (+)

21A

14

22A

15

Coil 2 Out (-)

16B

16

Coil 3 Out (+)

17B

17

18B

18

Coil 3 Out (-)

19 20

EDGE-CONNECTOR

B (H/S Ext) 12A

1

13A

2

V POS (+)

14A

3

V POS (-)

12B

4

V SET PT (+)

13B 14B

5 V SET PT (-)

6

2A

7

MAN-SHTDWN/

2B

8

MAN-SEL/

3A

9

LOWER/

3B

10

RAISE/

4A

11

PRTY-RAISE/

4B

12

PRTY-LOWER/

5A

13

MANUAL/

5B

14

SERVO-BAD/

Digital Inputs

Digital Outputs

15 16 17 1B

18

1A 6A

19

+ 24VDC RTN + 24VDC RTN

20

+ 24VDC

Recommended grounding: Figure 3-288 shows shields grounded at the halfshell. Insert a #6 screw in the hole located near the shield terminal on halfshell block “A” and add six jumpers (as shown). Six holes have been drilled on each halfshell block for this purpose. Figure 3-288. QVP Wiring Diagram (Using #6 Screws)

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3-44. QVP

Installation Data Sheet A (QHS)

CARD

LVDT A(+)

8A

1

9A

2

10A

3

LVDT A(-)

8B

4

LVDT B(+)

9B

5

10B

6

LVDT B(-)

16A

7

VOSC (+)

17A

8

18A

9

VOSC (-)

20B

10

Coil 1 Out (+)

21B

11

22B

12

Coil 1 Out (-)

20A

13

Coil 2 Out (+)

21A

14

22A

15

Coil 2 Out (-)

16B

16

Coil 3 Out (+)

17B

17

18B

18

Coil 3 Out (-)

EDGE-CONNECTOR B (H/S Ext) V POS (+)

12A

1

13A

2

14A

3

V POS (-)

12B

4

V SET PT (+)

13B

5

14B

6

2A

7

MAN-SHTDWN/

2B

8

MAN-SEL/

3A

9

LOWER/

3B

10

RAISE/

4A

11

PRTY-RAISE/

4B

12

PRTY-LOWER/

5A

13

MANUAL/

5B

14

SERVO-BAD/

V SET PT (-)

Digital Inputs

Digital Outputs

15 1B

16

+ 24VDC RTN

1A

17

+ 24VDC RTN

6A

18

+ 24VDC

Recommended grounding: Figure 3-289 shows shields grounded at the halfshell. Insert a #6 screw in the hole located near the shield terminal on halfshell block “A” and add six jumpers (as shown). Six holes have been drilled on each halfshell block for this purpose. Figure 3-289. QVP Wiring Diagram (Using #8 Screws)

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3-44. QVP

For CE MARK Certified System *

CARD

A

1

A LVDT A(+)

8A

1

1

9A

2

2

10A

3

3

LVDT A(-)

8B

4

4

LVDT B(+)

9B

5

5

10B

6

6

LVDT B(-)

16A

7

7

VOSC (+)

17A

8

8

18A

9

9

VOSC (-)

20B

10

10

Coil 1 Out (+)

21B

11

11

22B

12

12

Coil 1 Out (-)

20A

13

13

Coil 2 Out (+)

21A

14

14

22A

15

15

Coil 2 Out (-)

16B

16

16

Coil 3 Out (+)

17B

17

17

18B

18

18

PE

PE

Coil 3 Out (-)

EDGE-CONNECTOR

*

A

2

A V POS (+)

12A

1

1

13A

2

2

14A

3

3

V POS (-)

12B

4

4

V SET PT (+)

13B

5

5

14B

6

6

2A

7

7

MAN-SHTDWN/

3A

8

8

LOWER/

2B

9

9

MAN-SEL/

3B

10

10

RAISE/

4B

11

11

PRTY-LOWER/

4A

12

12

PRTY-RAISE/

5A

13

13

MANUAL/

V SET PT (-)

Digital Inputs

Digital Outputs

14

14

5B

15

15

SERVO-BAD/

1A

16

16

+ 24VDC RTN

1B

17

17

+ 24VDC RTN

6A

18

18

+ 24VDC

PE

PE

* DIN-rail mounted tension clamp terminal block Figure 3-290. QVP CE MARK Wiring Diagram

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Appendix A. Worksheets A-1. Section Overview The following pages contain three worksheets which can be used to assign and record Q-Card addresses and Q-Crate slot assignments.

•

Worksheet A shows the possible Q-Card hardware addresses, and provides space to record the card which is assigned each address.

•

Worksheet B can be used to record the Q-Crate slot assignment and assigned hardware address for each card (when default naming is not used).

•

Worksheet C can be used to record the Q-Crate slot assignment for each card (when default naming is used). The address associated with each card slot (for default naming) is shown also.

Both Worksheets B and C show the card-edge connector identification and half-shell location (zone-row) for each Q-Crate slot, and provide space to record the card type and group. For additional information on the default naming option, refer to “MAC Utilities User’s Guide” (U0-0136).

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A-1 Westinghouse Proprietary Class 2C

M0-0053

A-1. Section Overview

Worksheet A Q-Card Address Assignments *80 81 82 83 84 85 86 87

*90 91 92 93 94 95 96 97

*A0 A1 A2 A3 A4 A5 A6 A7

*B0 B1 B2 B3 B4 B5 B6 B7

*C0 C1 C2 C3 C4 C5 C6 C7

D0 D1 D2 D3 *D4 D5 D6 D7

*E0 E1 E2 E3 *E4 E5 E6 E7

*F0 F1 F2 F3 *F4 F5 F6 F7

*88

*98

*A8

*B8

*C8

*D8

89 8A 8B 8C 8D 8E 8F

99 9A 9B 9C 9D 9E 9F

A9 AA AB AC AD AE AF

B9 BA BB BC BD BE BF

C9 CA CB *CC CD CE CF

D9 DA DB *DC DD DE DF

*E8 E9 EA EB *EC ED EE EF

*F8 F9 FA FB FC FD FE FF

00 01 02 03 04 05 06 07

*10

*20

*30

*40

*50

*60

11 12 13 14 15 16 17

21 22 23 24 25 26 27

31 32 33 34 35 36 37

41 42 43 44 45 46 47

51 52 53 54 55 56 57

61 62 63 64 65 66 67

*70 71 72 73 74 75 76 77

*08 09 0A 0B 0C 0D 0E 0F

*18

*28 29 2A 2B 2C 2D 2E 2F

*38

*48

*58

39 3A 3B 3C 3D 3E 3F

49 4A 4B 4C 4D 4E 4F

59 5A 5B 5C 5D 5E 5F

*68 69 6A 6B 6C 6D 6E 6F

19 1A 1B 1C 1D 1E 1F

*78 79 7A 7B 7C 7D 7E 7F

Indicates restricted address – DO NOT USE Indicates reserved address (80 = QTB; AA and 55 = QBO; F8-FB = QRT) Available only if QTB and/or DIOB checking is not implemented * Indicates address used with default naming feature Q-Cards with: 12 channels (QAX) must start at zero and use 2 blocks of 6 addresses 8 or 6 channels (QAH, QAV, QAW, QLI, QLJ) must start at x0, x8 4 channels (QAI, QAO, QPA, QSE) must start at x0, x4, x8, xC 2 channels (QAA, QAM, QLC) must start at x0, x2, x4, x6, x8, xA, xC, xE where x = 0 through F Other cards (QBI, QCI, QDI, QID, QRO, QSC, QSP, QTO) may use any address Note QBI and QDI are being replaced by the QID card

Figure A-1. Q-card Hardware Address Selection Form

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Worksheet B Q-Line I/O Layout Cabinet No.

Drop No. Q-Crate 1 (Q1) Slot

1

2

3

4

5

6

7

8

9

10

11

12

Card Type

13 QBE

Group Card Edge

102

104

106

108

110

112

114

116

118

120

122

124

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

A6

B6

2

3

4

5

6

7

8

9

10

11

12

Address Half-Shell

Q-Crate 2 (Q2) Slot

1

Card Type

13 QBE

Group Card Edge

202

204

206

208

210

212

214

216

218

220

222

224

C1

D1

C2

D2

C3

D3

C4

D4

C5

D5

C6

D6

2

3

4

5

6

7

8

9

10

11

12

Address Half-Shell

Q-Crate 3 (Q3) Slot

1

Card Type

13 QBE

Group Card Edge 302

304

306

308

310

312

314

316

318

320

322

324

F1

E2

F2

E3

F3

E4

F4

E5

F5

E6

F6

2

3

4

5

6

7

8

9

10

11

12

Address Half-Shell

E1

Q-Crate 4 (Q4) Slot

1

Card Type

13 QBE

Group Card Edge 402

404

406

408

410

412

414

416

418

420

422

424

H1

G2

H2

G3

H3

G4

H4

G5

H5

G6

H6

Address Half-Shell

G1

Worksheet B

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Worksheet C Q-Line I/O Layout (Default Naming Option) Cabinet No.

Drop No. Q-Crate 1 (Q1) Slot

1

2

3

4

5

6

7

8

9

10

11

12

Card Type

13 QBE

Group Card Edge

102

104

106

108

110

112

114

116

118

120

122

124

Address

08

10

18

20

28

30

38

40

48

50

58

60

Half-Shell

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

A6

B6

2

3

4

5

6

7

8

9

10

11

12

Q-Crate 2 (Q2) Slot

1

Card Type

13 QBE

Group Card Edge

202

204

206

208

210

212

214

216

218

220

222

224

Address

68

70

78

80

88

90

98

A0

A8

B0

B8

C0

Half-Shell

C1

D1

C2

D2

C3

D3

C4

D4

C5

D5

C6

D6

2

3

4

5

6

7

8

9

10

11

12

Q-Crate 3 (Q3) Slot

1

Card Type

13 QBE

Group Card Edge

302

304

306

308

310

312

314

316

318

320

322

324

Address

C8

CC

D0

D4

D8

DC

E0

E4

E8

EC

F0

F4

Half-Shell

E1

F1

E2

F2

E3

F3

E4

F4

E5

F5

E6

F6

2

3

4

5

6

7

8

9

10

11

12

Q-Crate 4(Q4) Slot

1

Card Type

13 QBE

Group Card Edge

402

404

406

408

410

412

414

416

418

420

422

424

G1

H1

G2

H2

G3

H3

G4

H4

G5

H5

G6

H6

Address Half-Shell

Worksheet C

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Appendix B. Setting Q-Card Addresses B-1. Introduction This appendix shows how to set the appropriate jumpers to define an address on a Q-card. Figure B-1 shows the connector handle and position of the address jumpers. Figure B-2 shows a head-on view of the address jumpers. The figure also shows the conversion of the hexadecimal address (supplied by Westinghouse on the worksheets) and the binary equivalent via jumpering. Table B-1 shows the binary equivalent for hexadecimal 00 to FF (256)

28 (Last Address Jumper) 27 26 25 24 23 22 21 (First Address Jumper Location)

WD

PF Q- L II i I/ n e O

Note: The first 20 locations are reserved for card wiring.

Figure B-1. Address Jumpers on Cable Connector (“B” Cabinet Terminations)

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B-1 Westinghouse Proprietary Class 2C

M0-0053

B-1. Introduction

DIOB CARD ADDRESS = 00100011 = 23H

BLANK: A7 = 0 BLANK: A6 = 0 JUMPER: A5 = 1 BLANK: A4 = 0 BLANK: A3 = 0 BLANK: A2 = 0 JUMPER: A1 = 1 JUMPER: A0 = 1

Figure B-2. Card Address Jumper Assembly

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B-1. Introduction

Table B-1. Conversion of Hexadecimal Number to Jumper Address

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Hexadecimal Card Address

A7

A6

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Jumper Settings A5 A4 A3 A2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1


0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

A1

A0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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B-1. Introduction

Table B-1. Conversion of Hexadecimal Number to Jumper Address (Cont’d)

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A7

A6

22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1


1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0


0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0

0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

A1

A0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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B-1. Introduction


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A7

A6

44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1


0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0

0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1

A1

A0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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B-1. Introduction


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A7

A6

66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0


1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0


0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

A1

A0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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B-1. Introduction


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A7

A6

88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1


0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

A1

A0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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B-1. Introduction


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A7

A6

AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1


1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0


0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1

0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

A1

A0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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B-1. Introduction


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A7

A6

CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1


0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1

A1

A0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

M0-0053

B-1. Introduction

Table B-1. Conversion of Hexadecimal Number to Jumper Address (Cont’d) Hexadecimal Card Address

A7

A6

EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

A1

A0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

For an adjacent cabinet, the next 256 (decimal) addresses are obtained by adding a jumper below the A0 (or number 20) location as seen in Figure B-2.

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Appendix C. Card-Edge Field Termination C-1. Section Overview The DPU drop utilizes one of two methods of field signal terminations. This appendix discusses the card-edge termination, where the drop is packaged in a single “A” Cabinet. In the second method (cabinet termination), the drop is packaged in dual (“A” and “B”) cabinets. Refer to Section 2 for information on the cabinet method of signal termination. Note There are two types of A and B cabinets, the Standard and the Enhanced. With the Enhanced cabinets, there are more slots for Q-Cards, more half-shell zones, and more terminals per half-shell zone.

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C-1 Westinghouse Proprietary Class 2C

M0-0053

C-2. Card-Edge Connectors Card-edge terminations are recommended only for “A” Cabinets with three Q-crates with a maximum of 12 Q-cards per crate, providing a maximum of 36 cards. When using card-edge termination, field connections are made to screw-down terminals on each card’s edge connector. Note Use of card-edge connections is not recommended with the Enhanced “A” cabinet with 4 Q-Crates. Field termination edge connectors are used at each Q-card for user field signal connections. Q-Card addresses are assigned using jumper clips which are inserted into the termination card-edge connector. The field termination card-edge connector also contains address selection slots 20 through 28, as shown in Figure C-1. These 9 slots are located on the top right side of the connector. A specific card address is selected by the insertion of jumpers into the appropriate slots. Note The card-edge termination connector cannot be used with a QAA or QAX card.

Figure C-1. Address Jumpers on Card-Edge Termination Connector

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Figure C-2 shows the standard card-edge termination hardware, with an exploded view of a card-edge connector. The cabinet illustrated in Figure C-2 is a Standard cabinet. An Enhanced cabinet would contain four Q-Crate zones.

Edge Connector for Field Terminations C A R D

Q C R A T E

Q1

E D G E

Q2 Paddle Card for Expansion

Z O N E Q3 S

Q-Crate Slot 1 Q-Card

F U S E

C O N N E C T O R

Electronics A-Cabinet Front

Figure C-2. Standard Card-Edge Field Connections

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As shown in Figure C-3, each connector contains 20 screw-down terminals for field signal terminations. The top 7 screw-down terminals (1 through 7) are field termination tie points, which duplicate the function of the B-block in the half-shell type terminations. These tie points are not used in analog terminations. Field connections to and from the card-edge connector can be made using up to No. 14 AWG conductor wire. However, for ease of connector removal and replacement after installation, Westinghouse recommends that No. 16 AWG or smaller conductor wire be used. Each connector’s wires are bundled together after the field connections are completed, and are tie-wrapped to the cabinet frame directly under the Q-crate.

7 6 Fuse

5 4 3

Field Signal Terminations

19B 17B 15B 13B 11B 9B 7B 5B 3B 1B

2 1 19A 17A 15A 13A 11A 9A 7A 5A 3A 1A

Field Termination Tie Points

Field Signal Terminations

Figure C-3. Screw-Down Terminal Numbers

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Table C-1, which illustrates the Q-crate terminal locations, can be used to locate terminals for field signal connection. Table C-1. Card-Edge Terminal Locations Card Slot Numbers 1

2

3

4

5

6

7

8

9

10

11

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

12

19B • 19A •• Q1 •• 1B• 1A

Q 19B • 19A C •• Q2 R •• A 1B• T 1A E 19B 19B 19B 19B 19B 19B 19B 19B 19B 19B 19B 19B • 19A • 19A • 19A • 19A • 19A • 19A • 19A • 19A • 19A • 19A • 19A • 19A •• •• •• •• •• •• •• •• •• •• •• •• Q3 •• •• •• •• •• •• •• •• •• •• •• •• 1B• 1B• 1B• 1B• 1B• 1B• 1B• 1B• 1B• 1B• 1B• 1B• 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

19B • 19A •• •• 1B• 1A

Note: Field Termination Tie Points not shown.

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C-3. Field Wiring Card-Edge Terminations Follow these procedures for field wiring the WDPF System to the termination card-edge connectors within the electronics cabinet. Use the custom Termination Lists supplied for the system to locate specific termination points. Also refer to the specific card information provided in Section 3. WARNING Remove drop power and use extreme caution when making field connections to these edge-connectors. A shock hazard to personnel may exist on some of the higher voltage signals. 1. Select a card-edge termination connector for field wiring. It is usually best to start at Q-crate 1, slot 1. Then work across to slot 12 of Q-crate 1, and then move down to Q-crate 2, slot 1 and so on. Another option is to start at Q-crate 3, working up to Q-crate 1. 2. If not previously done at the factory, insert the appropriate jumpers in the upper-right hand side of the connector. Each card’s selected address should be in compliance with the terminations list. Caution After address selection, take care not to switch connectors between cards. Doing so will indiscriminately switch card addresses. 3. Locate the field wires or cables to be connected to the selected edge-connector and make connections to the screw-down terminals. Connection to these terminals may be made with up to No. 14 AWG conductors. However, for ease of connector installation and removal, Westinghouse recommends no greater than No. 16 AWG conductors be used. Only wires and/ or cables which comply with each field connection’s signal and noise minimization requirements should be used. 4. Bundle the wires connected to the terminal block with tie wraps and then tie-wrap to the cabinet frame directly under the Q-crate. Use wire tags to identify the cables. Remember to leave service loops to relieve stress and/or to permit access to the cabinet when it is to be moved out of position for maintenance purposes. 5. Repeat the procedures of Steps 1 through 4 for each remaining edge-connector until all field terminations to the cabinet have been completed.

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Index Numerics 12 Point Analog Input card 3-173 8039 3-423

A A/D converter 3-49 actuator auto manual card 3-14 actuator position 3-15 address blocks 2-29 address jumpers B-1 address selection slot C-2 address selection via jumper 2-36 addresses setting B-1 addressing constraints 2-32 Air Temperatures 2-39 analog conditioning card 3-37 analog high level input point 3-148 analog input card 3-61 analog input point 3-49 analog output card 3-100 analog position 3-19 analog signal conditioner 3-37 analog signal filtering 2-12 Analog Signal Shielding Techniques 2-15 analog to digital 3-119, 3-148, 3-173 analog velocity 3-18 analog-to-digital converters 3-61 Auto mode 3-344, 3-353 Automatic mode 3-91 Automatic/Manual card 3-74

B B Cabinet compensation 2-19 enhanced 2-23 standard 2-23 Termination Structure 2-25 Beck drive 3-14 bridge power supply 2-19 Bridge Resistor 3-436, 3-439

C cabinet number, def. 2-5 Cabinet Termination 2-22 cable length 3-260 cable routing 2-37 card replacement 2-37

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Card Type Index 3-179, 3-180 card-edge connectors 2-3, C-2, C-6 field termination C-1 termination 2-22, C-6 cascaded control loop 3-332 CCI 2-21 CCO 2-21 CD 3-179, 3-180 CE MARK Certified System 3-49, 3-61, 3100, 3-119, 3-148, 3-173, 3-193, 3-200, 3224, 3-235, 3-254, 3-265, 3-276, 3-282, 3296, 3-317, 3-318, 3-351, 3-365, 3-398, 3399, 3-420, 3-421, 3-458, 3-483, 3-512, 3541, 3-553, 3-573 Chattering 3-483, 3-490 clock 3-86, 3-87 Clock Synchronizing 3-500 Cold Junction 3-193 common mode rejection 3-128 common-mode voltage 2-11 compensation B-cabinet 2-19 half-shell 2-18 on-board 2-20 configuration constants 3-325, 3-338 configuration data 3-325, 3-338 contact allocations 3-417 contact input card 3-254 contact-wetting voltage 3-254 Continuous Scan 3-50 control timing 3-66 copper RTD 3-423 Current Amplifier card 3-235 current to pressure, I/P converter 3-74

D database limitations 2-35 daughter card 3-16 derived QPA functions 3-386 diagnostic test card 3-276 differential input 3-50 digital contact input 3-254 Digital Controller 3-265 digital input 3-213, 3-266 digital input card 3-212 digital multiplexed interface 3-61

Index-1 Westinghouse Proprietary Class 2C

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Index H

digital output card 3-224 digital signal 3-100 digital signal isolation 2-11 digital, increased cable length 3-296 digital-to-analog 3-100 DIOB 3-70, 3-318, 3-332, 3-359 Addressing 3-381 definition 3-366 interface 3-20, 3-44, 3-79 monitor 3-283 DIP switch 3-99 Display mode 3-279 DPU 2-2 drops 1-1

half-shell 2-3 compensation 2-18 Termination 2-38 termination C-4 zone location, def. 2-5 hardware addresses 2-29 available 2-29 determining 2-29 restricted blocks 2-29 Selection Form 2-31 worksheet A-1 HART 3-552 highways 1-1 Hl/LO jumper 2-36 Hl/LO signal 2-32 Humidity Rating 2-39

E E/P, voltage to pressure 3-74 EEPROM 3-325 elapsed time measurement 3-365 electromagnetic 2-13 electromagnetic field 2-11 electrostatic 2-13 electrostatic field 2-11 ENABLE jumper 2-36 Enable signal 2-32 errors, LED 3-546

I I/P, current to pressure 3-74 increased cable length (digital) 3-296 Input Amplifier Four Wire RTD card 3-399 Input Amplifier card 3-421

J

F fast acting actuator 3-14 field signal connections 2-38 termination 2-22, C-1 list 2-3 wiring 2-2 field termination 2-2 field wiring 2-1, 2-2 FLAG 3-366 flag bit 3-133, 3-160 flow-rate meter 3-365 Four Wire RTD Input Amplifier 3-399 frequency summation 3-421 frozen 3-366

G ground connection, def. 2-5 Grounding 2-13

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jumper 2-36, 3-19, 3-34, 3-57, 3-97, 3-131, 3135, 3-158, 3-178, 3-196, 3-207, 3-228, 3257, 3-290, 3-326, 3-339, 3-380, 3-415, 3416, 3-435, 3-455, 3-500, 3-503, 3-543, 3544, 3-546, 3-558, 3-561, 3-568 ENABLE 2-36 HI/LO 2-36

L lamps 3-224 LED 3-33, 3-95, 3-114, 3-134, 3-137, 3-162, 3-164, 3-185, 3-207, 3-221, 3-231, 3-262, 3-274, 3-278, 3-291, 3-306, 3-326, 3-339, 3-349, 3-353, 3-357, 3-457, 3-472, 3-503, 3-543, 3-546, 3-568 LIM 1-4, 3-319, 3-333, 3-343 Block Diagram 3-344 Components 3-349 Features 3-344 groups 3-10 power consumption 2-41 ranges 3-10


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Index overrange bit 3-49, 3-160

Specifications 3-348 limit check 3-121, 3-149 line frequency switching 3-562 links DIOB backplane 3-200 LMAN 3-19 LMNA 3-19 Local mode 3-345, 3-353 Loop Interface card 3-318 with output readback 3-332 Loop Interface Module 3-343 low pass filtering 2-9 Lower output 3-344, 3-352 Lower setpoint 3-344, 3-352 low-level signal, shielding 2-15

P pin assignments 3-261 platinum 3-423 platinum RTD 3-423 plug braking 3-14 point number, def. 2-4 position encoder 3-365 position feedback 3-14 potentiometers 3-98 Power Consumption 2-40 power line frequency 2-9 Proper Grounding and Shielding 2-13 Pulse Accumulator 3-365

M Manual mode 3-91, 3-345, 3-353 memory bus 3-359 Memory Bus Terminator card 3-359 monitor DIOB 3-283 mother card 3-16 multiple channel hardware address 2-32 multiplex 3-61 multi-speed DPU 2-35

N nickel RTD 3-423 noise class 2-10 discrimination 2-7 minimization techniques 2-7 problems 2-37 source 2-10 noise and signal sources 2-10 noise minimization techniques 2-1 noise rejection 2-11 noise-sensitive suppression 2-12

O On-Board Compensation 2-20 open thermocouple detection 3-64 optical isolator 2-11 output data 3-159 output flashing 3-232 Output Signal Noise Rejection 2-12 Ovation QAV 3-139 QAX 3-180

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Q QAA 1-4, 3-14 Card Addressing 3-20 Card Outline 3-16 Controls and Indicators 3-23 groups 3-4 power consumption 2-40 ranges 3-4 Specifications 3-18 Tuning 3-24 Word Format 3-20 QAC 1-4, 3-37 Block Diagram 3-37 Controls and Indicators 3-48 groups 3-4 power consumption 2-40 ranges 3-4 Specifications 3-42 QAH 1-4, 3-49 Block Diagram 3-49 Card Addressing 3-53 CE MARK Wiring Diagram 3-60 Controls and Indicators 3-57 groups 3-4 Installation Data Sheet 3-59 power consumption 2-40 ranges 3-4 Specifications 3-50 QAI 1-4, 3-61 Block Diagram 3-61 Card Addressing 3-70 Card Diagram 3-71


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Index CE MARK Wiring Diagram 3-73 groups 3-4, 3-62 Installation Data Sheet 3-72 power consumption 2-40 ranges 3-4 Specifications 3-63 QAM 1-4, 3-74 Block Diagram 3-74 Controls and Indicators 3-91 groups 3-5 power consumption 2-40 ranges 3-5 Reset 3-94 Specifications 3-78 QAO 1-4, 3-100 Block Diagram 3-100 Card Addressing 3-113 CE MARK Wiring Diagram 3-117 Controls and Indicators 3-113 groups 3-5, 3-101 Installation Data Sheet 3-116 power consumption 2-40 ranges 3-5 Specifications 3-105 QAV 1-4, 2-19 analog input point 3-119 Block Diagram 3-119 Card Addressing 3-131 CE MARK Wiring Diagram 3-147 Controls and Indicators (Level 6 and earlier) 3-134 (Level 8 and later) 3-136 Features 3-123 groups 3-5 Installation Data Sheet 3-143 power consumption 2-40 ranges 3-5 Specifications 3-126 QAW 1-4, 3-148 Block Diagram 3-148 Card Addressing 3-158 CE MARK Wiring Diagram 3-172 Controls and Indicators 3-162, 3-163 groups 3-6 Installation Data Sheets 3-165 power consumption 2-40 ranges 3-6 Specifications 3-151

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QAX 1-4, 3-173 Block Diagram 3-173 Card Addressing 3-178 CE MARK Wiring Diagram 3-189 Controls and Indicators 3-184 groups 3-6 Installation Data Sheet 3-186 power consumption 2-40 ranges 3-6 Specifications 3-176 QAXD 1-4, 3-190 groups 3-6 power consumption 2-40 ranges 3-6 QAXT 1-4, 3-193 Block Diagram 3-193 Controls and Indicators 3-195 groups 3-6 power consumption 2-40 ranges 3-6 Specifications 3-194 Wiring 3-196 QBE 1-4, 3-200 Block Diagram 3-200 Controls and Indicators 3-207 groups 3-6 power consumption 2-40 ranges 3-6 Specifications 3-205 QBI 1-4, 3-212 Block Diagram 3-215 Card Addressing 3-217 Controls and Indicators 3-221 groups 3-7 Installation Data Sheet 3-222 power consumption 2-40 QID replacement 3-296 ranges 3-7 Specifications 3-215 QBI - QID equivalence 3-212 QBO 1-4, 3-224 Block Diagram 3-224, 3-226, 3-228, 3-229, 3-231, 3-232, 3-233, 3-234 Card Addressing 3-228 CE MARK Wiring Diagram 3-234 Controls and Indicators 3-231 groups 3-7 Installation Data Sheet 3-233


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Index power consumption 2-40 ranges 3-7 Specifications 3-227 QCA 1-4, 3-235 Card Outline 3-248, 3-249, 3-250, 3-251, 3252, 3-253 CE MARK Wiring Diagram 3-253 Controls and Indicators 3-248 groups 3-7 Installation Data Sheets 3-251 Operation 3-240 power consumption 2-40 ranges 3-7 Signal Interface 3-238 Specifications 3-236 Q-Card 3-1 hardware address 2-29 Hardware Address Selection 2-34 Q-card address, def. 2-4 Q-Card Addresses setting B-1 Q-card Hardware Address A-2 Q-Cards 1-3 list of available 1-4 QCI 1-4, 3-254 Block Diagram 3-254 Card Addressing 3-257 CE MARK Wiring Diagram 3-264 Controls and Indicators 3-262 groups 3-7 Installation Data Sheet 3-263 power consumption 2-40 ranges 3-7 Specifications 3-256 Q-Crate card slots 2-35 QDC 1-4, 3-265 groups 3-7 power consumption 2-40 ranges 3-7 QDI 1-4 Block Diagram 3-267 Card Addressing 3-269 Controls and Indicators 3-274 groups 3-8, 3-267 Installation Data Sheet 3-275 power consumption 2-40 QID replacement 3-296 ranges 3-8

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Specifications 3-268 QDI - QID, equivalence 3-266 QDT 1-4, 3-276 Block Diagram 3-276 Controls and Indicators 3-279 groups 3-8 power consumption 2-41 ranges 3-8 Specifications 3-277 QFR 1-4, 3-282 groups 3-8 ranges 3-8 QIC 1-4, 3-283 Block Diagram 3-283, 3-289, 3-290, 3-293, 3-294 Controls and Indicators 3-290 groups 3-8 power consumption 2-41 ranges 3-8 Signal Interface 3-292 Specifications 3-289 QID 1-4, 3-212, 3-266 Block Diagram 3-296 Card Addressing 3-305 CE MARK Wiring Diagram 3-314 Controls and Indicators 3-306 groups 3-9 Installation Data Sheet 3-310 power consumption 2-41 Q-Line Digital Input 3-296 ranges 3-9 Specifications 3-300 Wiring 3-307 QID - QBI equivalence 3-212 QID - QDI, equivalence 3-266 QLC 1-4, 3-317, 3-552 groups 3-9 power consumption 2-41 ranges 3-9 QLI 1-4, 3-318, 3-343, 3-351 Block Diagram 3-318 Card Addressing 3-323 CE MARK Wiring Diagram 3-330 Circuit Description 3-322 Controls and Indicators 3-324 groups 3-9 Installation Data Sheet 3-327 Interface Specifications 3-322


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Index power consumption 2-41 ranges 3-9 Specifications 3-321 Q-Line Bus Extender 3-200 Q-Line DIOB Monitor 3-283 Q-Line Loop Interface Card 3-318, 3-332 Q-Line RTD Input Amplifier RTD card 3-421 Q-line Serial Link Controller 3-317 QLJ 1-4, 3-332 Block Diagram 3-332 Card Addressing 3-337 Circuit Description 3-336 Controls and Indicators 3-338 groups 3-10 Installation Data Sheet 3-340 power consumption 2-41 ranges 3-10 Specifications 3-335 QMT 1-4, 3-359 Block Diagram 3-359, 3-361 groups 3-10 ranges 3-10 Signal Requirements 3-363 QPA 1-4, 3-365 Addressing 3-377 Applications 3-386 Average Inverse Speed Measurement 3-390 Block Diagram 3-365 CE MARK Wiring Diagram 3-395 Definitions 3-366 Elapsed Time Measurement 3-388 External Inputs’ Digital Filter Clock 3-376 groups 3-10 Implementation Example 3-390 Installation Data Sheet 3-393 Internal Timebase Clocks 3-376 power consumption 2-41 ranges 3-10 Specifications 3-373 Speed Measurement 3-387 Speed Ratio Measurement 3-389 QRC 1-4, 3-398 power consumption 2-41 QRF 1-4, 3-399 Block Diagram 3-400 Card Addressing 3-405 CE MARK Wiring Diagram 3-409

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Controls and Indicators 3-407 groups 3-11 Installation Data Sheet 3-408 power consumption 2-41 ranges 3-11 Specifications 3-402 QRO 1-4, 3-410 Block Diagram 3-410 Card Addressing 3-415 Controls and Indicators 3-416 groups 3-11 Installation 3-417 Installation Data Sheet 3-419 power consumption 2-41 ranges 3-11 Specifications 3-412 QRS 1-4, 3-420 groups 3-11 power consumption 2-41 ranges 3-11 QRT 1-4, 2-19, 3-421 Application Information 3-435 Block Diagram 3-421 Card Addressing 3-434 CE MARK Wiring Diagram 3-451 Controls and Indicators 3-435 Definition of Terms 3-422 Field Input Connection 3-432 groups 3-11 Installation Data Sheet 3-447 power consumption 2-41 ranges 3-11 Specifications 3-429 QSC 1-4, 3-453 Block Diagram 3-453 Controls/Indicators 3-457 groups 3-11 power consumption 2-41 ranges 3-11 Specifications 3-455 Wiring 3-457 QSD 1-4, 3-458 Card Addressing 3-471 CE MARK Wiring Diagram 3-481 Controls and Indicators 3-471 groups 3-11 Installation Data Sheet 3-481 Operator Interface 3-468


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Index power consumption 2-41 ranges 3-11 Specifications 3-460 QSE 1-4, 3-483 Application Information 3-505 Card Addressing 3-503 CE MARK Wiring Diagram 3-511 chattering 3-490 Circuit Description 3-492 Controls and Indicators 3-503 Firmware Considerations 3-500 groups 3-11 Installation Data Sheet 3-510 power consumption 2-41 ranges 3-11 Signal Interface 3-490 Specifications 3-486 QSR 1-4, 3-512 CE MARK Wiring Diagram 3-537 Controls and Indicators 3-526 groups 3-11 Installation Data Sheet 3-535 Operation 3-522 power consumption 2-41 ranges 3-11 Signal Interface 3-518 Specifications 3-513 Test Points 3-534 Valve Calibration 3-528 QSS 1-4, 3-541 Block Diagram 3-541 CE MARK Wiring Diagram 3-551 Controls and Indicators 3-546 groups 3-12 Installation Data Sheet 3-548 power consumption 2-41 ranges 3-12 replacing QSC 3-453 Specifications 3-544 QST 1-4, 3-552 groups 3-12 power consumption 2-41 ranges 3-12 QTB 1-4, 3-553 Block Diagram 3-553 Control and Indicators 3-559 groups 3-12 power consumption 2-41

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ranges 3-12 Specifications 3-554 QTO 1-4, 3-562 Block Diagram 3-562 Card Addressing 3-568 Controls and Indicators 3-568 groups 3-12 Installation Data Sheet 3-572 power consumption 2-41 ranges 3-12 Specifications 3-566 QVP 1-4 CE MARK Wiring Diagram 3-582, 3-583, 3584 power consumption 2-41

R Raise output 3-344, 3-352 Raise setpoint 3-344, 3-352 Redundant Station Interface card 3-420 reference junction compensation 3-193 relay coils 3-224 relay output card 3-410 relay switching 3-410 Remote I/O Fiber-Optic Interface 3-282 Remote Q-Line Controller card 3-398 reset 3-493 resistors 3-95 restricted block address 2-29 row 2-23 RTD 3-399, 3-423 copper 3-423 Input Amplifier card 3-421 nickel 3-423 signal field connection 2-19 use of 3-443

S safe operation 3-414 Scan and Hold 3-50 scan rate 3-50 sequence of events 3-483 serial link controller 3-317 servo driver card 3-235, 3-458 Servo Driver with Positional Readback card 3512 setpoint zero 3-98 shielding 2-13


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Index low-level signal 2-15 sign bit 3-160 signal termination 2-1 signal wire coupling 2-11 Simulator mode 3-278 single-speed DPU 2-35 site preparation and planning 2-37 slidewire power supply 3-36 SLIM 1-4, 3-319 Block Diagram 3-352 CE MARK Certified System 3-358 Components 3-356 Features 3-352 groups 3-10 power consumption 2-41 ranges 3-10 Small Loop Interface Module 3-351 Specifications 3-356 slot assignment worksheet A-1 smart transmitter interface 3-552 smart transmitter interface card 3-552 solid-state AC switching 3-562 sort-by-hardware 2-3 sort-by-point 2-3 speed channel card 3-453 speed measurement 3-365 speed ratio measurement 3-365 speed sensor card 3-541 SSR 3-570 SST 3-552 standard card-edge termination hardware C-3 stepping motors 3-224 STI 3-552 Surge Protection 2-14 switching transients 2-9

coefficient 3-181 considerations 2-18 grounding 2-20 thresholding 2-8 tie point C-4 time base card 3-553 Time Interval (Ti) 3-490 timing signal 3-553 transient noise 2-9 TRIAC Output card 3-562 tuning constant 3-345 turning constant 3-353 twisted pairs 2-13

V Valve Actuator 3-465 Vibration 2-39 voltage to pressure, E/P 3-74

W W2500 I/O subsystem 3-283 watchdog timer 3-15, 3-19, 3-75, 3-465, 3493, 3-546 WDPF field wiring 2-1 WDPF Installation 1-1, 1-2 WEMAC 3-14 worksheets A-1

Z zone 2-23

T tachometer 3-365 tachometer signal pulse 3-453, 3-541 Temperatures 2-39 terminal block temperature sensing 3-193 terminal strip connection points, def. 2-5 termination cabinet 2-22, 2-38 card-edge 2-22 point 2-38 thermocouple 3-66, 3-120, 3-193

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Ovation Q Line

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