Modeling the Effect of Velocity Saturation in Nanoscale Mosfet

MODELING THE EFFECT OF VELOCITY SATURATION IN NANOSCALE MOSFET

MICHAEL TAN LOONG PENG

UNIVERSITI TEKNOLOGI MALAYSIA

PSZ 19:16 (Pind. 1/97)

UNIVERSITI TEKNOLOGI MALAYSIA

BORANG PENGESAHAN STATUS TESIS JUDUL: MODELING THE EFFECT OF VELOCITY SATURATION SATURATION

IN NANOSCALE MOSFET SESI PENGAJIAN: 2006/2007

MICHAEL TAN LOONG PENG

Saya

(HURUF BESAR)

mengaku membenarkan tesis (PSM / Sarjana / Doktor Falsafah)* ini disimpan di Perpustakaan Universiti Teknologi Malaysia dengan syarat-syarat kegunaan seperti berikut: 1. 2. 3. 4.

Tesis adalah hakmilik Universiti Teknologi Malaysia. Perpustakaan Universiti Teknologi Malaysia dibenarkan membuat salinan untuk tujuan  pengajian sahaja. Perpustakaan dibenarkan membuat salinan tesis ini sebagai bahan pertukaran antara institusi pengajian tinggi. **Sila tandakan (

)

SULIT

(Mengandungi maklumat yang berdarjah keselamatan atau kepentingan Malaysia seperti yang termaktub di dalam AKTA RAHSIA RASMI 1972)

TERHAD

(Mengandungi maklumat TERHAD yang telah ditentukan oleh organisasi/badan di mana penyelidikan dijalankan)

TIDAK TERHAD Disahkan oleh

(TANDATANGAN PENULIS)

(TANDATANGAN PENYELIA)

Alamat Tetap: 293 LORONG MERBAU

PROF. MADYA DR. RAZALI ISMAIL

TAMAN BERSATU

 Nama Penyelia

09000 KEDAH

Tarikh:

Tarikh:

CATATAN: CATATAN: * Potong yang tidak berkenaan. **Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak   berkuasa/organisasi berkenaan dengan menyatakan sekali sebab dan tempoh tesis ini  perlu dikelaskan sebagai SULIT atau TERHAD. Tesis dimaksudkan sebagai tesis bagi Ijazah Doktor Falsafah dan Sarjana secara   penyelidikan, atau disertai bagi pengajian secara kerja kursus dan penyelidikan atau Laporan Projek Sarjana Muda (PSM)

PSZ 19:16 (Pind. 1/97)

UNIVERSITI TEKNOLOGI MALAYSIA

BORANG PENGESAHAN STATUS TESIS JUDUL: MODELING THE EFFECT OF VELOCITY SATURATION SATURATION

IN NANOSCALE MOSFET SESI PENGAJIAN: 2006/2007

MICHAEL TAN LOONG PENG

Saya

(HURUF BESAR)

mengaku membenarkan tesis (PSM / Sarjana / Doktor Falsafah)* ini disimpan di Perpustakaan Universiti Teknologi Malaysia dengan syarat-syarat kegunaan seperti berikut: 1. 2. 3. 4.

Tesis adalah hakmilik Universiti Teknologi Malaysia. Perpustakaan Universiti Teknologi Malaysia dibenarkan membuat salinan untuk tujuan  pengajian sahaja. Perpustakaan dibenarkan membuat salinan tesis ini sebagai bahan pertukaran antara institusi pengajian tinggi. **Sila tandakan (

)

SULIT

(Mengandungi maklumat yang berdarjah keselamatan atau kepentingan Malaysia seperti yang termaktub di dalam AKTA RAHSIA RASMI 1972)

TERHAD

(Mengandungi maklumat TERHAD yang telah ditentukan oleh organisasi/badan di mana penyelidikan dijalankan)

TIDAK TERHAD Disahkan oleh

(TANDATANGAN PENULIS)

(TANDATANGAN PENYELIA)

Alamat Tetap: 293 LORONG MERBAU

PROF. MADYA DR. RAZALI ISMAIL

TAMAN BERSATU

 Nama Penyelia

09000 KEDAH

Tarikh:

Tarikh:

CATATAN: CATATAN: * Potong yang tidak berkenaan. **Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak   berkuasa/organisasi berkenaan dengan menyatakan sekali sebab dan tempoh tesis ini  perlu dikelaskan sebagai SULIT atau TERHAD. Tesis dimaksudkan sebagai tesis bagi Ijazah Doktor Falsafah dan Sarjana secara   penyelidikan, atau disertai bagi pengajian secara kerja kursus dan penyelidikan atau Laporan Projek Sarjana Muda (PSM)

“I hereby declare that I have read this thesis and in my

opinion this thesis is sufficient in terms of scope and quality for the award of the degree of Master of Engineering (Electrical)”

Signature

:

  Name of Supervisor Date

.……………………………………….… :

:

Professor Madya Dr. Razali Bin Ismail . .

BAHAGIAN A – Pengesahan Kerjasama*

Adalah disahkan bahawa projek penyelidikan tesis ini telah dilaksanakan melalui kerjasama antara_______________ dengan _________________ 

Disahkan oleh: Tandatangan : ………………………………………… Tarikh: ……………..   Nama : ……………………………………………… Jawatan : ……………………………………………… (Cop rasmi) * Jika penyediaan tesis/projek melibatkan kerjasama.

BAHAGIAN B – Untuk kegunaan Pejabat Fakulti Kejuruteraan Elektrik 

Tesis ini telah diperiksa dan diakui oleh:  Nama dan Alamat Pemeriksa Luar

:

Prof. Dr. Burhanuddin Yeop Majlis Director Institute of Microengineering and Nanoelectronics (IMEN) Universiti Kebangsaan Malaysia 43600 UKM Bangi, Selangor

 Nama dan Alamat Pemeriksa Dalam 1

:

Dr. Abdul Manaf bin Hashim Microelectronics & Computer Engineering Department (MiCE) Fakulti Kejuruteraan Elektrik  Universiti Teknologi Malaysia 81300 Skudai, Johor

Pemeriksa Dalam 2

:

Prof. Madya Dr. Abu Khari bin A’ain Microelectronics & Computer Engineering Department (MiCE) Fakulti Kejuruteraan Elektrik  Universiti Teknologi Malaysia 81300 Skudai, Johor

  Nama Penyelia lain (jika ada)

:

Disahkan oleh Timbalan Dekan (Pengajian Siswazah & Penyelidikan)/Ketua Jabatan Program Siswazah: Tandatangan : …………………………………………  

Nama

Tarikh: ……………..

: …………………………………………

MODELING THE EFFECT OF VELOCITY SATURATION IN NANOSCALE MOSFET

MICHAEL TAN LOONG PENG

A thesis submitted in fulfilment of the requirements for the award of the degree of  Master of Engineering (Electrical)

Faculty of Electrical Engineering Universiti Teknologi Malaysia

DECEMBER 2006

ii

I declare that this thesis entitled “Modeling the Effect of Velocity Saturation in

 Nanoscale MOSFET” is the result of my own research except as cited in references. The thesis has not been accepted for any degree and is not concurrently submitted in candidature of any other degree.

Signature  

:

Name Date

MICHAEL TAN LOONG PENG . :

:

MICHAEL TAN LOONG PENG . .

iii

To my wonderful parents and family, for their guidance, support, love and enthusiasm. I am so thankful for that blessing and for the example you both are to me over the years. I would not have made it this far without your motivation and dedication to my success. Thank you, mom and dad, I love you both.

iv

ACKNOWLEDGEMENTS

First of all, I am thankful to my supervisor, Associate Professor Dr Razali Ismail for his precious insight, guidance, advice and time. I would like to take this opportunity to record my sincere gratitude for his supports and dedication throughout the years.

My thankfulness also goes to my manager in Intel Penang Design Center, Mr  Ravisangar Muniandy. His immense support and encouragement was keeping me going during the times when I was encountering problems at every turn. I wish to express my most heartfelt thankre abroad and even made themselves available when I had questions after our meeting.

I thank the many good friends I met here, Kaw Kiam Leong, Ng Choon Peng, Lee Zhi Feng and many others for the encouragement and unforgettable memories. They have always given me the chance to discuss my academic issues as well as my   personal issues. Without them, I could not have been completed my study. Very valuable advice was also given by fellow friend, Dr Kelvin Kwa for his sharing of  experience, sachets of tea and coffee, books and advices. Also, thank to my friends Sim Tze Yee, Liu Chin Foon, Liew Eng Yew, Gan Hock Lai and Alvin Goh Shing Cyhe. I cherish the ideas they have given me, their support and warmhearted friendship.

On a personal note, I would like to thank my family who has always supported me and the encouragement they have given me.

v

ABSTRACT

MOSFET scaling throughout the years has enabled us to pack million of  MOS transistors on a single chip to keep in pace with Moore’s Law. The introduction of 65 nm and 90 nm process technology offer low power, high-density and highspeed generation of processor with latest technological advancement. When gate length is scaled into nanoscale regime, second order effects are becoming a dominant issue to be dealt with in transistor design.

In short channel devices, velocity

saturation has redefined the current-voltage ( I-V ) curve. New models have been modified and studied to provide a better representation of device performance by understanding the effect of quantum mechanical effect. This thesis studies the effect of velocity saturation on transistor’s internal characteristic and external factor. Velocity saturation dependence on temperature, substrate doping concentration and longitudinal electric field for n-MOSFET are investigated. An existing currentvoltage ( I-V ) compact model is utilized and modified by appending a simplified threshold voltage derivation and a more precise carrier mobility model. The compact model also includes a semi empirical source drain series resistance modeling. The model can simulate the performance of the device under the influence of velocity saturation. The results obtained can be used as a guideline for future nanoscale MOS development.

vi

ABSTRAK 

Penskalaan mendadak MOSFET dari tahun ke tahun selari dengan Hukum Moore membolehkan berjuta-juta transistor dimuatkan ke dalam serpihan silikon. Berikutan pengenalan teknologi proses 65 nm and 90 nm, arus pembaharuan yang dramatik telah membawa kepada penumpuan pemproses yang pantas, berkuasa rendah dan berdensiti tinggi dengan pendekatan teknologi terbaru. Kesan tertib kedua menjadi satu isu dominan untuk ditangani dalam rekaan transistor apabila panjang saluran mencecah nanometer. Salah satu daripandanya ialah halaju tepu yang telah membawa definasi baru bagi ciri-ciri voltan and arus (I-V) dalam peranti saluran/kanal pendek. Model-model baru telah diperkenalkan untuk memberi representasi prestasi yang jelas dengan mengambil kira teori fizik kuantum. Penyelidikan ini bertujuan untuk meneliti kesan halaju tepu ke atas faktor luaran dan dalam ke atas transistor. Hubungan hanyut dan halaju tepu dengan suhu, kepekatan   pendopan and medan elektrik diperhatikan. Model voltan-arus (I-V) sedia ada digabungkan bersama model kebolehgerakan elektron yang lebih terperinci untuk  menganalisis parameter-parameter di atas. Model padat tersebut juga mengandungi model perintang bersiri sumber-salir semiempirik. Persamaan voltan ambang telah diterbitkan dan berupaya memberikan ketepatan yang sama dengan silikon sebenar  dan dibuktikan dengan teknik kesesuaian pemadanan. Melalui pendekatan simulasi, model-model ini dapat memberi prestasi peranti di bawah pengaruh halaju tepu. Keputusan penyelidikan ini boleh digunakan sebagai panduan untuk perkembangan MOS pada masa depan.

vii

TABLE OF CONTENTS

CHAPTER

1

2

TITLE

PAGE

DECLARATION

ii

DEDICATION

iii

ACKNOWLEDGEMENTS

iv

ABSTRACT

v

ABSTRAK 

vi

TABLE OF CONTENTS

vii

LIST OF TABLES

xi

LIST OF FIGURES

xii

LIST OF ABBREVIATIONS

xvi

LIST OF SYMBOLS

xviii

INTRODUCTION

1

1.1

Background

1

1.2

Problem Statements

4

1.3

Objectives

5

1.4

Research Scope

5

1.5

Contributions

6

1.6

Thesis Organization

7

LITERATURE REVIEW

9

2.1

Non Ideal Effects in MOSFET

9

2.2

Velocity Saturation

10

viii

3

2.3

Oxide Charges and Traps

13

2.4

Device Modeling

15

2.5

SPICE Model

16

2.6

Threshold Voltage Model

17

2.7

Mobility Model

17

2.8

Drain Current and Voltage Model ( I-V )

18

2.9

Velocity Field Model

19

2.10

Source/Drain Series Resistance Model

21

2.11

Hot Carrier Effects

22

2.12

Reducing Hot Carrier Degradation

24

RESEARCH METHODOLOGY

29

3.1

Velocity Saturation Electrical Modeling

29

3.2

Intel Proprietary Softwares

31

3.3

Parameters Extraction for Proposed

32

Model 3.4

MOSFET Modeling for Circuit

33

Simulation 3.5

4

NMOS Transistor

A PHYSICS BASED THRESHOLD

34

35

VOLTAGE MODELING

4.1

Introduction

35

4.2

Threshold Voltage Model

36

4.3

Short Channel Threshold Voltage Shift

40

4.4

Narrow Width Effects

41

ix 5

PHYSICALLY BASED MODEL FOR 

44

EFFECTIVE MOBILITY FOR ELECTRON IN THE INVERSION LAYER 

6

5.1

Introduction

44

5.2

Schwarz and Russek Mobility Model

44

5.3

Proposed Mobility Model

47

5.3.1

Phonon Scattering

52

5.3.2

Coulomb Scattering

52

5.3.3

Surface Roughness Scattering

53

A PHYSICALLY BASED COMPACT I-V 

54

MODEL

7

6.1

Introduction

54

6.2

Short Channel I-V Model

55

6.3

Compact I-V Model

59

6.4

Source Drain Resistance

62

VELOCITY FIELD MODEL

64

7.1

Introduction

64

7.2

Velocity Saturation Region Length

63

7.3

A Pseudo 2D Model for Velocity

66

Saturation Region

8

RESULT AND DISCUSSION

70

8.1

Introduction

70

8.2

 I-V Model Evaluation

70

8.3

Threshold Voltage

74

8.4

Doping Concentration Dependence

76

8.5

Temperature Dependence

79

8.6

Peak Field At The Drain

81

x 9

CONCLUSIONS AND

83

RECOMMENDATIONS

9.1

Summary and Conclusion

83

9.2

Recommendations

84

REFERENCES

APPENDICES A-G

86

92 - 107

xi

LIST OF TABLES

TABLE NO.

TITLE

PAGE

2.1

Approaches of Compact Modeling

15

2.2

BSIM SPICE Level

16

4.1

Values of α and β for various semiconductors

38

xii

LIST OF FIGURES

FIGURE NO.

TITLE

PAGE

1.1

Growth of transistor counts for Intel processors accordance to Moore's Law

2

1.2

Feature Size Growth

2

1.3

MOSFET Source to Drain Cross Section

4

2.1

Drift velocity versus electric field in Silicon

11

2.2

Drift velocity versus electric field in for three different semiconductor 

11

2.3

Depiction of electrons density in channel under  electric field

12

2.4

Charges and their location in thermally oxidized silicon

13

2.5

Post oxidation dangling bonds that will become interfacial traps

14

2.6

Coordinate system used for the model derivation.

20

2.7

Comparison of  I-V characteristic for a constant mobility and for field-dependent mobility and velocity saturation effects.

20

2.8

Simplified Cross Section of Parasitic Resistance of  a NMOS

22

2.9

Hot Carrier Generation

23

2.10

Schematic cross section of “inside” and “outside” LDD

24

2.11

A schematic diagram of half of a n-channel MOSFET

25

xiii 2.12

Cross-sectional images showing a strained-Si MOSFET with a 25 nm gate length and its strainedSi layer 

26

2.13

TEM micrographs of 45-nm p-type MOSFET

27

2.14

TEM micrographs of 45-nm n-type MOSFET

27

2.15

DI-LDD device cross section

28

2.16

Surface electric field at drain edge for conventional and DI-LDD devices from 2D device simulation, VSUB = -1V and L=0.6 µm

28

3.1

Electrical Model Development Process

31

3.2

Running Basic Simulation Using Circuit

32

3.3

Parameter Extraction for Proposed Models

32

3.4

Schematic of an NMOS transistor

34

4.1

Metal-semiconductor work function difference versus doping concentration for aluminum, gold, and n+ and p+ polysilicon gates

37

4.2

Charge sharing in the short channel threshold voltage model

40

4.3

Cross section of an NMOS showing the depletion region along the width of the device

42

4.4

Qualitative variation of threshold voltage with channel length

43

4.5

Qualitative variation of threshold voltage with channel width

43

5.1

Comparison of calculated and measured μ eff  versus  E eff  for several channel doping levels without Coulomb scattering and surface roughness scattering

46

5.2

Comparison of calculated and measured μ eff  versus  E eff  for several channel doping levels with Coulomb scattering and surface roughness scattering

46

5.3

Schematic diagram of  E eff  and doping concentration dependence of mobility in inversion layer by three dominant scattering mechanism

47

xiv 5.4

A diamond structure with (100) lattice plane at [100] direction

49

5.5

A diamond structure with (110) lattice plane at [110] direction

50

5.6

A diamond structure with (111) lattice plane at [111] direction

50

5.7

Visualization of surface scattering at Si-SiO2 interface

51

6.1

Charge Distribution in a MOS Capacitor

57

6.2

Source ( R s) and Drain ( Rd ) Resistance

62

6.3

Current patterns in the source/drain region and its resistance

63

7.1

Velocity saturation region in MOSFET

65

7.2

Comparison of commonly used velocity field models

66

7.3

Analysis of velocity saturation region

67

8.1

Comparison of calculated (pattern) versus measured (solid lines) I-V characteristics for a wide range of gate voltage at resistivity 3.5 x10 -5 Ω/cm

71

8.2

Comparison of calculated I-V characteristics for a wide range of gate voltage at resistivity 3.5e-5 Ω/cm (solid lines) and 4.5 x10 -5 Ω/cm (pattern)

72

8.3

Comparison of calculated I-V characteristics for a wide range of gate voltage at resistivity 4.5e-5 Ω/cm (solid lines) and 5.5 x10 -5 Ω/cm (pattern)

72

8.4

Comparison of calculated I-V characteristics for a wide range of gate voltage at resistivity 3.5 x10 -5 Ω/cm with (pattern marking) and without channel length modulation (solid lines)

73

8.5

Threshold Voltage without Short Channel Effect (SCE) and Narrow Width Effect (NWE)

74

8.6

Short channel and narrow width effect

75

8.7

Threshold voltage modification with doping concentration

76

xv 8.8

Normalized effective mobility versus transverse electric field at different doping concentration

77

8.9

Normalized drift velocity versus longitudinal electric field at different doping concentration

78

8.10

Normalized effective mobility versus transverse electric field at different temperature

80

8.11

Normalized drift velocity versus longitudinal electric field at different temperature

80

8.12

Normalized longitudinal electric field along the channel

81

8.13

Normalized saturation drain current versus gate overdrive

82

8.14

Normalized saturation drain current versus drain voltage

82

xvi

LIST OF ABBREVIATIONS

ASIC

-

Application Specific Integrated Circuits

BSIM3 v3

-

Berkeley Short-Channel IGFET Model Three Version Three

CMOS

-

Complementary Metal Oxide Semiconductor 

CSV

-

Comma Separated Values

EDA

-

Electronic Design Automation

FET

-

Field Effect Transistor 

GCA

-

Gradual Channel Approximation

GUI

-

Graphical User Interface

IC

-

Integrated Circuit

MOS

-

Metal Oxide Semiconductor 

MOSFET

-

Metal Oxide Semiconductor Field Effect Transistor 

 

NMOS

-

n-channel MOSFET

PMOS

-

p-channel MOSFET

SOE

-

Second Order Effects

VLSI

-

Very Large Scale Device

VSR 

-

Velocity Saturation Region

GHz

-

Giga Hertz

GaAr 

-

Galium Arsenide

InP

-

Indium Phosphide

xvii k 

-

Boltzmann’s constant

 L

-

Channel length

S 

-

Spacer thickness

Si

-

Silicon

S/D

-

Source and Drain

xviii

LIST OF SYMBOLS

A

-

Ampere (unit for current)

Cu2S

-

Copper Sulfide

C ox

-

Gate oxide capacitance

 E 

-

Electric Field

 E eff 

-

Effective transverse electric field

 E c

-

Critical electric field

 E  g 

-

Energy bandgap variation

ε Si

-

Dielectric permittivity of the silicon

ε ox

-

Dielectric constant of the oxide

 I-V 

-

Drain current versus drain voltage

 I ds

-

MOSFET drain current

 I dsat 

-

Drain current saturation

InP

-

Indium Phosphide

 J n

-

Drift current density

k 

-

Boltzmann’s constant

 L

-

Channel length

μ eff 

-

Effective mobility

μ m

-

micrometer 

μ c

-

Coulombic scattering

μ  ph

-

Phonon scattering

xix μ  sr 

-

Surface roughness scattering

φ  f 

-

Fermi potential

φ  fp

-

Fermi surface potential for p-type semiconductor 

φ  fn

-

Fermi surface potential for n-type semiconductor 

 N  A

-

Acceptor doping concentration

 N  D

-

Receptor doping concentration

 N  I 

-

Number of electrons per unit area in the inversion layer 

 N c

-

Density of states function in conduction band

 N v

-

Density of states function in valence band

ni

-

Intrinsic carrier concentration

nm

-

nanometer 

n

-

Free electron density

 p

-

Fuchs factoring scattering

 ρ 

-

Effective resistivity

Qtot 

-

Effective net charges per unit area

Q I 

-

Inversion charge per unit area

Qn

-

Inversion Charge

 R sd 

-

Source and drain resistance

 Rd 

-

Source resistance

 Rext 

-

Extrinsic resistance

 Rint 

-

Intrinsic resistance

 Rac

-

Accumulation resistance

 R sp

-

Sreading resistance

 R sh

-

Sheet resistance

 Rco

-

Contact resistance

xx

S 

-

Spacer thickness

φ ms

-

Work Function

t ox

-

Oxide thickness

vd 

-

Drift velocity

V

-

Voltage (unit for potential difference)

V ds

-

Drain voltage

V dsat.

-

Drain voltage saturation

V c

-

Critical Voltage

V  FB

-

Flat band voltage

V  gs

-

Gate Voltage

V t 

-

Threshold Voltage

ν sat 

-

Carrier saturation velocity

W 

-

Channel width

 xdT 

-

Depletion width

 x j

-

Junction depth

 χ 

-

Oxide electron affinity

 Z 

-

Averaged inversion layer width

 Z cl 

-

Classical channel width

 Z QM 

-

Quantum mechanically broadened width

Ω

-

ohm (unit for resistivity)

xxi

LIST OF APPENDICES

APPENDIX

TITLE

PAGE

A

Publication

93

B

Roadmap of Semiconductor since 1977

99

C

Roadmap of Semiconductor into 32nm Process Technology

100

D

CMOS Layout Design

101

E

Mobility in Strained and Unstrained Silicon

102

F

Threshold Voltage Model

103

G

 I-V Model

105

CHAPTER I

INTRODUCTION

1.1

Background

Silicon is one of the semiconductor materials which is commonly used in chip manufacturing to make integrated circuit from miniaturized transistor. Metal Oxide Semiconductor (MOS) transistor have shrunk from a micrometer into sub 100 nm regime with transistor scaling, which increases the number of transistor per  size by a factor of two every 18 months in accordance to Moore’s Law (Moore, 1965). Many improved lithographic and semiconductor fabrication equipments were designed to be on track with the curve and one step ahead of the technology. So far, Moore’s law has been a valuable way of describing the general progress of integrated circuits and the number of transistors fitted into each generation of Intel processors, as shown in Figure 1.1.

In silicon chip manufacturing, feature size and wafer size is the two most important parameter as they determined the cost of a plant and production line equipments. Presently, 300 mm wafers is the largest silicon wafers which produce more than double as many chips as the older 200 mm wafers. Since the end of 2005, Intel is the first manufacturer offering single and core 2 duo processors based on 65 nm production technologies. 65 nm generation transistors come with gates that are able to turn a transistor on and off measuring only 35 nm which is roughly 30 percent smaller than 90 nm technology gate lengths. Intel claims that 65 nm transistors cut current leakage by four times compared to previous process technology. According to Figure 1.2, new technology generation is introduced every 24 months and this

2 successfully extends their 15-year record of mass production in Intel

.

As

 performance technology improves, the gate length start to get smaller than predicted   by the ideal feature size trend of each process technology.

This allows higher 

transistor density, squeezing more of them on a single chip. The roadmap of  semiconductor from 1977 to 2018 can be seen in Appendix B and Appendix C.

Figure 1.1

Growth of transistor counts for Intel processors accordance to

Moore's Law

Feature Size Gate Length

Gate Length Scales Faster

Figure 1.2

Feature Size Growth

3 In nanoscale dimension, new problems began to occur. The magnitude of the electric field is comparably higher in short channel devices than long channel devices where the channel length is comparable to the depletion region width of the drain and source. Here, Secondary Order Effect (SOE) exists and must be considered to model the generation of a more precise short channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Velocity saturation is a vital parameter of the SOE which occur in high electric field.

At low electric field, the drift velocity of electron, vd  is proportional to the electric field, E as shown in Eq. (1.1).

vd

= μ eff E  

(1.1)

where µeff  is the effective mobility. When the electric field applied is increase, nonlinearities appear in the mobility and carriers in the channel will have an increased velocity. In high field, charge carriers gain and lose their energy rapidly   particularly through phonon emission until the drift velocity reaches a maximum value called velocity saturation. Velocity saturation in MOSFET will yield a smaller  lower drain current and voltage. A cross section of a MOSFET is illustrated in Figure 1.3. This research focuses on the role of velocity saturation has on the characteristic of MOSFET in term of the carrier velocity field, carrier doping concentration, drain current versus drain voltage curve. Intel proprietary software is used to generate the experimental drain current versus drain voltage characteristic for  90nm generation of MOSFET. After parameter extraction is carried out, several compact models are employed to study the effect of velocity saturation and the impact of high electric field. The modified device models will be able the predict   behavior of electrical devices based on fundamental physics. Characteristics and gives us the mobility and the drift velocity of the electrons versus transverse and longitudinal electric field respectively.

4

Source

Gate

Drain

Contact/via

Metal Lines Interlayer Dielectric (ILD)

Gate Oxide +

N

+

+

N

N

Poly Si Gate

Drain Regions Isolation

P Substrate/ Well Source: PN Junction (Diode)

Figure 1.3

1.2

Gate MOS Capacitor 

Drain: PN Junction (Diode)

MOSFET Source to Drain Cross Section

Problem Statements

This research utilizes a newly developed short channel models to study velocity saturation in 90 nm process technology and reports the results it has on the transistor basic characteristic. Questions that are bound to be answered through the high field analysis are:

(i)

What is velocity saturation?

(ii)

What is the different between short and long channel devices? What is the limitation of nanometer MOSFET?

(iii)

How does velocity saturation affect the transistor?

(iv)

What models can be represented to predict the characteristics and   behaviors of Complementary Metal Oxide Semiconductor (CMOS) transistor in nanometer dimension?

(v)

What are the limitations of conventional long channel models?

5 1.3

Objectives

The following are the objectives of this study.

(i)

To understand high field effects in nanoscale transistor in 90nm  process technology.

(ii)

To formulate simple analytical and semi-empirical equations for  device model applicable to nanoscale devices by taking into account velocity saturation.

(iii)

To analyze velocity saturation effects on temperature, doping concentration, longitudinal and transverse electric field.

1.4

Research Scope

The goal of this research is to investigate the role and characteristic of  velocity saturation on the following parameters.

(i) (ii)

Longitudinal electric field Transverse electric field

(iii)

Doping concentration

(iv)

Mobility

(v) (vi)

Drain current and voltage ( I-V) curve Temperature

The research is divided into three major phases. In the beginning, literature review and previous researches in this field is carried out. Strengths and weaknesses of available model and equations are compared. The second phase begins with the modeling based on the literature review. A semi-empirical model for velocity saturation due to high field mobility degradation is presented. Best fit model  parameters are extracted from the experimental results. The results compared with a

6 set of published experimental data points and validated. The final phase is preceded with analysis incorporating all the derived and modified models.

Future improvements and suggestion for the model are presented at the end of  the thesis. N-channel MOSFET with polysilicon gate is used in this research. The

 I ds compact model is derived by studying and analyzing Berkeley Short-Channel IGFET Model 3 Version 3 (BSIM3v3) standard (Berkeley, 2005). The one region equation from linear to saturation is based on the modification of the conventional long channel model with the addition of second order effects, each parameter with its  physical meanings. Other semi empirical models include threshold voltage, mobility and source drain series resistance.

1.5

Contributions

The semiconductor industry particularly microchip industry strives to develop high performance processor which is capable to cater for the demanding market. MOSFET-based integrated circuits have become the dominant driving force in the industry. It is important for the research and development’s designer team to investigate how transistor behaves differently in nanometer dimension. These characteristic includes the electric field, carrier velocity field, carrier mobility, carrier  concentration, carrier in saturation velocity region and drain current versus drain voltage in short channel devices.

The modified short channel models are able to overcome the limitations of    previously long channel analytical and semi empirical models without velocity saturation. It is also the interest of this study to find out the critical voltage and electric field when velocity saturation appears. Based on this evaluation, it can  provide a guideline for designers in term of graphical representation on figures and as well as parameter dependency relationship on the mobility behaviour, including threshold voltage, doping concentration and temperature. Designer can examine the   behavior of the device when it is saturated at high electric field under specific

7 temperature and doping concentration.

They can improve their design after a

thorough testing to prevent device breakdown.

Long channel  I-V  (current voltage) model is based on one dimensional theory. The modified short channel model is more accurate for nanoscale MOSFET than long channel model which cover Poisson's equation using gradual channel approximation and coherent Quasi 2 Dimensional (2D) analysis in the velocity saturation region. We have included the drain source resistance as well as the high longitudinal electric field effects into the  I-V  model. Furthermore, the threshold voltage model also includes the aspect of non ideal effects such as short channel threshold voltage shift and narrow width effects. In addition, through these calculated results, a bigger picture is given on how velocity saturation can be sustained. On top of that, several enhancement and insight is discussed to overcome the challenges in MOSFET design particularly the reduced drive strength. By investigating the effects of velocity saturation, the author attempts to give general guidelines of how  parameters should be chosen.

1.6

Thesis Organization

This thesis consists of 8 chapters. Chapter 1 introduces the background of this research. The problem statements, research objectives, research scope, research contributions and thesis organization are also provided. Chapter 2 provides an overview of the literatures reviewed throughout the research. A detailed description on velocity saturation effects is presented.

Previous long channel model

characteristics and related research are summarized.

Chapter 3 deals with the work flow of this research. It also introduce the modeling process as well as the Intel Proprietary Schematic Editor and Circuit Simulator. Chapter 4 marks the beginning of the proposed models formulation with the introduction of threshold voltage modeling.

Chapter 5 discusses about the

electron mobility model in MOS inversion layer. A comprehensive semi empirical

8 drain current and voltage model is explained in Chapter 6 by studying the long channel characteristics and short channel effects. In addition, this chapter also includes the derivation of source and drain resistance equation which normally omitted in long channel devices. In Chapter 7, we study the velocity field model which describes the effects of high vertical and lateral field in inversion layer pinch off and velocity saturation.

In Chapter 8, the calculated data is observed and validated against the experimental data generated from simulations to investigate effects of velocity saturation. Analysis was carried out on the simulated results and the findings are discussed. Finally, Chapter 9 concludes the thesis with summary of contributions and suggestions for possible future development.

CHAPTER II

LITERATURE REVIEW

2.1

Non Ideal Effects in MOSFET

Integrated circuit (IC) is an electronic circuit built on a thin semiconductor  substrate. It can be categorized into two groups based on the type of transistors they contain which are the bipolar integrated circuits and MOS integrated circuits. There are three types of ICs.

Memory, processor and application specific integrated

circuits (ASIC). In the new millennium, IC has indeed transformed our modern life, making it easy to perform complicated tasks. IC can be found in everything from satellite to personal computers to cell phones.

Advances in IC manufacturing process have led to tremendous growth in the semiconductor industry. As CMOS is scaled, the density and speed of the IC is increased. A schematic of a nanoscale CMOS can be seen in Appendix D. With the latest technological advancement, 65 nm and 90 nm generation of processor has a major improvement over performance, thermal design power and the system functionality. In this context, thermal design power refers to the maximum amount of power the thermal solution in a computer system is required to dissipate. The introduction of multiple core architecture in single processor has a positive impact on  power efficiency. Nevertheless, these same advances come at a price as they affect the stability and reliability of the devices. As process technology improved to a point where devices could be fabricated into nano dimension, MOSFET began to exhibit a   phenomena not predicted by long channel models. Such phenomenon is called

10 second order effects (SOE) and occurs in short channel device is where the effective channel length is approximately equal to the source and drain junction depth.

Among the SOE which need to be examined carefully in short channel device design are mobility degradation, velocity saturation, hot carrier effects, short channel effects and narrow width effects (Taur  et al., 1997). Without doubt, one of the most widely discussed effects is velocity saturation that has a significant implication upon the current voltage characteristics of the short channel MOSFET.

2.2

Velocity Saturation

It is up most important to predict the drain current of scaled devices, both in linear and saturation regions particularly short channel MOS transistor. Velocity saturation reduces the saturation current below the value predicted by the conventional long channel. As a result, this issue reduces the speed of digital IC. At the performance level, whereby charging and discharging of parasitic capacitances takes a longer time. Velocity saturation also lift the pinch off condition in long channel model as the carrier density does not appear to be vanished at the saturation   point. (Arora, 1989). This research addresses the effects of velocity saturation on temperature, doping concentration, longitudinal and transverse electric field in short channel MOSFET. Old models of long channel MOSFET fails to give an accurate numeral equation for MOSFET in sub-100 nm regime (Arora, 2000).

In this dimensions, the functionality of the device is now governed by quantum mechanic as described by Yu et al. (1997). When devices are reduced in size the electric field,  E  increases and the carriers in the channel have an increased velocity. However, at high electric fields in the gate and channel of the MOSFET, there is no longer a linear relation between the electric field and the drift velocity as the velocity gradually saturates reaching the saturation velocity as shown in Figure 2.1.

11

   )   s    /   m   c    (        d

     v

E (V/cm)

Figure 2.1

Drift velocity versus electric field in Silicon

Velocity saturation is caused by the increased scattering rate of highly energetic electrons, primarily due to optical phonon emission and degrading effect of  the carrier mobility, resulting in the breakdown of Ohm's law behaviour (Bringuier, 2002). The electric field at which saturation occurs differ with different semiconductors; Silicon, Gallium Arsenide and Indium Phosphide. This is illustrated in Figure 2.2.

3x10

7

InP

   )   s    / 7   m 2x10   c    (      d

     V

 ,   y    t    i   c   o    l   e    V 7    t 1x10    f    i   r    D

Si

GaAs

0

5

10

15

20

4 

 Electric Field E (10 V/cm)

Figure 2.2

Drift velocity versus electric field in for three different semiconductor 

12 When  E  is applied, the random electrons drifts in a direction that is opposite to the direction of applied electric, which in this situation is the direction from right to left. In Figure 2.3, the random carrier is accelerated by the electric field in a streamlined motion. The electrons will collide with each other and at a critical electric field, the drift velocity becomes saturated and thus making Ohm’s law invalid (Arora, 2000). The density of arrows in an indicator of electrons and left-right motion in an electric field when a concentration gradient is present.

n ( -l )

n( )

n ( x+l ) l   E C   E  F 

l   E 

Figure 2.3

 E V 

Depiction of electrons density in channel under electric field

(Arora, 2000)

Previous studies namely by Frank  et al. (2000), Agnello (2002) and Lochtefeld et al. (2002) provide proper guidelines for further scaling of CMOS and its limitation in regards to carrier velocity. Takeuchi and Fukuma (1994) has incorporated velocity saturation model into the  I-V  model and the extracted  parameters was validated by numerical data from the device simulator. In this work, the impact of velocity saturation on device performance is broadened to include variation of drift velocity and effective mobility versus external and internal factor  such as temperature and doping concentration

13 2.3

Oxide Charges and Traps

In silicon technology, one of the critical components in device fabrication lies in the silicon dioxide which acts as an insulator between the silicon and the  polycrystalline silicon. In an ideal insulator, the silicon oxide and the silicon oxide interface is electrically neutral and there is no charge exchange between them. However, unwanted charges always present in the practical devices. In general, there are four general categories of oxide charge as shown in Figure 2.4. They are the mobile ionic charge, oxide trapped charge, fixed oxide charge and interface trap charge.

Metal +

K 

+

Na

Mobile ionic charge (Qm) SiO2 Oxide trapped charge (Q ot) Fixed oxide charge (Q f ) SiOX

Interface trap charge (Q it)

Figure 2.4

Si

Charges and their location in thermally oxidized silicon

Mobile ionic charge, Q m is introduced during device fabrication due to sodium or potassium contaminants. The major sources of sodium in a clean room environment is human being through sweat and skin peeling (Contant et al., 2000) while potassium contamination is due to potassium hydroxide (KOH) or water deep etching environment (Aslam et al., 1993). When electric field is applied, these mobile ionic charges can move from one location to the other end of the oxide with increasing temperature. Oxide trapped charges, Qot is also distributed around the SiO2 layer. They are created during ionizing radiation during electron hole pairs

14 generation, by hot electron injection or high current passing into the SiO 2. This has  become a more prominent problem as oxide thickness is scaled down.

Further down into the oxide layer at close range to the SiO 2/Si interface, there exist fixed oxide charges, Q f  due to the abruptly incomplete oxidized silicon. The   presence of these charges affects the flat band voltage. As a charged scattering center, it is responsible for the mobility degradation. Interface trapped charge, Q it is represented by X at the SiO2/Si interface in Figure 2.16 and is caused by excess Si, oxygen and impurities. Here, Qit have energy states in the forbidden energy gap of  the Si which is called the surface states. This arises from the dangling/incomplete   bonds as a result of a disruption of the crystal lattice as pictured in Figure 2.5. Surface states act like a localized generation and recombination centers. They captured electron from the conduction band or a hole from the valence band. The electrons or holes trapped in this state are called interface trap charge.

O

SiO2

O

Si

O

O

O

Si

O

O

Interfacial trap

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Figure 2.5

Post oxidation dangling bonds that will become interfacial traps

15 2.4

Device Modeling

Semiconductor device modeling creates models to characterize the behavior  of electrical devices based on fundamental physics. A meticulous method to describe the operation of the transistor is to write semiconductor equations in three dimensions and solve it numerically by using program. This approach is not recommended for general circuit simulation. The efficient way is to use compact model or Computer Aided Design (CAD) model. There are a various types of  compact models. A physical model is based purely on device physics. An empirical model on the other relies on curve fitting, coefficient and has no physical significance. Semi empirical model however is the combination of both models mention beforehand. The last compact model is a table model which places the input and output data is in the form of a table. The value is read by a program instead of  calculating them and this saves a great deal of processing time. There are a couple of  approaches of selecting the types of compact modeling, which are based on the charged based model or the surface potential based models as shown in Table 2.1. These two categories of advanced MOSFET model are being model today and are available commercially as Electronic and Electrical Computer Aided Design (ECAD) tools.

Table 2.1

Approaches of Compact Modeling

Charge-Based Models

ACM - Advanced Compact Model

Surface-Potential Based Models

HiSIM - Hiroshima-university STARC IGFET Model

EKV - Enz-Krummenacher-Vittoz

MM11 - MOS Model 11

Model BSIM - Berkeley Short-channel IGFET Model

SP - An Advanced Surface-Potential Based Compact MOSFET Model

16 2.5

SPICE Model

SPICE (Simulation Program with Integrated Circuits Emphasis) is a general   purpose analog circuit simulator (Sheu et al., 1987). It is a great program that is widely used in IC and board level design to check circuit designs and to predict circuit behavior. It can simulate the performance analog and mixed analog/digital systems. By solving sets of non-linear differential equations in the frequency domain, steady state and time domain, SPICE can simulate the behavior of transistor and gate designs.

BSIM is selected to be the core model formulation since it well considered  being the standard model from deep submicron into nanoscale CMOS circuit design. It is widely adopted by IC companies such as Intel, IBM, AMD, National Semiconductor, Texas Instrument, TSMC, Samsung, Siemen and NEC for modeling devices with a good accuracy (Xuemei and Mohan, 2006). It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer  Sciences (EECS) at the University of California, Berkeley. Table 2.2 shows the SPICE level of each BSIM since it is first released in 1984.

Table 2.2

BSIM SPICE Level

MOSFET Model Description

SPICE Level

BSIM1

13

BSIM2

29

BSIM3

39

BSIM3v2

47

BSIM3v3

49

BSIM4

54

17 2.6

Threshold Voltage Model

There are varieties of definition models that can be used to measure and   predict the threshold voltage of a MOSFET. Old long channel threshold voltage model need to be modified to give a more accurate value for nanoscale devices as new physic is being discovered and new materials being used (Wang et al., 1971). Presently, analytical models can adequately describe the threshold behaviour very well both in definition and extraction method (Zhou et al., 1999). In this work, a short-channel threshold voltage model for short channel MOSFET is derived for nchannel MOSFET with n+ polysilicon gate and p-type silicon. For precision formulation, short channel effect and narrow width effect is taken into consideration (Yu et al., 1997).

The analytical definition of the long channel threshold voltage is given as

VT

where φ  f  is the

= 2φ f + VFB +

(

2ε Si qN A 2φ f

)

Cox

 

(2.1)

Fermi potential,  N  A is the substrate doping concentration, k is the

Boltzmann’s constant, is the C ox gate

oxide

capacitance, V  FB is the flat band

voltage, ε Si is the dielectric permittivity of the silicon.

2.7

Mobility Model

The accuracy of inversion layer mobility modeling is crucial for simulating today’s Very Large Scale Device (VLSI) circuits. An effective carrier mobility as function of transverse electric field is utilized in the work. The mobility is based on the original model developed by Scwarz and Russek (1983) with some improvement on the scattering mechanism as previous phonon scattering models does not include surface roughness and Coulomb scattering. Operation in high transverse field and channel doping concentration requires all of these scatterings mechanism to be accounted as devices are scaled down.

18 The electron effective mobility due to the transverse field is modeled semi-empirically

and calculated using Matthiessen's rule by incorporating the individual scatterings as shown below.

μ eff 

⎡ 1 1 1 ⎤ =⎢ + + ⎥ ⎢⎣ μ ph μ sr μ c ⎥⎦

−1

(2.2)

where μ c is Coulombic scattering due to doping concentration, μ  ph is  phonon scattering and μ  sr  is surface roughness scattering.

2.8

Drain Current and Voltage Model (I-V)

This velocity saturation has a very significant implication upon the current voltage characteristics of the short channel MOSFET. It reduces the saturation mode current below the current value predicted by the conventional long channel equation Simpler approximations for long channel MOS transistor are no longer valid as the accuracy of a drain current model is directly affected by occurrence of velocity saturation effect. The long channel numerator will be divided by velocity saturation to get newly improved short channel drain current equation. Below are equation for  short and long channel current in the linear region for NMOS. The current in the saturation region is a linear function of  V  gt  instead of V  gt 2 as in the long channel.

I ds ( long channel ) =

I ds ( short channel ) =

μ eff C ox W  2

⋅

 L

μ eff C ox W  2

⋅

 L

⋅ ⎡⎣ 2Vgt Vds − Vds 2  ⎤⎦

(2.3)

⎡⎣ 2Vgt Vds − V ds 2 ⎤⎦ ⋅

(2.4)

V  1 + ds V c

19 The saturation drain current in for long and short channel can be expressed as

I ds ( long channel ) =

I ds ( short channel ) =

μ eff C ox W 

⋅

2

 L

⋅ (Vgs − VT ) 

μ eff C ox W 

⋅

2

 L

2

 

⋅ (Vgs − VT )Vc  

(2.5)

(2.6)

where V c is the critical voltage defined in Eq. (6.12), V ds is the drain voltage, V  gs is gate voltage, W  is the width and  L is the length of the channel. In this research, a newly developed unified one-region current-voltage (I-V) compact model for linear  and saturation region is adopted (Zhou and Lim, 1997). The model is formulated on the analysis of second order effects on the long channel model.

2.9

Velocity Field Model

The accuracy of a drain current model is directly affected by how the velocity saturation effect is implemented. The most commonly used carrier velocity model is in Eq. (2.7) and Eq. (2.8) as shown below (Jeng, Ko and Hu, 1998).

μ eff  E  1 + ( E E c )

v

(E

,

( E ≥ Ec )

<

E c ) 

(2.7)

= v sat

where

,

 

(2.8)

ν sat  is the carrier saturation velocity and  E c is critical electric field for velocity

saturation defined by

 E c

=

v sat  μ eff 

(2.9)

20 The channel of the MOS transistor can be generally divided into two regions, a gradual channel region and a velocity saturated region, as shown in Figure 2.6. In the gradual channel region ν <ν  sat  and E  <  E c, while in the velocity saturation region, ν  =ν  sat  and E ≥ E c (Takeuchi and Fukuma, 1994).

Source

Drain 0

 LC 

L EFF 

Gradual Channel  E=E C  VS Region Region V=V C 

v
Figure 2.6

v=v sat 

Coordinate system used for the model derivation.

Velocity saturation will yield an  I dsat  value smaller than that predicted by the ideal relation, and it will yield a smaller V dsat  value than predicted. Figure 2.7 shows a comparison of drain current versus drain to source voltage characteristic for  constant mobility and for field dependent mobility.

Constant Mobility Velocity Saturation

   A   m    s      d

V ds (V)

Figure 2.7

Comparison of  I-V characteristic for a constant mobility and for field-

dependent mobility and velocity saturation effects

21 2.10

Source and Drain Series Resistance Model

When current flow into the channel through the terminal contact, there is a tiny voltage drop in the source and drain region. This is associated with the resistance that appears in the device. This resistance has several components:

(i)

The resistance of the doped source/drain region.

(ii)

The resistance of the metal-to-silicon contact.

(iii)

The “spreading resistance” due to current traveling from the doped source/drain region to the inversion charge in the channel.

In long channel device, source drain resistance is negligible compared to the channel resistance. Nevertheless, in short channel devices the source drain parasitic is becoming comparable with the channel resistance. In reality, the assumption of  source and drain being a perfect conductor is not applicable and the resistivity should  be taken into consideration.

In general, series resistance is undesirable because it reduces the drive strength and contributes to the RC delay. Therefore, the inclusion of a compact series-resistance model for nanoscale MOSFET would give a better accuracy on the modeling. The physical model has a bias-dependent intrinsic and a bias-independent extrinsic component (Zhou and Lim, 2000). The final S/D series resistance is given  by

R  s / d   = Rext

+ Rint  =

2 ρ S  υ  + x jW VGS  − VT   

(2.10)

where  Rext  is the extrinsic resistance,  Rint  is intrinsic resistance,  x j is the junction depth, S  is the spacer thickness and  ρ  is taken as effective resistivity of the S/D regions (including contacts). The component of the drain source resistance expression will be discussed in Section 6.4.

22 The parasitic source and drain resistance of a NMOS is shown in Figure 2.8.

Source

Gate

Drain

Metal Lines Interlayer Dielectric (ILD)

Poly Si Gate

Contact/via

Gate Oxide

+

N

Inversion Layer 

+

N

R S

+

R D

N

Drain Resistance

Source Resistance Substrate/ Well

Figure 2.8

2.11

Simplified Cross Section of Parasitic Resistance of a NMOS

Hot Carrier Effects

It was shown that the peak electric field,  E max in Figure 8.12 can attain high value at low drain voltage for short channel device. When the carrier in velocity saturation region gain adequate kinetic energy to generate electron-hole pairs, avalanche process occurs. Electrons from the conduction band gains energy as they move down the channel. They possess high kinetic energy and travel at saturation velocity. On impact with the lattice, they generate a secondary electron and holes by   breaking the bond, ionizing the valence electron from the valence band into the conduction band. As of this moment, there are now three carriers; the original electron and the electron-hole pair. Subsequently, the newly generated pair that gains enough energy will collide with the lattice to generate more electron hole pairs. This   phenomenon is referred to as impact ionization. The effect is more pronounced at drain end where fields are highest. The generated electrons which are attracted to the drain will cause a rise in drain current while the generated holes which flow through

23 the substrate to the body terminal will form substrate hole current. The potential difference between substrate and source will create a forward bias near the source terminal. All these effects are shown in Figure 2.9 below.

|V  g | V  s = 0 V 

V ds 4

Source n

Drain

SiO2

- -

+

  -

  -   -

1

-

-

+

n

-

Avalanche 2

  -

Forward injection Substrate Current

  -

Depletion region 3

p-type Si substrate V b

Figure 2.9

Hot Carrier Generation

Under this circumstances, electrons from the source inject themselves into the substrate and a fraction of them will diffuse into the drain space charge region. This triggers a positive feedback and increases the avalanche process. Another issue with hot carrier effect that concern designer is when electron that has enough energy to overcome the Si-SiO2 interface barrier enter the oxide layer. The trapped electrons in the oxide produce a net negative charge and contribute to the total oxide charge in Eq. (4.13). The trapped oxide charge results in a positive shift in threshold voltage, which in turn increases surface scattering, reduces mobility as well as drain current and transconductance. Eventually, this will lead to the reduction of speed and cause the circuit to fail the speed test specification. Since these processes are continuous, device will degrade over a period of time and stability is at stake. Ultimately, the lifespan of the device will decrease and breakdown may occur sooner than expected.

24 2.12

Reducing Hot Carrier Degradation

Hot carrier effect in nanoscale devices is a serious problem. We identify that as device is scaled down, electric field increases dramatically. This enhances the  breakdown effect of near avalanche breakdown and near punch through breakdown. There are various methods that can be employed to suppress and reduce the hot carrier degradation. This involves introducing a new structure and strengthening the Si-SiO2 interface barrier to improve device performance. One of a way to diminish hot carrier effects is to reduce the magnitude of the maximum electric in the channel which is contributing to the breakdown mechanism. The most reasonable approach is to limit the power supply voltage. However, this option might not best as it leads to a performance trade-off. Next, we can modify the structure of a conventional MOSFET so it is less sensitive to hot carrier degradation. Lightly Doped DrainSource (LDD) has been reported to effectively improve NMOSFET with reduced lateral electric fields, higher operating voltage and a channel length reduction (Ogura, 1980).

 Narrow self aligned n- region are placed between the channel and n+ source drain diffusion as shown in Figure 2.10. Optimized n- doses in LDD spreads the high field at pinchoff along the n- region and reduces the peak value of the longitudinal electric field along the channel length. It also increases the breakdown voltage and limit the impact ionization.

+

n

n-

n-

 p-

Figure 2.10

n+

n+ -

-

n

n

n+

 p-

Schematic cross section of “inside” and “outside” LDD

25 A close up view is shown in Figure 2.11. The gate is now extend from the LDD which makes it the effective channel shorter than conventional MOSFET where

 Loverlap is the length of the LDD-gate overlap region.  Leff  is the length of silicon surface region in which its conductivity is effectively controlled by the gate bias and

 Lmet is the physical separation between the source channel junction and the drainchannel junction near silicon surface.

 L gate /2  Lmet  /2

 Loverlap

gate electrode

spacer  x

n+ source y

LDD

 p- substrate

Figure 2.11

A schematic diagram of half of a n-channel MOSFET

Another innovation that is well received in the industry is the introduction of  strained-silicon layers into a MOSFET, demonstrated in modern CMOS integration  by IBM and Intel in 2004. It is known that high-k gate dielectrics causes significant carrier degradation in the channel. The improvement of High-K transistor over  conventional gate oxides will not be possible without strained silicon technology. Here, channel made of a thin layer of strained silicon is used to improve the current drive in the transistor. The epitaxial strained Si layers is grown on relaxed SiGe as depicted in Figure 2.13 so that the amount of current flows more smoothly from source to drain. Higher drive current causes a transistor to switch between its on-off  states faster, ultimately creating a higher frequency and speed device.

26

Figure 2.12

Cross-sectional images showing a strained-Si MOSFET with a 25 nm

gate length and its strained-Si layer (Goo et al ., 2003).

There are several different approaches for introducing strain into the Si channel of nanoscale MOSFETs. Of these, two of the well known strained silicon options are process-induced (uniaxial) strain and bulk wafer (biaxial) strain. Recently, biaxial strained-Si has received substantial attention. In biaxial strained silicon, the electronic band structure is modified by pulling the individual silicon atoms moderately apart. As a result, higher currents in the transistor can be achieved as electrons and holes can move faster in the layer. This can be in Appendix E where mobility is higher for strained device compared to unstrained silicon and the universal mobility curve by Takagi et al. (1994).

More attention has been paid to uniaxial strained-Si as it enables the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer. Furthermore, uniaxial stressed Si for PMOS demonstrates tremendous hole mobility improvement at a given strained and mobility enhancement is present at large vertical fields. The process flow consists of selective epitaxial SiGe in the source/drain regions to create longitudinal uniaxial compressive strain in the PMOS as illustrated in Figure 2.14. On the other hand, specially engineered high tensile Si nitride-capping layer is used to introduce tensile uniaxial strain as shown in Figure 2.15 (Thompson et al., 2004). The technology is proven to be remarkable and has increases saturated n-type and p-type MOSFET drive currents by 10 and 25%, respectively. Since then, it has been implemented and ramped into high volume

27 manufacturing to fabricate the next generation Pentium® and Intel® Centrino TM  processor families.

Figure 2.13

TEM micrographs of 45-nm p-type MOSFET (Thompson et al ., 2004)

Figure 2.14

TEM micrographs of 45-nm n-type MOSFET (Thompson et al ., 2004)

For short channel VLSI transistors, LDD MOSFETs are commonly implemented to reduce high fields inside devices. The drain to source punchthrough is a serious problem when device scaling goes on continuously. Punchthrough suppression becomes less effective at gate length approaches nanometer dimension. Therefore, double implanted LDDs using halo implant is introduced.

A p-type

dopants is locally implanted under the lightly doped region of the LDD as shown in Figure 2.16. The halo implant uses the same implant type as the original well dopant. For instance, halo device uses p-type dopant as punchthrough stoppers for p well of the NMOS device adjacent to the n+ source and drain. They improve the

28 short channel effect such as threshold voltage roll-off characteristics, DIBL and  punch-through voltage and also electric field peak at drain end as illustrated in Figure 2.17.

Figure 2.15

Figure 2.16

DI-LDD device cross section (Codella and Ogura, 1985)

Surface electric field at drain edge for conventional and DI-LDD

devices from 2D device simulation, VSUB = -1V and L=0.6 µm (Ogura et al ., 1982)

CHAPTER III

RESEARCH METHODOLOGY

3.1

Velocity Saturation Electrical Modeling

The objective of this research is to develop electrical models to investigate the velocity saturation effects in nanoscale NMOS and it dependence on temperature, doping concentration and longitudinal electric field. The electrical model mentioned here is a circuit representation that has the electrical properties and characteristics of  the component.

The electronic design automation (EDA) tools run on UNIX

workstation that can accessed via Microsoft Windows XP operating system.

In short, this research will develop an analytical short-channel MOSFET for  90nm process technology to predict the drain current of scaled devices, both in the linear and saturation regions in the perspective of Ohm’s law. The investigation is carried out on temperature, substrate doping concentration and longitudinal electric field dependence. The approximation is based of several assumptions, which are considerably acceptable for a wide range of analysis.

To begin with, hands-on review of UNIX environment is essential which include basic UNIX commands, directory structuring, file editor and interactive communications. At the same time, theoretical backgrounds of the available analytical and semi empirical models derivations are attained through literature review. Comparison between the models is made and proposed semi empirical models are implemented.

30

Physical parameters or elements are extracted from the  I-V  curve in order to analyze the velocity saturation response. In this stage, schematic design of the   NMOS is carried out by using Intel Proprietary Schematic Editor. Circuit netlist is then generated and the  I-V  curve is displayed by running Intel Proprietary Circuit Simulator. The numerical values of the extracted parameters are feed into the semi empirical models.

Verification is performed on the model to ensure it is able to reflect the actual characteristics of the electrons behaviour during velocity saturation. After the models are verified, it is validated and analyze to obtained a better insights of the velocity response to the variation of input parameters. Data analysis of the figures are generated in Microsoft Excel.

Figure 3.1 shows the generic steps used in the

research to develop the electrical model.

Invoke Schematics Editor 

Create and Edit Schematics

Check Schematics

 Netlist Schematics

Invoke Circuit Simulator 

Circuit Simulator 

Parameters Extraction Proposed Models

Figure 3.1

Electrical Model Development Process

31 3.2

Intel Proprietary Softwares

Intel Proprietary Schematic Editor and Intel Proprietary Circuit Simulator is used to provide the experimental data for this research. Intel Proprietary Circuit Simulator provides a full Spice simulation and support industry standard. It has customizable graphical user interface (GUI) makes it easier to perform most tasks. The GUI can be customized to include your own buttons and menus. Once schematic symbols are created in the schematic editor, the circuit description is written into a netlist file that served as the input file to circuit simulator program. Then, a design is   build. The type of simulation process is defined and the input sources as well as output probing point are chosen. By defining the probes, the simulator will provide the type of data to be shown at a particular circuit object. The range of the display output waves need to be set so that the simulation results can presented satisfactorily. Finally, measurement can be done. The data output can be exported to Microsoft Excel in Comma Separated Values (CSV) format.

Invoke Circuit Simulator 

Build a Design From Netlist

Define Input and Output Probes

Define Analysis Type

Set Parameter 

Run Simulation

Measure Results

Export to CSV

Figure 3.2

Running Basic Simulation Using Circuit Simulator 

32 3.3

Parameters Extraction for Proposed Models

Threshold voltage, effective mobility, doping concentration, source/drain series resistance, diffused junction depth, gate oxide thickness, gate oxide capacitance and others related empirical parameter would be among parameters extracted from the experimental data. Subsequently, curves based on the newly developed threshold voltage model, effective mobility model and  I-V  model are plotted. The velocity longitudinal field equation is then incorporated to model the velocity saturation region (VSR).

Finally, based on the graphs depicted, the velocity saturation

relationship between the models is analyzed. Figure 3.3 shows the flowchart of each extraction process. The threshold voltage is an analytical model while the rest; velocity field,  I-V  with  Rds series resistance and mobility model are based on semi empirical formulation. The  I-V  model is a unified SPICE model which uses single equation for both linear and saturation region.

Several assumption and

approximation is used and this is discussed in detailed in the following Chapter 4 to Chapter 6. Appropriate values are chose so that the models are able to predict  behaviour as close as possible to measurements.

Simulated Experimental Data

Parameters Extraction

Threshold Voltage Model

Velocity Field Model

 I-V  Model

Analysis on the Velocity Saturation

Figure 3.3

Parameter extraction

Mobility Model

33 3.4

MOSFET Modeling for Circuit Simulation

Two main types of compact model are utilized in this research.

a)

Physical model This model is based on device physics formulation and each parameter in the model has a physical significance such as flat band voltage, doping concentration and Fermi potential. The threshold voltage model discussed here is a physical model.

 b)

Physical based semi-empirical model This model is based on device physics formulation and partly on empirical measurements as a curve fitting expression. The parameter includes additional coefficients that can be used by the equation to fits data on the curve. The mobility, drain current-voltage, velocity field and source and drain series resistance models discussed here are physical based semi-empirical models.

In developing the models, several effects that occur in a given region of operation is combined into one physical model. Several phenomena which simpler model ignore is taken into account to derive a good model in term of accurate parameter extraction.

3.5

NMOS Transistor

The NMOS transistors consist of three terminals: gate, drain, and source. The source is biased at a lower potential (often 0V) than the drain. In this case, the source and body are both grounded. The drain current is induced based on voltages applied at the gate and drain of the transistor. Every NMOS transistor contains a threshold voltage. The voltage applied to the gate terminal determines whether current can flow between the source and drain terminals. In order for the transistor to operate, V  gs must be greater than Vt. Once this condition has been met, the resulting drain current

34 can be controlled by the voltages supplied at the gate and the drain. The relationship  between V  gs, V ds, and I ds is described by three regions of operation; the cut off region, the triode region and the saturation region. Figure 3.4 illustrates a schematic of an  NMOS transistor.

Figure 3.4

Schematic of an NMOS transistor 

CHAPTER IV

A PHYSICS BASED THRESHOLD VOLTAGE MODELING

4.1

Introduction

A new effective threshold voltage model is derived in this section based on the long channel device by considering the effects of short and narrow channel effects. The following discussion applies for NMOS. The threshold voltage equation for n-channel MOSFET is defined as

VT

where φ  f  is the

= 2φ f + V FB +

(

2ε si qN A 2φ f

C ox

)

 

(4.1)

Fermi potential,  N  A is the substrate doping concentration, k is the

Boltzmann’s constant, C ox is the gate oxide capacitance, V  FB is the flat band voltage, ε Si is the dielectric permittivity of the silicon. The full derivation can be seen is Appendix F.

36 4.2

Threshold Voltage Model

The MOSFET is fabricated with polysilicon gates over a p-type silicon substrate or well. The gate is heavily degenerately doped as the source and drain regions.

The metal semiconductor work function difference is determined by

φms

= χ ' − (χ ' + =

χ' − χ' −

 E  g 

2e  E  g  2e

+ φ fp ) 

−

φ fp ) 

⎛ E  ⎞ = − ⎜  g  + φ  fp ⎟ ⎝ 2e ⎠

(4.2)

where χ is the oxide electron affinity. φ  fp and φ  fn is the Fermi surface potential for ptype and n-type semiconductor substrate respectively. They are written as

φ  fp (T ) =

kT 

φ  fn (T ) =

kT 

q

q

⎛ N  ⎞ ⎟ ⎝ ni ⎠

(4.3)

⎛ N  D ⎞ ⎟ ⎝ ni ⎠

(4.4)

ln ⎜

ln ⎜

where N  A is the acceptor doping concentration,  N  D is the donor doping concentration. The intrinsic carrier concentration, ni is given by

ni

= ( N c N v )

1

2

⎛  E  g  ⎞ ⎟ ⎝ 2kT  ⎠

exp ⎜ −

(4.5)

Figure 4.1 shows experimentally determined values of the gate-to-substrate work function difference φ ms for various type of gate materials. The Fermi level in the n+ polysilicon is essentially at the edge of conduction band while for p + substrate is below the intrinsic Fermi level. Polysilicon gate has a smaller work function

37 compared to the substrate, which make make it negative.

The magnitude magnitude of  φ ms ms for 

n+ polysilicon with p + substrate decreases with doping as the Fermi level for the substrate proceed to travel down further from the mid-gap.

Polysilicon is preferable to a metal gate as it is able to give a lower threshold voltage due to its small work function difference. When metal was used for long channel devices, gate voltage is still relatively large to overcome the work function difference between metal and silicon substrate. A transistor with a high threshold voltage would not be practical in nanoscale devices.

Figure 4.1

Metal-semiconductor

work

function

difference

versus

doping

concentration for aluminum, gold, and n+ and p+ polysilicon gates (Sze, 1981)

38 The energy bandgap variation,  E  g with temperature in Eq. (4.5) is defined as

E g (T ) = Eg ( 0) −

α T 2

(4.6)

(T + β )

where  E  g  (0) is the initial value of the band gap at 0 K while

α and β are constant.

(Zeghbroeck, 2004). The band gap of a semiconductor is the energy difference  between the top of its valence band and the bottom of its conduction. The bandgap is a forbidden energy range between the valence and conduction bands. In order to be be in the conduction band and taking part in conduction, electron in the valence band must absorb sufficient energy to leap across the band gap. The fitting parameters for  germanium, silicon and gallium arsenide in listed in Table 4.1.

Table 4.1

Values of α  of α and and β   β for for various semiconductors (Zeghbroeck, 2004)

Germanium

Silicon

GaAs

[eV]

0.7437

1.166

1.519

α 

[eV/K]

4.77 x 10 -4

4.73 x 10 -4

5.41 x 10 -4

 β 

[K]

235

636

204

 E  g (0)

The bandgap of semiconductor decreases as temperature increases. A raise in temperature enable atoms to have a higher thermal energy. This resulted in larger  atomic vibrations. The greater atomic vibrations have the tendency to broaden the distances between the atoms which causes lattice expansion. This increase in interatomic separations lower the potential. potential. Less energy is needed needed to break the bonds bonds and release electrons from the valence to the conduction band, thus reducing the   bandgap.

The temperature dependence for silicon energy bandgap can be

approximated as

 E g (T ) = 1.17 −

4.73 x 10 -4T 2 (T  + 636)

(eV)

(4.7)

39 The effective hole and electron masses used in the calculations are given by

mn =1.08 m0

(4.8)

= 0.81 m0

(4.9)

and

m p

The parameter  N c in Eq. (4.5) is the effective density of states function in the conduction band and can be defined as

Nc

≅ 5.42x1015 T

3

2

( cm− ) 3

(4.10)

 N v, the effective density of states function in valence band is defined as

Nv

≅ 3.52x1015 T

3

2

( cm− ) 3

(4.11)

The product of equation Eq. (4.10) and Eq (4.11) yields

Nc Nv

= 1.908x1031 T 3 ( cm−6 )

(4.12)

The flat band voltage in Eq. (4.1) can be calculated by

V FB

= φ ms −

Qtot 

(4.13)

C ox

2

where Qtot  is effective net charges per unit area at the Si-SiO 2 (C/cm ) and is a sum of fixed oxide charge, Q f  and interface trap charge, Qit which is discussed is Section 2.4. Using Eq. (4.2) and Eq. (4.13), Eq. (4.1) can be written as

V T

= φ fp +

(

2ε si qN A 2φ f

Cox

)

 

⎛ E  Q ⎞ − ⎜  g  + tot  ⎟ ⎝ 2e C ox ⎠

(4.14)

40 4.3

Short Channel Threshold Voltage Shift

Additional effects on V T  occur as the device shrink in size. The short channel threshold voltage shift reduce V T    predicted by the long channel. The source and drain distance becomes comparable to the MOS depletion width. The net charge in the depletion region has to be considered since a portion of the charge is shared among the gate, source and drain charge. The fraction of the charged induced by the source and drain becomes significant as the channel length reduces. Therefore, the charge-sharing model (Yau, 1974) is utilized. This model assumes the chargeinduced by gate voltage is contained in a region that can be best described by a trapezoid, as shown in the Figure 4.2. The total charge contributing to the threshold under the gate contact is represented by the rectangle with a width of  xdT  and a length of  L. VG VS

VD L

n+

 xdm

r  j

n+ L’

 p substrate

VB Figure 4.2

Charge sharing in the short channel threshold voltage model

The bulk charge inside the trapezoid is controlled by the gate is given by

Q 'B

 L + L ' ⎞

= qN A xdT ⎛⎜   ⎝

2

⎟ ⎠

(4.15)

41 The depletion width,  xdT  extending into the p substrate is written as

1/ 2

⎛ 4ε siφ fp ⎞  xdT  = ⎜ ⎟ ⎝ qN  A ⎠

(4.16)

The threshold voltage shift due to short channel effects (Neaman, 2003) can be expressed as

ΔV T  = −

qN A xdT ⎡ r  j

⎤ − 1⎥ ⎢ 1+ L r  ⎢⎣ ⎥⎦ j

Cox

2 xdT

 

(4.17)

By taking Eq. (4.17) into account, the threshold voltage now can be approximated by

VT

= 2φ fp + V FB +

qN A xdT Cox

⎧⎪ ⎡ r  j ⎛ ⎨1 − ⎢ ⎜⎜ ⎪⎩ ⎢⎣ L ⎝

⎞ ⎤ ⎫⎪ 1+ −1⎟ ⎥ ⎬ ⎟⎥⎪ r j ⎠⎦⎭ 2 xdT

 

(4.18)

= VT (Long Channel ) + ΔV T  

(4.19)

where

VT ( Short Channel )

4.4

Narrow Width Effects

The effect of narrow-width, which causes an increase in the threshold voltage as the channel width is reduced, is also included in this modeling. As the depletion region edge approaches the edge of the device, it makes a transition from the deep depletion under the gate to the shallow depletion region under the thick oxide. This transition region is shown in the Figure 4.3.

For wide widths, the size of this augmented charge at each end of the channel width relative to the bulk charge is small and can be neglected. However, as the width is reduced, this ratio increases and becomes significant. This additional charge increases the bulk charge and causes V T  to increase. As the width becomes smaller, the shift in threshold voltage becomes larger.

42 The additional space charge due to narrow width effect is given by Neamen (2003) and it is shown to be

qNxdT ⎡ ξ xdT

ΔV T  =

where W  is the channel width while width and normally given to be

Cox

⎤  ⎢⎣ W  ⎥⎦

(4.20)

ξ is a fitting parameter for lateral space charge

π/2

for a semicircle width. By adding this extra

charge into Eq. (4.18), the final threshold voltage expression can be approximated as

VT

= 2φ fp + V FB +

qN A xdT Cox

⎧⎪ ⎡ r  ⎛  j ⎨1 − ⎢ ⎜⎜ ⎪⎩ ⎢⎣ L ⎝

1+

2 xdT

rj

⎞ ⎤ ξ xdT ⎫⎪ − 1⎟ ⎥ + ⎟ ⎥ W ⎬⎪ ⎠⎦ ⎭

 

(4.21)  

W

SiO2

TTH Tox

Si

WTH

WD Actual Depletion Boundary Ideal Depletion Boundary

Figure 4.3

Cross section of an NMOS showing the depletion region along the

width of the device

43 The final model is able to provide a better representation of the threshold voltage instead of Eq. (4.14) as it takes into account the influences of other effects as mentioned above. The effect of short channel and narrow width is shown in Figure 4.4 and Figure 4.5 respectively.

A larger threshold voltage is noted for narrow

channel device. On the hand, the short channel device has a decreasing threshold voltage with channel length. Note that adding the doping concentration value does not necessarily increase the threshold voltage. This device parameter should be considered thoroughly to give the optimized results.

V T 

L

Figure 4.4

Qualitative variation of threshold voltage with channel length

V T 

W Figure 4.5

Qualitative variation of threshold voltage with channel width

CHAPTER V

PHYSICALLY BASED MODEL FOR EFFECTIVE MOBILITY FOR  ELECTRON IN THE INVERSION LAYER 

5.1

Introduction

The effective mobility of inversion layer carriers is a substantial element in the performance of a MOSFET. A physically based semi-empirical equation is employed to model surface roughness, phonon and coulomb scattering. In long channel device, mobility is assumed to be constant along the channel. However, this is not the case for short channel device. The term effective is used to describe the average mobility in the channel. On the whole, mobility depends on many process  parameters and bias conditions. For example, mobility can be a dependence on the gate oxide thickness, substrate doping concentration, threshold voltage, gate and substrate voltages. The proposed effective mobility model is transverse electric field dependent based on the concept introduced by Sabnis and Clemens (1979) which lumps many process parameters and bias conditions together. The modeling begin with a brief study of previous mobility model.

5.2

Schwarz and Russek Mobility Model

A portion of Schawrz and Russek (1983) model is adopted in this research. Developed in 1983, it is consist of bulk phonon scattering, μ bph and a surface mobility term, μ  s which represent the scattering by surface phonons and fixed interface charge.

45 The equations are as follows

⎛ 1 1 ⎞ + μ eff  = ⎜ ⎜ μbph μ s ⎟⎟ ⎝ ⎠ μ bph

μ  s

=

2qZ

pm*υ th

−1

(5.1)

=1150T n −2.5 =

(5.2)

Z 

(5.3)

3.2x10 −9 pTn1 2  

⎛ N  I  ⎞ T −1 N  ⎟ n f  ⎝  Z  ⎠

 p = 0.09Tn1.5 + 1.5x10 −8 ⎜ Z

 Z cl

=

(5.4)

= Z cl + ZQM   

3 2kT 

q E eff 

= 0.0388 T n E eff−1

(5.5)

(5.6)

 

1

⎡ 9 ( h 2π )2 ⎤ 3 −5 − 13 1.24x10 =  E eff  Z QM = ⎢ ⎥ * ⎢⎣ 4m q E eff  ⎥⎦

 

(5.7)

where  p is the Fuchs factoring scattering which describe the probability of diffuse scattering,  Z is the averaged inversion layer width,  N  f  is the interface charge density,

 Z cl  is the classical channel width and  Z QM  is the quantum mechanically broadened width due to the two dimensional quantization of the energy levels in the inversion layer, h is the Planck's constant, m* is the electron effective mass and υ th is thermal velocity and q is electronic charge.

The above-mentioned equations lack of a surface roughness and columbic scattering. Therefore, these scatterings are accounted in this semi empirical equation as the nanoscale MOSFET is operating at high transverse electric field and high doping concentration level. This is supported by the finding from Takagi et al. (1994) which reveal that the deviation at the low and higher field is caused by Coulomb scattering from dopant in the channel and surface roughness scattering respectively. Figure 5.1 illustrates the failure of the equation to fit nicely into the experimental data in both low and high field region roll off as there is no Coulomb scattering and surface roughness scattering taken into account. On the other hand,

46 Figure 5.2 includes both scattering and show an excellent agreement with measured data.

Figure 5.1

Comparison of calculated and measured μ eff  versus  E eff  for several

channel doping levels without Coulomb scattering and surface roughness scattering (Shin et al., 1991).

Figure 5.2

Comparison of calculated and measured μ eff  versus  E eff  for several

channel doping levels with Coulomb scattering and surface roughness scattering (Shin et al., 1991).

47 5.3

Proposed Mobility Model

In order to develop the model, Matthiessen’s rule in Eq. (2.2) is applied. It gives the approach to extract the individual contribution to the mobility as well as data on the charged interface scattering density, surface roughness scattering coefficient and effective fixed oxide charge density. Figure 5.3 shows a set of data on mobility versus  E eff  and its contributing element.

   )   s      V    /    2   m   c    (    Y    T    I    L    I    B    O    M

Coulomb Scattering

Low

Phonon Scattering

Surface Roughness Scattering

High

Total Mobility

EFFECTIVE FIELD (V/cm)

Figure 5.3

Schematic diagram of  E eff  and doping concentration dependence of 

mobility in inversion layer by three dominant scattering mechanism

The universal curve can be divided into rising curve influenced by phonon scattering term, the mid section governed by columbic scatte ring term and the roll off  contributed by the surface roughness term. The equations to calculate effective mobility of electron in MOS (Shin et al., 1991) based on the three dominant scattering are given below.

⎛ 1 1 1 ⎞ + + μ eff  = ⎜ ⎜ μ ph μ sr μ c ⎟⎟ ⎝ ⎠

−1

(5.8)

−1

−1 ⎡ ⎤ − 1 ⎛ ⎞ 2 qZ   K  ⎢ ⎥ μ ph = ( K BT n ) + ⎜ ⎟ * ⎢⎣ ⎝  pm υ th ⎠ ⎥⎦ −1 −1 ⎡ ⎤ −2.5 −1 ⎛  Z cl + Z QM   ⎞ ⎥ = ⎢(1400T n ) + ⎜ −9 12 ⎟ 3.2x10  pT  ⎢⎣ ⎝ ⎠ ⎥⎦ n T 

(5.9)

48

 p = 0.09T

1.75 n

=

 Z cl

 Z QM

3 2kT 

q E eff 

= 0.0388 T n E eff−1

 K cT n1.5 2  BH 

BH

=

N I z

Tn

2

 

(5.12) (5.13)

γ 2 BH   N  )− 2 γ   BH  + 1 γ 

ln (1 + γ 2 BH  ) −

 K γ 

 

1

1.1x10 −21T n1.5

=

 

(5.10)

(5.11)

 

1

= K sr Eeff−2 = 6x1014 E eff−2

ln (1 + γ 

γ 

Tn −1 N f 

1

=

2

−0.25

= KQM Eeff− 3 =1.73x10 −5 Eeff− 3

μ sr

μ c

+ 4.53x10

⎛ N  I  ⎞ ⎜  Z  ⎟ ⎝ ⎠

−8

=

γ 

1

2  BH 

2  BH 

 N  A

+1

2x1019

N I 

(5.14)

T n2 z  

(5.15)

where T n is the normalized temperature at 300 K given as

T n

=

T ( K )

(5.16)

300

γ 2 BH  is the Brooks Herring constant while  K  B,  K QM ,  K  sr ,  K c and  K γ  are numerical coefficients that provide best agreements with the experimental data. The total number of electrons per unit area in the inversion layer,  N  I  in Eq. (5.10) can be calculated by using

 N I

=

2ε  si

q

( E

eff

− E 0 )

(5.17)

49 The effective transverse field can be expressed as

Eeff

=

1 ε  si

(η Qinv + QB )

(5.18)

where η  is a fitting parameter. The best values are η  = 1/2 for (100) electrons (Sabnis and Clemens, 1979) and η  = 1/3 for holes and (111) or (110) electrons (Takagi et al., 1994). A set of three vector integers in parentheses describe the crystal planes in a lattice while the vector component in brackets are used to designate direction. The lattice point of the diamond structure is represented by a dot. The three types of lattice planes along the a , b and c axis is shown in Figure 5.4, Figure 5.5 and Figure 5.6.

c

b

a

Figure 5.4

[100]

A diamond structure with (100) lattice plane at [100] direction

50

c

b

[110]

a

Figure 5.5

A diamond structure with (110) lattice plane at [110] direction

c

[111]

b

a Figure 5.6

A diamond structure with (111) lattice plane at [111] direction

The effective electric field can also be defined as

 E eff  =

 E s + E 0 2

where E  s is the transverse electric field at the gate dielectric silicon interface.

(5.19)

51 The transverse electric field at the edge of the inversion layer,  E 0 is given as

qN B

 E 0 =

ε si

=

QB ε si

qN A xdT  

=

qN  A ⎛ 4ε siφ fp

ε si 1/ 2

⎞ = ⎜ ⎟ ε si ⎝ qN A ⎠ 1/ 2 ⎛ 4qN Aφ fp ⎞ =⎜ ⎟ ⎝ ε  si ⎠

(5.20)

Carrier transport primarily occurs in the surface on the inversion layer. The induced transverse and longitudinal electric field influence the velocity of the carrier  toward and parallel to the silicon-silicon oxide interface respectively. The carrier  near the surface suffers collision with the silicon interface which resemble a zig zag motion which is shown in Figure 5.7.

Gate S

D

Silicon Oxide n

+

n

+

Depletion region

Figure 5.7

Visualization of surface scattering at Si-SiO2 interface

The importance of three scattering mechanisms mentioned above is determined by the temperature and the strength of electric field which interact with the charges in the silicon-silicon oxide interface.

52 5.3.1

Phonon Scattering

Mobility that is due to the various modes of lattice vibration including surface acoustic phonons and optical phonons is called phonon scattering. Phonon scattering is dominant in strong inversion where interaction between electrons and vibrating lattice atom is frequent.

It is dominant at high temperature and weak at low

temperature. Phonon scattering is also known as lattice scattering.  K  B and  K T  in Eq. (5.9) is fitting parameter for bulk phonon scattering.  K  B=1400 and  K T=   2.5 and found to have good agreement with measured data as described by Shin (1991).

5.3.2

Coulomb Scattering

Coulomb scattering is due to collision between charged centers near the silicon-silicon oxide interface. The proposed model not only includes fixed oxide charge, and interface-state charge but also localized charge due to ionized doping impurities. The effects of Coulomb scattering are significant for lightly inverted surfaces. A large percentage of the total carriers are able to interact with these ionized impurity and interface traps.

However, it is less effective for a heavily inverted surface because of carrier  screening from the ionized impurities. Carrier screening is essentially the weakening of electric charges due to large numbers of carriers in the surrounding of the charge. The Brooks-Herring equation for screened Coulomb scattering is adopted in Eq. (5.14) and Eq. (5.15). High surface-charge densities or substrate doping concentrations increases Coulomb scattering as the probability of a carrier  encountering a charge is higher. When Coulomb scattering rises, mobility of the remaining free carriers is reduced.

53 5.3.4

Surface Roughness Scattering

Surface roughness scattering is due to the microscopic roughness of the silicon-silicon oxide interface. This type of scattering is important under high field and strong inversion conditions because the strength of t he interaction is governed by the distance of the carriers from the surface. In nanoscale device, transverse electric field can go up to 10 6 V/cm because of a thinner gate oxide and short channel length. As carriers get closer to the interface layer, the stronger will be the scattering due to surface roughness. The value of  K  sr = 6 x 1014 in Eq. (5.13) provide the best agreement with the I-V curve generated by Intel Proprietary Software.

CHAPTER VI

A PHYSICALLY BASED COMPACT I-V MODEL

6.1

Introduction

Long channel MOSFET drain current derivation can be described by solving Poisson equation and drift-diffusion current density equations in one-dimensional form. The drain current can be modeled based on gradual channel approximation (GCA). GCA assumes that the variation of the electric field in the y direction ( E  y) along the channel is much less than the corresponding variation in the x-direction ( E  x) which is perpendicular to the channel as in Eq. (6.1).

∂ E  y ∂ y



∂ E  x ∂x

(6.1)

In the GCA, a two dimensional problem can be separated into two independent one dimensional problems and solve them in sequence. The first piece would be the vertical electrostatics problem relating the gate voltage to the channel charge and the depletion region. The second piece is the longitudinal problem involving the voltage drop along the channel and drift current. By solving the latter  equation for the inversion charge per unit area, Q I , the drain current can be calculated. Nevertheless, GCA is valid for most channel region except beyond the  pinch off point as the gradient of the longitudinal field becomes comparable to the gradient of the transverse electric field.

Pao and Sah (1966) model was used

alternatively to calculate Q I  numerically. The charge sheet MOSFET introduced by

55 Baccarani and Brews (1978) has make calculation simpler by avoiding numerical analysis needed in Pao-Sah model and became one of the most widely adopted model. Charged sheet approximation assumes that all the inversion charges are located at the silicon surface like a sheet of charge and there is no potential drop and no band bending across the inversion layer.

6.2

Short channel I-V Model

In this section, the charge sheet model is employed to derive the expression for drain current in linear and saturation region. To gain insight into short channel effects, velocity saturation coefficient is incorporated. The current flow in silicon is driven by two mechanism; the drift of carriers and the diffusion of carrier. In this section, the carrier concentration within the silicon is assumed to be uniform. Therefore, diffusion current which is caused by an electron or hole concentration gradient in silicon is omitted from the calculation.

Under thermal equilibrium, carrier move in a random direction through the silicon crystal with an average thermal velocity, vth of the order of 107 cm/s and kinetic energy proportional to kT  at room temperature. When an electric field is applied to an inversion layer containing free carriers, the electrons in this case are accelerated in the direction opposite the field and acquire a drift velocity over a mean free path between collision. The drift velocity of the electron with mass m* gain during a mean free time

τ between collision is

vd  =

−qE  yτ  m*

(6.2)

Drift velocity returns to zero after a collision event where velocity is randomized and the whole process repeats all over again.

56 The  I-V  derivation is shown below while a more detailed explanation can be seen Appendix G. The mobility of the electron can be defined as

μ  =

qτ  *

m

=

ql  m*vth

(6.3)

where the mean free path, l is

l = vthτ 

(6.4)

For n-type silicon with a free electron density n, drift current density  J n, under an electric is given by

Jn

= qnvd 

(6.5)

where vd  under the influence of velocity saturation is a function of 

vd  =

μ eff E y

(6.6)

1 + E y E c

where  E  is the longitudinal electric field while  E c is the critical electric field before velocity saturation occurs. The total charge per unit area at a point  y along the inversion layer can be given as

Qs ( y ) = Cox ⎡⎣VGS − VT

−  V ( y ) ⎤⎦

= Cox [VGT  − V ( y)]

(6.7)

where C ox is the capacitance per unit area and given as

C ox

=

ε ox

t ox

(6.8)

ε ox is dielectric constant of the oxide and t ox is oxide thickness as shown in Figure 6.1.

57

GATE 

++++++++++++

 Z 

 xi

 L

Charge Distribution in a MOS Capacitor 

Figure 6.1

The total current at a point y along the inversion layer can be represented as

I ds

⎛ μ   E  ⎞ = nv qvd A = nv q ⋅ ⎜⎜ eff y ⎟⎟ ( zxi ) ⎝ 1 + E y E c ⎠

(6.9)

where A is the area of the inversion width,  xi as shown in Figure 6.1.  I ds can also be written as

I ds ⎡⎣1 + ( ∂V

∂y )(1 Ec )⎤⎦ = Cox ⎡⎣VGT − V ( y )⎤⎦ ⋅ μ eff z ⋅ ( ∂ V ∂y )

(6.10)

By integrating from 0 to L the drain current for short channel device is given by

 I ds =

Cox μ eff z (VGT .Vds

− Vds2 2  )

L [ L + Vds LEc ] 

(6.11)

where the critical voltage, V c is given as

VC

= LEc = L

v sat 

(6.12)

μ eff 

Therefore, the equation given for short channel current in the linear region is

 I ds

=

⎡⎣2VGT Vds − V ds2 ⎤⎦ ⋅ ⋅ V   L 1 + ds

μ eff C ox W  2

V C 

(6.13)

58 A better approximation of the drain current in second order term in the power series expansion would include a body-effect coefficient, m (Tsividis, 1999 and Zhou et al., 1999) as shown below.

 I ds

=

⎡⎣ 2VGT Vds − mVds2 ⎤⎦  ⋅ ⋅ V   L 1 + ds

μ eff C ox W  2

(6.14)

V C 

 Next is the derivation of short channel saturation voltage and current. Note that the short channel current without body-effect coefficient in the linear region is used here for an easier calculation. I dsat  can written as

I dsat

= ns qvsat W     = Cox (VGT − Vdsat ) vsat W  

 

(6.15)

Drain saturation current can also be approximated by letting V = V dsat  in Eq. (6.14)

 I dsat  =

2 ⎡⎣2VGT Vdsat − mVdsat  ⎤⎦  ⋅ ⋅ V   L 1 + dsat 

μ eff C ox W  2

(6.16)

V C 

Substituting I ds from Eq (6.15) into Eq. (6.16), one can obtain V dsat  in quadratic form

2 Vdsat

− 2VGT VC + 2 VdsatVC =  0 

(6.17)

V dsat  can be found by solving the quadratic equation

V dsat  =

−2VC ±

⎛ = V C  ⎜⎜ ⎝

4VC 2 + 8VGT VC

 

 

2 1+ 2

⎞ − 1 ⎟⎟ V C  ⎠

V GT 

(6.18)

59 From Eq. (6.15), when V GT  >> V c and V c is small, V dsat  can be approximated by

Vdsat

≈

2VGT V C

(6.19)

 

Rearranging Eq (6.17), one obtain

2 Vdsat

= 2VC (VGT − Vdsat )   

(6.20)

Therefore, if one uses the Eq (6.18) for  V dsat  and Eq (6.20) for  V 2dsat , the integration in Eq. (6.15) for short channel saturation drain current can be carried out to yield

I dsat

6.3

= Cox vsat W VGT    

(6.21)

Compact I-V Model

The electrical characteristics of bulk MOS transistors are also influenced by the bias applied to the substrate. The body effect coefficient or body factor represents the dependence of the source voltage on the gate bias.

For example, the more

  positive the source-substrate bias the larger number of acceptor atoms that are depleted. As such, I dsat  in Eq (6.21) can be written as  I dsat0 to include the body effect coefficient (Zhou and Lim, 2001).

I dsat 0

= Cox vsat W (VG − VT − mVdsat )  

(6.22)

When drain source resistance, Rds is considered, V  gs and V d  in Eq (6.22) are replaced as shown below

I dsat

= Cox vsat W {(VG − I dsat Rs ) − VT − m ⎡⎣Vdsat − I dsat ( RS + RD ) ⎤⎦}

(6.23)

60 Rearranging Eq. (6.23), one obtains

 I dsat  =

 I dsat 0 1 − Cox vsat W

(6.24)

⎡⎣( m − 1) RS + mRD ⎤⎦

Substituting Eq. (6.24) into Eq. (6.11), V dsat  dsat  becomes

aVd2sat

+ bVdsat  + c = 0

(6.25)

The extracted V dsat  dsat  can be obtained by solving the quadratics equation

V dsat  =

−b − b 2 − 4ac

(6.26)

2a

where

a = vsatWCox mRS

(6.27)

 

b = − ⎡Vg

⎤ ⎣ − Vt + vsatWCox (Vg − Vt ) ( 2 RS + mRSD + mEsat L ) ⎦

c = (Vg

(6.28)

2

− Vt ) Esat L + 2vsatWCox RSD SD (Vg − Vt )   

(6.29)

In order to have one drain current equation which cover both linear and saturation region, a smoothing transition function is utilized.

Vdeff

1 2 = Vdsat − ⎡⎢Vdsat − Vds − δ s + (Vdsat − Vds − δ s ) + 4δ sVdsat ⎤⎥  ⎦ 2⎣

V deff  deff  is used to replace the V ds ds. δ is a fixed parameter.

 

(6.30)

61 By incorporating Eq. (6.30), into Eq. (6.16), the unified one region equation is given as  I ds 0

=

μ eff C ox W 

⋅

2

 L

⎡⎣ 2VGT Vdeff − mVd2eff  ⎤⎦  ⋅ 1+

V deff 

(6.31)

V C 

 I ds0  R sd = 0, therefore when  R sd  is calculated, the expression ds0 denoted the condition for  R  becomes

 I ds 0

=

 I ds 0 1 + I ds 0 Rsd Vdeff   

(6.32)

where Rch is the resistance along the channel. Channel length modulation (CLM) is a non ideal characteristic that present in short channel MOSFET. Therefore, the effective early voltage, V Aeff  is included into the formulation. formulation. It is considered to be  positive and defined as

V  Aeff 

=

Esat Leff ( Esat Leff

+ Vds ) 

ξ V deff 

(6.33)

where ξ is a fitting parameter. With CLM effect, Eq. (6.31) can be rewritten as

 I deff

⎛ V − V  ⎞ = ⎜⎜1 + ds deff  ⎟⎟ I ds 0 V  Aeff  ⎠ ⎝

(6.34)

With the inclusion of Eq (6.33), the drain current is given by

 I ds

=

 I deff  1 + ( Rsd I deff

)V

deff   

(6.35)

62 6.4

Source Drain Resistance

In reality, there are parasitic resistances associated with the source and drain regions other than the channel resistance ( Rch) as illustrated in Figure 6.2. These source drain resistance should be taken into consideration in short channel modeling as it causes a substantial drain current degradation besides contributing to the RC delay.

 R s

Rd 

 Rch

V ds ds Figure 6.2

Source ( R s) and Drain ( Rd ) Resistance

The model is based on the concept introduced by Zhou and Lim (2000).  R sd  is the sum of  R  R s and  Rd  when both resistance are equal in magnitude. It is also compose of  extrinsic ( R  Rext ) and intrinsic resistance ( R  Rint )

R sd  = Rext

+ Rint  

(6.36)

The bias dependent or  R  Rint  is given by

Rint = Rsp

+ Rac

(6.37)

where Rac and R sp is accumulation and spreading resistance respectively. On the other  hand, the bias independent or extrinsic resistance ( Rext ) is given as

Rext

= R sh + Rco

where R sh and  Rco is sheet and contact resistances respectively.

(6.38)

63 The extrinsic resistance Rext  and intrinsic resistance Rint  can be rewritten as

 Rext  =

2 ρ S   jW 

 Rint  =

υ 

(6.39)

(6.40)

VGS  − V T 

where ρ is average resistivity in the spacer region, S is the spacer thickness, x j is the  junction depth and υ is treated as a fixed fitting parameter in Ω - V unit. All of these resistance component is illustrated in Figure 6.3.

Lwin

S

GATE

Xj Metallurgical Junction

 Rac/2  Rco/2

 R sh/2

 R sp/2

Figure 6.3 Current patterns in the source/drain region and its resistance (Ng and Lynch, 1986)

CHAPTER VII

VELOCITY FIELD MODEL

7.1

Introduction

Drift velocity saturation in the channel of a MOSFET is an important factor  in the modeling of short channel devices. I t does not only limit the current at the point of  current saturation in a transistor but also reduces the quadratic relationship of the saturation current on gate voltage into a virtually linear relationship. The velocity model for electron is  presented as well as analysis on the velocity saturation region.

7.2

Velocity Saturation Region Length

Carrier velocity saturation occurs at a section called the velocity saturation region (VSR) length. It is also known as the width of the high-field region where impact ionization takes place as shown in Figure 7.1. The patterned box depicted in Figure 7.1 as Δ L in length is the portion affected with velocity saturation.

65 V  g  V  s

V d  Gate

Source

 L-  L

SiO2

L

n+

Drain n+ Depletion layer

 L ′ 

 L p-type Si substrate

Figure 7.1

Velocity saturation region in MOSFET

The two commonly used empirical velocity longitudinal field relationship models in the inversion layer described by Trofinen (1965) and Caughey and Thomas (1967) respectively as

vd  =

μ eff E y

(7.1)

1 + ( E y E c )

and

vd  =

μ eff  E  y 12

⎡1 +  E E  2 ⎤ ⎢⎣ (  y c ) ⎥⎦

(7.2)

 E c is the critical electric field before the occurrence of velocity saturation defined by

 E c

=

v sat 

(7.3)

eff 

 E  y is the longitudinal electric field given by

 E  y

=

Vd

− IRsd   L

(7.4)

66

The accuracy of Eq. (2.7), Eq. (2.8), Eq. (7.1) and Eq (7.2) is depicted in Figure 7.2. Electric field should be large enough than  E c in order for Eq. (7.1) to approach

νsat. Eq. (2.7) is able to fit the experimental data nicely in the linear region

than the complicated Eq. (7.1) while Eq. (7.2) fits the data quite accurately. The simpler Eq (7.2) reaches saturation at a much later point than Eq (7.1).

8 1.0E+08 1x10

   ) 7   c 1x10 1.0E+07   e   s    /   m   c    ( 6   y 1.0E+06 1x10    t    i   c   o    l   e    V 5

μ 0

= 710 cm 2 /Vsec

E c = 2 .8x10 4 V/cm for Eq.( 2. 7 ) and Eq.( 2. 8 )

ν sat

= 1x10 7 cm/sec

E c = 1 . 1x10 4 V/cm for Eq.( 7. 1) and Eq.( 7. 2 )

Eq. (2.7) & Eq. (2.8)

Eq. (7.1)

Eq. (7.2)

Eq (2.7) & Eq (2.8)

1.0E+05 1x10

4

1x10 1.0E+04 2

1x10 1.0E+02

3

4

1x10 1.0E+03

1x10 1.0E+04

5

1x10 1.0E+05

6

1x10 1.0E+06

Electric Field (V/cm) Figure 7.2

7.3

Comparison of commonly used velocity field models

A Pseudo 2D Model for Velocity Saturation Region

A pseudo 2 dimensional model for the MOSFET operating in the velocity saturation region illustrated in Figure 7.3 can be adopted to yield  E(y).

ABCD

represent the Gaussian box, with boundary AB marks the starting of the saturation  point extending to CD which is the drain junction depth. The value of  E  sat  and V dsat  is located at the edge of VSR point A. In the following analysis, the mobile carrier are assumed to spread evenly in the VSR. The drain junction is heavily doped with a square corner and conducting perfectly.

67

GATE   E  x (0,y)

t ox

(0,0) A

D y

 E  sat 

B

 x j  x j

C x

Figure 7.3

E max

VSR 

Δ L

Analysis of velocity saturation region

Pseudo 2 dimensional model includes the effect of gate field into the analysis and comprises both depletion charge density, qN a and mobile charge density qN m. The Poisson’s equation with field gradient in the x direction is now given by

∂ 2V ( x , y ) ∂ 2V ( x , y ) qN a ( x , y ) qN m ( x , y) + = + ∂x 2 ∂y 2 ε si ε si ∂ E x ( x ) ∂ E y ( y ) qN a qN m   + = + ∂x ∂y ε si ε si

It is assumed that the value of  ∂ E x average value ∂ E x

(7.5)

∂x at each point can be represented by the

∂x from x=0 to x= x j. The value E x ( x j ,y) is assumed to be close to

zero while  E x at the Si-SiO2 interface is denoted by  E x (0,y). The average value

∂ E x ∂x can be approximated by ∂ E x ( x ) ∂Ex ( 0, y ) − ∂Ex ( x j , y ) = ∂ x x j =

∂E x ( 0, y )  x j

(7.6)

68

 E x (0,y) can be rewritten as  E  si (0,y). The field at the surface of the silicon is related to the field in the oxide by the equation

Esi ( 0, y ) =

ε ox ε  si

Eox ( 0 , y )

(7.7)

Eox ( 0, y ) can be expressed as

Eox ( 0 , y ) =

− VFB − 2φ f − V ( y )

VGS

(7.8)

t ox

Substituting Eq. (7.8) into Eq. (7.5) yields

∂Ey ( y ) ⎛ ε ox ⎞⎛ 1 ⎞ ⎛ VGS − VFB − 2φ f − V ( y ) ⎞ qN   qN   + ⎜ ⎟⎜ ⎟ ⎜⎜ ⎟⎟ = a + m ∂y xj ε si ⎝ ε si ⎠⎝ tox ⎠ ⎝ ⎠ ε si

(7.9)

Since V(y=0) = V dsat , Eq. (7.8) can be given as

 E ox ( y = 0 ) =

VGS

− VFB − 2φ f − V dsat

 

t ox

(7.10)

and  E ox ( y = 0 ) =

Qc ε ox

⎛ qN + qN m  ⎞ = x j ⎜ a ⎟ ε ox ⎝ ⎠

(7.11)

Hence

⎛ ε ox ⎞⎛ 1 ⎞ ⎛ VGS − VFB − 2φ f − V dsat ⎞  ⎛ qN a qN m  ⎞ + ⎟⎟ = ⎜ ⎜ ⎟⎜ ⎟ ⎜⎜ ⎟ ε t x ε ε  j si si ⎝ si ⎠⎝ ox ⎠ ⎝ ⎝ ⎠ ⎠

(7.12)

69 Substituting the right hand side of Eq. (7.9) with Eq (7.12) yields

∂ E y ( y ) ⎛ ε ox ⎞⎛ 1 ⎞ ⎛ 1 ⎞ = ⎜ ⎟⎜ ⎟ ⎜⎜ ⎟⎟ ⎡⎣V ( y ) − V dsat  ⎤⎦ ∂y ⎝ ε si ⎠⎝ tox ⎠ ⎝ x j ⎠ ⎡V ( y ) − V dsat  ⎤⎦ =⎣ 2

(7.13)

l 

where l  is the characteristic effective length of the VSR. Eq. (7.13) is a linear first order differential equation which can be solved with boundary condition V(0) = V dsat  and E(0) = E  sat , The general solution of Eq. (7.13) is

y −y ⎡⎣V ( y ) − V dsat  ⎤⎦ l l  = e + Be 2

(7.14)

l 

The coefficients in Eq. (7.14) are found to be A= lE  sat /2 and B=-lE  sat /2. Thus, the expression for V (y) and E y (y) in the VSR is

V ( y ) = Vdsat

+ lEsat sinh ( y l)    

(7.15)

and Ey ( y) =

∂V ( y ) = Vdsat + lEsat cosh (y l)     ∂ x

(7.16)

By solving V (y=ΔL) = V ds and E y (y=ΔL)= E max, they yield

2 ⎡V − V ⎤ ⎛ ⎞ V − V   d dsat d dsat   Δ L = l ln ⎢ + ⎜ ⎟ + 1 ⎥⎥ ⎢ lEsat lE   sat   ⎠ ⎝ ⎣ ⎦

(7.17)

2

Emax

⎛ V − V  ⎞ 2 = Ey ( y = ΔL ) = ⎜ d dsat ⎟  + E sat  ⎝ lE  sat  ⎠

 

(7.18)

CHAPTER VIII

RESULT AND DISCUSSION

8.1

Introduction

In this chapter, the simulated device measurements from the mathematical models calibrated to silicon are compared with the experimental/measured data generated from Intel Proprietary Softwares. This is the case for  I-V  model which is gate biased at 0.7 V, 0.8 V, 0.9 V, 1.0 V and 1.2 V. Two average resistivity values are being employed for evaluation. The short channel NMOS  L is 80 nm with the widths of 1.3 micron. The mobility model has parallel field dependence in the  I-V  model to describe the effect of high longitudinal field for velocity saturation effects. The investigation of velocity saturation is based on the electron drift velocity, effective mobility and electric field in the VSR. The  I-V  curve, saturation electron velocity, effective mobility, effective electric field corresponding to the gate voltage and drain voltage are presented in normalized value due to a Confidentiality/ NonDisclosure Agreement. All of the simulated results are generated using Microsoft Excel while the experimental data is taken from Intel Proprietary Software for 90 nm technology process.

8.2

 I-V Model Evaluation

The measured  I-V  curve generated by Intel Proprietary Schematic Editor and Intel Proprietary Circuit Simulator is shown as solid lines in Figure 8.1, Figure 8.2 and Figure 8.3 for gate voltage 0.7 V, 0.8 V, 0.9 V, 1.0 V, 1.1 V and 1.2 V. In order 

71 to validate the short channel MOSFET developed for this work, the  I-V  model calculated in Section 6.2 is compared to those calculated by a compact  I-V  model in Section 6.3. Initially, the analytical short channel model from Eq. (6.10) and Eq. (6.15) are used to calculate the drain current. However, the model is not able to   predict the drain voltage precisely beyond saturation drain current due to channel length modulation. Furthermore, drain series resistance is not included in this model which affects the degree of accuracy. Therefore, a unified MOSFET compact I-V model from cutoff to saturation has been utilized to fit the graph. In addition to that, a physically based semi empirical series resistance model is also incorporated with   parasitic resistance, ρ  of 3.5x10-5

Ω/cm,

4.5x10 -5

Ω/cm

and 5.5x10 -5

Ω/cm.

The

calculated curve shows an excellent agreement with the  I-V experimental data across a wide range of gate voltage in Figure 8.1. The calculated results show that the lower  ρ  in Figure 8.1 gives a fairly accurate prediction than Figure 8.2 and 8.3. The reason for this is that drain current is inversely proportional to the source drain series resistance. Lower  R sd  will give a higher drain current and vice versa. Further analysis show that there is a slight  I ds inconsistency for  V  g  above 1.0 V from Figure 8.2 and Figure 8.3 with V ds  ranging from 0.8 V-1.5 V.

1.2 Calculated Data VGS = 1.2V

Measured Data 1.0

   t   n   e   r   r 0.8   u    C   n    i   a   r 0.6    D    d   e   z    i    l 0.4   a   m   r   o    N 0.2

VGS = 1.1V VGS = 1.0V VGS = 0.9V VGS = 0.8V VGS = 0.7V

0.0 0

Figure 8.1

0.2

0.4

0.6 0.8 1 Drain Voltage (V)

1.2

1.4

1.6

Comparison of calculated (pattern) versus measured (solid lines) I-V

characteristics for a wide range of gate voltage at resistivity 3.5x10 -5

Ω/cm

72

1.2 3.5e-5

/cm

4.5e-5

1.0    t   n   e   r   r   u    C0.8   n    i   a   r    D0.6    d   e   z    i    l   a   m0.4   r   o    N

/cm

VGS = 1.2V VGS = 1.1V VGS = 1.0V VGS = 0.9V VGS = 0.8V VGS = 0.7V

0.2

0.0 0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

Drain Voltage (V)

Figure 8.2

Comparison of calculated I-V characteristics for a wide range of gate

voltage at resistivity 3.5x10 -5 Ω/cm (solid lines) and 4.5x10 -5 Ω/cm (pattern)

1.2 4.5e-5

5.5e-5

/cm

1.0    t   n   e   r   r   u    C0.8   n    i   a   r    D0.6    d   e   z    i    l   a   m0.4   r   o    N

/cm

VGS = 1.2V VGS = 1.1V VGS = 1.0V VGS = 0.9V VGS = 0.8V VGS = 0.7V

0.2

0.0 0

0.2

0.4

0.6

0.8

1

1.2

1.4

Drain Voltage (V)

Figure 8.3

Comparison of calculated I-V characteristics for a wide range of gate

voltage at resistivity 4.5x10 -5 Ω/cm (solid lines) and 5.5x10 -5 Ω/cm (pattern)

1.6

73 The author also analyze the effect of Channel Length Modulation (CLM) has on the

 I-V  curve. Notable differences can be found in Figure 8.4 where the saturation drain current is predicted higher in the saturation region compared to the shaded lines (without CLM). Since the channel length is modulated by the drain current when it is in saturation,  I dsat  increases with increasing V ds. In other word, the deviation of the drain current from its ideal I-V  curve is due to increased average electric field at decreasing effective channel length. The velocity saturation extracted from these figure is found to be satisfactory with the default velocity suggested by the process technology file.

1.2 With CLM

Without CLM

1.0    t   n   e   r   r   u    C0.8   n    i   a   r    D0.6    d   e   z    i    l   a   m0.4   r   o    N

VGS = 1.2V VGS = 1.1V VGS = 1.0V VGS = 0.9V VGS = 0.8V VGS = 0.7V

0.2

0.0 0

0.2

0.4

0.6

0.8

1

1.2

1.4

Drain Voltage (V)

Figure 8.4

Comparison of calculated I-V characteristics for a wide range of gate

voltage at resistivity 3.5e-5 Ω/cm with (pattern marking) and without channel length modulation (solid lines)

1.6

74 8.3

Threshold Voltage

Short channel effect also alter the threshold voltage characteristic of long channel MOSFET. The combined effects of reduced gate length and gate width   produce a change in V T . Figure 8.5 show the long channel like threshold voltage  behaviour generated using Eq. (4.14). In the beginning, threshold voltage is negative as device is lightly doped in which the positive oxide charge and work function difference is overwhelming.

0.9 Threshold Voltage      h

    t      V 0.6

  e    )   a    t    V    l    (   o   e   g 0.3    V   a    t    d    l    l   o   o    V    h   s   e   r    h 0.0    T

-0.3

17

16

Figure 8.5

18

1x10 1x10 1.E+17 1.E+18 -3 Doping Concentration (cm )

1x10 1.E+16

19

1x10 1.E+19

Threshold Voltage without Short Channel Effect (SCE) and Narrow

Width Effect (NWE)

To get a good calculation, two short channel effects on the threshold voltage of MOSFET namely the short channel voltage shift and narrow gate width effect. Short channel effect decreases the threshold voltage due to the charge sharing under  gate oxide and can be plotted using Eq. (4.17). The threshold voltage shift decreases dramatically at higher channel doping. When the channel length approaches the  junction depletion region width of source and drain, a greater portion of the channel

75 depletion region begins to overlap the space charge in the junction depletion regions. As a result, less gate charge is needed to cause inversion in short channel MOSFET. Hence, a smaller threshold voltage is needed to turn on a short channel device and changes the ideal threshold voltage as shown in Figure 8.6. An additional effect that also modifies the expected V T  is the narrow width effect and is represented using Eq. (4.20). Although, this effect is less critical than short channel effect as illustrated in Figure 8.6, it causes a positive shift for threshold voltage. In Figure 8.7, the effect of short channel and narrow width effects from becomes more pronounced as the doping concentration goes beyond 1x10 16 cm-3. The final V T  in Figure 8.7 is given  by Eq. (4.21).

3.0 Short Channel Effect 2.0

Narrow Width Effect

1.0

   )    V    ( 0.0   e   g   a    t    l   o -1.0    V -2.0 -3.0 -4.0 14 1.E+14 1x10

15

1.E+15 1x10

16 1.E+16 1x10

17 1.E+17 1x10

18

1.E+18 1x10 -3

Doping Concentration (cm )

Figure 8.6

Short channel and narrow width effect

19

1.E+19 1x10

76

0.6

0.3      h     t

     V

  e    ) 0.0   a    V    t    (    l   e   o   g    V   a    t    l -0.3    d    l   o   o    V    h   s   e   r    h    T-0.6

-0.9 13 11x10 .E+13

Figure 8.7

8.4

Threshold Voltage

14

1x10 1.E+14

15

16

17

1x10 1x10 1.E+15 1.E+16 1x10 1.E+17 -3 Doping Concentration (cm )

18

1x10 1.E+18

19

1x10 1.E+19

Threshold voltage modification with doping concentration

Doping Concentration Dependence

The transport of free charge carriers in semiconductor is described by studying semiconductor’s conductivity via mobility.

The mobility is higher for 

electrons than holes due to lower effective mass. Many microelectronics applications favor semiconductor with higher mobility of charge carrier that provides moderate and high device performance.

Scattering is the motion-impending collisions

interaction within the crystal. These collisions can be an electron bumping into another electron, a hole, with the thermal vibrations of the lattice and with the ionized impurities atom in a direction dictated by the electric field. The three major  scattering mechanisms that affect the mobility of the carrier are Coulomb, surface roughness and phonon scatterings.

Scattering may may increase increase or decrease with

increasing electric component perpendicular to the direction of current flow and temperature. These scattering limits the mobility at certain portion along the transverse electric field. For example, the mobility drop or roll-off of the effective mobility in the low field region as shown in Figure 8.8 is attributed by the Coulomb

77 scattering while the mobility degradation is contributed by the surface scattering. Eq. (5.8) is employed to plot the mobility curve.

1.2 15

-3

 N  A Na = 1x10 cm cm = 1.0 E+15

1.0   y    t    i    l    i    b   o 0.8    M   e   v    i    t   c   e    f    f 0.6    E    d   e   z    i    l 0.4   a   m   r   o    N 0.2

T = 300K  T = 300 K 

-3

16

-3

 N  A = 1x10 cm -3 Na = 1.0 E+16 cm 17

-3

 N  A = 1x10 cm -3 Na = 1.0 E+17 cm 18

 N  A = 1x10

-3

cm

Na = 1.0 E+18cm

-3

0.0 1.1x10 00E+404

Figure 8.8

5

11x10 .00E6+06 Effective Transverse Electric Field (V/cm) 1.00E+05 1x10

11x10 .00E+707

Normalized effective mobility versus transverse electric field at

different doping concentration

Although each of the individual mobility curves for the four doping concentration in Figure 8.8 has different initial mobility, they formed a unique universal mobility curve versus transverse electric field.

Coulomb scattering

considerably degrades the mobility on higher impurity concentration as the deviation from the universal curve becomes larger. It is caused by the Coulomb interaction  between the carrier in the inversion layer and the interface charges localized in SiO2. When the doping concentration is low, the mobility is higher as Coulomb scattering is lower. The mobility of the carriers begins to decrease gradually when concentration of the dopants increases. Consequently, there are more carriers to  bump into and scattering becomes more frequent. Therefore, the Coulomb scattering equation described in the mobility model includes both scattering caused by fixed interface charge and doping impurities for better modeling. As the channel inversion

78 increases, the number of impurities and charge which are able to interact with the carriers decreases. This can be ascribed to the carrier screening effect which is less effective for a heavily inverted surface. The velocity saturation dependence on doping concentration is depicted in Figure 8.9 and determined by using Eq. (7.2).

1.0

TT=300K  = 300 K  0.8

  y    t    i   c   o    l   e    V0.6    t    f    i   r    D    d   e   z0.4    i    l   a   m   r   o    N0.2

15

-3 -3

16

-3 -3

1.01x10 E+15 cm 1.0e15cm-3 cm 1.01x10 E+16 cm 1.0e16cm-3 cm

-3

17 -3 1.0e17cm-3 1.01x E+17 10 cm cm 18

-3 -3

1.01x10 E+18 cm 1.0e18cm-3

0.0 1.0E1x10 +03

3

4

1.01x10 E+04

5

11x10 .0E+05

6

1x10 1.0E+06

Effective Longitudinal Longitudinal Electric Field (V/cm)

Figure 8.9

Normalized drift velocity versus longitudinal electric field at different

doping concentration

The drift velocity as a function of the longitudinal field for different doping concentrations are essentially similar due to the domination of surface roughness scattering at higher field. Surface-roughness scattering within within the inversion layer is a function of the effective field independent of the doping concentration. When drift velocity is plotted as a function of the longitudinal field for different doping concentrations of 10 15 cm-3, 1016 cm-3, 1017 cm-3 and 1018 cm-3 as shown in Figure 8.9, they are essentially similar due to the limitation of surface roughness scattering. At first glance, doping concentration does not have a significant influence on drift velocity at high field as they overlap each other. This is due to the fact that the mobility for different doping concentrations is taken from the mobility curve in

79 Figure 8.8 at a fixed transverse field. In reality, the transverse field at a given gate   bias for different doping concentrations will be different due to the different V T  at different substrate doping concentration. For the same gate bias, the higher doped substrate will experience a higher transverse field, and lower mobility at the high fields experienced when the device is on. However, this also means that the critical field will be higher for higher doped substrates and higher doped substrate will reach saturated velocity later. The saturation field, E  sat  is chosen to be twice of the critical field, 2 E c as it has been the range of vertical field in MOSFET device reported in the literature.

8.5

Temperature Dependence

  Normalized effective mobility versus longitudinal electric field at 77 K, 300 K, 400 K and 450 K is illustrated in Figure 8.10 by utilizing Eq. (5.8). At low temperature of 77 K, saturation velocity is substantially influence by surface roughness scattering. Devices at low temperature have a higher drift velocity as a result of a high effective mobility as illustrated in Figure 8.10. However, as temperature is increase to 300K and above, the calculated mobility shows that scattering mechanism transit to phonon scattering for moderately doped devices  biased at moderate vertical field. The drift velocity curve for 77 K, 300 K, 400 K and 430 K is depicted in Figure 8.11 by employing Eq. (7.2).

At 77 K, drift velocity reaches saturation earlier compared to 300 K. This is then followed by 400 K and 430 K. Velocity saturation is achieved for all four  temperatures at 1x106 V/cm onwards. In short, temperature plays a vital role in device operation. On one hand, mobility increa ses inversely proportional temperature due increased phonon scattering at higher temperature. On the other hand, drift velocity increases proportionally with mobility only to be limited by velocity saturation. Critical longitudinal electric field also increases with temperature. The finding shows that the operation of the MOSFET revolves at high field beyond 1x10 6 V/cm for both E  x and E y as a result of a very short  L at 80nm.

80

1.2

70 K 

1.0

  y    t    i    l    i    b   o 0.8    M   e   v    i    t   c   e    f    f 0.6    E    d   e   z    i    l 0.4   a   m   r   o    N0.2

70K  T = 70 K  300K  T = 300 K  400K  T = 400 K  450K  T = 450 K 

300 K  400 K  450 K 

0.0

1x10 1.0E+04

4

5

6

1x10 1.0E+05

7

1x10 1.0E+06

1x10 1.0E+07

Effective Transverse Electric Field (V/cm)

Normalized effective mobility versus transverse electric field at

Figure 8.10

different temperature

1.2

1.2 V Gate Voltage = 1.1V 1.0

  y    t    i   c   o    l   e0.8    V    t    f    i   r    D0.6    d   e   z    i    l   a   m   r0.4   o    N

T = 70 K  77K  T = 300 K  300K  T = 400 K  400K  T = 450 K  430K 

0.2

0.0 3

1.00E+03 1x10

4

1.00E+04 1x10

5

1.00E+05 1x10

6

1.00E+06 1x10

7

1.00E+07 1x10

8

1.00E+0 1x10

Effective Longitudinal Electric Field (V/cm)

Figure 8.11

temperature

Normalized drift velocity versus longitudinal electric field at different

81 8.6

Peak Field At The Drain

Figure 8.12 illustrates the normalized longitudinal electric field along the channel  position for drain voltage of 1.2 V. The strength of the longitudinal electric field is determined by the device V T , source and drain series resistance and  L as expressed in Eq. (7.4). Shorter channel length yield larger  E  y and correspondingly higher velocity. By using Eq. (7.16), the longitudinal electric field versus  L is plotted. It has a linear  relationship with the channel up to  E  sat  where V dsat  occurred.

From this point

onward, the electric field grows exponentially to  E max near the drain end in the velocity saturation region.  E max is calculated using Eq. (7.18). Under the influence of  saturation velocity, electron drift velocity becomes constant and independent of the effective longitudinal field,  E  y. In short channel devices, the saturation of drain currents occur at a much lower voltage due to velocity saturation. The  I dsat  is approximately linear with gate overdrive, instead of having a square law dependence   predicted in long channel device in Figure 8.13. The saturation drain current is equally spaced voltage against drain voltage at different gate voltages as shown in Figure 8.14. The value of  I dsat  is determined by using Eq. (6.26) and Eq. (6.33).

1.2

   d    l   e    i    F 1.0   c    i   r    t   c   e    l 0.8    E    l   a   n    i    d   u 0.6    t    i   g   n   o    L    d 0.4   e   z    i    l   a   m   r 0.2   o    N

Emax

Vds = 1.2V 1.2 V

Emax

Esat

0.0 0 0.0E+00 0x10

Figure 8.12

-6 2.0E-06 2x10

-6 4.0E-06 4x10

-6

6.0E-06 6x10

Channel Position y (m)

-6 8.0E-06 8x10

-5

1.0E-05 1x10

Normalized longitudinal electric field along the channel

82

1.0

   t   n   e 0.8   r   r   u    C   n    i   a   r 0.6    D   n   o    i    t   a   r   u 0.4    t   a    S    d   e   z    i    l   a 0.2   m   r   o    N

-3

16 Doping Concentration: 11x10 E+16 cm -3

0.0 0.2

0.3

0.4

0.5 0.6 0.7 Gate Overdrive VG-VT (V)

0.8

0.9

Normalized saturation drain current versus gate overdrive

Figure 8.13

1.2 -3

16 Doping Concentration: 11x10 E+16 cm-3 cm

   t   n1.0   e   r   r   u    C   n0.8    i   a   r    D   n   o0.6    i    t   a   r   u    t   a    S0.4    d   e   z    i    l   a   m0.2   r   o    N

Vgs = 1.2 V Vgs = 1.1 V Vgs = 1.0 V Vgs = 0.9 V Vgs = 0.8 V Vgs = 0.7 V Vgs = 0.6 V Vgs = 0.5 V

0.0 0.0

Figure 8.14

0.1

0.2 0.3 Drain Voltage Vd (V)

0.4

0.5

Normalized saturation drain current versus drain voltage

0.6

CHAPTER IX

CONCLUSIONS AND RECOMMENDATIONS

9.1

Summary and Conclusions

Velocity saturation is caused by the increased scattering rate of energetic electrons, particularly optical phonon emission resulting in the degrading effect of  the carrier mobility. Under the influence of saturation velocity, electron drift velocity   becomes constant and independent of the effective longitudinal field. Velocity saturation becomes more pronounced in short channel devices as they operate at high electric field. It yields smaller drain saturation current and voltage value than that  predicted by the ideal long channel relation. The capability of long channel models is limited as they are unable to provide an accurate representation of drain current model for short channel devices due to a lack of physicals component consideration.

Initially, the work done by Shin (1991) is limited to effective mobility. He studied a variation of effective mobility versus temperature, doping concentration and longitudinal electric field. On the other hand, the investigation of the effect of  the velocity saturation by Takeuchi and Fukuma (1994) is carried out only for drain voltage dependence and scaling. Hence, this research extends the work into drift velocity versus longitudinal electric field for a variation of temperature, substrate doping concentration and longitudinal electric field in nanoscale MOSFET.

84 Several newly developed models are modified and employed to analyze the characteristics and behaviors of transistor in sub-100 nm. They are the threshold voltage model, physically based model for effective mobility and compact  I-V , velocity field model and source drain resistance model. It is vital to investigate the   physical insight into the device’s operating principles at high field to diminish hot carrier effect and avoid catastrophic breakdown of the device via punchthrough. The abovementioned models are improvement upon existing long channel models and include various effects discussed in previous chapters.

Intel Proprietary Schematic Editor and Circuit Simulator are used to generate experimental data. The relevant parameters are then extracted from the  I-V  curve. Finally, the modified models are utilized to characterize the effects of velocity saturation and effective mobility on drain voltage, gate voltage, temperature and doping concentration. Simulated results show that the temperature effect on velocity saturation depends on the predominant scattering mode. It is shown that at high fiel ds where surface roughness is predominant, the mobility has a negative temperature coefficient and the velocity saturates at lower temperatures. Substrate doping concentration changes the transverse field and scattering modes for a given gate bias, and hence the saturation velocity is achieved at different longitudinal fields

9.2

Recommendations for Future Work 

(i)

The V T  model can be modified to account for nonuniform channel doping profile. When the MOSFET channel is nonuniformly doped, designer has the flexibility to tailor the desired threshold voltage and the off current requirement. Among the advanced MOSFET variation is

threshold

voltage

adjustment

implantation,

punchthrough

implantation and halo implantation. (ii)

The electron mobility model can be extended into strained and doped silicon transport. The presence of a Ge alloy in strained silicon has additional implications for the effective mobility over the universal

85 mobility curve. Alloy scattering can be added describe the carrier  collision with the SiGe alloy substrate. (iii)

The implication of velocity saturation effects on PMOS can also be examined. With the simulated results, research can be carried out in order to observe the hot carrier effects focusing on CMOS in  processor particularly at high temperature operation.

(iv)

By using PSpice Model Editor, the derived model can be exported to the library and configured to simulate the design output for DC analysis. Instead of using Microsoft Excel, the analytical and semi empirical models can be redefined into SPICE models and added into a circuit as a schematic symbol to perform basic simulation.

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 Device Letter . 25(4):191-193. Trofinenkoff, F. N. (1965). Field dependent mobility analysis of the field effect transistor. Proceedings of the IEEE , 53:1765. Tsividis, Y. Operation and Modeling of The MOS Transistor . 2nd Edition. Madison Avenue, New York :Oxford University Press Inc. 1999. Wang, R., Dudley, J., DeMassa, T. A. and Jelsma, L. F. (1971). Threshold voltage variations with temperature in MOS transistors. IEEE Trans. Electron

 Devices . 18:386-388. Wolf, S. Silicon Processing For The VLSI Era Volume 3: The Submicron MOSFET . Sunset Beach, California :Lattice Press. 1995. Xuemei, X., and Mohan, D. (2006). BSIM3 homepage. http://www-device.eecs.berkeley.edu/~bsim3/latenews.html

 BSIM Research Group. Yu, B., Wann, C. H. J., Nowak, E. D., Noda, K. and Hu, C. (1997). Short-channel effect improved by lateral channel-engineering in deep-submicrometer  MOSFET’s. IEEE Trans. Electron Devices . 44:627-633 Yu, Z., Shao, X., Zhang, D. and Tian L. Quantum Mechanical Carrier Transport and  Nano-scale MOS Modeling.  Institute of Microelectronics, Tsinghua

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http://ece-www.colorado.edu/~bart/book/book/chapter2/ch2_3.htm#tab2_3 . Zeitzoff, P.M. (2004). Challenges and key potentia l technological innovations for  scaling MOSFETS through the end of the roadmap.   International Conference

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 Devices Magazine. 21(1):4-15.

91 Zhou, X., Lim, K. Y. and Lim D. (1999). A simple and unambiguous definition of  threshold voltage and its implications in deep-submicron MOS device modeling.  IEEE Trans. Electron Devices. 46(4):807-809. Zhou, X. and Lim, K. Y. (2000). Physically-based semi-empirical series resistance model for deep-submicron MOSFET  I-V  modeling.   IEEE Transactions on

 Electron Devices. 47(6):1300-1302. Zhou, X. and Lim, K. Y. (2001). Unified MOSFET compact  I-V  model formulation through physics-based effective transformation. IEEE Transactions on

 Electron Device. 48(5):887-896.

APPENDICES

93

APPENDIX A

PUBLICATION

A1 Michael Tan Loong Peng, Razali Ismail, Ravisangar Muniandy and Wong Vee Kin. (2005). Velocity Saturation Dependence on Temperature, Substrate Doping Concentration and Longitudinal Electric Field in Nanoscale MOSFET . Proceedings IEEE National Symposium on Microelectronics. pp. 210214

94

Velocity Saturation Dependence on Temperature, Substrate Doping Concentration and Longitudinal Electric Field in  Nanoscale MOSFET Michael Tan Loong Peng 1, Student Member , IEEE, Razali Ismail1 , Ravisangar Muniandy 2 and Wong Vee Kin2 1

Department of Microelectronics and Computer Engineering, Universiti Teknologi Malaysia, 81300 Skudai, Johor, MALAYSIA Email: [email protected], [email protected] 2

Penang Design Center (PG12), Intel Microelectronics (M) Sdn. Bhd., Bayan Lepas Free Industrial Zone, 11900 Penang, MALAYSIA Email: [email protected], [email protected]

 Abstract  – This paper reports the drift and velocity saturation dependence on temperature, substrate doping concentration and longitudinal electric field for n-MOSFET. This study observes the velocity in response to the variation of above input parameters. An existing current-voltage ( I-V ) compact model is utilized and modified by appending a simplified threshold voltage derivation and a more precise carrier mobility model. The threshold voltage derivation provides similar accuracy when compared to actual devices and comprises major short channel effect as well as narrow width effect. The compact model also includes a semi empirical source drain series resistance modeling. The models show good agreement with the experimental data over a wide range of gate and drain bias.

I.

I NTRODUCTION

VELOCITY saturation occurs in high electric fields when the drift velocity of electron in the inversion channel reaches a limiting value, at 107 cm/s due to mobility degradation. Linear  velocity field relationship is applicable as long as the electric field is low. Here, Ohm Law’s is still valid. Electrons in nanoelectronic devices are   being driven by a tremendously high electric field [1] and can go up to 10 6 V/cm. At high critical electric field, the average carrier energy and scattering rate of highly energetic electrons increases. Under these circumstances, the carrier  loses their energy by optical-phonon emission nearly as fast as they acquire from the field. This resulted in mobility degradation. Second order  effects (SOE) in 50-100nm generation of ultra

submicron transistor designs such as velocity saturation, short channel effect (SCE), channel length modulation (CLM) and narrow width effect (NWE) is increasingly becoming a great concern for designers [2]. Velocity saturation deteriorates the drive strength in the saturation velocity region. SOE could be ignored in   previous long channel CMOS generation as the effects are not that significant. Nevertheless, these undesirable effects are inevitable when devices are gradually scaled down to gain higher  speed, performance and chip density [3]. Many research have been carried out [4-5] for  the development of semi empirical model for  nanoscale MOSFET under the influence of  velocity saturation. More investigation has to be done to examine the velocity saturation dependence on transverse electric field, substrate doping concentration and temperature. This analysis is crucial when taking into account MOSFET scaling on device performance. In this   paper, the impact of velocity saturation, on the   parameters mentioned above is presented. The   paper is organized as follows. We began with a survey of studies on limitation of scaling of  MOSFET and effect of the velocity saturation [6]. Section II provides further description of the employed models. Firstly, a simple semi empirical threshold voltage is derived for  nanoscale MOSFET [7]. It is then incorporated with a modified semi empirical I-V model by considering a more accurate description of  mobility model [8]. Finally, a velocity field model is used to analyze the carrier drift velocity in the channel. Result are presented and discussed in Section III. Section IV concludes the study.

95 II.

MODEL A ND METHODS

 B. The Mobility Model 

The outcome of this model will depend   primarily on the original mobility model The threshold voltage, V T  is one of the key developed by Schwarz and Russek described by  parameters in MOSFET design and modeling to [10] with some improvement on the scattering   predict the device performance. There are mechanism. The electron effective mobility due various kinds of definitions and extraction to the vertical field [11] is modeled semimethods proposed [9], each with a focus on empirically incorporating three basic scatterings mechanisms in the inversion layer is namely, different aspects. This model formulation starts with the modeling of threshold voltage for nCoulombic scattering due to doping channel MOSFET with n+ polysilicon gate and concentration, phonon scattering and surface  p-type silicon substrate. The model assumes that roughness scattering as shown below there is no substrate bias effect. The analytical −1 definition of the threshold voltage is ⎡ 1 1 1 ⎤ (5) μ eff  = ⎢ + + ⎥

 A. The Threshold Voltage Model 

VT

= 2φ f + VFB +

(

2ε Si qN A 2φ f

)

Cox

where φ  f  is the Fermi potential,  N  A is the substrate doping concentration, k is the Boltzmann’s constant, is the C ox gate oxide capacitance, V  FB is the flat band voltage, ε Si is the dielectric permittivity of the silicon. Next, SCE which decreases the MOSFET threshold voltage as the channel length is reduced is included as follow:

ΔV T for s c =−

qNxdT ⎡ r  j Cox

⎤ 2x ⎢ 1 + dT − 1 ⎥ r j ⎢⎣ L ⎥⎦

(2)

where  xdT  is the lateral space charge width and r  j is the diffused junction. In addition, there is also a shift in threshold voltage in the positive direction for the devices due to a narrow-width effect. qNxdT ⎡ ξ xdT ⎤  (3) ΔV T for n w = Cox ⎢⎣ W  ⎥⎦ where ξ is the empirical parameter that account for the shape of the fringe depletion region and q is the electronic charge. Hence, the final threshold voltage expression is as shown

VT

−

= 2φ fp + V FB ±

qNxdT Cox

(

2ε qN  2φ  f 

⎢⎣ μ ph

(1)  

)

μ c ⎥⎦

μ sr

Matthiessen’s rule is used to calculate each different scattering contribution to the effective mobility. The effective mobility is a function of  the effective transverse electric field,  E ⊥eff  [12] and is defined by the following equations

E⊥eff

=

1 ε si

(η Qinv + QB ) =

1 6t ox

(Vgs + Vt )

 

(6)  

where η  is ½ for <100> electrons. From (6), it can be seen that the effective electric field is   proportional to the channel inversion charge, Qinv and depletion charge, Q B. It can be written as a function of gate overdrive and gate oxide thickness, t ox for as long as V  gs > V t . The model developed by [13] has been used. The mobility due to phonon and fixed interface charge scattering, μ  ph is −1 ⎤ −1 ⎛ ⎡ ⎞ ⎛ ⎞ μ   z  ⎟ ⎥ μ  ph = ⎢⎜ − B2.5 ⎟ + ⎜ 1 ⎢⎜ T  ⎟ ⎜ ⎥ −9 2 ⎟ ⎢⎣⎝ n ⎠ ⎝ 3.2x10  pT n ⎠ ⎥⎦

−1

(7)

while the surface roughness scattering, μ  sr  is defined as μ sr = K sr E ⊥eff − 2

(8)

C ox

⎡⎛ r  j ⎞ ⎛ ξ x 2x ⎢⎜ 1 + dT − 1⎟ − ⎜ dT ⎟ ⎝ W rj ⎢⎣⎜⎝ L ⎠

⎞⎤⎥ ⎟⎥ ⎠⎦

and coulomb scattering, μ c can be expressed as  

(4)  

μ c

=

1.1x10 −21T n1.5

⎡ γ  2 BH  ⎤ 2 ⎢ln (1 + γ  BH ) − γ 2 ⎥ N A 1 +  BH  ⎣ ⎦

(9)

96 where  p is the Fuchs factor,  z is the average inversion layer width including quantum channel   broadening effects. In the above T n is the normalized temperature at 300K. The mobile inversion layer charge density is given as

Qinv

= qN I = 2ε si ( E⊥eff +  E0 )  

(10)

and  E  y is the longitudinal electric field.  E  y is given by V − IRs / d   (16)  E  y = d  L When  E  >>  2E c , vd   becomes μ eff  E c. Quasi two dimensional approach by Ko [18] is applied here to model the velocity saturation region (VSR).

and depletion region charge density is III.

QB

= q ⋅ N A ⋅ xd = 2q ⋅ N A ⋅ε si ⋅ 2φ F

 

R ESULTS A ND DISCUSSION

(11) 1.2

Gate Voltage = 1.1V

C. The I-V model 

1.0

The  I-V  model is much simpler than the BSIM3v3 expression and taken from the compact model given by Xing Zhou et al . [14]. The final complete  I ds model includes the effect of CLM and R s/d  and is given by

 I ds

=

 I deff  1 + ( Rs / d I deff

)

(12)

Vdeff   

= Rext + Rint = 

2 ρ S 

x jW

υ 

VGS

− VT    

(13)

 D. The Velocity-Field Model  The electron velocity-longitudinal field relationship in the inversion layer given in [16] is described as

vd  =

μ eff E y 1n

⎡1 + ( E y E c ) ⎤ ⎢⎣ ⎥⎦ n

(14)

with n=2 for electrons,  E c is the critical electric field for velocity saturation defined by

 E c

=

v sat  μ eff 

300K 

400K 

430K 

0.2

0.0 1.00E+03

Fig. 1

+

77K 

1.00E+04

1.00E+05

1.00E+06

1.00E+07

1.00E+08

Effective Longitudinal Electric Field (V/cm)

where V deff  is the smoothing function to replace V ds for a smooth transition from linear to saturation region while  I deff  is the smoothing function for  I ds0iwith effective early voltage. A   physically-based source/drain (S/D) series resistance, R s/d  model for deep submicron MOSFET is included comprising a biasdependent (intrinsic) component and a biasindependent (extrinsic) to give a precise reading [15]. The final S/D series resistance is given by

Rs / d

  y    t    i   c   o    l   e0.8    V    t    f    i   r    D0.6    d   e   z    i    l   a   m   r0.4   o    N

(15)

Normalized υ d  versus  E  y for different temperature as indicated.

The saturation electron velocity, effective mobility, effective electric field corresponding to the gate voltage and drain voltage are summarized here. Under the influence of  saturation velocity, electron drift velocity   becomes constant and independent of the effective longitudinal field,  E  y. The saturation field,  E  sat  is chosen to be twice of the critical field, 2 E c as it has been the range of vertical field in MOSFET device reported in literature [17]. In short channel devices, the saturation of drain currents occur at a much lower voltage due to velocity saturation. It can be concluded that for a higher vertical field, the effective mobility is lower but the critical field becomes higher as shown in (15). At low temperature at 77 K , saturation velocity is substantially influence by surface roughness scattering. Devices at low temperature have a higher drift velocity as a result of a high effective mobility as illustrated in Figure 2. However, as temperature is increase to 300K and above, the extracted mobility show that scattering mechanism transit to phonon scattering for moderately doped devices biased at moderate vertical field. The drift velocity curve for 300 K , 400 K  and 430 K  appear lower  compared to 77 K  as depicted in Figure 1 but

97 velocity saturation is achieved for all four  temperature at 1 x106 V/cm onwards. 1.2

Na = 1.0 E+15 cm

  y 1.0    t    i    l    i    b   o    M0.8   e   v    i    t   c   e    f    f 0.6    E    d   e   z    i    l 0.4   a   m   r   o    N0.2

-3

Na = 1.0 E+16 cm

-3

1.2

Na = 1.0 E+17 cm

-3

Na = 1.0 E+18cm

-3

0.0 1.00E+04

Fig. 2 3

channel, thus, making the velocity saturation effects less pronounced. Nevertheless, the drive current of the transistor still suffers from the reduced transconductance.

1.00E+05 1.00E+06 Effective Transverse Electric Field (V/cm)

1.00E+07

Normalized μ eff  versus  E ⊥eff  for different doping concentration. ( N  A=1015cm-3, 1016cm-

,

   d    l   e    i    F 1.0   c    i   r    t   c   e    l    E 0.8    l   a   n    i    d   u 0.6    t    i   g   n   o    L    d 0.4   e   z    i    l   a   m   r 0.2   o    N

Emax

Vds = 1.2V

Esat

0.0 0.0E+00

2.0E-06

4.0E-06

6.0E-06

8.0E-06

1.0E-05

Channel Position y (m)

17

-3

18

-3

10 cm and 10 cm )

Fig. 4

Normalized  E  the channel and  y along illustration of velocity saturation region.

1.00

0.80

  y    t    i   c   o    l   e    V0.60    t    f    i   r    D    d   e   z 0.40    i    l   a   m   r   o    N

1.0 E+15 cm 1.0e15cm-3

-3

1.0 E+16 cm 1.0e16cm-3

-3

1.0e17cm-3 1.0 E+17 cm

-3

1.0 E+18 cm 1.0e18cm-3

-3

0.20

0.00 1.0E+03

Fig. 3

1.0E+04 1.0E+05 Effective Longitudinal Electric Field (V/cm)

1.0E+06

Plot of the normalized υ d  dependence of  E  y for four doping level

At a high enough transverse field, the mobility for different doping concentrations are taken from the mobility curve in Figure 2. If we   plot the drift velocity as a function of the longitudinal field for different doping concentrations as shown in Figure 3, they are essentially similar due to surface roughness scattering as discussed in [18]. In reality, the transverse field at a given gate bias for different doping concentrations will be different due to the different V T  at different substrate doping concentration; for the same gate bias, the higher  doped substrate will experience a higher  transverse field, and lower mobility at the high fields experienced when the device is ON. However, this also means that the critical field will be higher for higher doped substrates and higher doped substrate will reach saturated velocity later. Conventional deep submicron devices use halo implantation to control short channel effects and this has the undesired effect of raising the substrate concentration in the

Figure 4 illustrates the normalized  E  y along the channel position for  V ds=1.2V. The strength of the longitudinal electric field is determined by the device V T,  source/drain series resistance and  L as expressed in (16). Shorter  L will yield larger   E  y and correspondingly higher velocity.  E  y shown here has a linear relationship with the channel up to  E  sat  or where V dsat  occurred. From here onward, the velocity saturation region   begins and rises exponentially to  E max near the drain end. IV.

CONCLUSION

In this paper, the V T  model, μ eff  model,  I-V  model and the  Rd/s model are employed to investigate the velocity saturation in nanoscale MOSFET. Major physical mechanisms contributing to velocity saturation have been considered, discussed and analyzed. The temperature effect on velocity saturation depends on the predominant scattering mode. We have shown that at high fields where surface roughness is predominant, the mobility has a negative temperature coefficient and the velocity saturates at lower temperatures. Substrate doping changes the transverse field and scattering modes for a given gate bias, and hence the saturation velocity is achieved at different longitudinal fields. For digital circuit designers, these effects of saturation velocity moves the regions of operation for the MOSFET, and can   be compensated by increasing the drive current using novel process technologies such as using strained silicon

98 ACKNOWLEDGEMENT The authors would like to thank Intel Penang Design Center (PDC) for providing the experimental data and simulation tools for this work. The authors are also indebted to Prof  Vijay K. Arora who gave them continuous encouragement during the study of saturation velocity. Fruitful discussions on the modeling with Dr. Kelvin Kwa Sian Kiat, Lock Choon Hou, Kaw Kiam Leong, Alvin Goh Shing Chye and Lim Kiang Leng are greatly appreciated. R EFERENCE [1]

[2]

[3]

[4]

[5]

[6]

[7]

V. K. Arora, “High-Field Effects in Sub IEEE   Proceedings Micron Devices,” Conference on Optoelectronic and  Microelectronic Materials and Devices (COMMAD), pp. 33-40 (2000). Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S.-H. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind, and H.-S. Wong, “CMOS Scaling into the  Nanometer Regime,” Proceedings of the IEEE , vol. 85, pp. 486-504 (1997). Y. Taur, “CMOS Design Near the Limit of  Scaling,” IBM J. Res. & Dev., vol. 46, no. 2/3,  pp. 213-222 (2002). J. B. Roldan, F. Gamiz, J.A. Lopez-Villanueva, and J.E Carceller, “Modeling Effects of  Electron-Velocity Overshoot in a MOSFET,”   IEEE Transactions on Electron Devices, vol. 44, no. 5, pp 841-846 (1997). M. Pattanaik and S. Banerjee, “A new approach to model  I-V  characteristics for nanoscale MOSFETs,” VLSI Technology, Systems, and    Applications 2003 International Symposium ,  pp. 92-95 (2003). A. Lochtefeld, I. J. Djomehri, G. Samudra and D. A. Antoniadis, “New insights into carrier  transport in n-MOSFETs,” IBM J. Res. & Dev., vol. 46, no. 2/3, pp. 347-358 (2002). R. Wang, J. Dunkley, T. A. DeMassa and L.F. Jelsma, “Threshold Voltage Variations with Temperature in MOS Transistors,”  IEEE  Trans. Electron Dev, vol. 18, no. 6, pp. 386388 (1971).

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

[16]

[17] [18]

J. R. Hauser, “Extraction of experimental mobility data for MOS devices,”  IEEE  Transactions Electron Devices, vol. 43, no. 11,  pp. 1981-1988 (1996). X. Zhou, K. Y. Lim, D. Lim, “A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling,”   IEEE Trans. Electron  Devices, vol. 46, no. 4, pp. 807-809 (1999). S. A. Schwarz and S. E. Russek, “Semiempirical equations for electron velocity in silicon: Part II—MOS inversion layer,”  IEEE  Trans. Electron Devices, vol. 30, no. 12, pp. 1634-1639 (1983). K. Y. Lim and X. Zhou, “A physically-based semi-empirical effective mobility model for  MOSFET compact I–V modeling,” Solid-State  Electron, vol. 45, no. 1, pp. 193-197 (2001). A. G. Sabnis and J. T. Clemens, “Characterization of the electron mobility in the inverted <100> Si surface,”   IEDM Tech.  Dig , pp. 18-21 (1979). H. Shin, G. M. Yeric, A. F. Tasch, and C. M. Maziar, “Physically-based Models for Effective Mobility and Local Field Mobility of Electrons in MOS Inversion Layers,” Solid-State  Electron, vol. 34, no 6, pp. 545-552 (1991) X. Zhou and K. Y. Lim, “Unified MOSFET compact  I-V  model formulation through   physics-based effective transformation,” IEEE  Transactions on Electron Devices, vol. 48, no 5, pp. 887-896 (2001). X. Zhou and K. Y. Lim, “Physically-based semi-empirical series resistance model for  deep-submicron MOSFET  I-V  modeling,”   IEEE Transactions on Electron Devices, vol. 47, no. 6, pp.1300-1302 (2000). F. Assaderaghi, P.K. Ko, C. Hu, “Observation of velocity overshoot in silicon inversion layers,” IEEE Electron Device Letters, vol. 14, no 10, pp. 484-486 (1993). P. K. Ko, “Approaches to scaling,” Advanced  MOS Device Physics, vol. 18, no. 1, pp. 1-37 (1989). F. Gamiz, J. A. Lopez-Villanueva, J. Banqueri, J. E. Carceller, P. Cartujo, “Universality of  electron mobility curves in MOSFETs: A Monte Carlo study”,   IEEE Transactions on   Electron Devices, vol. 42, no. 2, pp. 258-265 (1995).

99 APPENDIX B ROADMAP OF SEMICONDUCTOR SINCE 1977

Past Trend of MOSFET Scaling (Hu, 1995)

MOSFET Technology Projection (Hu, 1995)

100 APPENDIX C ROADMAP OF SEMICONDUCTOR INTO 32NM PROCESS TECHNOLOGY

High Performance Logic Technology Requirement (ITRS, 2003)

101

APPENDIX D

CMOS LAYOUT DESIGN

Schematic cross section of a planar PMOS and NMOS (Zeitzoff and Chung, 2005)

102

APPENDIX E

MOBILITY IN STRAINED AND UNSTRAINED SILICON

Electron mobility enhancement in strained Si MOSFET. Electron enhancement of 

∼1.8 x persist up to high  E eff  (∼ 1 MV/cm). Strained Si allows “moving off” of the universal mobility curve. (Zeitzoff and Chung, 2005)

103

APPENDIX F

THRESHOLD VOLTAGE MODEL

F.1

Modified Threshold Voltage Model

 N c , density of states in conduction band 2 ⎡⎣ 2π m p kT / h 2 ⎤⎦

3

2 3

⎡ 2π  x 1.08 x 9.11 x 10 -31kg x1.38 x 10 -23 J / K ⎤ 2  3 ⎥ T  2 ≅ 2⎢ 2 ⎢ ⎥ ⎡⎣6.625x 10 -34 J ⋅ S ⎤⎦ ⎣ ⎦ ≅ 5.42x1015 T

3

2

( cm− ) 3

 N v , density of states in valence band 2 ⎡⎣ 2π m p kT / h 2 ⎤⎦

3

2 3

⎡ 2π  x 0.81 x 9.11 x 10 -31kg x1.38 x 10 -23 J / K ⎤ 2  3 ⎥ T  2 ≅2⎢ 2 -34 ⎢ ⎥ ⎡⎣6.625x 10  J ⋅ S ⎤⎦ ⎣ ⎦ ≅ 3.52x1015 T

3

2

( cm− ) 3

104 Eq. (4.1) can expanded by using Eq. (4.2) and Eq. (4.13). It yield

VT

= 2φ fp + V FB +

(

2ε si qN A 2φ f

 

C ox

(

⎛ Q ⎞ = 2φ fp + ⎜ φ ms − tot  ⎟ + Cox ⎠ ⎝

2ε si qN A 2φ f

(

2ε si qN A 2φ f

Cox

)

)

 

C ox

⎛ E  ⎞ Q = 2φ fp − ⎜  g  + φ fp ⎟ − tot  + ⎝ 2e ⎠ Cox = φ  fp +

)

 

(

2ε si qN A 2φ f

)

 

C ox

⎛ E  Q ⎞ − ⎜  g  + tot  ⎟ ⎝ 2e C ox ⎠

The final threshold voltage expression can be approximated as

VT ( Short Channel )

= VT ( Long Channel ) + ΔV T   = VT ( Long Channel ) + VT (Short Channel Effects ) + V T (Narrow Width Effects )

(

)

⎞ ⎤ qN x ξ x − 1⎟ ⎥ + A dT ⎛⎜ dT ⎞⎟   ⎟⎥ Cox Cox rj Cox ⎝ W ⎠ ⎠⎦ 2ε si qN A ( 2φ fp ) ⎞  ⎤ 2 xdT qN  A qNxdT ⎡ r  j ⎛ ⎢ = 2φ fp + VFB + ⋅ ⋅ xdT −   − 1⎟ ⎥ ⎜ 1+ ⎜ ⎟⎥ 4 ε φ  Cox Cox ⎢ L ⎝ rj   si fp ⎠⎦ ⎣ ξ x qN x + A dT ⎛⎜ dT ⎞⎟  Cox ⎝ W  ⎠ ⎞ ⎤ qN x ξ x 2x qN x qN x ⎡ r  ⎛ = 2φ fp + V FB + A dT   − A dT ⎢  j ⎜ 1 + dT − 1⎟ ⎥ + A dT ⎛⎜ dT ⎞⎟   ⎟⎥ C ox Cox ⎢ L ⎜ rj Cox ⎝ W ⎠   ⎠⎦ ⎣ ⎝ ⎡ r  j ⎛ ⎞ ⎛ ξ xdT ⎞ ⎤ ⎫⎪  2 xdT qN A xdT ⎧ ⎪ ⎥ = 2φ fp + V FB + − 1⎟ + ⎜ ⎨1 − ⎢ ⎜ 1 + ⎟ ⎝ W ⎟⎠ ⎥ ⎬⎪ Cox ⎪ ⎢ L ⎜ rj   ⎠ ⎦⎭ ⎩ ⎣ ⎝ = 2φ fp + V FB +

2ε si qN A 2φ fp

−

qN A xdT ⎡ r  j ⎛

⎢ ⎜ ⎢⎣ L ⎜⎝

1+

2 xdT

 

105

APPENDIX G

 I-V MODEL

G.1

Modified I-V Model

The total current at a point  y along the inversion layer can be represented as

I ds

⎛ μ   E  ⎞ = nv qvd A = nv q ⋅ ⎜⎜ eff y ⎟⎟ ( zxi ) ⎝ 1 + E y E c ⎠ ⎛ ⎞ ∂V ∂y = ( nv xi ) ⋅ qμ eff z ⋅ ⎜⎜  ⎟⎟ ⎝ 1 + ( ∂V ∂y )(1 E c ) ⎠ ⎛ ⎞ ∂V ∂y = ns q ⋅ μ eff z   ⋅ ⎜⎜ ⎟⎟ ⎝ 1 + ( ∂V ∂y )(1 E c ) ⎠ ⎛ ⎞ ∂V ∂y = Cox ⎡⎣VGT − V ( y ) ⎤⎦ ⋅ μ eff z ⋅ ⎜⎜   ⎟⎟ ⎝ 1 + ( ∂V ∂y )(1 E c ) ⎠

where ns

= nv xi . The I ds

integration of Eq. (6.10) from 0 to L yield

∫ ⎡⎣1 + ( ∂V ∂y )(1 E )⎤⎦ ∂y = C I ∫ ∂y + 1 E ∫ ∂V = C c

L

ds

0

μ eff z

ox

μ eff

Vds

c

0

I ds L [ L + Vds LEc ]  I ds

∫ ⎡⎣V −V ( y )⎤⎦ ⋅( ∂V z ∫  ⎡⎣V − V ( y ) ⎤⎦ ∂V

ox

GT

 

VD

0

 

GT

 

= Cox μ eff z (VGT .Vds − Vds2  2 ) =

Cox μ eff z (VGT .Vds

− Vds2 2  )

L [ L + Vds LEc ] 

∂y ) ∂y  

106

V dsat in quadratic form is obtained by substituting I ds from Eq (6.15) into Eq. (6.16).

μ eff C ox W  2 2 (VGT

⋅

 L

2 ⋅ ( 2VGT Vdsat − Vdsat ) = Cox (VGT − Vdsat ) vsatW 

− Vdsat ) 2VGT VC

vsat L ⎛

⎜1 +

μ eff

⎝

⎞  2 ⎟ = 2VGT − Vdsat V c ⎠

V dsat

 

 

 

2 − 2 VdsatVC + 2 VGT VC − 2 Vdsat =   0 2 − 2VGT VC + 2 VdsatVC =  0  Vdsat

V dsat  in Eq. (6.18) can be approximated when V GT  >> V c and V c is small to be

Vdsat

⎛ ⎞ V  = V C ⎜⎜  1 + 2 GT  − 1⎟⎟ V C  ⎝ ⎠ ⎛ V  ⎞ ≈ V C  ⎜⎜ 2 GT  ⎟⎟ ⎝ V C  ⎠ ≈ 2VGTV C 

2 is obtained by rearranging Eq (6.17) V dsat 

− 2VGT VC + 2 VdsatVC =  0  2 = 2 VGT VC − 2 VdsatVC     Vdsat 2 = 2VC (VGT − Vdsat )    Vdsat 2 Vdsat

The short channel saturation drain current is given as

I dsat

= ns qvsat W     = Cox = Cox = Cox

μ eff 

 L μ eff   L μ eff 

W (VGT W

− Vdsat ) Vc

⎛1 2 ⎞ ⎜ 2 V dsat ⎟   ⎝ ⎠

W ( 2VGT VC 2 L = Cox vsat W VGT   

)