5
D
4
3
2
Bitland Confidential
1
D
M/B Schematics Document C
Intel Braswell-M Platform
C
V1.2
B
2015-04-15
B
5
4
3
2
1
D
D
C
C
B
B
5
4
3
2
1
D
D
C
C
B
B
5
4
3
2
1
BATTERY
7.4V 25WHr
AC ADAPTER
CHARGER
+VDC
OZ8782
CPU VCORE
+VCORE@7A
RT8171B
Power States
D
CPU GXFCORE
28V 45W
D
+VGFX@11A
RT8171B VDDQ
Output power rail Input power rail for power transition
DDR_VTT
+V_VDDQ_VR@5A
[email protected] OFF
Input power rail for end IC
uP1740P/Q
+5V LDO
+3V LDO C
+5VA
+3VA
[email protected]
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF OFF
OFF
OFF
[email protected]
OFF
OFF
OFF
[email protected]+1.2A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
[email protected]+1.83A
RT8205MGQW
C
OFF OFF
1.05A
[email protected]
OFF OFF
uP1741P
OFF
[email protected]
1.8A LDO
[email protected]+0.11A
uP0104SSW8
B
[email protected]
1.24A LDO
B
[email protected]
uP0104SSW8
+VDDQ_VR@5A
1.15S LDO
[email protected]
uP0104SSW8
[email protected]+1.2A
MOS SWITCH
OFF
[email protected]
5
4
3
2
1
D
D
C
C
B
B
5
D
4
3
2
CPU VR
HDMI
EDID0
1
D
Charger
SM BUS0
Braswell I2C 0
Gsensor 0
I2C 1
Gsensor 1
I2C 2
Touch panel
EC
Battery
SM BUS2
Thermal
SM BUS2
C
C
I2C 3
SM BUS1 PS2 Port0
PS2
SMBus block diagram
FST_SPI_CLK 33MHz
B
3 2 . 7 6 8 K H Z
1 9 . 2 M H Z
PCH
PCIE_CLK0/1/2_P/N 100MHz
FST_SPI B
WiFi/LAN/Card Reader
CK_LPC_0_R 25MHz
EC
CK_DDR0/1_DP/DN 800MHz
DDR3L
Clock block diagram
Touch pad
5
4
3
2
1
D
D
C
C
B
B
Bitland Information Technology Co.,Ltd.
A
Page Name
Cover Page
Size B
Braswall-M
Project Name
Rev 1.0
Date: Tuesday, June 09, 2015 Sheet 6 of 52 PROPERTY NOTE : this document contains information confidential and property to Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
A
